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FPGA_Development_Boards.mw
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FPGA_Development_Boards.mw
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This section contains a list of boards, and certain details, that there are push-button synthesis builds for in ORPSoC.
Once you have your board up and running, you may find the guide to [[Debugging physical targets (FPGA/ASIC)|debugging physical targets]] useful.
== ORSoC OpenRISC development boards ==
[http://orsoc.se/fpga-development-board/ More about this board on manufacturer's website]
=== The NEW OpenRISC FPGA development board (ordb2a-ep4ce22) ===
* Board path: altera/ordb2a-ep4ce22 (will be released soon)
* FPGA: Altera Cyclone IV (P/N: ep4ce22)
* CPU core frequency: 70MHz
* Supported devices
** Ethernet
** GPIO
** PCI
** SD Card
** SDRAM (32MByte)
** SPI Flash (up to 8MByte)
** 2xUART
** 2xJTAG
** USB Host/Slave
** Another optional USB
More information about the board can be found [[ordb2a-ep4ce22|here]]
=== ProASIC3E 1500 ===
* Board path: actel/ordb1a3pe1500
* FPGA: A3PE1500
* CPU core frequency: 20MHz
* Supported devices
** Ethernet
** GPIO
** SD Card
** SDRAM (32MB)
** SPI
** UART
** USB 1.1
==== Pre-built image ====
[ftp://ocuser:[email protected]/orpsoc/images/orpsoc-ordb1a3pe1500-20MHz.pdb orpsoc-ordb1a3pe1500-20MHz.pdb]
Please use the Actel FlashPro tool to program the FPGA with this image.
=== ProASIC3 1000 ===
* Board path: actel/ordb1a3pe1500
* FPGA: A3P1000
* CPU core frequency: 20MHz
* OR1200 cache sizes: instruction cache 4 kB, data cache 1 kB
* Boot mode: Loop at zero
* Supported devices
** JTAG_DEBUG
** SDRAM (32MB)
** SPI flash
** UART
Note: The same board path and makefiles are used as the ProASIC3E 1500 FPGA. Call the makefile with parameters like this:
make all FPGA_FAMILY=ProASIC3 FPGA_PART=A3P1000
==== Pre-built images ====
Please use the Actel FlashPro tool to program the FPGA with these images.
[ftp://ocuser:[email protected]/orpsoc/images/orpsoc-ordb1a3p1000-20MHz.pdb orpsoc-ordb1a3p1000-20MHz.pdb] (boot with endless loop at memory address 0)
[ftp://ocuser:[email protected]/orpsoc/images/orpsoc-ordb1a3p1000-20MHz-flashboot.pdb orpsoc-ordb1a3p1000-20MHz-flashboot.pdb] (boot from programmed SPI flash)
See the difference between the Actel FPGAs at the [http://www.actel.com/products/pa3/default.aspx Actel product overview page].
== Xilinx ML501 ==
* Board path: xilinx/ml501
* CPU core frequency: 66MHz
* Supported devices
** Ethernet
** GPIO
** DDR2 SDRAM (256MB)
** CFI flash (32MB)
** SRAM
** SPI
** UART
** AC97 (tested)
** PS/2 (tested)
[http://www.xilinx.com/products/boards-and-kits/HW-V5-ML501-UNI-G.htm More about this board on manufacturer's website]
=== Pre-built image for SPI flash ===
[ftp://ocuser:[email protected]/orpsoc/images/orpsoc-ml501-66MHz.mcs orpsoc-ml501-66MHz.mcs]
See the ML501 documentation in ORPSoC for instructions on programming this image into the board's SPI flash.
=== Flash boot image with U-boot programmer ===
[ftp://ocuser:[email protected]/orpsoc/images/orpsoc-ml501-66MHz-flashboot.mcs orpsoc-ml501-66MHz-flashboot.mcs] FPGA image for SPI flash
[ftp://ocuser:[email protected]/orpsoc/images/ml501-flash-uboot-programmer.elf ml501-flash-uboot-programmer.elf ] Bare-metal programmer app to embed U-boot into CFI flash for boot.
Load the SPI flash as per the instructions, and execute the software to program U-boot into the board's flash. The board will then power up with the U-boot prompt.
== Digilent Atlys ==
* Board path: xilinx/atlys
* CPU core frequency: 50MHz
* Supported devices
** AC97
** Ethernet
** GPIO
** PS/2
** DDR2 SDRAM (128MB)
** SPI
** UART
** VGA
[http://www.digilentinc.com/atlys/ More about this board on manufacturer's website]
== Xilinx XtremeDSP Starter Platform - Spartan-3A DSP 1800 Edition==
* Board path: xilinx/s3adsp1800
* CPU core frequency: 25MHz
* Supported devices
** Ethernet
** GPIO
** DDR2 SDRAM (128MB)
** SPI
** UART
[http://www.xilinx.com/products/boards-and-kits/HW-SD1800A-DSP-SB-UNI-G.htm More about this board on manufacturer's website]
=== Pre-built image ===
[ftp://ocuser:[email protected]/orpsoc/images/orpsoc-s3adsp1800-25MHz.bit orpsoc-s3adsp1800-25MHz.bit]
See the ORPSoC documentation for information on how to program and use the FPGA with this image.
== Terasic DE0 Nano ==
(Not yet pushed to main orpsoc repo. Git repo can be found at git://openrisc.net/stefan/orpsoc)
* Board path: altera/de0_nano
* CPU core frequency: 50MHz
* Supported devices
** GPIO
** SDRAM (32MB)
** UART
** SPI FLASH (8MB)
** I2C
[http://de0-nano.terasic.com/ More about this board on manufacturer's website]
=== Pre-built image with orpsoc, U-Boot and Linux ===
[ftp://ocuser:[email protected]/orpsoc/images/orpsoc-de0-nano-50mhz.tar.gz orpsoc-de0-nano-50mhz.tar.gz]
Use the following command to program the .jic image onto flash:
<nowiki>quartus_pgm --mode=jtag -o pi\;orpsoc.jic</nowiki>