8260585: AArch64: Wrong code generated for shifting right and accumulating four unsigned short integers

Reviewed-by: iveresov, dlong, njian, aph

Author: Dong Bo

src/hotspot/cpu/aarch64/aarch64.ad

@@ -18855,11 +18855,7 @@ instruct vsrla8B_imm(vecD dst, vecD src, immI shift) %{
   format %{ "usra    $dst, $src, $shift\t# vector (8B)" %}
   ins_encode %{
     int sh = (int)$shift$$constant;
-    if (sh >= 8) {
-      __ eor(as_FloatRegister($src$$reg), __ T8B,
-             as_FloatRegister($src$$reg),
-             as_FloatRegister($src$$reg));
-    } else {
+    if (sh < 8) {
       __ usra(as_FloatRegister($dst$$reg), __ T8B,
              as_FloatRegister($src$$reg), sh);
     }
@@ -18874,11 +18870,7 @@ instruct vsrla16B_imm(vecX dst, vecX src, immI shift) %{
   format %{ "usra    $dst, $src, $shift\t# vector (16B)" %}
   ins_encode %{
     int sh = (int)$shift$$constant;
-    if (sh >= 8) {
-      __ eor(as_FloatRegister($src$$reg), __ T16B,
-             as_FloatRegister($src$$reg),
-             as_FloatRegister($src$$reg));
-    } else {
+    if (sh < 8) {
       __ usra(as_FloatRegister($dst$$reg), __ T16B,
              as_FloatRegister($src$$reg), sh);
     }
@@ -18893,12 +18885,8 @@ instruct vsrla4S_imm(vecD dst, vecD src, immI shift) %{
   format %{ "usra    $dst, $src, $shift\t# vector (4H)" %}
   ins_encode %{
     int sh = (int)$shift$$constant;
-    if (sh >= 16) {
-      __ eor(as_FloatRegister($src$$reg), __ T8B,
-             as_FloatRegister($src$$reg),
-             as_FloatRegister($src$$reg));
-    } else {
-      __ ushr(as_FloatRegister($dst$$reg), __ T4H,
+    if (sh < 16) {
+      __ usra(as_FloatRegister($dst$$reg), __ T4H,
              as_FloatRegister($src$$reg), sh);
     }
   %}
@@ -18912,11 +18900,7 @@ instruct vsrla8S_imm(vecX dst, vecX src, immI shift) %{
   format %{ "usra    $dst, $src, $shift\t# vector (8H)" %}
   ins_encode %{
     int sh = (int)$shift$$constant;
-    if (sh >= 16) {
-      __ eor(as_FloatRegister($src$$reg), __ T16B,
-             as_FloatRegister($src$$reg),
-             as_FloatRegister($src$$reg));
-    } else {
+    if (sh < 16) {
       __ usra(as_FloatRegister($dst$$reg), __ T8H,
              as_FloatRegister($src$$reg), sh);
     }