diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index d27e2a392..c722abf81 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -230,9 +230,9 @@ section_header "Installing/Updating RISC-V GNU Toolchain" STATUS="riscv-gnu-toolchain" cd "$RISCV" # Temporarily pin riscv-gnu-toolchain to use GCC 13.2.0. GCC 14 does not work with the Q extension. -if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2" "b488ddb"; then +if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2"; then cd riscv-gnu-toolchain - git reset --hard && git clean -f && git checkout b488ddb #&& git pull + git reset --hard && git clean -f && git checkout master && git pull ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] if [ "$clean" ]; then diff --git a/tests/coverage/Makefile b/tests/coverage/Makefile index e09d17fa3..63b605679 100644 --- a/tests/coverage/Makefile +++ b/tests/coverage/Makefile @@ -1,35 +1,43 @@ -CEXT := c -CPPEXT := cpp -AEXT := s -SEXT := S -SRCEXT := \([$(CEXT)$(AEXT)$(SEXT)]\|$(CPPEXT)\) -#SRCS = $(wildcard *.S) -#PROGS = $(patsubst %.S,%,$(SRCS)) -SRCDIR = . -SRCEXT = S +# Disable builtin rules because they are a shorter (but incorrect) path that Make will use by default +MAKEFLAGS += --no-builtin-rules +SRCDIR := . +SRCEXT := S +AEXT := s +OBJEXT := o +EXEEXT := elf SOURCES ?= $(shell find $(SRCDIR) -type f -regex ".*\.$(SRCEXT)" | sort) -OBJEXT = elf -OBJECTS := $(SOURCES:.$(SEXT)=.$(OBJEXT)) +ELFS := $(SOURCES:.$(SRCEXT)=.$(EXEEXT)) +OBJDUMPS := $(addsuffix .objdump, $(ELFS)) +MEMFILES := $(addsuffix .memfile, $(ELFS)) -all: $(OBJECTS) +all: $(OBJDUMPS) $(MEMFILES) +# Create dissassembly %.elf.objdump: %.elf + riscv64-unknown-elf-objdump -S -D $< > $@ + extractFunctionRadix.sh $@ -# Change many things if bit width isn't 64 -%.elf: $(SRCDIR)/%.$(SEXT) WALLY-init-lib.h Makefile - riscv64-unknown-elf-gcc -g -o $@ -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 -mcmodel=medany \ - -nostartfiles -T../../examples/link/link.ld $< - riscv64-unknown-elf-objdump -S -D $@ > $@.objdump - riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile - extractFunctionRadix.sh $@.objdump - -sim: %.elf +# Create memfile +%.elf.memfile: %.elf + riscv64-unknown-elf-elf2hex --bit-width 64 --input $< --output $@ + +# Link object file to create executable +.PRECIOUS: %.$(EXEEXT) +%.$(EXEEXT): %.$(OBJEXT) + riscv64-unknown-elf-gcc -g -o $@ -mcmodel=medany -nostartfiles -T../../examples/link/link.ld $*.o + +# Assemble into object files +%.$(OBJEXT): %.$(AEXT) + riscv64-unknown-elf-as -g -o $@ -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 $< + +# Preprocess assembly files +%.$(AEXT): %.$(SRCEXT) WALLY-init-lib.h + riscv64-unknown-elf-gcc -E -g -o $@ $< + +sim: %.$(EXEEXT) spike +signature=%.signature.output +signature-granularity=8 %.elf diff --ignore-case %.signature.output %.reference_output || exit echo "Signature matches! Success!" clean: - rm -f *.elf *.objdump *.signature.output *.addr *.lab *.memfile - - - + rm -f *.elf *.objdump *.signature.output *.addr *.lab *.memfile *.o *.s diff --git a/tests/coverage/WALLY-init-lib.h b/tests/coverage/WALLY-init-lib.h index 7e2aee771..0ce72fd6b 100644 --- a/tests/coverage/WALLY-init-lib.h +++ b/tests/coverage/WALLY-init-lib.h @@ -7,20 +7,20 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw -// +// // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You // may obtain a copy of the License at // // https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// @@ -41,21 +41,21 @@ csrw medeleg, zero # Don't delegate exceptions # li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again # li t1, 0x02004000 # MTIMECMP in CLINT -# sd t0, 0(t1) - li t0, 0x80 -# li t0, 0x00 +# sd t0, 0(t1) + li t0, 0x80 +# li t0, 0x00 csrw mie, t0 # Enable machine timer interrupt - la t0, topoftrapstack + la t0, topoftrapstack csrw mscratch, t0 # MSCRATCH holds trap stack pointer csrsi mstatus, 0x8 # Turn on mstatus.MIE global interrupt enable # set up PMP so user and supervisor mode can access full address space csrw pmpcfg0, 0xF # configure PMP0 to TOR RWX - li t0, 0xFFFFFFFF + li t0, 0xFFFFFFFF csrw pmpaddr0, t0 # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses j main # Call main function in user test program done: - li a0, 4 # argument to finish program + li a0, 4 # argument to finish program ecall # system call to finish program j self_loop # wait forever (not taken) @@ -69,11 +69,11 @@ csrr t1, mtval # And the trap value bgez t0, exception # if msb is clear, it is an exception -interrupt: # must be a timer interrupt +interrupt: # must be a timer interrupt li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again li t1, 0x02004000 # MTIMECMP in CLIN - sd t0, 0(t1) - csrw stimecmp, t0 # sets stimecmp to big number so it doesnt interrupt + sd t0, 0(t1) + csrw stimecmp, t0 # sets stimecmp to big number so it doesnt interrupt li t0, 32 csrc sip, t0 # clears stimer interrupt j trap_return # clean up and return @@ -99,7 +99,7 @@ interrupt: # must be a timer interrupt trap_return: # return from trap handler csrr t0, mepc # get address of instruction that caused exception - li t1, 0x20000 + li t1, 0x20000 csrs mstatus, t1 # set mprv bit to fetch instruction with permission of code that trapped lh t0, 0(t0) # get instruction that caused exception csrc mstatus, t1 # clear mprv bit to restore normal operation @@ -139,8 +139,8 @@ trap_return: # return from trap handler slli a0, a0, 16 # use two shifts of 16 bits each to be compatible with compiling either RV32 or 64 setmsbdone: ret # return to calller - -.section .tohost + +.section .tohost tohost: # write to HTIF .dword 0 fromhost: @@ -148,7 +148,7 @@ tohost: # write to HTIF .EQU XLEN,64 begin_signature: - .fill 6*(XLEN/32),4,0xdeadbeef # + .fill 6*(XLEN/32),4,0xdeadbeef # end_signature: scratch: @@ -159,7 +159,7 @@ tohost: # write to HTIF .space 512 topofstack: # And another stack for the trap handler -.bss +.bss .space 512 topoftrapstack: diff --git a/tests/coverage/amoAccessFault.S b/tests/coverage/amoAccessFault.S index a8ecf5f0d..b69c545a4 100644 --- a/tests/coverage/amoAccessFault.S +++ b/tests/coverage/amoAccessFault.S @@ -7,20 +7,20 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw -// +// // Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You // may obtain a copy of the License at // // https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// @@ -40,7 +40,7 @@ main: li t2, 2 li t3, 3 amoadd.d t3, t2, (t1) - + fence.I finished: diff --git a/tests/coverage/csrwrites.S b/tests/coverage/csrwrites.S index aa3cc438f..fb5cfd436 100644 --- a/tests/coverage/csrwrites.S +++ b/tests/coverage/csrwrites.S @@ -7,20 +7,20 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw -// +// // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You // may obtain a copy of the License at // // https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// @@ -44,7 +44,7 @@ main: li a0, 1 ecall # enter supervisor mode - li a0, 0 + li a0, 0 ecall # enter user mode li a0, 1 diff --git a/tests/coverage/dcache1.py b/tests/coverage/dcache1.py index 59259567b..d8740bdda 100644 --- a/tests/coverage/dcache1.py +++ b/tests/coverage/dcache1.py @@ -4,23 +4,23 @@ # Written: avercruysse@hmc.edu 18 April 2023 # # Purpose: Test Coverage for D$ -# (For each way, trigger a CacheDataMem write enable while chip enable is low) +# (For each way, trigger a CacheDataMem write enable while chip enable is low) # # A component of the CORE-V-WALLY configurable RISC-V project. -# +# # Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University # # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 # -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You # may obtain a copy of the License at # # https://solderpad.org/licenses/SHL-2.1/ # -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions # and limitations under the License. ################################################ @@ -28,7 +28,7 @@ test_name = "dcache1.S" dcache_num_ways = 4 -dcache_way_size_in_bytes = 4096 +dcache_way_size_in_bytes = 4096 # warning i$ line size is not currently parameterized. # arbitrary start location of where I send stores to. @@ -48,7 +48,7 @@ def wl(line="", comment=None, fname=test_name): to_write = " " * indent + line + comment + "\n" f.write(to_write) - + def write_repro_instrs(): """ Assumes that the store location has been fetched to d$, and is in t0. @@ -72,7 +72,7 @@ def write_repro_instrs(): wl(comment="This file is generated by dcache1.py (run that script manually)") wl('#include "WALLY-init-lib.h"') wl('main:') - + # excercise all 4 D$ ways. If they're not all full, it uses the first empty. # So we are sure all 4 ways are exercised. for i in range(dcache_num_ways): @@ -82,5 +82,5 @@ def write_repro_instrs(): wl(comment=f"i$ boundary, way test #{i+1}") write_repro_instrs() mem_addr += dcache_way_size_in_bytes # so that we excercise a new D$ way. - + wl("j done") diff --git a/tests/coverage/dcache2.S b/tests/coverage/dcache2.S index 7d5905288..d5a18a708 100644 --- a/tests/coverage/dcache2.S +++ b/tests/coverage/dcache2.S @@ -4,47 +4,47 @@ // Written: avercruysse@hmc.edu 18 April 2023 // // Purpose: Test Coverage for D$ -// (for all 4 cache ways, trigger a FlushStage while SetDirtyWay=1) +// (for all 4 cache ways, trigger a FlushStage while SetDirtyWay=1) // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw -// +// // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You // may obtain a copy of the License at // // https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// #include "WALLY-init-lib.h" main: - // way 0 + // way 0 li t0, 0x80100770 sd zero, 0(t0) sd zero, 1(t0) - // way 1 + // way 1 li t0, 0x80101770 sd zero, 0(t0) sd zero, 1(t0) - // way 2 + // way 2 li t0, 0x80102770 - sd zero, 0(t0) + sd zero, 0(t0) sd zero, 1(t0) // way 3 li t0, 0x80103770 sd zero, 0(t0) sd zero, 1(t0) - + j done diff --git a/tests/coverage/ebu.S b/tests/coverage/ebu.S index fa7927d95..872e37394 100644 --- a/tests/coverage/ebu.S +++ b/tests/coverage/ebu.S @@ -7,20 +7,20 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw -// +// // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You // may obtain a copy of the License at // // https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// @@ -36,22 +36,22 @@ main: csrs menvcfg, t5 # menvcfg.PBMTE = 1, CBZE, CBCFE, CBIE all 1 # Page table root address at 0x80010000; SV48 - li t5, 0x9000000000080010 + li t5, 0x9000000000080010 csrw satp, t5 # sfence.vma x0, x0 # switch to supervisor mode - li a0, 1 + li a0, 1 ecall - # + # # Tricky case to cover. I$ miss concurrent with DTLB miss. HPTW has to hit the first # access in the cache and miss a later one. Trigger this by doing a load that touches # a page not in the DTLB but where the top-level PTE is already there. Has to happen # near the end of the 16-instruction I$ line. -# +# # Condition Coverage for instance /core/ebu/ebu/ebufsmarb -- # # File ../src/ebu/ebufsmarb.sv @@ -66,8 +66,8 @@ main: # LSUReq N '_1' not hit Hit '_1' # IFUReq N No hits Hit '_0' and '_1' # -# Rows: Hits FEC Target Non-masking condition(s) -# --------- --------- -------------------- ------------------------- +# Rows: Hits FEC Target Non-masking condition(s) +# --------- --------- -------------------- ------------------------- # Row 1: 2 HREADY_0 ((LSUReq ~& IFUReq) && FinalBeatD) # Row 2: 14 HREADY_1 ((LSUReq ~& IFUReq) && FinalBeatD) # Row 3: 1 FinalBeatD_0 ((LSUReq ~& IFUReq) && HREADY) @@ -78,7 +78,7 @@ main: # Row 8: ***0*** IFUReq_1 ((HREADY & FinalBeatD) && LSUReq) - li a0, 0x80000000 + li a0, 0x80000000 li a1, 0x80A00000 j label1 @@ -166,7 +166,7 @@ label1: .align 16 # root Page table situated at 0x80010000 -pagetable: +pagetable: .8byte 0x200044C1 # 0x00000000-0x80_00000000: PTE at 0x80011000 C1 dirty, accessed, valid .8byte 0x00000000000010CF # misaligned terapage at 0x80_00000000 @@ -175,7 +175,7 @@ pagetable: .8byte 0x00000000000010CF # misaligned gigapage at 0x00000000 .8byte 0x00000000200058C1 # PTE for pages at 0x40000000 .8byte 0x00000000200048C1 # gigapage at 0x80000000 pointing to 0x80120000 - + # Next page table at 0x80012000 for gigapage at 0x80000000 .align 12 @@ -260,7 +260,7 @@ pagetable: .8byte 0x80000000200060CF .8byte 0x80000000200060CF .8byte 0x80000000200060CF - + .8byte 0x800000002000A0CF .8byte 0x800000002000A0CF .8byte 0x800000002000A0CF diff --git a/tests/coverage/floatmisc.S b/tests/coverage/floatmisc.S index d91229dac..46bbc5418 100644 --- a/tests/coverage/floatmisc.S +++ b/tests/coverage/floatmisc.S @@ -6,7 +6,7 @@ .global rvtest_entry_point rvtest_entry_point: lui t0, 0x02 # turn on Floating point and XS - csrs mstatus, t0 + csrs mstatus, t0 la a6, begin_signature la a7, rvtest_data @@ -53,9 +53,9 @@ write_tohost: self_loop: j self_loop # wait - + .align 6 -.section .tohost +.section .tohost tohost: # write to HTIF .dword 0 fromhost: @@ -75,10 +75,10 @@ rvtest_data: .EQU XLEN,64 begin_signature: - .fill 8*(XLEN/32),4,0xdeadbeef # + .fill 8*(XLEN/32),4,0xdeadbeef # end_signature: # Initialize stack with room for 512 bytes .bss .space 512 -topofstack: \ No newline at end of file +topofstack: diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S index 497ba0207..760898306 100644 --- a/tests/coverage/fpu.S +++ b/tests/coverage/fpu.S @@ -7,20 +7,20 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw -// +// // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You // may obtain a copy of the License at // // https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// @@ -48,9 +48,9 @@ main: fcvt.h.q fs1, fs0 fcvt.s.q fs1, fs0 # round for now because these tests are excluded from Zfa until rounding is implemented - fround.s fs1, fs0 + fround.s fs1, fs0 froundnx.s fs1, fs0 - fround.d fs1, fs0 + fround.d fs1, fs0 froundnx.d fs1, fs0 fround.h fs1, fs0 froundnx.h fs1, fs0 @@ -146,7 +146,7 @@ main: sd t0, 0(t1) csrsi mstatus, 0b1000 # enable interrupts with mstatus.MIE li t1, 0x0200bff8 # read MTIME in CLINT - ld t0, 0(t1) + ld t0, 0(t1) addi t0, t0, 11 li t1, 0x02004000 # MTIMECMP in CLINT sd t0, 0(t1) # write mtime+10 to cause interrupt soon This is very touchy timing and is sensitive to cache line fetch latency @@ -166,7 +166,7 @@ main: .word 0xc5000007 // Attempting to toggle (Op7 != 7) to 0 on line 97 in fctrl, not sure what instruction this works out to .word 0xe0101053 // toggling (Rs2D == 0) to 0 on line 139 in fctrl. Illegal Intsr (like fclass but incorrect rs2) .word 0xe0100053 // toggling (Rs2D == 0) to 0 on line 141 in fctrl. Illegal Intsr (like fmv but incorrect rs2) - .word 0x40D00053 // toggling (Rs2D[4:2] == 0) to 0 on line 145 in fctrl. + .word 0x40D00053 // toggling (Rs2D[4:2] == 0) to 0 on line 145 in fctrl. .word 0x40300053 // toggling SupportFmt2 to 0 on line 145 in fctrl. .word 0x42100053 // toggling (Rs2D[1:0] != 1) to 0 on line 147 in fctrl. Illegal Instr .word 0xf0100053 // toggling (Rs2D == 0) to 0 on line 143 in fctrl. Illegal Instr diff --git a/tests/coverage/gshare.S b/tests/coverage/gshare.S index 788b7743d..ef0fcab77 100644 --- a/tests/coverage/gshare.S +++ b/tests/coverage/gshare.S @@ -8,20 +8,20 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw -// +// // Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You // may obtain a copy of the License at // // https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// @@ -41,7 +41,7 @@ main: jal ra, global_hist_2_space_test jal ra, global_hist_1_space_test jal ra, global_hist_0_space_test - + fence.I finished: @@ -100,7 +100,7 @@ oneLoopTest5: # instruction addi t3, t3, 1 bne t3, t4, oneLoopTest5 # this branch toggles between taken and not taken. - + ret .section .text @@ -116,10 +116,10 @@ loop_6: # instruction addi t3, t3, 1 addi t3, t3, 1 - addi t3, t3, 1 - addi t3, t3, 1 - addi t3, t3, 1 - addi t3, t3, 1 + addi t3, t3, 1 + addi t3, t3, 1 + addi t3, t3, 1 + addi t3, t3, 1 beqz t4, zero_6 # this branch toggles between taken and not taken. li t4, 0 j one_6 @@ -129,12 +129,12 @@ zero_6: addi t3, t3, 1 addi t3, t3, 1 add t1, t1, t4 - + one_6: - addi t3, t3, 1 - addi t3, t3, 1 - addi t3, t3, 1 - addi t3, t3, 1 + addi t3, t3, 1 + addi t3, t3, 1 + addi t3, t3, 1 + addi t3, t3, 1 addi t2, t2, -1 bnez t2, loop_6 @@ -153,8 +153,8 @@ loop_4: # instruction addi t3, t3, 1 addi t3, t3, 1 - addi t3, t3, 1 - addi t3, t3, 1 + addi t3, t3, 1 + addi t3, t3, 1 beqz t4, zero_4 # this branch toggles between taken and not taken. li t4, 0 j one_4 @@ -162,9 +162,9 @@ zero_4: li t4, 1 addi t3, t3, 1 add t1, t1, t4 - + one_4: - addi t3, t3, 1 + addi t3, t3, 1 addi t2, t2, -1 bnez t2, loop_4 @@ -183,8 +183,8 @@ loop_3: # instruction addi t3, t3, 1 addi t3, t3, 1 - addi t3, t3, 1 - addi t3, t3, 1 + addi t3, t3, 1 + addi t3, t3, 1 beqz t4, zero_3 # this branch toggles between taken and not taken. li t4, 0 j one_3 @@ -192,9 +192,9 @@ zero_3: li t4, 1 addi t3, t3, 1 add t1, t1, t4 - + one_3: - addi t3, t3, 1 + addi t3, t3, 1 addi t2, t2, -1 bnez t2, loop_3 @@ -220,7 +220,7 @@ loop_2: zero_2: li t4, 1 add t1, t1, t4 - + one_2: addi t2, t2, -1 bnez t2, loop_2 @@ -245,13 +245,13 @@ loop_1: zero_1: li t4, 1 add t1, t1, t4 - + one_1: addi t2, t2, -1 bnez t2, loop_1 ret - + .section .text .globl global_hist_0_space_test .type global_hist_0_space_test, @function @@ -269,10 +269,9 @@ loop_0: zero_0: li t4, 1 add t1, t1, t4 - + one_0: addi t2, t2, -1 bnez t2, loop_0 ret - diff --git a/tests/coverage/hptwAccessFault.S b/tests/coverage/hptwAccessFault.S index e1a2ea49c..86f681d21 100644 --- a/tests/coverage/hptwAccessFault.S +++ b/tests/coverage/hptwAccessFault.S @@ -8,20 +8,20 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw -// +// // Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You // may obtain a copy of the License at // // https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// @@ -39,20 +39,20 @@ main: # sfence.vma x0, x0 # switch to supervisor mode - li a0, 1 + li a0, 1 ecall li t5, 0 li t2, 0x1000 - li t0, 0x8000001000 + li t0, 0x8000001000 lw t1, 0(t0) # this load is a valid virtual address, but the page table will access an invalid address so it should cause a load access fault li t1, 0x00008067 # this store is a valid virtual address, but the page table will access an invalid address so it should cause a store access fault - add t0, t0, t2 + add t0, t0, t2 sw t1, 0(t0) j jumppoint -jumppoint: +jumppoint: .align 6 # aligns to cache line size sw t1, 0(t0) sw t1, 4(t0) @@ -74,7 +74,7 @@ jumppoint: lw t3, 8(t0) lw t3, 12(t0) lw t3, 16(t0) - + fence.I finished: @@ -84,15 +84,15 @@ finished: .align 16 # Page table situated at 0x80010000 -pagetable: - .8byte 0x200044C1 +pagetable: + .8byte 0x200044C1 .8byte 0x300044C1 # point to invalid region of physical memory .align 12 .8byte 0x00000040200048C1 .8byte 0x00000000200048C1 .8byte 0x00000000200048C1 - + .align 12 .8byte 0x0000000020004CC1 @@ -138,7 +138,7 @@ pagetable: .8byte 0x200074CF .8byte 0x200078CF .8byte 0x20007CCF - + .8byte 0x200080CF .8byte 0x200084CF .8byte 0x200088CF diff --git a/tests/coverage/ieu.S b/tests/coverage/ieu.S index 7ec318632..43e7b6604 100644 --- a/tests/coverage/ieu.S +++ b/tests/coverage/ieu.S @@ -7,20 +7,20 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw -// +// // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You // may obtain a copy of the License at // // https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// @@ -53,7 +53,7 @@ main: ori x0, x0, 1 ori x0, x0, 2 ori x0, x0, 3 - + # Test illegal instructions are detected .word 0x80000033 // illegal R-type instruction @@ -100,9 +100,8 @@ main: cbo.inval (x2) cbo.clean (x3) cbo.flush (x1) - - j done + j done diff --git a/tests/coverage/ifu.S b/tests/coverage/ifu.S index 4b085d845..72c515287 100644 --- a/tests/coverage/ifu.S +++ b/tests/coverage/ifu.S @@ -7,20 +7,20 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw -// +// // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You // may obtain a copy of the License at // // https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// @@ -37,7 +37,7 @@ main: // binary version 0000 0000 0000 0000 0010 0000 0000 0000 mv s0, sp c.fld fs0, 0(s0) // Previously uncovered instructions - c.fsd fs0, 0(s0) + c.fsd fs0, 0(s0) .hword 0x2002 // c.fldsp fs0, 0 .hword 0xA002 // c.fsdsp fs0, 0 .hword 0x9C41 // line 134 Illegal compressed instruction @@ -72,9 +72,9 @@ main: .hword 0x9C71 // c.zext.w s0 # c.not s0 // exercise c.not .hword 0x9C75 // c.not s0 - + .hword 0x9C7D // Reserved instruction from line 187 with op = 01, Instr[15:10] = 100111, Instr[6:5] = 11, and 0's everywhere else - + # exercise all the cache ways j way0code @@ -100,6 +100,6 @@ way3code: .align 12 way00code: ret - - + + j done diff --git a/tests/coverage/ifuCamlineWrite.S b/tests/coverage/ifuCamlineWrite.S index db873dec4..fed86756e 100644 --- a/tests/coverage/ifuCamlineWrite.S +++ b/tests/coverage/ifuCamlineWrite.S @@ -2,28 +2,28 @@ // ifuCamlineWrite.S // // Written: Miles Cook and Kevin Box 4/17 -// -// Acknowledgements: The pagetable and outline for this test was written by Manuel Mendoza -// and Noah Limpert. // -// Purpose: Test coverage for TLBCamlines in IFU +// Acknowledgements: The pagetable and outline for this test was written by Manuel Mendoza +// and Noah Limpert. +// +// Purpose: Test coverage for TLBCamlines in IFU // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw -// +// // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You // may obtain a copy of the License at // // https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// @@ -38,10 +38,10 @@ main: csrw satp, t5 # switch to supervisor mode - li a0, 1 + li a0, 1 ecall - li t0, 0x80015000 # base addr + li t0, 0x80015000 # base addr li t2, 0 # i = 0 li t3, 33 # Max amount of Loops = 32 @@ -49,9 +49,9 @@ main: loop: bge t2, t3, finished # exit loop if i >= loops li t4, 0x1000 li t1, 0x00008067 # load in jalr - sw t1, 0 (t0) + sw t1, 0 (t0) fence.I - jalr t0 + jalr t0 add t0, t0, t4 addi t2, t2, 1 j loop @@ -63,14 +63,14 @@ finished: .align 16 # Page table situated at 0x80010000 -pagetable: +pagetable: .8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong .align 12 .8byte 0x0000000000000000 .8byte 0x00000000200048C1 .8byte 0x00000000200048C1 - + .align 12 .8byte 0x0000000020004CC1 @@ -117,7 +117,7 @@ pagetable: .8byte 0x200074CF .8byte 0x200078CF .8byte 0x20007CCF - + .8byte 0x200080CF .8byte 0x200084CF .8byte 0x200088CF diff --git a/tests/coverage/lsu.S b/tests/coverage/lsu.S index 0e065010e..1c1d7fea6 100644 --- a/tests/coverage/lsu.S +++ b/tests/coverage/lsu.S @@ -7,20 +7,20 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw -// +// // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You // may obtain a copy of the License at // // https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// @@ -34,4 +34,4 @@ main: li a0, 0x80000001 # misaligned address amoadd.w t0, a0, (a0) # amo access to misaligned address - j done \ No newline at end of file + j done diff --git a/tests/coverage/nonleafpbmtfault.S b/tests/coverage/nonleafpbmtfault.S index 8a580ce02..d4aa723f7 100644 --- a/tests/coverage/nonleafpbmtfault.S +++ b/tests/coverage/nonleafpbmtfault.S @@ -8,20 +8,20 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw -// +// // Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You // may obtain a copy of the License at // // https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// @@ -39,17 +39,17 @@ main: # sfence.vma x0, x0 # switch to supervisor mode - li a0, 1 + li a0, 1 ecall li t5, 0 li t2, 0x1000 - li t0, 0x8000001000 + li t0, 0x8000001000 lw t1, 0(t0) # valid virtual address, valid physical address, but invalid PBMT in middle of page table. - li t1, 0x00008067 - add t0, t0, t2 + li t1, 0x00008067 + add t0, t0, t2 sw t1, 0(t0) # valid virtual address, valid physical address, but invalid PBMT in middle of page table. - + fence.I finished: @@ -59,15 +59,15 @@ finished: .align 16 # Page table situated at 0x80010000 -pagetable: - .8byte 0x200044C1 - .8byte 0x200044C1 +pagetable: + .8byte 0x200044C1 + .8byte 0x200044C1 .align 12 .8byte 0x40000040200048C1 .8byte 0x00000000200048C1 .8byte 0x00000000200048C1 - + .align 12 .8byte 0x0000000020004CC1 @@ -113,7 +113,7 @@ pagetable: .8byte 0x200074CF .8byte 0x200078CF .8byte 0x20007CCF - + .8byte 0x200080CF .8byte 0x200084CF .8byte 0x200088CF diff --git a/tests/coverage/pmp.S b/tests/coverage/pmp.S index ab5a60ccc..9680bfdeb 100644 --- a/tests/coverage/pmp.S +++ b/tests/coverage/pmp.S @@ -4,10 +4,10 @@ // Created 2023-04-09 23:20:54.863039 /////////////////////////////////////////// - - - -#include "WALLY-init-lib.h" + + + +#include "WALLY-init-lib.h" main: @@ -107,12 +107,12 @@ li t4, 1733894653101739012 csrw pmpcfg2, t4 -// Testing - +// Testing + // END Configuration and Testing Starting at Register: 0 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - + + ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// // BEGIN Configuration and Testing Starting at Register: 1 // @@ -209,12 +209,12 @@ li t4, 1155173425015948313 csrw pmpcfg2, t4 -// Testing - +// Testing + // END Configuration and Testing Starting at Register: 1 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - + + ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// // BEGIN Configuration and Testing Starting at Register: 2 // @@ -311,12 +311,12 @@ li t4, 576491624729942289 csrw pmpcfg2, t4 -// Testing - +// Testing + // END Configuration and Testing Starting at Register: 2 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - + + ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// // BEGIN Configuration and Testing Starting at Register: 3 // @@ -413,12 +413,12 @@ li t4, 7903341188813065 csrw pmpcfg2, t4 -// Testing - +// Testing + // END Configuration and Testing Starting at Register: 3 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - + + ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// // BEGIN Configuration and Testing Starting at Register: 4 // @@ -515,12 +515,12 @@ li t4, 2023255344336144641 csrw pmpcfg2, t4 -// Testing - +// Testing + // END Configuration and Testing Starting at Register: 4 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - + + ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// // BEGIN Configuration and Testing Starting at Register: 5 // @@ -617,12 +617,12 @@ li t4, 1444534086185583003 csrw pmpcfg2, t4 -// Testing - +// Testing + // END Configuration and Testing Starting at Register: 5 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - + + ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// // BEGIN Configuration and Testing Starting at Register: 6 // @@ -719,12 +719,12 @@ li t4, 865844589318216595 csrw pmpcfg2, t4 -// Testing - +// Testing + // END Configuration and Testing Starting at Register: 6 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - + + ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// // BEGIN Configuration and Testing Starting at Register: 7 // @@ -821,12 +821,12 @@ li t4, 295285980948829067 csrw pmpcfg2, t4 -// Testing - +// Testing + // END Configuration and Testing Starting at Register: 7 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - + + ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// // BEGIN Configuration and Testing Starting at Register: 8 // @@ -923,12 +923,12 @@ li t4, 1806234828062034819 csrw pmpcfg2, t4 -// Testing - +// Testing + // END Configuration and Testing Starting at Register: 8 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - + + ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// // BEGIN Configuration and Testing Starting at Register: 9 // @@ -1025,12 +1025,12 @@ li t4, 1227514141142123288 csrw pmpcfg2, t4 -// Testing - +// Testing + // END Configuration and Testing Starting at Register: 9 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - + + ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// // BEGIN Configuration and Testing Starting at Register: 10 // @@ -1127,12 +1127,12 @@ li t4, 648970879321184272 csrw pmpcfg2, t4 -// Testing - +// Testing + // END Configuration and Testing Starting at Register: 10 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - + + ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// // BEGIN Configuration and Testing Starting at Register: 11 // @@ -1229,12 +1229,12 @@ li t4, 115848442837209096 csrw pmpcfg2, t4 -// Testing - +// Testing + // END Configuration and Testing Starting at Register: 11 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - + + ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// // BEGIN Configuration and Testing Starting at Register: 12 // @@ -1331,12 +1331,12 @@ li t4, 11210457292615976960 csrw pmpcfg2, t4 -// Testing - +// Testing + // END Configuration and Testing Starting at Register: 12 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - + + ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// // BEGIN Configuration and Testing Starting at Register: 13 // @@ -1433,12 +1433,12 @@ li t4, 10631735484709601308 csrw pmpcfg2, t4 -// Testing - +// Testing + // END Configuration and Testing Starting at Register: 13 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - + + ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// // BEGIN Configuration and Testing Starting at Register: 14 // @@ -1535,12 +1535,12 @@ li t4, 10052905250353847316 csrw pmpcfg2, t4 -// Testing - +// Testing + // END Configuration and Testing Starting at Register: 14 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - + + ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// // BEGIN Configuration and Testing Starting at Register: 15 // @@ -1637,10 +1637,10 @@ li t4, 9446317844957238284 csrw pmpcfg2, t4 -// Testing - +// Testing + // END Configuration and Testing Starting at Register: 15 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - - j done \ No newline at end of file + + + j done diff --git a/tests/coverage/pmpadrdecs.S b/tests/coverage/pmpadrdecs.S index 51ca4d148..8e6701d8e 100644 --- a/tests/coverage/pmpadrdecs.S +++ b/tests/coverage/pmpadrdecs.S @@ -2,8 +2,8 @@ // Liam Chalk, lchalk@hmc.edu, 4/27/2023 // Setting AdrMode to 2 or 3 for pmpadrdecs[0-4] -#include "WALLY-init-lib.h" -main: +#include "WALLY-init-lib.h" +main: # Writing values to pmpcfg0 to change AdrMode to 2 or 3 # pmpadrdec[0] @@ -19,4 +19,4 @@ main: li t0, 0x1000000000 csrw pmpcfg0, t0 - j done \ No newline at end of file + j done diff --git a/tests/coverage/pmpcbo.S b/tests/coverage/pmpcbo.S index 2e7eab642..3a7638404 100644 --- a/tests/coverage/pmpcbo.S +++ b/tests/coverage/pmpcbo.S @@ -2,14 +2,14 @@ // David_Harris@hmc.edu 1/21/24 // Cover PMP checks of cache management instructions -#include "WALLY-init-lib.h" -main: +#include "WALLY-init-lib.h" +main: # set up PMP so user and supervisor mode can access partial address space li t0, 0x080F; # li t0, 0x0808; csrw pmpcfg0, t0 # configure PMP0 to TOR RWX and PMP1 to TOR no access - li t0, 0x2003FFFF + li t0, 0x2003FFFF li t1, 0xFFFFFFFF csrw pmpaddr0, t0 # configure PMP0 top of range to 0x800FFFFF to allow all 32-bit addresses csrw pmpaddr1, t1 # configure PMP1 top of range to 0xFFFFFFFF to prohibit accesses above @@ -28,4 +28,4 @@ main: cbo.zero (a0) cbo.inval (a0) - j done \ No newline at end of file + j done diff --git a/tests/coverage/pmpcfg.S b/tests/coverage/pmpcfg.S index bcc8f3950..1013439b7 100644 --- a/tests/coverage/pmpcfg.S +++ b/tests/coverage/pmpcfg.S @@ -1,11 +1,11 @@ // pmpcfg part 1 // Kevin Wan, kewan@hmc.edu, 4/18/2023 // Liam Chalk, lchalk@hmc.edu, 4/25/2023 -// locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR. +// locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR. // See the next part in pmpcfg1.S -#include "WALLY-init-lib.h" -main: +#include "WALLY-init-lib.h" +main: li t0, 0x90000000 csrw pmpaddr0, t0 @@ -103,4 +103,4 @@ main: li t0, 0x8800 csrw pmpcfg0, t0 - j done \ No newline at end of file + j done diff --git a/tests/coverage/pmpcfg1.S b/tests/coverage/pmpcfg1.S index 96264c55f..37dcec14b 100644 --- a/tests/coverage/pmpcfg1.S +++ b/tests/coverage/pmpcfg1.S @@ -1,12 +1,12 @@ -// another set of pmpcfg tests. A new file is made because pmpcfg register fields are -// locked forever after writing 1 to the lock bit for the first time. +// another set of pmpcfg tests. A new file is made because pmpcfg register fields are +// locked forever after writing 1 to the lock bit for the first time. // Kevin Wan, kewan@hmc.edu, 4/13/2023 -// This set tests locking the pmpXcfg fields in descending order again, without setting the TOR bits. +// This set tests locking the pmpXcfg fields in descending order again, without setting the TOR bits. // for the other part of the tests, see pmpcfg.S -#include "WALLY-init-lib.h" -main: +#include "WALLY-init-lib.h" +main: li t0, 0x800 csrw pmpcfg0, t0 li t0, 0x8000000 @@ -45,4 +45,4 @@ main: - j done \ No newline at end of file + j done diff --git a/tests/coverage/pmpcfg2.S b/tests/coverage/pmpcfg2.S index 5966e3cdc..4e0002e6e 100644 --- a/tests/coverage/pmpcfg2.S +++ b/tests/coverage/pmpcfg2.S @@ -1,12 +1,12 @@ // pmpcfg part 3 // Kevin Wan, kewan@hmc.edu, 4/18/2023 -// locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR. +// locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR. // See the next part in pmpcfg1.S -#include "WALLY-init-lib.h" -main: +#include "WALLY-init-lib.h" +main: li t0, 0x80 csrw pmpcfg0, t0 - j done \ No newline at end of file + j done diff --git a/tests/coverage/pmppriority.S b/tests/coverage/pmppriority.S index da2f0f40c..8a30c6019 100644 --- a/tests/coverage/pmppriority.S +++ b/tests/coverage/pmppriority.S @@ -1,29 +1,29 @@ // pmppriority test cases // Kevin Wan kewan@hmc.edu 4/27/2023 // want memory ranges to match: -// 1. only the most significant address and none of the lower ones, -// 2. the most significant address and ANY of the lower ones. +// 1. only the most significant address and none of the lower ones, +// 2. the most significant address and ANY of the lower ones. -#include "WALLY-init-lib.h" -main: +#include "WALLY-init-lib.h" +main: li t1, 0x21FFFFFF // start at 0x8000000 with a range of 1000000. Address format is set to NAPOT in pmpcfg. - csrw pmpaddr0, t1 + csrw pmpaddr0, t1 csrw pmpaddr1, t1 - csrw pmpaddr2, t1 + csrw pmpaddr2, t1 csrw pmpaddr3, t1 - csrw pmpaddr4, t1 + csrw pmpaddr4, t1 csrw pmpaddr5, t1 csrw pmpaddr6, t1 csrw pmpaddr7, t1 csrw pmpaddr8, t1 csrw pmpaddr9, t1 - csrw pmpaddr10, t1 + csrw pmpaddr10, t1 csrw pmpaddr11, t1 - csrw pmpaddr12, t1 + csrw pmpaddr12, t1 csrw pmpaddr13, t1 csrw pmpaddr14, t1 csrw pmpaddr15, t1 @@ -34,59 +34,59 @@ main: sw zero, 0(sp) li t0, 0x1F00 - csrw pmpcfg0, t0 + csrw pmpcfg0, t0 sw zero, 0(sp) li t0, 0x1F1F - csrw pmpcfg0, t0 + csrw pmpcfg0, t0 sw zero, 0(sp) li t0, 0x1F0000 - csrw pmpcfg0, t0 + csrw pmpcfg0, t0 sw zero, 0(sp) - + li t0, 0x1F1F1F - csrw pmpcfg0, t0 + csrw pmpcfg0, t0 sw zero, 0(sp) li t0, 0x1F000000 - csrw pmpcfg0, t0 + csrw pmpcfg0, t0 sw zero, 0(sp) - + li t0, 0x1F1F1F1F - csrw pmpcfg0, t0 + csrw pmpcfg0, t0 sw zero, 0(sp) li t0, 0x1F00000000 - csrw pmpcfg0, t0 + csrw pmpcfg0, t0 sw zero, 0(sp) - + li t0, 0x1F1F1F1F1F - csrw pmpcfg0, t0 + csrw pmpcfg0, t0 sw zero, 0(sp) li t0, 0x1F0000000000 - csrw pmpcfg0, t0 + csrw pmpcfg0, t0 sw zero, 0(sp) - + li t0, 0x1F1F1F1F1F1F - csrw pmpcfg0, t0 + csrw pmpcfg0, t0 sw zero, 0(sp) li t0, 0x1F000000000000 - csrw pmpcfg0, t0 + csrw pmpcfg0, t0 sw zero, 0(sp) - + li t0, 0x1F1F1F1F1F1F1F - csrw pmpcfg0, t0 + csrw pmpcfg0, t0 sw zero, 0(sp) li t0, 0x1F00000000000000 - csrw pmpcfg0, t0 + csrw pmpcfg0, t0 sw zero, 0(sp) - + li t0, 0x1F1F1F1F1F1F1F1F - csrw pmpcfg0, t0 + csrw pmpcfg0, t0 sw zero, 0(sp) li t0, 0x0 @@ -156,6 +156,3 @@ main: j done - - - \ No newline at end of file diff --git a/tests/coverage/priv.S b/tests/coverage/priv.S index 105a61e11..1af15add7 100644 --- a/tests/coverage/priv.S +++ b/tests/coverage/priv.S @@ -7,20 +7,20 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw -// +// // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You // may obtain a copy of the License at // // https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// @@ -33,26 +33,26 @@ main: csrw sepc, t1 sret sretdone: - addi t2, x0, 42 + addi t2, x0, 42 # switch to user mode - li a0, 0 + li a0, 0 ecall sret #should be treated as illegal instruction mret #mret in user mode and should be illegal # switch to supervisor mode - li a0, 1 + li a0, 1 ecall # Test read to stimecmp fails when MCOUNTEREN_TM is not set li t1, -3 csrw stimecmp, t1 - csrr t0, stimecmp + csrr t0, stimecmp # satp write with mstatus.TVM = 1 - bseti t0, zero, 20 + bseti t0, zero, 20 csrs mstatus, t0 csrw satp, zero @@ -62,7 +62,7 @@ sretdone: ecall # starts in M-mode li t1, -3 csrw stimecmp, t1 # sets stimecmp to large value to prevent it from interrupting immediately - li t0, 2 + li t0, 2 csrs mstatus, t0 # enables sie li t0, 32 csrs sie, t0 # enables sie.stie @@ -111,7 +111,7 @@ sretdone: csrw fcsr, t0 # switch to supervisor mode - li a0, 1 + li a0, 1 ecall # Test write to STVAL, SCAUSE, SEPC, and STIMECMP CSRs @@ -125,8 +125,8 @@ sretdone: # Switch to machine mode - li a0, 3 - ecall + li a0, 3 + ecall # Write to MCOUNTINHIBIT CSR csrw mcountinhibit, t0 @@ -149,7 +149,7 @@ sretdone: csrw 2828, t0 csrw 2829, t0 csrw 2830, t0 - csrw 2831, t0 + csrw 2831, t0 csrw 2832, t0 csrw 2833, t0 csrw 2834, t0 @@ -165,7 +165,7 @@ sretdone: csrw 2844, t0 csrw 2845, t0 csrw 2846, t0 - csrw 2847, t0 + csrw 2847, t0 # Testing the HPMCOUNTERM performance counter: reading csrr t0, 2817 @@ -181,7 +181,7 @@ sretdone: csrw 958, t0 - # Testing writes to MTVAL, MCAUSE + # Testing writes to MTVAL, MCAUSE li t0, 0 csrw mtval, t0 csrw mcause, t0 @@ -195,7 +195,7 @@ sretdone: # Test writes to floating point CSRs csrw frm, t0 csrw fflags, t0 - + # CSRC MCOUNTEREN Register # Go to machine mode li a0, 3 @@ -228,7 +228,7 @@ sretdone: li a0, 0 ecall #set status TVM to 0 by writing to bit 20 of mstatus as 0 - #bseti t0, zero, 20 + #bseti t0, zero, 20 sfence.vma zero, zero # Go to supervisor mode @@ -241,7 +241,7 @@ sretdone: ecall # Write to satp when status.TVM is 1 from machine mode - bseti t0, zero, 20 + bseti t0, zero, 20 csrs mstatus, t0 csrw satp, t0 @@ -315,15 +315,12 @@ sretdone: ecall # enter machine mode bseti t0, zero, 17 csrs mstatus, t0 # set MPRV - li t1, 0x00001800 + li t1, 0x00001800 csrs mstatus, t1 # set MPP=3 la t1, finished - csrr t0, mepc + csrr t0, mepc csrw mepc, t1 # set mepc for mret to jump to mret finished: j done - - - diff --git a/tests/coverage/tlbASID.S b/tests/coverage/tlbASID.S index 25cf650ca..bb870429a 100644 --- a/tests/coverage/tlbASID.S +++ b/tests/coverage/tlbASID.S @@ -9,20 +9,20 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw -// +// // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You // may obtain a copy of the License at // // https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// @@ -35,19 +35,19 @@ # run-elf.bash find this in project description main: # Page table root address at 0x80010000 - li t5, 0x9000000000080080 // try making asid = 0. + li t5, 0x9000000000080080 // try making asid = 0. csrw satp, t5 # sfence.vma x0, x0 # switch to supervisor mode - li a0, 1 + li a0, 1 ecall li t0, 0xC0000000 li t2, 0 # i = 0 - li t5, 0 # j = 0 // now use as a counter for new asid loop + li t5, 0 # j = 0 // now use as a counter for new asid loop li t3, 32 # Max amount of Loops = 32 loop: bge t2, t3, finished # exit loop if i >= loops @@ -56,7 +56,7 @@ loop: bge t2, t3, finished # exit loop if i >= loops sw t1, 0(t0) fence.I jalr t0 - li t5, 0x9001000000080080 // try making asid = 1 + li t5, 0x9001000000080080 // try making asid = 1 csrw satp, t5 jalr t0 li t5, 0x9000000000080080 // try making asid = 0 @@ -65,16 +65,16 @@ loop: bge t2, t3, finished # exit loop if i >= loops add t0, t0, t4 addi t2, t2, 1 j loop - + finished: j done .data .align 19 # level 3 Page table situated at 0x8008 0000, should point to 8008,1000 -pagetable: +pagetable: .8byte 0x200204C1 - + .align 12 // level 2 page table, contains direction to a gigapage .8byte 0x0 .8byte 0x0 @@ -129,5 +129,3 @@ pagetable: .8byte 0x200084CF .8byte 0x200088CF .8byte 0x20008CCF - - diff --git a/tests/coverage/tlbGLB.S b/tests/coverage/tlbGLB.S index de1541610..affc4e49d 100644 --- a/tests/coverage/tlbGLB.S +++ b/tests/coverage/tlbGLB.S @@ -9,20 +9,20 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw -// +// // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You // may obtain a copy of the License at // // https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// @@ -34,7 +34,7 @@ # run-elf.bash find this in project description main: # Page table root address at 0x80010000 - li t5, 0x9000000000080080 // try making asid = 0. + li t5, 0x9000000000080080 // try making asid = 0. csrw satp, t5 # switch to supervisor mode @@ -82,9 +82,9 @@ nASID: #swap to different address space -> jump to each address .data .align 19 # level 3 Page table situated at 0x8008 0000, should point to 8008,1000 -pagetable: +pagetable: .8byte 0x200204C1 - + .align 12 // level 2 page table, contains direction to a gigapageg .8byte 0x0 .8byte 0x0 @@ -179,7 +179,3 @@ pagetable: .8byte 0x200084EF .8byte 0x200088EF .8byte 0x20008CEF - - - - \ No newline at end of file diff --git a/tests/coverage/tlbGP.S b/tests/coverage/tlbGP.S index bbdb703b4..da1301cb0 100644 --- a/tests/coverage/tlbGP.S +++ b/tests/coverage/tlbGP.S @@ -8,20 +8,20 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw -// +// // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You // may obtain a copy of the License at // // https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// @@ -38,10 +38,10 @@ main: # sfence.vma x0, x0 # switch to supervisor mode - li a0, 1 + li a0, 1 ecall - li t5, 0 - li t0, 0xC0200000 // go to first gigapage + li t5, 0 + li t0, 0xC0200000 // go to first gigapage li t4, 0x40000000 // put this outside the loop. li t2, 0 # i = 0 li t3, 64 # Max amount of Loops = 16 @@ -63,97 +63,92 @@ finished: .align 16 # Page table situated at 0x80010000 -pagetable: +pagetable: .8byte 0x200044C1 -.align 12 +.align 12 .8byte 0x000000CF //8000 0000 .8byte 0x100000CF - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF .8byte 0x200000CF - .8byte 0x200000CF .8byte 0x200000CF .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - - .8byte 0x200000CF .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF + .8byte 0x200000CF .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF .8byte 0x200000CF - .8byte 0x200000CF .8byte 0x200000CF .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - - .8byte 0x200000CF .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF + .8byte 0x200000CF .8byte 0x200000CF .8byte 0x200000CF .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF + + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF .8byte 0x200000CF - .8byte 0x200000CF .8byte 0x200000CF .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF - .8byte 0x200000CF .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF .8byte 0x200000CF .8byte 0x200000CF .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF + + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF .8byte 0x200000CF - .8byte 0x200000CF .8byte 0x200000CF .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF .8byte 0x200000CF .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF - + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF diff --git a/tests/coverage/tlbKP.S b/tests/coverage/tlbKP.S index 4382673ea..ca72a16db 100644 --- a/tests/coverage/tlbKP.S +++ b/tests/coverage/tlbKP.S @@ -8,20 +8,20 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw -// +// // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You // may obtain a copy of the License at // // https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// @@ -38,7 +38,7 @@ main: # sfence.vma x0, x0 # switch to supervisor mode - li a0, 1 + li a0, 1 ecall li t0, 0x80015000 @@ -60,14 +60,14 @@ finished: .align 16 # Page table situated at 0x80010000 -pagetable: +pagetable: .8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong .align 12 .8byte 0x0000000000000000 .8byte 0x00000000200048C1 .8byte 0x00000000200048C1 - + .align 12 .8byte 0x0000000020004CC1 @@ -114,7 +114,7 @@ pagetable: .8byte 0x200074CF .8byte 0x200078CF .8byte 0x20007CCF - + .8byte 0x200080CF .8byte 0x200084CF .8byte 0x200088CF diff --git a/tests/coverage/tlbM3.S b/tests/coverage/tlbM3.S index eba37ae99..986fb378a 100644 --- a/tests/coverage/tlbM3.S +++ b/tests/coverage/tlbM3.S @@ -8,20 +8,20 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw -// +// // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You // may obtain a copy of the License at // // https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// @@ -38,7 +38,7 @@ main: # sfence.vma x0, x0 # switch to supervisor mode - li a0, 1 + li a0, 1 ecall li t0, 0x1000 @@ -57,7 +57,7 @@ loop: bge t2, t3, interim # exit loop if i >= loops interim: li t0, 0xFFFFFFFF000 li t2, 0 # i = 0 - + loop2:bge t2, t3, finished # exit loop if i >= loops lw t1, 0(t0) @@ -72,14 +72,14 @@ finished: .align 16 # Page table situated at 0x80010000 -pagetable: +pagetable: .8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong .align 12 .8byte 0x00000000200048C1 .8byte 0x00000000200048C1 .8byte 0x00000000200048C1 - + .align 12 .8byte 0x0000000020004CC1 @@ -126,7 +126,7 @@ pagetable: .8byte 0x200074CF .8byte 0x200078CF .8byte 0x20007CCF - + .8byte 0x200080CF .8byte 0x200084CF .8byte 0x200088CF diff --git a/tests/coverage/tlbMP.S b/tests/coverage/tlbMP.S index f6dc4c597..5f35c5879 100644 --- a/tests/coverage/tlbMP.S +++ b/tests/coverage/tlbMP.S @@ -8,20 +8,20 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw -// +// // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You // may obtain a copy of the License at // // https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// @@ -38,10 +38,10 @@ main: # sfence.vma x0, x0 # switch to supervisor mode - li a0, 1 + li a0, 1 ecall - li t5, 0 + li t5, 0 li t0, 0x84000000 // go to first megapage li t4, 0x200000 // put this outside the loop. li t2, 0 # i = 0 @@ -63,19 +63,19 @@ finished: .align 16 # Page table situated at 0x80010000 -pagetable: +pagetable: .8byte 0x200044C1 .align 12 .8byte 0x00000000200048C1 .8byte 0x00000000200048C1 .8byte 0x00000000200048C1 - + .align 12 // megapages starting at 8000 0000 going to 8480 0000 (32*2 MiB beyond that) .8byte 0x200000CF // access 8000,0000 - .8byte 0x200800CF // access 8020,0000 + .8byte 0x200800CF // access 8020,0000 .8byte 0x201000CF // acesss 8040,0000 .8byte 0x201800CF // acesss 8060,0000 @@ -85,37 +85,37 @@ pagetable: .8byte 0x203800CF // access 80E0,0000 .8byte 0x204000CF // access 8100,0000 - .8byte 0x204800CF - .8byte 0x205000CF - .8byte 0x205800CF + .8byte 0x204800CF + .8byte 0x205000CF + .8byte 0x205800CF .8byte 0x206000CF // access 8180,0000 - .8byte 0x206800CF - .8byte 0x207000CF - .8byte 0x207800CF + .8byte 0x206800CF + .8byte 0x207000CF + .8byte 0x207800CF .8byte 0x208000CF // access 8200,0000 - .8byte 0x208800CF - .8byte 0x209000CF - .8byte 0x209800CF + .8byte 0x208800CF + .8byte 0x209000CF + .8byte 0x209800CF .8byte 0x20A000CF // access 8280,0000 - .8byte 0x20A800CF - .8byte 0x20B000CF - .8byte 0x20B800CF + .8byte 0x20A800CF + .8byte 0x20B000CF + .8byte 0x20B800CF .8byte 0x20C000CF // access 8300,0000 - .8byte 0x20C800CF - .8byte 0x20D000CF + .8byte 0x20C800CF + .8byte 0x20D000CF .8byte 0x20D800CF .8byte 0x20E000CF // access 8380,0000 - .8byte 0x20E800CF - .8byte 0x20F000CF + .8byte 0x20E800CF + .8byte 0x20F000CF .8byte 0x20F800CF .8byte 0x200000CF // access 8000,0000 I AM REPEATING PTE TO SAVE TIME. - .8byte 0x200800CF // access 8020,0000 + .8byte 0x200800CF // access 8020,0000 .8byte 0x201000CF // acesss 8040,0000 .8byte 0x201800CF // acesss 8060,0000 @@ -125,40 +125,40 @@ pagetable: .8byte 0x203800CF // access 80E0,0000 .8byte 0x204000CF // access 8100,0000 - .8byte 0x204800CF - .8byte 0x205000CF - .8byte 0x205800CF + .8byte 0x204800CF + .8byte 0x205000CF + .8byte 0x205800CF .8byte 0x206000CF // access 8180,0000 - .8byte 0x206800CF - .8byte 0x207000CF - .8byte 0x207800CF + .8byte 0x206800CF + .8byte 0x207000CF + .8byte 0x207800CF .8byte 0x208000CF // access 8200,0000 - .8byte 0x208800CF - .8byte 0x209000CF - .8byte 0x209800CF + .8byte 0x208800CF + .8byte 0x209000CF + .8byte 0x209800CF .8byte 0x20A000CF // access 8280,0000 - .8byte 0x20A800CF - .8byte 0x20B000CF - .8byte 0x20B800CF + .8byte 0x20A800CF + .8byte 0x20B000CF + .8byte 0x20B800CF .8byte 0x20C000CF // access 8300,0000 - .8byte 0x20C800CF - .8byte 0x20D000CF + .8byte 0x20C800CF + .8byte 0x20D000CF .8byte 0x20D800CF .8byte 0x20E000CF // access 8380,0000 - .8byte 0x20E800CF - .8byte 0x20F000CF + .8byte 0x20E800CF + .8byte 0x20F000CF .8byte 0x20F800CF .8byte 0x20004CC1 // Kilopage entry, for addresses from 8400, 0000 to 841F, FFFF - // point to ... + // point to ... -.align 12 // should start at 84000000 +.align 12 // should start at 84000000 .8byte 0x210000CF .8byte 0x210004CF .8byte 0x210008CF @@ -198,4 +198,3 @@ pagetable: .8byte 0x210074CF .8byte 0x210078CF .8byte 0x21007CCF - diff --git a/tests/coverage/tlbMisaligned.S b/tests/coverage/tlbMisaligned.S index e683c9a86..13506646d 100644 --- a/tests/coverage/tlbMisaligned.S +++ b/tests/coverage/tlbMisaligned.S @@ -7,20 +7,20 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw -// +// // Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You // may obtain a copy of the License at // // https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// @@ -42,11 +42,11 @@ main: # sfence.vma x0, x0 # switch to supervisor mode - li a0, 1 + li a0, 1 ecall li t5, 0 li t2, 0x1000 - li t0, 0x1000 // go to first gigapage + li t0, 0x1000 // go to first gigapage li t4, 0x40000000 // put this outside the loop. lw t1, 1(t0) # load a misaligned aligned cached address @@ -58,7 +58,7 @@ main: lw t1, 1(t0) # load a misaligned aligned uncached address should fault add t0, t0, t2 # go to the next page sw t1, 1(t0) # store to another misaligned uncached address should falt. - + fence.I finished: @@ -68,14 +68,14 @@ finished: .align 16 # Page table situated at 0x80010000 -pagetable: - .8byte 0x200044C1 +pagetable: + .8byte 0x200044C1 .align 12 .8byte 0x00000000200048C1 .8byte 0x00000000200048C1 .8byte 0x00000000200048C1 - + .align 12 .8byte 0x0000000020004CC1 @@ -122,7 +122,7 @@ pagetable: .8byte 0x200074CF .8byte 0x200078CF .8byte 0x20007CCF - + .8byte 0x200080CF .8byte 0x200084CF .8byte 0x200088CF diff --git a/tests/coverage/tlbNAPOT.S b/tests/coverage/tlbNAPOT.S index 508eb057c..c38472ad0 100644 --- a/tests/coverage/tlbNAPOT.S +++ b/tests/coverage/tlbNAPOT.S @@ -9,20 +9,20 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw -// +// // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You // may obtain a copy of the License at // // https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// @@ -36,13 +36,13 @@ main: slli t5, t5, 62 csrs menvcfg, t5 # Page table root address at 0x80010000; SV48 - li t5, 0x9000000000080010 + li t5, 0x9000000000080010 csrw satp, t5 # sfence.vma x0, x0 # switch to supervisor mode - li a0, 1 + li a0, 1 ecall li t4, 0x200000 # address step size @@ -90,7 +90,7 @@ finished: jr a1 changetoipfhandler: - li a0, 3 + li a0, 3 ecall # switch to machine mode la a0, ipf_handler csrw mtvec, a0 # point to new handler @@ -99,7 +99,7 @@ changetoipfhandler: ret changetodefaulthandler: - li a0, 3 + li a0, 3 ecall # switch to machine mode la a0, trap_handler csrw mtvec, a0 # point to new handler @@ -137,7 +137,7 @@ ipf: .align 16 # root Page table situated at 0x80010000 -pagetable: +pagetable: .8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong # next page table at 0x80011000 @@ -146,7 +146,7 @@ pagetable: .8byte 0x00000000200058C1 # gigapage at 0x40000000 used for non-NAPOT with PPN bit 3 set .8byte 0x00000000200048C1 # gigapage at 0x80000000 used for testing NAPOT huge pages .8byte 0x00000000200050C1 # gigapage at 0xC0000000 mapped to ill-formed NAPOT with wrong PPN - + # Next page table at 0x80012000 for gigapage at 0x80000000 .align 12 @@ -231,7 +231,7 @@ pagetable: .8byte 0x80000000200060CF .8byte 0x80000000200060CF .8byte 0x80000000200060CF - + .8byte 0x800000002000A0CF .8byte 0x800000002000A0CF .8byte 0x800000002000A0CF @@ -437,4 +437,3 @@ pagetable: .8byte 0x00000000200060CF .8byte 0x000000002000A0CF .8byte 0x000000002000E0CF - diff --git a/tests/coverage/tlbTP.S b/tests/coverage/tlbTP.S index f4b0a142e..89b5d1ec7 100644 --- a/tests/coverage/tlbTP.S +++ b/tests/coverage/tlbTP.S @@ -8,20 +8,20 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw -// +// // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You // may obtain a copy of the License at // // https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// @@ -38,10 +38,10 @@ main: # sfence.vma x0, x0 # switch to supervisor mode - li a0, 1 + li a0, 1 ecall - li t5, 0 - li t0, 0x80000000 // go to first gigapage + li t5, 0 + li t0, 0x80000000 // go to first gigapage li t4, 0x8000000000 // put this outside the loop. li t2, 0 # i = 0 li t3, 64 # run through 64 PTEs @@ -63,7 +63,7 @@ finished: .align 16 # Page table situated at 0x80010000 -pagetable: +pagetable: .8byte 0x0CF .8byte 0x0CF .8byte 0x0CF @@ -142,4 +142,4 @@ pagetable: .8byte 0x0CF .8byte 0x0CF .8byte 0x0CF - .8byte 0x0CF \ No newline at end of file + .8byte 0x0CF diff --git a/tests/coverage/tlbmisc.S b/tests/coverage/tlbmisc.S index f64645689..9e660bdc4 100644 --- a/tests/coverage/tlbmisc.S +++ b/tests/coverage/tlbmisc.S @@ -7,20 +7,20 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw -// +// // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You // may obtain a copy of the License at // // https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// @@ -38,21 +38,21 @@ main: # store ret instruction in case we jump to an address mapping to 80000000 li t0, 0x80000000 li t5, 0x8082 # return instruction opcode - sw t5, 0(t0) + sw t5, 0(t0) fence.i - # Test not being able to write illegal SATP mode - li t5, 0xA000000000080010 + # Test not being able to write illegal SATP mode + li t5, 0xA000000000080010 csrw satp, t5 # Page table root address at 0x80010000; SV48 - li t5, 0x9000000000080010 + li t5, 0x9000000000080010 csrw satp, t5 # sfence.vma x0, x0 # switch to supervisor mode - li a0, 1 + li a0, 1 ecall # Instruction fetch from misaligned pages @@ -65,27 +65,27 @@ main: jalr ra, t0 # jump to misaligned megapage li t0, 0x7FFFFFFF80000000 - + jalr ra, t0 # jump to page with UpperBitsUnequal li t0, 0x0000000080C00000 jalr ra, t0 # jump to page with bad reserved bits 60:54 in PTE - - # test with ENVCFG_ADUE = 1: switch to machine mode, set ADUE, access page with A=0, clear ADUE, + + # test with ENVCFG_ADUE = 1: switch to machine mode, set ADUE, access page with A=0, clear ADUE, li a0, 3 ecall # switch to machine mode li t0, 1 - slli t0, t0, 61 + slli t0, t0, 61 csrs menvcfg, t0 # set menvcfg.ADUE - li a0, 1 + li a0, 1 ecall # switch back to supervisor mode li t0, 0x0000000080E00000 jalr ra, t0 # jump to page without accessed bit yet set li a0, 3 ecall # switch to machine mode li t0, 1 - slli t0, t0, 61 + slli t0, t0, 61 csrc menvcfg, t0 # clear menvcfg.ADUE - li a0, 1 + li a0, 1 ecall # switch back to supervisor mode # exercise malformed PBMT pages @@ -147,9 +147,9 @@ ConcurrentICacheMissDTLBMiss: # jump to address for TLB miss to trigger HPTW to make access with DisableTranslation = 1, Translate = 0 li t0, 0x80805000 - jalr ra, t0 + jalr ra, t0 li t0, 0x80807000 # again, triggering setting access bit - jalr ra, t0 + jalr ra, t0 # atomic access to uncachable memory #li t0, 0x80806000 @@ -168,7 +168,7 @@ ConcurrentICacheMissDTLBMiss: jalr ra, t0 # jump to page to exercise ITLB with PBMT !=0 when ENVCFG_PMTE=0 # Load and AMO operation on page table entry that causes access fault - li t0, 0x81000000 + li t0, 0x81000000 lw t1, 0(t0) sfence.vma amoadd.w t0, t0, 0(t0) @@ -190,7 +190,7 @@ ConcurrentICacheMissDTLBMiss: lw t1, 0(t0) # AMO operation on page table entry that causes page fault due to malformed PBMT - li t0, 0x81200000 + li t0, 0x81200000 jalr t0 # Attempt to fetch instruction from address causing faulty page walk lw t1, 0(t0) sfence.vma @@ -198,10 +198,10 @@ ConcurrentICacheMissDTLBMiss: # point top-level page table to an illegal address and verify it faults li t0, 0x9000000000070000 # trap handler at non-existing memory location - csrw satp, t0 # should cause trap + csrw satp, t0 # should cause trap sfence.vma nop - + # change back to default trap handler after checking everything that might cause an instruction page fault jal changetodefaulthandler @@ -263,7 +263,7 @@ ConcurrentICacheMissDTLBMiss: ecall - + # wrap up li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry @@ -274,7 +274,7 @@ backandforth: ret changetoipfhandler: - li a0, 3 + li a0, 3 ecall # switch to machine mode la a0, ipf_handler csrw mtvec, a0 # point to new handler @@ -283,7 +283,7 @@ changetoipfhandler: ret changetodefaulthandler: - li a0, 3 + li a0, 3 ecall # switch to machine mode la a0, trap_handler csrw mtvec, a0 # point to new handler @@ -301,8 +301,8 @@ ipf_handler: csrrw tp, mscratch, tp # swap MSCRATCH and tp sd t0, 0(tp) # Save t0 and t1 on the stack sd t1, -8(tp) - li t5, 0x9000000000080010 - csrw satp, t5 # make sure we are pointing to the root page table + li t5, 0x9000000000080010 + csrw satp, t5 # make sure we are pointing to the root page table csrr t0, mcause # Check the cause li t1, 8 # is it an ecall trap? andi t0, t0, 0xFC # if CAUSE = 8, 9, or 11 @@ -329,7 +329,7 @@ fixsatptraphandler: .align 16 # root Page table situated at 0x80010000 -pagetable: +pagetable: .8byte 0x200044C1 # VA 0x00000000-0x7F_FFFFFFFF: PTE at 0x80011000 C1 dirty, accessed, valid .8byte 0x00000000000010CF # misaligned terapage at 0x80_00000000 .8byte 0x00000000000000CF # access fault terapage at 0x100_00000000 @@ -345,9 +345,9 @@ pagetable: .8byte 0x0 .8byte 0x0 .8byte 0x0 -SpecialPage: +SpecialPage: .8byte 0x00000000200000CF # 0x2_0000_0000 1GiB page1 - + # Next page table at 0x80012000 for gigapage at 0x80000000 .align 12 @@ -429,7 +429,7 @@ SpecialPage: .8byte 0x80000000200060CF .8byte 0x80000000200060CF .8byte 0x80000000200060CF - + .8byte 0x800000002000A0CF .8byte 0x800000002000A0CF .8byte 0x800000002000A0CF @@ -475,4 +475,3 @@ SpecialPage: .8byte 0x00000000200000CF # valid rwx for VA 80805000 for covering ITLB translate .8byte 0x20000000200000CF # PBMT=1 for VA 80806000 for covering ITLB BadPBMT .8byte 0x000000002000000F # valid rwx for VA 80807000 for covering UpdateDA - diff --git a/tests/coverage/vm64check.S b/tests/coverage/vm64check.S index 2e03a4e1a..0cc16ef8d 100644 --- a/tests/coverage/vm64check.S +++ b/tests/coverage/vm64check.S @@ -7,27 +7,27 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw -// +// // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You // may obtain a copy of the License at // // https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// // Cover IMMU vm64check block by jumping to illegal virtual addresses // Need a nonstandard trap handler to deal with returns from theses jumps // assign eq_46_38 = &(VAdr[46:38]) | ~|(VAdr[46:38]); - // assign eq_63_47 = &(VAdr[63:47]) | ~|(VAdr[63:47]); + // assign eq_63_47 = &(VAdr[63:47]) | ~|(VAdr[63:47]); // assign UpperBitsUnequal = SV39Mode ? ~(eq_63_47 & eq_46_38) : ~eq_63_47; .section .text.init @@ -41,9 +41,9 @@ rvtest_entry_point: csrw mtvec, t0 # Initialize MTVEC to trap_handler # set up PMP so user and supervisor mode can access full address space csrw pmpcfg0, 0xF # configure PMP0 to TOR RWX - li t0, 0xFFFFFFFF + li t0, 0xFFFFFFFF csrw pmpaddr0, t0 # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses - + # SATP in non-39 mode csrw satp, zero @@ -118,8 +118,8 @@ self_loop: trap_handler: csrw mepc, ra # return to address in ra mret - -.section .tohost + +.section .tohost tohost: # write to HTIF .dword 0 fromhost: @@ -146,7 +146,7 @@ topofstack: lw t1, 0(t0) li t1, 0x0000010080000000 lw t1, 0(t0) - li t0, 0x8000000000000000 + li t0, 0x8000000000000000 csrw satp, t0 # SV39 mode li t0, 0x0000000080000000 lw t1, 0(t0) @@ -158,7 +158,7 @@ topofstack: lw t1, 0(t0) li t1, 0x0000010080000000 lw t1, 0(t0) - li t0, 0x9000000000000000 + li t0, 0x9000000000000000 csrw satp, t0 # SV48 mode li t0, 0x0000000080000000 lw t1, 0(t0) @@ -170,5 +170,5 @@ topofstack: lw t1, 0(t0) li t1, 0x0000010080000000 lw t1, 0(t0) - li t0, 0x0000000000000000 - csrw satp, t0 # disable virtual memory \ No newline at end of file + li t0, 0x0000000000000000 + csrw satp, t0 # disable virtual memory