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In the wt_dcache_missunit.sv, there is a module exp_backoff.sv instantiated in it. Above this module there is a comment stating "back-off mechanism for LR/SC completion guarantee".
Regrading this I have following questions:
Why do we need a hardware mechanism for LR/SC? I mean we can identify the failure in the software in case of LR/SC (if the operation is successful it'll return 0, otherwise not).
Is this some kind of a retry mechanism? If so how does it work?
How effective is this with respect to software?
The text was updated successfully, but these errors were encountered:
Hi,
In the wt_dcache_missunit.sv, there is a module exp_backoff.sv instantiated in it. Above this module there is a comment stating "back-off mechanism for LR/SC completion guarantee".
Regrading this I have following questions:
Why do we need a hardware mechanism for LR/SC? I mean we can identify the failure in the software in case of LR/SC (if the operation is successful it'll return 0, otherwise not).
Is this some kind of a retry mechanism? If so how does it work?
How effective is this with respect to software?
The text was updated successfully, but these errors were encountered: