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[BUG] : Aligned CVA6 Design with CSR embedded Doc #1739

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AyoubJalali opened this issue Dec 29, 2023 · 1 comment
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[BUG] : Aligned CVA6 Design with CSR embedded Doc #1739

AyoubJalali opened this issue Dec 29, 2023 · 1 comment
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@zchamski
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CV32A65X Part: Embedded configuration PARAM:CSR CSR Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system

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@AyoubJalali
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Is there an existing CVA6 bug for this?

  • I have searched the existing bug issues

Bug Description

In the CSR embedded doc list, there is a list of the supported CSR in the embedded application of the CVA6, the problem here that the CVA6 still have some of the unsupported CSR in the Design and it can compute read/write operation like MCOUNTINHIBIT should we aligned the design with the doc ?
@AyoubJalali AyoubJalali added the Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system label Dec 29, 2023
Gchauvon pushed a commit to Gchauvon/cva6 that referenced this issue Jan 24, 2024
@MikeOpenHWGroup
Merge pull request openhwgroup#1739 from cathales/remove-bad-file
1c4b3e7 
remove empty cva6/sim/uart
@JeanRochCoulon JeanRochCoulon added the CV32A65X Part: Embedded configuration label Jan 2, 2025
@JeanRochCoulon
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This register is well described in RISC-V specification:

Image

But this register is not described in the CSR chapter of design documentation, this is due to a riscv-config generation issue. #2738 superseeds this issue. #2738 will fix this issue.

@JeanRochCoulon JeanRochCoulon mentioned this issue Jan 24, 2025
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CV32A65X Part: Embedded configuration PARAM:CSR CSR Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system
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@JeanRochCoulon @zchamski @AyoubJalali