diff --git a/docs/01_cva6_user/CSR_CV32A60AX.rst b/docs/01_cva6_user/CSR_CV32A60AX.rst new file mode 100644 index 0000000000..259ade0ffd --- /dev/null +++ b/docs/01_cva6_user/CSR_CV32A60AX.rst @@ -0,0 +1,25 @@ +.. + Copyright (c) 2023 OpenHW Group + Copyright (c) 2023 Thales DIS design services SAS + + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +.. Level 1 + ======= + + Level 2 + ------- + + Level 3 + ~~~~~~~ + + Level 4 + ^^^^^^^ + +.. _CSR_CV32A60AX: + + +CV32A60AX Control Status Registers +================================== + +*This chapter is not yet available.* diff --git a/docs/01_cva6_user/CSR_CV32A60AX_list.rst b/docs/01_cva6_user/CSR_CV32A60AX_list.rst new file mode 100644 index 0000000000..3c42ef14c7 --- /dev/null +++ b/docs/01_cva6_user/CSR_CV32A60AX_list.rst @@ -0,0 +1,25 @@ +.. + Copyright (c) 2023 OpenHW Group + Copyright (c) 2023 Thales DIS design services SAS + + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +.. Level 1 + ======= + + Level 2 + ------- + + Level 3 + ~~~~~~~ + + Level 4 + ^^^^^^^ + +.. _CSR_CV32A60AX_list: + + +CV32A60AX Control Status Registers List +======================================= + +*This chapter is not yet available.* diff --git a/docs/01_cva6_user/CSR_CV32A60X.rst b/docs/01_cva6_user/CSR_CV32A60X.rst new file mode 100644 index 0000000000..c24ac207b7 --- /dev/null +++ b/docs/01_cva6_user/CSR_CV32A60X.rst @@ -0,0 +1 @@ +.. include:: ../csr-from-ip-xact/cv32a60x/csr.rst \ No newline at end of file diff --git a/docs/01_cva6_user/CSR_CV32A60X_list.rst b/docs/01_cva6_user/CSR_CV32A60X_list.rst new file mode 100644 index 0000000000..0d260dfa47 --- /dev/null +++ b/docs/01_cva6_user/CSR_CV32A60X_list.rst @@ -0,0 +1 @@ +.. include:: ../csr-from-ip-xact/cv32a60x/csr_list.rst \ No newline at end of file diff --git a/docs/01_cva6_user/Programmer_View.rst b/docs/01_cva6_user/Programmer_View.rst index b601ade72b..461e5b0c12 100644 --- a/docs/01_cva6_user/Programmer_View.rst +++ b/docs/01_cva6_user/Programmer_View.rst @@ -60,7 +60,7 @@ Notes: *The following tables detail the availability of extensions for the various CVA6 configurations:* CV32A60AX extensions -~~~~~~~~~~~~~~~~~~~ +~~~~~~~~~~~~~~~~~~~~ These extensions are available in CV32A60AX: @@ -128,7 +128,7 @@ Note: The addition of the H Extension is in the process. After that, HS, VS, and *The following tables detail the availability of privileges modes for the various CVA6 configurations:* CV32A60AX privilege modes -~~~~~~~~~~~~~~~~~~~~~~~~ +~~~~~~~~~~~~~~~~~~~~~~~~~ These privilege modes are available in CV32A60AX: @@ -181,7 +181,7 @@ Notes for the integrator: *These are the addressing modes supported by the various CVA6 configurations:* CV32A60AX virtual memory -~~~~~~~~~~~~~~~~~~~~~~~ +~~~~~~~~~~~~~~~~~~~~~~~~ CV32A60AX integrates an MMU and supports both the **Bare** and **Sv32** addressing modes. diff --git a/docs/01_cva6_user/RISCV_Instructions.rst b/docs/01_cva6_user/RISCV_Instructions.rst index 0398c0ae1e..414f883ba7 100644 --- a/docs/01_cva6_user/RISCV_Instructions.rst +++ b/docs/01_cva6_user/RISCV_Instructions.rst @@ -162,7 +162,7 @@ The notations below are used in the description of instructions. - **>>u**: Right shift of 2 unsigned values. -- **M[address]**: Value existe in the address of the memory. +- **M[address]**: Value exists in the address of the memory. - **/s**: Division of 2 signed values. diff --git a/docs/01_cva6_user/RISCV_Instructions_RVZbs.rst b/docs/01_cva6_user/RISCV_Instructions_RVZbs.rst index 06cf980356..85341b2a19 100644 --- a/docs/01_cva6_user/RISCV_Instructions_RVZbs.rst +++ b/docs/01_cva6_user/RISCV_Instructions_RVZbs.rst @@ -29,9 +29,9 @@ "CV32A60X", "Implemented extension" -============================ +============================== RVZbs: Single-bit instructions -============================ +============================== The single-bit instructions provide a mechanism to set, clear, invert, or extract a single bit in a register. The bit is specified by its index. The following instructions (and pseudoinstructions) comprise the Zbs extension: diff --git a/docs/01_cva6_user/index.rst b/docs/01_cva6_user/index.rst index df4f0514da..255fa8544b 100644 --- a/docs/01_cva6_user/index.rst +++ b/docs/01_cva6_user/index.rst @@ -18,7 +18,6 @@ CVA6 User Manual ================ -Editor: **Jerome Quevremont** .. toctree:: :maxdepth: 2 @@ -33,24 +32,30 @@ Editor: **Jerome Quevremont** Traps_Interrupts_Exceptions Compiler_Command_Lines RISCV_Instructions - RISCV_Instructions_RV32I - RISCV_Instructions_RV32M - RISCV_Instructions_RV32A - RISCV_Instructions_RV32C - RISCV_Instructions_RVZba - RISCV_Instructions_RVZbb - RISCV_Instructions_RVZbc - RISCV_Instructions_RVZbs - RISCV_Instructions_RV32ZCb - RISCV_Instructions_RVZicsr - RISCV_Instructions_RVZifencei - RISCV_Instructions_RVZicond - CV32A6_Control_Status_Registers - CV64A6_Control_Status_Registers + RV32I + RV32M + RV32A + RV32C + RV32Zcb + RVZba + RVZbb + RVZbc + RVZbs + RVZicsr + RVZifencei + RVZicond + CV32A60X CSR List + CV32A60X CSR Details + CV32A60AX CSR List + CV32A60AX CSR Details + CV64A6 CSR CSR_Cache_Control - CSR_Performance_Counters + CSR Performance Counters Parameters_Configuration Interfaces + AXI Bus Interface + CV-X-IF Interface Core_Integration - CVX_Interface_Coprocessor - AXI_Interface + + +