diff --git a/core/alu.sv b/core/alu.sv index 3ff3c1a4c3..040c2ded24 100644 --- a/core/alu.sv +++ b/core/alu.sv @@ -275,11 +275,11 @@ module alu import ariane_pkg::*; #( BSET, BSETI: result_o = fu_data_i.operand_a | bit_indx; // Count Leading/Trailing Zeros - CLZ, CTZ : result_o = (lz_tz_empty) ? (lz_tz_count + 1) : lz_tz_count; + CLZ, CTZ : result_o = (lz_tz_empty) ? ({{riscv::XLEN-$clog2(riscv::XLEN){1'b0}}, lz_tz_count} + 1) : {{riscv::XLEN-$clog2(riscv::XLEN){1'b0}}, lz_tz_count}; CLZW, CTZW: result_o = (lz_tz_wempty) ? 32 : {{riscv::XLEN-5{1'b0}}, lz_tz_wcount}; // Count population - CPOP, CPOPW: result_o = {{(riscv::XLEN-($clog2(riscv::XLEN))){1'b0}}, cpop}; + CPOP, CPOPW: result_o = {{(riscv::XLEN-($clog2(riscv::XLEN)+1)){1'b0}}, cpop}; // Sign and Zero Extend SEXTB: result_o = {{riscv::XLEN-8{fu_data_i.operand_a[7]}}, fu_data_i.operand_a[7:0]}; diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index fdb14984a6..9c4f6ade84 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -151,7 +151,7 @@ module csr_regfile import ariane_pkg::*; #( riscv::pmpcfg_t [15:0] pmpcfg_q, pmpcfg_d; logic [15:0][riscv::PLEN-3:0] pmpaddr_q, pmpaddr_d; logic [MHPMCounterNum+3-1:0] mcountinhibit_d,mcountinhibit_q; - int index; + logic [3:0] index; localparam riscv::xlen_t IsaCode = (riscv::XLEN'(CVA6Cfg.RVA) << 0) // A - Atomic Instructions extension | (riscv::XLEN'(CVA6Cfg.RVC) << 2) // C - Compressed extension @@ -270,7 +270,7 @@ module csr_regfile import ariane_pkg::*; #( riscv::CSR_MIMPID: csr_rdata = '0; // not implemented riscv::CSR_MHARTID: csr_rdata = hart_id_i; riscv::CSR_MCONFIGPTR: csr_rdata = '0; // not implemented - riscv::CSR_MCOUNTINHIBIT: csr_rdata = mcountinhibit_q; + riscv::CSR_MCOUNTINHIBIT: csr_rdata = {{(riscv::XLEN-(MHPMCounterNum+3)){1'b0}}, mcountinhibit_q}; // Counters and Timers riscv::CSR_MCYCLE: csr_rdata = cycle_q[riscv::XLEN-1:0]; riscv::CSR_MCYCLEH: if (riscv::XLEN == 32) csr_rdata = cycle_q[63:32]; else read_access_exception = 1'b1; @@ -691,7 +691,7 @@ module csr_regfile import ariane_pkg::*; #( if (!CVA6Cfg.RVV) begin mstatus_d.vs = riscv::Off; end - mstatus_d.wpri3 = 8'b0; + mstatus_d.wpri3 = 9'b0; mstatus_d.wpri1 = 1'b0; mstatus_d.wpri2 = 1'b0; mstatus_d.wpri0 = 1'b0; @@ -883,7 +883,7 @@ module csr_regfile import ariane_pkg::*; #( riscv::CSR_PMPADDR14, riscv::CSR_PMPADDR15: begin // index is specified by the last byte in the address - automatic int index = csr_addr.csr_decode.address[3:0]; + automatic logic [3:0] index = csr_addr.csr_decode.address[3:0]; // check if the entry or the entry above is locked if (!pmpcfg_q[index].locked && !(pmpcfg_q[index+1].locked && pmpcfg_q[index].addr_mode == riscv::TOR)) begin pmpaddr_d[index] = csr_wdata[riscv::PLEN-3:0]; @@ -1221,7 +1221,9 @@ module csr_regfile import ariane_pkg::*; #( // ---------------------- always_comb begin : exception_ctrl csr_exception_o = { - '0, '0, 1'b0 + {riscv::XLEN{1'b0}}, + {riscv::XLEN{1'b0}}, + 1'b0 }; // ---------------------------------- // Illegal Access (decode exception) @@ -1303,11 +1305,11 @@ module csr_regfile import ariane_pkg::*; #( csr_rdata_o = csr_rdata; unique case (csr_addr.address) - riscv::CSR_MIP: csr_rdata_o = csr_rdata | (irq_i[1] << riscv::IRQ_S_EXT); + riscv::CSR_MIP: csr_rdata_o = csr_rdata | ({{riscv::XLEN-1{1'b0}}, irq_i[1]} << riscv::IRQ_S_EXT); // in supervisor mode we also need to check whether we delegated this bit riscv::CSR_SIP: begin csr_rdata_o = csr_rdata - | ((irq_i[1] & mideleg_q[riscv::IRQ_S_EXT]) << riscv::IRQ_S_EXT); + | ({{riscv::XLEN-1{1'b0}}, (irq_i[1] & mideleg_q[riscv::IRQ_S_EXT])} << riscv::IRQ_S_EXT); end default:; endcase @@ -1388,8 +1390,8 @@ module csr_regfile import ariane_pkg::*; #( stval_q <= {riscv::XLEN{1'b0}}; satp_q <= {riscv::XLEN{1'b0}}; // timer and counters - cycle_q <= {riscv::XLEN{1'b0}}; - instret_q <= {riscv::XLEN{1'b0}}; + cycle_q <= 64'b0; + instret_q <= 64'b0; // aux registers en_ld_st_translation_q <= 1'b0; // wait for interrupt diff --git a/core/cvxif_fu.sv b/core/cvxif_fu.sv index 7896c0576d..53eda687d7 100644 --- a/core/cvxif_fu.sv +++ b/core/cvxif_fu.sv @@ -69,7 +69,7 @@ module cvxif_fu import ariane_pkg::*; #( x_valid_o = cvxif_resp_i.x_result_valid; //Read result only when CVXIF is enabled x_trans_id_o = x_valid_o ? cvxif_resp_i.x_result.id : '0; x_result_o = x_valid_o ? cvxif_resp_i.x_result.data : '0; - x_exception_o.cause = x_valid_o ? cvxif_resp_i.x_result.exccode : '0; + x_exception_o.cause = x_valid_o ? {{(riscv::XLEN-6){1'b0}}, cvxif_resp_i.x_result.exccode} : '0; x_exception_o.valid = x_valid_o ? cvxif_resp_i.x_result.exc : '0; x_exception_o.tval = '0; x_we_o = x_valid_o ? cvxif_resp_i.x_result.we : '0; diff --git a/core/frontend/instr_queue.sv b/core/frontend/instr_queue.sv index ae86e94068..ab7742c3d5 100644 --- a/core/frontend/instr_queue.sv +++ b/core/frontend/instr_queue.sv @@ -279,7 +279,7 @@ module instr_queue import ariane_pkg::*; #( end fetch_entry_o.instruction = instr_data_out[i].instr; fetch_entry_o.ex.valid = instr_data_out[i].ex != ariane_pkg::FE_NONE; - fetch_entry_o.ex.tval = {{64-riscv::VLEN{1'b0}}, instr_data_out[i].ex_vaddr}; + fetch_entry_o.ex.tval = {{(riscv::XLEN-riscv::VLEN){1'b0}}, instr_data_out[i].ex_vaddr}; fetch_entry_o.branch_predict.cf = instr_data_out[i].cf; pop_instr[i] = fetch_entry_valid_o & fetch_entry_ready_i; end diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index 8a3af5a8b1..f0c434f76b 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -38,7 +38,7 @@ package ariane_pkg; localparam ISSUE_WIDTH = 1; // depth of store-buffers, this needs to be a power of two - localparam int unsigned DEPTH_SPEC = 4; + localparam logic [2:0] DEPTH_SPEC = 'd4; localparam int unsigned DCACHE_TYPE = int'(cva6_config_pkg::CVA6ConfigDcacheType); // if DCACHE_TYPE = cva6_config_pkg::WT @@ -47,7 +47,7 @@ package ariane_pkg; // to longer paths into the commit stage // if DCACHE_TYPE = cva6_config_pkg::WB // allocate more space for the commit buffer to be on the save side, this needs to be a power of two - localparam int unsigned DEPTH_COMMIT = (DCACHE_TYPE == int'(cva6_config_pkg::WT)) ? 4 : 8; + localparam logic [2:0] DEPTH_COMMIT = 'd4; localparam bit FPGA_EN = cva6_config_pkg::CVA6ConfigFPGAEn; // Is FPGA optimization of CV32A6 diff --git a/core/issue_read_operands.sv b/core/issue_read_operands.sv index 7d4ccb6cbf..8591417148 100644 --- a/core/issue_read_operands.sv +++ b/core/issue_read_operands.sv @@ -150,6 +150,7 @@ module issue_read_operands import ariane_pkg::*; #( if(CVA6Cfg.FpPresent) begin fu_busy = ~fpu_ready_i; end + else fu_busy = 1'b0; LOAD, STORE: fu_busy = ~lsu_ready_i; CVXIF: diff --git a/core/mmu_sv32/cva6_mmu_sv32.sv b/core/mmu_sv32/cva6_mmu_sv32.sv index 47c84bde50..f7442ccdd1 100644 --- a/core/mmu_sv32/cva6_mmu_sv32.sv +++ b/core/mmu_sv32/cva6_mmu_sv32.sv @@ -388,7 +388,7 @@ module cva6_mmu_sv32 import ariane_pkg::*; #( lsu_dtlb_ppn_o = {{riscv::PLEN-riscv::VLEN{1'b0}},lsu_vaddr_n[riscv::VLEN-1:12]}; end else begin lsu_paddr_o = lsu_vaddr_q[riscv::PLEN-1:0]; - lsu_dtlb_ppn_o = lsu_vaddr_n[riscv::VLEN-1:12]; + lsu_dtlb_ppn_o = lsu_vaddr_n[riscv::PPNW-1:0]; end lsu_valid_o = lsu_req_q; lsu_exception_o = misaligned_ex_q; diff --git a/core/multiplier.sv b/core/multiplier.sv index 57f2ab5efe..8389cb7fb7 100644 --- a/core/multiplier.sv +++ b/core/multiplier.sv @@ -53,7 +53,7 @@ module multiplier import ariane_pkg::*; #( always_comb begin clmul_d = '0; for (int i = 0; i <= riscv::XLEN; i++) begin - clmul_d = ((operand_b >> i) & 1) ? clmul_d ^ (operand_a << i) : clmul_d; + clmul_d = (|((operand_b >> i) & 1)) ? clmul_d ^ (operand_a << i) : clmul_d; end end diff --git a/core/serdiv.sv b/core/serdiv.sv index 73704d9448..45404fa52e 100644 --- a/core/serdiv.sv +++ b/core/serdiv.sv @@ -107,8 +107,8 @@ module serdiv import ariane_pkg::*; #( .empty_o ( lzc_b_no_one ) ); - assign shift_a = (lzc_a_no_one) ? WIDTH : lzc_a_result; - assign div_shift = lzc_b_result - shift_a; + assign shift_a = (lzc_a_no_one) ? WIDTH : {1'b0, lzc_a_result}; + assign div_shift = {1'b0, lzc_b_result} - shift_a; assign op_b = op_b_i <<< $unsigned(div_shift);