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119 workflow run results
119 workflow run results

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Clarify pmpcfgX on illegal write combination (fixes #1694) Verible #69: Pull request #1711 opened by zarubaf
December 14, 2023 13:49 50s
December 14, 2023 13:49 50s
csr: Implement menvcfg Verible #68: Pull request #1653 synchronize by zarubaf
December 14, 2023 13:43 50s
December 14, 2023 13:43 50s
Draft: User config Verible #67: Pull request #1704 synchronize by cathales
December 14, 2023 13:39 55s
December 14, 2023 13:39 55s
ci: report embedded CoreMark/MHz score Verible #66: Pull request #1710 opened by cathales
December 14, 2023 11:38 46s
December 14, 2023 11:38 46s
refactor(decoder): simplify interrupt indexing Verible #65: Pull request #1709 opened by cathales
December 14, 2023 11:05 58s
December 14, 2023 11:05 58s
Mmu unify task 1 - sv32 and sv39 Verible #64: Pull request #1707 opened by AngelaGonzalezMarino
December 13, 2023 15:38 1m 3s
December 13, 2023 15:38 1m 3s
Added CSR covegroups for read and write operations, hvp updated accordantly Verible #63: Pull request #1706 opened by AnouarZajni
December 13, 2023 14:05 55s
December 13, 2023 14:05 55s
[Skip CI] Change CV32E6?X to CV32E-X to ease file management Verible #62: Pull request #1705 opened by jquevremont
December 13, 2023 09:55 57s
December 13, 2023 09:55 57s
Updated user manual to address several configuration (second pass) Verible #61: Pull request #1696 synchronize by JeanRochCoulon
December 13, 2023 09:10 1m 3s
December 13, 2023 09:10 1m 3s
Draft: User config Verible #60: Pull request #1704 opened by cathales
December 13, 2023 09:02 58s
December 13, 2023 09:02 58s
Code coverage: condition RTL With parameters Verible #59: Pull request #1703 synchronize by JeanRochCoulon
December 13, 2023 06:01 54s
December 13, 2023 06:01 54s
Code coverage: condition RTL With parameters Verible #58: Pull request #1703 synchronize by JeanRochCoulon
December 13, 2023 06:00 50s
December 13, 2023 06:00 50s
Code coverage: condition RTL With parameters Verible #57: Pull request #1703 synchronize by JeanRochCoulon
December 12, 2023 18:05 1m 13s
December 12, 2023 18:05 1m 13s
Code coverage: condition RTL With parameters Verible #56: Pull request #1703 opened by AEzzejjari
December 12, 2023 18:02 59s
December 12, 2023 18:02 59s
Update embedded config to improve trade-off performance gate count Verible #55: Pull request #1701 synchronize by JeanRochCoulon
December 12, 2023 16:55 54s
December 12, 2023 16:55 54s
Verilator Tandem Support Verible #54: Pull request #1702 opened by MarioOpenHWGroup
December 12, 2023 16:55 59s
December 12, 2023 16:55 59s
Update embedded config to improve trade-off performance gate count Verible #53: Pull request #1701 synchronize by JeanRochCoulon
December 12, 2023 16:07 1m 25s
December 12, 2023 16:07 1m 25s
Update embedded config to improve trade-off performance gate count Verible #52: Pull request #1701 opened by JeanRochCoulon
December 12, 2023 15:48 56s
December 12, 2023 15:48 56s
Updated user manual to address several configuration (first pass) Verible #51: Pull request #1685 synchronize by jquevremont
December 12, 2023 14:16 52s
December 12, 2023 14:16 52s
Update Verilator to v5.018 Verible #50: Pull request #1699 opened by MarioOpenHWGroup
December 12, 2023 08:47 46s
December 12, 2023 08:47 46s
Bump verif/core-v-verif from 6779193 to 76b887f Verible #49: Pull request #1698 opened by dependabot bot
December 11, 2023 18:33 1m 2s
December 11, 2023 18:33 1m 2s
CV32A60X-specific CSR DVplan Verible #48: Pull request #1697 opened by MikeOpenHWGroup
December 11, 2023 15:57 55s
December 11, 2023 15:57 55s
Updated user manual to address several configuration (second pass) Verible #47: Pull request #1696 opened by jquevremont
December 11, 2023 15:53 48s
December 11, 2023 15:53 48s
Set StallRandom I/O to 0 to gain performance on vcs-testharness bench Verible #46: Pull request #1695 opened by Gchauvon
December 11, 2023 15:09 53s
December 11, 2023 15:09 53s
Fix branch misalignement condition Verible #45: Pull request #1690 synchronize by JeanRochCoulon
December 10, 2023 20:54 1m 5s
December 10, 2023 20:54 1m 5s