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[XIF] Interrupts cleared too late #507
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This issue is similar to #325. A fix can maybe be done by blanking interrupts the cycle after receiving a load/store rvalid. The non-blanked interrupt presence should still lead to stop issuing new instructions in ID (otherwise blanking can be continued for a long series of loads/stores) |
Both CLIC and Basic should be studied and ideally same fix should be applied for both if needed |
Blanking interrupts for one cycle after a load or store has left WB. Refactored some assertions for CLIC, added a separate file for CLIC asserts. Signed-off-by: Oystein Knauserud <[email protected]>
This issue should have been fixed with PR #655. The XIF was not taken into account, so this issue needs to be revisited once the XIF is properly implemented. The existing assertions will likely fail when X_EXT is set to 1. |
Renamed with XIF prefix |
If an interrupt is cleared via a (non-bufferable) store, then the interrupt on irq_i will go low in the cycle after the store instruction left the WB stage. As the irq_i lines are registered inside the core, a following instruction can still get to see the interrupt that was supposed to be cleared.
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