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RTL code coverage hole in CV32E40P lzc #1022

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YoannPruvost opened this issue Jul 10, 2024 · 1 comment
Open

RTL code coverage hole in CV32E40P lzc #1022

YoannPruvost opened this issue Jul 10, 2024 · 1 comment
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Component:RTL For issues in the RTL (e.g. for files in the rtl directory) WAIVED:CV32E40P Issue does not impact a major release of CV32E40P and is waived

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@YoannPruvost
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YoannPruvost commented Jul 10, 2024

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Component:RTL

Issue Description

The interconnect between the core and the FPU has been designed to handle multiple cores to multiple FPU connections. As the verification has been done with a one-core setup, the LZC used to arbitrate between different core is under-utilized and some part of the code is unreachable in this setup.

As it was too late to implement a different solution in RTL due to long RISC-V ISA Formal Verification runs and requiring to update all waivers files as well, it has been decided to waive those holes in v2.

@YoannPruvost YoannPruvost added Component:RTL For issues in the RTL (e.g. for files in the rtl directory) WAIVED:CV32E40P Issue does not impact a major release of CV32E40P and is waived labels Jul 10, 2024
@MikeOpenHWGroup
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Hi @YoannPruvost, can you provide some addition insight into this code coverage hole?

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Labels
Component:RTL For issues in the RTL (e.g. for files in the rtl directory) WAIVED:CV32E40P Issue does not impact a major release of CV32E40P and is waived
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