diff --git a/clang/include/clang/Basic/BuiltinsRISCVCOREV.def b/clang/include/clang/Basic/BuiltinsRISCVCOREV.def index 7d79ae426e69..f5da1d378e42 100644 --- a/clang/include/clang/Basic/BuiltinsRISCVCOREV.def +++ b/clang/include/clang/Basic/BuiltinsRISCVCOREV.def @@ -177,6 +177,25 @@ TARGET_BUILTIN(bitmanip_cnt, "UZiUZi", "nc", "xcvbitmanip") TARGET_BUILTIN(bitmanip_ror, "UZiUZiUZi", "nc", "xcvbitmanip") TARGET_BUILTIN(bitmanip_bitrev, "UZiUZiIUcIUc", "nc", "xcvbitmanip") +TARGET_BUILTIN(mac_mac, "UZiUZiUZiUZi", "nc", "xcvmac") +TARGET_BUILTIN(mac_msu, "UZiUZiUZiUZi", "nc", "xcvmac") +TARGET_BUILTIN(mac_muluN, "UZiUZiUZiUc", "nc", "xcvmac") +TARGET_BUILTIN(mac_mulhhuN, "UZiUZiUZiUc", "nc", "xcvmac") +TARGET_BUILTIN(mac_mulsN, "SZiUZiUZiUc", "nc", "xcvmac") +TARGET_BUILTIN(mac_mulhhsN, "SZiUZiUZiUc", "nc", "xcvmac") +TARGET_BUILTIN(mac_muluRN, "UZiUZiUZiUc", "nc", "xcvmac") +TARGET_BUILTIN(mac_mulhhuRN, "UZiUZiUZiUc", "nc", "xcvmac") +TARGET_BUILTIN(mac_mulsRN, "SZiUZiUZiUc", "nc", "xcvmac") +TARGET_BUILTIN(mac_mulhhsRN, "SZiUZiUZiUc", "nc", "xcvmac") +TARGET_BUILTIN(mac_macuN, "UZiUZiUZiUZiUc", "nc", "xcvmac") +TARGET_BUILTIN(mac_machhuN, "UZiUZiUZiUZiUc", "nc", "xcvmac") +TARGET_BUILTIN(mac_macsN, "SZiUZiUZiSZiUc", "nc", "xcvmac") +TARGET_BUILTIN(mac_machhsN, "SZiUZiUZiSZiUc", "nc", "xcvmac") +TARGET_BUILTIN(mac_macuRN, "UZiUZiUZiSZiUc", "nc", "xcvmac") +TARGET_BUILTIN(mac_machhuRN, "UZiUZiUZiUZiUc", "nc", "xcvmac") +TARGET_BUILTIN(mac_macsRN, "SZiUZiUZiSZiUc", "nc", "xcvmac") +TARGET_BUILTIN(mac_machhsRN, "SZiUZiUZiSZiUc", "nc", "xcvmac") + #undef BUILTIN #undef TARGET_BUILTIN #undef PSEUDO_BUILTIN diff --git a/clang/test/CodeGen/RISCV/corev-intrinsics/mac.c b/clang/test/CodeGen/RISCV/corev-intrinsics/mac.c new file mode 100644 index 000000000000..eae3b806629a --- /dev/null +++ b/clang/test/CodeGen/RISCV/corev-intrinsics/mac.c @@ -0,0 +1,309 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple riscv32 -target-feature +xcvmac -emit-llvm %s -o - \ +// RUN: | FileCheck %s + + +#include + + + +// CHECK-LABEL: @test_mac_mac( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[Z_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4 +// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: store i32 [[Z:%.*]], ptr [[Z_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[Z_ADDR]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.mac.mac(i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK-NEXT: ret i32 [[TMP3]] +// +int32_t test_mac_mac(int32_t x, int32_t y, int32_t z) { + return __builtin_riscv_cv_mac_mac(x, y, z); +} + +// CHECK-LABEL: @test_mac_msu( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[Z_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4 +// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: store i32 [[Z:%.*]], ptr [[Z_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[Z_ADDR]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.mac.msu(i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) +// CHECK-NEXT: ret i32 [[TMP3]] +// +int32_t test_mac_msu(int32_t x, int32_t y, int32_t z) { + return __builtin_riscv_cv_mac_msu(x, y, z); +} + +// CHECK-LABEL: @test_mac_muluN( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4 +// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.mac.muluN(i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK-NEXT: ret i32 [[TMP2]] +// +uint32_t test_mac_muluN(uint32_t x, uint32_t y) { + return __builtin_riscv_cv_mac_muluN(x, y, 0); +} + +// CHECK-LABEL: @test_mac_mulhhuN( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4 +// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.mac.mulhhuN(i32 [[TMP0]], i32 [[TMP1]], i32 0) +// CHECK-NEXT: ret i32 [[TMP2]] +// +uint32_t test_mac_mulhhuN(uint32_t x, uint32_t y) { + return __builtin_riscv_cv_mac_mulhhuN(x, y, 0); +} + +// CHECK-LABEL: @test_mac_mulsN( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4 +// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.mac.mulsN(i32 [[TMP0]], i32 [[TMP1]], i32 1) +// CHECK-NEXT: ret i32 [[TMP2]] +// +int32_t test_mac_mulsN(uint32_t x, uint32_t y) { + return __builtin_riscv_cv_mac_mulsN(x, y, 1); +} + +// CHECK-LABEL: @test_mac_mulhhsN( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4 +// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.mac.mulhhsN(i32 [[TMP0]], i32 [[TMP1]], i32 1) +// CHECK-NEXT: ret i32 [[TMP2]] +// +int32_t test_mac_mulhhsN(uint32_t x, uint32_t y) { + return __builtin_riscv_cv_mac_mulhhsN(x, y, 1); +} + +// CHECK-LABEL: @test_mac_muluRN( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4 +// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.mac.muluRN(i32 [[TMP0]], i32 [[TMP1]], i32 2) +// CHECK-NEXT: ret i32 [[TMP2]] +// +uint32_t test_mac_muluRN(uint32_t x, uint32_t y) { + return __builtin_riscv_cv_mac_muluRN(x, y, 2); +} + +// CHECK-LABEL: @test_mac_mulhhuRN( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4 +// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.mac.mulhhuRN(i32 [[TMP0]], i32 [[TMP1]], i32 2) +// CHECK-NEXT: ret i32 [[TMP2]] +// +uint32_t test_mac_mulhhuRN(uint32_t x, uint32_t y) { + return __builtin_riscv_cv_mac_mulhhuRN(x, y, 2); +} + +// CHECK-LABEL: @test_mac_mulsRN( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4 +// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.mac.mulsRN(i32 [[TMP0]], i32 [[TMP1]], i32 3) +// CHECK-NEXT: ret i32 [[TMP2]] +// +int32_t test_mac_mulsRN(uint32_t x, uint32_t y) { + return __builtin_riscv_cv_mac_mulsRN(x, y, 3); +} + +// CHECK-LABEL: @test_mac_mulhhsRN( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4 +// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.mac.mulhhsRN(i32 [[TMP0]], i32 [[TMP1]], i32 3) +// CHECK-NEXT: ret i32 [[TMP2]] +// +int32_t test_mac_mulhhsRN(uint32_t x, uint32_t y) { + return __builtin_riscv_cv_mac_mulhhsRN(x, y, 3); +} + +// 16-bit x 16-bit multiply-accumulate +// CHECK-LABEL: @test_mac_macuN( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[Z_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4 +// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: store i32 [[Z:%.*]], ptr [[Z_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[Z_ADDR]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.mac.macuN(i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]], i32 4) +// CHECK-NEXT: ret i32 [[TMP3]] +// +uint32_t test_mac_macuN(uint32_t x, uint32_t y, uint32_t z) { + return __builtin_riscv_cv_mac_macuN(x, y, z, 4); +} + +// CHECK-LABEL: @test_mac_machhuN( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[Z_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4 +// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: store i32 [[Z:%.*]], ptr [[Z_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[Z_ADDR]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.mac.machhuN(i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]], i32 4) +// CHECK-NEXT: ret i32 [[TMP3]] +// +uint32_t test_mac_machhuN(uint32_t x, uint32_t y, uint32_t z) { + return __builtin_riscv_cv_mac_machhuN(x, y, z, 4); +} + +// CHECK-LABEL: @test_mac_macsN( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[Z_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4 +// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: store i32 [[Z:%.*]], ptr [[Z_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[Z_ADDR]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.mac.macsN(i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]], i32 5) +// CHECK-NEXT: ret i32 [[TMP3]] +// +int32_t test_mac_macsN(uint32_t x, uint32_t y, int32_t z) { + return __builtin_riscv_cv_mac_macsN(x, y, z, 5); +} + +// CHECK-LABEL: @test_mac_machhsN( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[Z_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4 +// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: store i32 [[Z:%.*]], ptr [[Z_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[Z_ADDR]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.mac.machhsN(i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]], i32 5) +// CHECK-NEXT: ret i32 [[TMP3]] +// +int32_t test_mac_machhsN(uint32_t x, uint32_t y, int32_t z) { + return __builtin_riscv_cv_mac_machhsN(x, y, z, 5); +} + +// CHECK-LABEL: @test_mac_macuRN( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[Z_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4 +// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: store i32 [[Z:%.*]], ptr [[Z_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[Z_ADDR]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.mac.macuRN(i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]], i32 6) +// CHECK-NEXT: ret i32 [[TMP3]] +// +uint32_t test_mac_macuRN(uint32_t x, uint32_t y, uint32_t z) { + return __builtin_riscv_cv_mac_macuRN(x, y, z, 6); +} + +// CHECK-LABEL: @test_mac_machhuRN( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[Z_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4 +// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: store i32 [[Z:%.*]], ptr [[Z_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[Z_ADDR]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.mac.machhuRN(i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]], i32 6) +// CHECK-NEXT: ret i32 [[TMP3]] +// +uint32_t test_mac_machhuRN(uint32_t x, uint32_t y, uint32_t z) { + return __builtin_riscv_cv_mac_machhuRN(x, y, z, 6); +} + +// CHECK-LABEL: @test_mac_macsRN( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[Z_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4 +// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: store i32 [[Z:%.*]], ptr [[Z_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[Z_ADDR]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.mac.macsRN(i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]], i32 7) +// CHECK-NEXT: ret i32 [[TMP3]] +// +int32_t test_mac_macsRN(uint32_t x, uint32_t y, int32_t z) { + return __builtin_riscv_cv_mac_macsRN(x, y, z, 7); +} + +// CHECK-LABEL: @test_mac_machhsRN( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[Z_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4 +// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: store i32 [[Z:%.*]], ptr [[Z_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[Z_ADDR]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.mac.machhsRN(i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]], i32 7) +// CHECK-NEXT: ret i32 [[TMP3]] +// +int32_t test_mac_machhsRN(uint32_t x, uint32_t y, int32_t z) { + return __builtin_riscv_cv_mac_machhsRN(x, y, z, 7); +} diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td index caf5f1b67855..954c5f21ee63 100644 --- a/llvm/include/llvm/IR/IntrinsicsRISCV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td @@ -1751,23 +1751,23 @@ class ScalarCoreVMacGprGprGprImmIntrinsic def int_riscv_cv_mac_mac : ScalarCoreVMacGprGprGprIntrinsic; def int_riscv_cv_mac_msu : ScalarCoreVMacGprGprGprIntrinsic; -def int_riscv_cv_mac_mulun : ScalarCoreVMacGprGPRImmIntrinsic; -def int_riscv_cv_mac_mulhhun : ScalarCoreVMacGprGPRImmIntrinsic; -def int_riscv_cv_mac_mulsn : ScalarCoreVMacGprGPRImmIntrinsic; -def int_riscv_cv_mac_mulhhsn : ScalarCoreVMacGprGPRImmIntrinsic; -def int_riscv_cv_mac_mulurn : ScalarCoreVMacGprGPRImmIntrinsic; -def int_riscv_cv_mac_mulhhurn : ScalarCoreVMacGprGPRImmIntrinsic; -def int_riscv_cv_mac_mulsrn : ScalarCoreVMacGprGPRImmIntrinsic; -def int_riscv_cv_mac_mulhhsrn : ScalarCoreVMacGprGPRImmIntrinsic; - -def int_riscv_cv_mac_macun : ScalarCoreVMacGprGprGprImmIntrinsic; -def int_riscv_cv_mac_machhun : ScalarCoreVMacGprGprGprImmIntrinsic; -def int_riscv_cv_mac_macsn : ScalarCoreVMacGprGprGprImmIntrinsic; -def int_riscv_cv_mac_machhsn : ScalarCoreVMacGprGprGprImmIntrinsic; -def int_riscv_cv_mac_macurn : ScalarCoreVMacGprGprGprImmIntrinsic; -def int_riscv_cv_mac_machhurn : ScalarCoreVMacGprGprGprImmIntrinsic; -def int_riscv_cv_mac_macsrn : ScalarCoreVMacGprGprGprImmIntrinsic; -def int_riscv_cv_mac_machhsrn : ScalarCoreVMacGprGprGprImmIntrinsic; +def int_riscv_cv_mac_muluN : ScalarCoreVMacGprGPRImmIntrinsic; +def int_riscv_cv_mac_mulhhuN : ScalarCoreVMacGprGPRImmIntrinsic; +def int_riscv_cv_mac_mulsN : ScalarCoreVMacGprGPRImmIntrinsic; +def int_riscv_cv_mac_mulhhsN : ScalarCoreVMacGprGPRImmIntrinsic; +def int_riscv_cv_mac_muluRN : ScalarCoreVMacGprGPRImmIntrinsic; +def int_riscv_cv_mac_mulhhuRN : ScalarCoreVMacGprGPRImmIntrinsic; +def int_riscv_cv_mac_mulsRN : ScalarCoreVMacGprGPRImmIntrinsic; +def int_riscv_cv_mac_mulhhsRN : ScalarCoreVMacGprGPRImmIntrinsic; + +def int_riscv_cv_mac_macuN : ScalarCoreVMacGprGprGprImmIntrinsic; +def int_riscv_cv_mac_machhuN : ScalarCoreVMacGprGprGprImmIntrinsic; +def int_riscv_cv_mac_macsN : ScalarCoreVMacGprGprGprImmIntrinsic; +def int_riscv_cv_mac_machhsN : ScalarCoreVMacGprGprGprImmIntrinsic; +def int_riscv_cv_mac_macuRN : ScalarCoreVMacGprGprGprImmIntrinsic; +def int_riscv_cv_mac_machhuRN : ScalarCoreVMacGprGprGprImmIntrinsic; +def int_riscv_cv_mac_macsRN : ScalarCoreVMacGprGprGprImmIntrinsic; +def int_riscv_cv_mac_machhsRN : ScalarCoreVMacGprGprGprImmIntrinsic; def int_riscv_cv_elw_elw : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td index e9213df1c005..befd28778026 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td @@ -778,23 +778,23 @@ let Predicates = [HasExtXcvmac] in { def : PatCoreVMacGprGprGpr<"mac", "MAC">; def : PatCoreVMacGprGprGpr<"msu", "MSU">; - def : PatCoreVMacGprGprUimm5<"mulun", "MULUN">; - def : PatCoreVMacGprGprUimm5<"mulhhun", "MULHHUN">; - def : PatCoreVMacGprGprUimm5<"mulsn", "MULSN">; - def : PatCoreVMacGprGprUimm5<"mulhhsn", "MULHHSN">; - def : PatCoreVMacGprGprUimm5<"mulurn", "MULURN">; - def : PatCoreVMacGprGprUimm5<"mulhhurn", "MULHHURN">; - def : PatCoreVMacGprGprUimm5<"mulsrn", "MULSRN">; - def : PatCoreVMacGprGprUimm5<"mulhhsrn", "MULHHSRN">; - - def : PatCoreVMacGprGprGprUimm5<"macun", "MACUN">; - def : PatCoreVMacGprGprGprUimm5<"machhun", "MACHHUN">; - def : PatCoreVMacGprGprGprUimm5<"macsn", "MACSN">; - def : PatCoreVMacGprGprGprUimm5<"machhsn", "MACHHSN">; - def : PatCoreVMacGprGprGprUimm5<"macurn", "MACURN">; - def : PatCoreVMacGprGprGprUimm5<"machhurn", "MACHHURN">; - def : PatCoreVMacGprGprGprUimm5<"macsrn", "MACSRN">; - def : PatCoreVMacGprGprGprUimm5<"machhsrn", "MACHHSRN">; + def : PatCoreVMacGprGprUimm5<"muluN", "MULUN">; + def : PatCoreVMacGprGprUimm5<"mulhhuN", "MULHHUN">; + def : PatCoreVMacGprGprUimm5<"mulsN", "MULSN">; + def : PatCoreVMacGprGprUimm5<"mulhhsN", "MULHHSN">; + def : PatCoreVMacGprGprUimm5<"muluRN", "MULURN">; + def : PatCoreVMacGprGprUimm5<"mulhhuRN", "MULHHURN">; + def : PatCoreVMacGprGprUimm5<"mulsRN", "MULSRN">; + def : PatCoreVMacGprGprUimm5<"mulhhsRN", "MULHHSRN">; + + def : PatCoreVMacGprGprGprUimm5<"macuN", "MACUN">; + def : PatCoreVMacGprGprGprUimm5<"machhuN", "MACHHUN">; + def : PatCoreVMacGprGprGprUimm5<"macsN", "MACSN">; + def : PatCoreVMacGprGprGprUimm5<"machhsN", "MACHHSN">; + def : PatCoreVMacGprGprGprUimm5<"macuRN", "MACURN">; + def : PatCoreVMacGprGprGprUimm5<"machhuRN", "MACHHURN">; + def : PatCoreVMacGprGprGprUimm5<"macsRN", "MACSRN">; + def : PatCoreVMacGprGprGprUimm5<"machhsRN", "MACHHSRN">; } //===----------------------------------------------------------------------===// diff --git a/llvm/test/CodeGen/RISCV/corev/mac.ll b/llvm/test/CodeGen/RISCV/corev/mac.ll index a15eb88816aa..bd68a3459cab 100644 --- a/llvm/test/CodeGen/RISCV/corev/mac.ll +++ b/llvm/test/CodeGen/RISCV/corev/mac.ll @@ -331,186 +331,186 @@ define i32 @test.msu(i32 %a, i32 %b, i32 %c) { ret i32 %1 } -declare i32 @llvm.riscv.cv.mac.mulun(i32, i32, i32) +declare i32 @llvm.riscv.cv.mac.muluN(i32, i32, i32) -define i32 @test.mulun(i32 %a, i32 %b) { -; CHECK-LABEL: test.mulun: +define i32 @test.muluN(i32 %a, i32 %b) { +; CHECK-LABEL: test.muluN: ; CHECK: # %bb.0: ; CHECK-NEXT: cv.mulun a0, a0, a1, 5 ; CHECK-NEXT: ret - %1 = call i32 @llvm.riscv.cv.mac.mulun(i32 %a, i32 %b, i32 5) + %1 = call i32 @llvm.riscv.cv.mac.muluN(i32 %a, i32 %b, i32 5) ret i32 %1 } -declare i32 @llvm.riscv.cv.mac.mulhhun(i32, i32, i32) +declare i32 @llvm.riscv.cv.mac.mulhhuN(i32, i32, i32) -define i32 @test.mulhhun(i32 %a, i32 %b) { -; CHECK-LABEL: test.mulhhun: +define i32 @test.mulhhuN(i32 %a, i32 %b) { +; CHECK-LABEL: test.mulhhuN: ; CHECK: # %bb.0: ; CHECK-NEXT: cv.mulhhun a0, a0, a1, 5 ; CHECK-NEXT: ret - %1 = call i32 @llvm.riscv.cv.mac.mulhhun(i32 %a, i32 %b, i32 5) + %1 = call i32 @llvm.riscv.cv.mac.mulhhuN(i32 %a, i32 %b, i32 5) ret i32 %1 } -declare i32 @llvm.riscv.cv.mac.mulsn(i32, i32, i32) +declare i32 @llvm.riscv.cv.mac.mulsN(i32, i32, i32) -define i32 @test.mulsn(i32 %a, i32 %b) { -; CHECK-LABEL: test.mulsn: +define i32 @test.mulsN(i32 %a, i32 %b) { +; CHECK-LABEL: test.mulsN: ; CHECK: # %bb.0: ; CHECK-NEXT: cv.mulsn a0, a0, a1, 5 ; CHECK-NEXT: ret - %1 = call i32 @llvm.riscv.cv.mac.mulsn(i32 %a, i32 %b, i32 5) + %1 = call i32 @llvm.riscv.cv.mac.mulsN(i32 %a, i32 %b, i32 5) ret i32 %1 } -declare i32 @llvm.riscv.cv.mac.mulhhsn(i32, i32, i32) +declare i32 @llvm.riscv.cv.mac.mulhhsN(i32, i32, i32) -define i32 @test.mulhhsn(i32 %a, i32 %b) { -; CHECK-LABEL: test.mulhhsn: +define i32 @test.mulhhsN(i32 %a, i32 %b) { +; CHECK-LABEL: test.mulhhsN: ; CHECK: # %bb.0: ; CHECK-NEXT: cv.mulhhsn a0, a0, a1, 5 ; CHECK-NEXT: ret - %1 = call i32 @llvm.riscv.cv.mac.mulhhsn(i32 %a, i32 %b, i32 5) + %1 = call i32 @llvm.riscv.cv.mac.mulhhsN(i32 %a, i32 %b, i32 5) ret i32 %1 } -declare i32 @llvm.riscv.cv.mac.mulurn(i32, i32, i32) +declare i32 @llvm.riscv.cv.mac.muluRN(i32, i32, i32) -define i32 @test.mulurn(i32 %a, i32 %b) { -; CHECK-LABEL: test.mulurn: +define i32 @test.muluRN(i32 %a, i32 %b) { +; CHECK-LABEL: test.muluRN: ; CHECK: # %bb.0: ; CHECK-NEXT: cv.mulurn a0, a0, a1, 5 ; CHECK-NEXT: ret - %1 = call i32 @llvm.riscv.cv.mac.mulurn(i32 %a, i32 %b, i32 5) + %1 = call i32 @llvm.riscv.cv.mac.muluRN(i32 %a, i32 %b, i32 5) ret i32 %1 } -declare i32 @llvm.riscv.cv.mac.mulhhurn(i32, i32, i32) +declare i32 @llvm.riscv.cv.mac.mulhhuRN(i32, i32, i32) -define i32 @test.mulhhurn(i32 %a, i32 %b) { -; CHECK-LABEL: test.mulhhurn: +define i32 @test.mulhhuRN(i32 %a, i32 %b) { +; CHECK-LABEL: test.mulhhuRN: ; CHECK: # %bb.0: ; CHECK-NEXT: cv.mulhhurn a0, a0, a1, 5 ; CHECK-NEXT: ret - %1 = call i32 @llvm.riscv.cv.mac.mulhhurn(i32 %a, i32 %b, i32 5) + %1 = call i32 @llvm.riscv.cv.mac.mulhhuRN(i32 %a, i32 %b, i32 5) ret i32 %1 } -declare i32 @llvm.riscv.cv.mac.mulsrn(i32, i32, i32) +declare i32 @llvm.riscv.cv.mac.mulsRN(i32, i32, i32) -define i32 @test.mulsrn(i32 %a, i32 %b) { -; CHECK-LABEL: test.mulsrn: +define i32 @test.mulsRN(i32 %a, i32 %b) { +; CHECK-LABEL: test.mulsRN: ; CHECK: # %bb.0: ; CHECK-NEXT: cv.mulsrn a0, a0, a1, 5 ; CHECK-NEXT: ret - %1 = call i32 @llvm.riscv.cv.mac.mulsrn(i32 %a, i32 %b, i32 5) + %1 = call i32 @llvm.riscv.cv.mac.mulsRN(i32 %a, i32 %b, i32 5) ret i32 %1 } -declare i32 @llvm.riscv.cv.mac.mulhhsrn(i32, i32, i32) +declare i32 @llvm.riscv.cv.mac.mulhhsRN(i32, i32, i32) -define i32 @test.mulhhsrn(i32 %a, i32 %b) { -; CHECK-LABEL: test.mulhhsrn: +define i32 @test.mulhhsRN(i32 %a, i32 %b) { +; CHECK-LABEL: test.mulhhsRN: ; CHECK: # %bb.0: ; CHECK-NEXT: cv.mulhhsrn a0, a0, a1, 5 ; CHECK-NEXT: ret - %1 = call i32 @llvm.riscv.cv.mac.mulhhsrn(i32 %a, i32 %b, i32 5) + %1 = call i32 @llvm.riscv.cv.mac.mulhhsRN(i32 %a, i32 %b, i32 5) ret i32 %1 } -declare i32 @llvm.riscv.cv.mac.macun(i32, i32, i32, i32) +declare i32 @llvm.riscv.cv.mac.macuN(i32, i32, i32, i32) -define i32 @test.macun(i32 %a, i32 %b, i32 %c) { -; CHECK-LABEL: test.macun: +define i32 @test.macuN(i32 %a, i32 %b, i32 %c) { +; CHECK-LABEL: test.macuN: ; CHECK: # %bb.0: ; CHECK-NEXT: cv.macun a2, a0, a1, 5 ; CHECK-NEXT: mv a0, a2 ; CHECK-NEXT: ret - %1 = call i32 @llvm.riscv.cv.mac.macun(i32 %a, i32 %b, i32 %c, i32 5) + %1 = call i32 @llvm.riscv.cv.mac.macuN(i32 %a, i32 %b, i32 %c, i32 5) ret i32 %1 } -declare i32 @llvm.riscv.cv.mac.machhun(i32, i32, i32, i32) +declare i32 @llvm.riscv.cv.mac.machhuN(i32, i32, i32, i32) -define i32 @test.machhun(i32 %a, i32 %b, i32 %c) { -; CHECK-LABEL: test.machhun: +define i32 @test.machhuN(i32 %a, i32 %b, i32 %c) { +; CHECK-LABEL: test.machhuN: ; CHECK: # %bb.0: ; CHECK-NEXT: cv.machhun a2, a0, a1, 5 ; CHECK-NEXT: mv a0, a2 ; CHECK-NEXT: ret - %1 = call i32 @llvm.riscv.cv.mac.machhun(i32 %a, i32 %b, i32 %c, i32 5) + %1 = call i32 @llvm.riscv.cv.mac.machhuN(i32 %a, i32 %b, i32 %c, i32 5) ret i32 %1 } -declare i32 @llvm.riscv.cv.mac.macsn(i32, i32, i32, i32) +declare i32 @llvm.riscv.cv.mac.macsN(i32, i32, i32, i32) -define i32 @test.macsn(i32 %a, i32 %b, i32 %c) { -; CHECK-LABEL: test.macsn: +define i32 @test.macsN(i32 %a, i32 %b, i32 %c) { +; CHECK-LABEL: test.macsN: ; CHECK: # %bb.0: ; CHECK-NEXT: cv.macsn a2, a0, a1, 5 ; CHECK-NEXT: mv a0, a2 ; CHECK-NEXT: ret - %1 = call i32 @llvm.riscv.cv.mac.macsn(i32 %a, i32 %b, i32 %c, i32 5) + %1 = call i32 @llvm.riscv.cv.mac.macsN(i32 %a, i32 %b, i32 %c, i32 5) ret i32 %1 } -declare i32 @llvm.riscv.cv.mac.machhsn(i32, i32, i32, i32) +declare i32 @llvm.riscv.cv.mac.machhsN(i32, i32, i32, i32) -define i32 @test.machhsn(i32 %a, i32 %b, i32 %c) { -; CHECK-LABEL: test.machhsn: +define i32 @test.machhsN(i32 %a, i32 %b, i32 %c) { +; CHECK-LABEL: test.machhsN: ; CHECK: # %bb.0: ; CHECK-NEXT: cv.machhsn a2, a0, a1, 5 ; CHECK-NEXT: mv a0, a2 ; CHECK-NEXT: ret - %1 = call i32 @llvm.riscv.cv.mac.machhsn(i32 %a, i32 %b, i32 %c, i32 5) + %1 = call i32 @llvm.riscv.cv.mac.machhsN(i32 %a, i32 %b, i32 %c, i32 5) ret i32 %1 } -declare i32 @llvm.riscv.cv.mac.macurn(i32, i32, i32, i32) +declare i32 @llvm.riscv.cv.mac.macuRN(i32, i32, i32, i32) -define i32 @test.macurn(i32 %a, i32 %b, i32 %c) { -; CHECK-LABEL: test.macurn: +define i32 @test.macuRN(i32 %a, i32 %b, i32 %c) { +; CHECK-LABEL: test.macuRN: ; CHECK: # %bb.0: ; CHECK-NEXT: cv.macurn a2, a0, a1, 5 ; CHECK-NEXT: mv a0, a2 ; CHECK-NEXT: ret - %1 = call i32 @llvm.riscv.cv.mac.macurn(i32 %a, i32 %b, i32 %c, i32 5) + %1 = call i32 @llvm.riscv.cv.mac.macuRN(i32 %a, i32 %b, i32 %c, i32 5) ret i32 %1 } -declare i32 @llvm.riscv.cv.mac.machhurn(i32, i32, i32, i32) +declare i32 @llvm.riscv.cv.mac.machhuRN(i32, i32, i32, i32) -define i32 @test.machhurn(i32 %a, i32 %b, i32 %c) { -; CHECK-LABEL: test.machhurn: +define i32 @test.machhuRN(i32 %a, i32 %b, i32 %c) { +; CHECK-LABEL: test.machhuRN: ; CHECK: # %bb.0: ; CHECK-NEXT: cv.machhurn a2, a0, a1, 5 ; CHECK-NEXT: mv a0, a2 ; CHECK-NEXT: ret - %1 = call i32 @llvm.riscv.cv.mac.machhurn(i32 %a, i32 %b, i32 %c, i32 5) + %1 = call i32 @llvm.riscv.cv.mac.machhuRN(i32 %a, i32 %b, i32 %c, i32 5) ret i32 %1 } -declare i32 @llvm.riscv.cv.mac.macsrn(i32, i32, i32, i32) +declare i32 @llvm.riscv.cv.mac.macsRN(i32, i32, i32, i32) -define i32 @test.macsrn(i32 %a, i32 %b, i32 %c) { -; CHECK-LABEL: test.macsrn: +define i32 @test.macsRN(i32 %a, i32 %b, i32 %c) { +; CHECK-LABEL: test.macsRN: ; CHECK: # %bb.0: ; CHECK-NEXT: cv.macsrn a2, a0, a1, 5 ; CHECK-NEXT: mv a0, a2 ; CHECK-NEXT: ret - %1 = call i32 @llvm.riscv.cv.mac.macsrn(i32 %a, i32 %b, i32 %c, i32 5) + %1 = call i32 @llvm.riscv.cv.mac.macsRN(i32 %a, i32 %b, i32 %c, i32 5) ret i32 %1 } -declare i32 @llvm.riscv.cv.mac.machhsrn(i32, i32, i32, i32) +declare i32 @llvm.riscv.cv.mac.machhsRN(i32, i32, i32, i32) -define i32 @test.machhsrn(i32 %a, i32 %b, i32 %c) { -; CHECK-LABEL: test.machhsrn: +define i32 @test.machhsRN(i32 %a, i32 %b, i32 %c) { +; CHECK-LABEL: test.machhsRN: ; CHECK: # %bb.0: ; CHECK-NEXT: cv.machhsrn a2, a0, a1, 5 ; CHECK-NEXT: mv a0, a2 ; CHECK-NEXT: ret - %1 = call i32 @llvm.riscv.cv.mac.machhsrn(i32 %a, i32 %b, i32 %c, i32 5) + %1 = call i32 @llvm.riscv.cv.mac.machhsRN(i32 %a, i32 %b, i32 %c, i32 5) ret i32 %1 }