From 4535d99b4e8dac33f3e7182bbb34d100b8c2f2b0 Mon Sep 17 00:00:00 2001 From: Qihan Cai Date: Tue, 5 Dec 2023 01:19:38 +1100 Subject: [PATCH] [RISCV][Clang] Implement XcvElw Clang Builtins --- .../include/clang/Basic/BuiltinsRISCVCOREV.def | 2 ++ clang/lib/CodeGen/CGBuiltin.cpp | 7 ++++--- clang/test/CodeGen/RISCV/corev-intrinsics/elw.c | 17 +++++++++++++++++ 3 files changed, 23 insertions(+), 3 deletions(-) create mode 100644 clang/test/CodeGen/RISCV/corev-intrinsics/elw.c diff --git a/clang/include/clang/Basic/BuiltinsRISCVCOREV.def b/clang/include/clang/Basic/BuiltinsRISCVCOREV.def index db97c6593c89..5de4b91920bc 100644 --- a/clang/include/clang/Basic/BuiltinsRISCVCOREV.def +++ b/clang/include/clang/Basic/BuiltinsRISCVCOREV.def @@ -218,6 +218,8 @@ TARGET_BUILTIN(alu_subuN, "UZiUZiUZiUc", "nc", "xcvalu") TARGET_BUILTIN(alu_subRN, "ZiZiZiUc", "nc", "xcvalu") TARGET_BUILTIN(alu_subuRN, "UZiUZiUZiUc", "nc", "xcvalu") +TARGET_BUILTIN(elw_elw, "iv*", "nc", "xcvelw") + #undef BUILTIN #undef TARGET_BUILTIN #undef PSEUDO_BUILTIN diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 6cbb97447691..a0c5c4014eea 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -19363,12 +19363,13 @@ static Value *EmitCoreVIntrinsic(CodeGenFunction &CGF, unsigned BuiltinID, for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) { if (Ops[i]->getType() != MachineType) { QualType type = E->getArg(i)->getType(); - assert((type->isSignedIntegerType() || type->isUnsignedIntegerType()) && + assert((type->isSignedIntegerType() || type->isUnsignedIntegerType() || + type->isPointerType()) && "Argument of Core-V builtin must have signed or unsigned integer " - "type"); + "or Pointer type"); if (type->isSignedIntegerType()) { Ops[i] = CGF.Builder.CreateSExt(Ops[i], MachineType); - } else { + } else if ((type->isUnsignedIntegerType())) { Ops[i] = CGF.Builder.CreateZExt(Ops[i], MachineType); } } diff --git a/clang/test/CodeGen/RISCV/corev-intrinsics/elw.c b/clang/test/CodeGen/RISCV/corev-intrinsics/elw.c new file mode 100644 index 000000000000..b32e1831671e --- /dev/null +++ b/clang/test/CodeGen/RISCV/corev-intrinsics/elw.c @@ -0,0 +1,17 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple riscv32 -target-feature +xcvelw -emit-llvm %s -o - \ +// RUN: | FileCheck %s + + +// CHECK-LABEL: @test_elw( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: store ptr [[B:%.*]], ptr [[B_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 +// CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr i8, ptr [[TMP0]], i32 8 +// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.elw.elw(ptr [[ADD_PTR]]) +// CHECK-NEXT: ret i32 [[TMP1]] +// +int test_elw(void *b) { + return __builtin_riscv_cv_elw_elw(b + 8); +}