diff --git a/.github/FUNDING.yml b/.github/FUNDING.yml new file mode 100644 index 0000000..c779659 --- /dev/null +++ b/.github/FUNDING.yml @@ -0,0 +1,6 @@ +##################################################################### +# SPDX-License-Identifier: CC0-1.0 +# SPDX-FileType: OTHER +# SPDX-FileCopyrightText: (c) 2022, OpenGateware authors and contributors +##################################################################### +custom: ["https://www.paypal.com/donate/?hosted_button_id=N7HXKEL8VJ9CN"] diff --git a/.github/ISSUE_TEMPLATE/BUG_REPORT.yml b/.github/ISSUE_TEMPLATE/BUG_REPORT.yml new file mode 100644 index 0000000..85bd4d9 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/BUG_REPORT.yml @@ -0,0 +1,82 @@ +##################################################################### +# SPDX-License-Identifier: CC0-1.0 +# SPDX-FileType: OTHER +# SPDX-FileCopyrightText: (c) 2022, OpenGateware authors and contributors +##################################################################### +name: "Bug Report" +description: "Let us know about an unexpected error, a crash, or an incorrect behavior." +title: 'Title of your Bug Report' +labels: + - bug +assignees: + - boogermann +body: + - type: markdown + attributes: + value: | + Hi there, + + Thank you for opening an issue. Please note that we try to keep the issue tracker reserved for bug reports. + Make sure to [search for existing issues](https://github.com/opengateware/arcade-digdug/issues?q=label%3Abug) before filing a new one! + + - type: input + id: version + attributes: + label: Version (or build number) + placeholder: "1.0.0" + description: | + You can find the version in the about dialog. + + If you are not running the latest version, please try upgrading because your issue may have already been fixed. + validations: + required: true + + - type: textarea + id: steps + attributes: + label: Steps to reproduce + description: | + Please list the full steps required to reproduce the issue + placeholder: | + - Be precise + - Include exact data used during testing for easy reference + - The steps have to be in the exact order + - Mention pre-requisites when applicable + validations: + required: false + + - type: textarea + id: expected_behavior + attributes: + label: Expected Behavior + description: If you want to include screenshots, paste them into the markdown editor below or follow up with a separate comment. + placeholder: What were you expecting? + validations: + required: false + + - type: textarea + id: actual_behavior + attributes: + label: Actual Behavior + placeholder: What happened instead? + validations: + required: true + + - type: textarea + id: bug_context + attributes: + label: Additional Context + description: | + Are there anything atypical about your situation that we should know? + validations: + required: false + + - type: input + id: bug_firmware + attributes: + label: Opened Issues and Pull Requests + placeholder: "#1234" + description: | + Are there any other GitHub issues (open or closed) or Pull Requests that should be linked here? For example: #1234 + validations: + required: false diff --git a/.github/ISSUE_TEMPLATE/QUESTION.yml b/.github/ISSUE_TEMPLATE/QUESTION.yml new file mode 100644 index 0000000..8d25241 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/QUESTION.yml @@ -0,0 +1,29 @@ +##################################################################### +# SPDX-License-Identifier: CC0-1.0 +# SPDX-FileType: OTHER +# SPDX-FileCopyrightText: (c) 2022, OpenGateware authors and contributors +##################################################################### +name: "Question" +description: "Ask a question about the project." +title: 'Title of your Question' +labels: + - question +assignees: + - boogermann +body: + - type: markdown + attributes: + value: | + Hi there, + + Please note that we try to keep the issue tracker reserved for bug reports. + Make sure to [search for existing questions](https://github.com/opengateware/arcade-digdug/issues?q=label%3Aquestion) before filing a new one! + + - type: textarea + id: question + attributes: + label: Ask a question about Galaga Compatible Gateware IP Core + placeholder: | + Ask your question here! Please keep the questions related to the FPGA Core only. + validations: + required: true diff --git a/.github/PULL_REQUEST_TEMPLATE.md b/.github/PULL_REQUEST_TEMPLATE.md new file mode 100644 index 0000000..3113e01 --- /dev/null +++ b/.github/PULL_REQUEST_TEMPLATE.md @@ -0,0 +1,44 @@ + + + + + + +## What does this do / why do we need it? + + + +{Please write here} + +Fixes # (issue) + +## Type of change + + + +- [ ] Bug fix (non-breaking change which fixes an issue) +- [ ] New feature (non-breaking change which adds functionality) +- [ ] Breaking change (fix or feature that would cause existing functionality to not work as expected) +- [ ] This change requires a documentation update +- [ ] Coding style (indentation, etc) +- [ ] {Please write custom change here} + +## What should a reviewer look out for in this PR? + + + +{Please write here} + +## Additional Comments (if any) + +{Please write here} diff --git a/.github/workflows/build-pocket.yml b/.github/workflows/build-pocket.yml new file mode 100644 index 0000000..dc0d629 --- /dev/null +++ b/.github/workflows/build-pocket.yml @@ -0,0 +1,128 @@ +################################################################################ +# SPDX-License-Identifier: CC0-1.0 +# SPDX-FileType: OTHER +# SPDX-FileCopyrightText: (c) 2022, OpenGateware authors and contributors +################################################################################ +name: Build/Release +################################################################################ +# How to create a tag to launch the workflow +# git tag -a "0.1.0" -m "Release v0.1.0" +# git push origin --tags +################################################################################ +on: + push: + tags: + - "[0-9]+.[0-9]+.[0-9]+" +################################################################################ +jobs: + synthesis: + runs-on: ubuntu-latest + env: + CORE: digdug + DISPLAY_NAME: "Namco Dig Dug" + CATEGORY: arcade + AUTHOR: boogermann + TARGET: pocket + STAGE_FOLDER: staging + RELEASE_FOLDER: release + RECIPE_FOLDER: rom-recipes + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + RAETRO_WEBHOOK: ${{ secrets.RAETRO_WEBHOOK }} + FPGAGAMING_WEBHOOK: ${{ secrets.FPGAGAMING_WEBHOOK }} + + steps: + - name: "🧰 Checkout Repository" + uses: actions/checkout@v3 + + - name: "🏗️ Compile Design" + run: | + docker run --rm -v ${{ github.workspace }}:/build raetro/quartus:pocket \ + quartus_sh --flow compile projects/${CORE}_${TARGET}.qpf + + - name: "🟦 Staging Files for Release" + if: startsWith(github.ref, 'refs/tags/') + id: stage + run: | + ############################################################ + # Create Tags + ############################################################ + VERSION=${GITHUB_REF#refs/*/} + DATE=$(date +'%Y-%m-%d') + CORE_FOLDER=${AUTHOR}.${CORE} + RBF_FILE=${CORE}_${TARGET}.rbf + echo ::set-output name=VERSION::${VERSION} + echo ::set-output name=REPO::${CATEGORY}-${CORE} + echo ::set-output name=TITLE::${DISPLAY_NAME} + echo ::set-output name=RELEASE_FOLDER::${RELEASE_FOLDER} + echo ::set-output name=RELEASE_FILE::${CORE_FOLDER}_${TARGET}-${VERSION}.zip + echo ::set-output name=RECIPE_FILE::${CORE_FOLDER}_rom-recipes-${VERSION}.zip + ############################################################ + # Clear/Create Folders + ############################################################ + rm -rf ${STAGE_FOLDER} ${RELEASE_FOLDER} + mkdir -p ${STAGE_FOLDER} ${RELEASE_FOLDER} + ############################################################ + # Copy Packaging Folder + ############################################################ + cp -R pkg/${TARGET}/* ${STAGE_FOLDER} + ############################################################ + # Clear git and png source files + ############################################################ + find ./${STAGE_FOLDER} -type f \( -name "*.png*" -o -name "*.gitkeep*" \) -delete; + ############################################################ + # Update core.json Version and Release Date + ############################################################ + sed -i -e "s/<%- VERSION %>/${VERSION}/g" -e "s/<%- RELEASE_DATE %>/${DATE}/g" ${STAGE_FOLDER}/Cores/${CORE_FOLDER}/core.json + ############################################################ + # Reverse Bitstream + ############################################################ + wget https://gist.githubusercontent.com/boogermann/fba1f59c87f9c8c9404cc68878b4eb1a/raw/7e93a3560902e0136dcb29fa6c41d06f06d78fb2/reverse_bits.c + g++ reverse_bits.c -o reverse_bits + ./reverse_bits projects/output_files/${RBF_FILE} ${STAGE_FOLDER}/Cores/${CORE_FOLDER}/bitstream.rbf_r + + - name: "📦 Create Distribution Files" + if: startsWith(github.ref, 'refs/tags/') + id: zip + run: | + pushd ./${STAGE_FOLDER} + zip -r ../${RELEASE_FOLDER}/${{ steps.stage.outputs.RELEASE_FILE }} . + popd + pushd ./pkg/${RECIPE_FOLDER} + zip -r ../../${RELEASE_FOLDER}/${{ steps.stage.outputs.RECIPE_FILE }} . + popd + + - name: "🚀 Create a new GitHub Release" + uses: softprops/action-gh-release@v0.1.14 + if: startsWith(github.ref, 'refs/tags/') + with: + name: Release v${{ steps.stage.outputs.VERSION }} + files: | + ${{ steps.stage.outputs.RELEASE_FOLDER }}/* + + - name: "📢 Send Discord Announcements" + if: startsWith(github.ref, 'refs/tags/') + run: | + declare -a StringArray=("${RAETRO_WEBHOOK}" "${FPGAGAMING_WEBHOOK}") + for webhook_url in ${StringArray[@]}; do + curl \ + -H "Content-Type: application/json" \ + -d '{ + "username": "OpenGateware", + "avatar_url": "https://avatars.githubusercontent.com/u/112050328", + "embeds": [{ + "color": 2021216, + "title": "A new core stable release is available for the Pocket", + "thumbnail": { "url": "https://github.com/opengateware/${{ steps.stage.outputs.REPO }}/raw/master/docs/git-social.jpg" }, + "fields": [ + { "name": "Title", "value": "[${{ steps.stage.outputs.TITLE }}](https://github.com/opengateware/${{ steps.stage.outputs.REPO }}/)", "inline": true }, + { "name": "Version", "value": "[${{ steps.stage.outputs.VERSION }}](https://github.com/opengateware/${{ steps.stage.outputs.REPO }}/releases/tag/${{ steps.stage.outputs.VERSION }})", "inline": true }, + { "name": "Category", "value": "Arcade" }, + { "name": "Developer", "value": "[Boogermann](https://github.com/boogermann)" }, + { "name": "Download Core", "value": "[${{ steps.stage.outputs.RELEASE_FILE }}](https://github.com/opengateware/${{ steps.stage.outputs.REPO }}/releases/download/${{ steps.stage.outputs.VERSION }}/${{ steps.stage.outputs.RELEASE_FILE }})" }, + { "name": "Download ROM Recipes", "value": "[${{ steps.stage.outputs.RECIPE_FILE }}](https://github.com/opengateware/${{ steps.stage.outputs.REPO }}/releases/download/${{ steps.stage.outputs.VERSION }}/${{ steps.stage.outputs.RECIPE_FILE }})" }, + { "name": "Previous Releases", "value": "[https://github.com/opengateware/${{ steps.stage.outputs.REPO }}/releases](https://github.com/opengateware/${{ steps.stage.outputs.REPO }}/releases)" } + ] + }] + }' \ + $webhook_url + done diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..b184a5b --- /dev/null +++ b/.gitignore @@ -0,0 +1,68 @@ +db +greybox_tmp +hps_isw_handoff +incremental_db +output_files +PLLJ_PLLSPE_INFO.txt +simulation +vip +.qsys_edit +*_netlist +*_sim +*.bak +*.bsf +*.cdf +*.cmp +*.csv +*.done +*.f +*.pin +*.pof +*.ptf.* +*.qar +*.qarlog +*.qdf +*.qws +*.rbf +*.rbf_r +*.rpt +*.sip +*.sld +*.smsg +*.sof +*.sopc_builder +*.sopcinfo +*.spd +*.summary +*.txt +*.xml +*~ +**/.DS_Store +build_id.mif +build_id.v +c5_pin_model_dump.txt +cr_ie_info.json +# Gateman directories and files +!.gateman/* +!gateware.json +!/pkg/* +/pkg/**/*.rom +/pkg/**/*.zip +/staging/* +/release/* +# Editor directories and files +.vscode/* +!.vscode/extensions.json +.idea +*.suo +*.ntvs* +*.njsproj +*.sln +*.sw? + +# Pocket directories and files +!info.txt + +# ROMS Checklist +!checklist.sha1 +!checklist.md5 diff --git a/AUTHORS b/AUTHORS new file mode 100644 index 0000000..bc9a50c --- /dev/null +++ b/AUTHORS @@ -0,0 +1,24 @@ +##################################################################### +# SPDX-License-Identifier: CC0-1.0 +# SPDX-FileType: OTHER +# SPDX-FileCopyrightText: (c) 2022, OpenGateware authors and contributors +##################################################################### +# Names should be added to this file as: +# Name or Organization +# +# Core Team Members +# Current project authors, maintainers and contributors. +##################################################################### +Marcus Andrade + +##################################################################### +# Partial list of people who authored and/or contributed code in +# other iterations or versions of the project. +# +# Thanks to all for their valuable +# time/code/hints/fixes/discussions and contributions. +##################################################################### +Alan Steremberg +Jim Gregory +Matt McConnell +MiSTer-X diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..745e604 --- /dev/null +++ b/LICENSE @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. 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If not, see . + +Also add information on how to contact you by electronic and paper mail. + + If the program does terminal interaction, make it output a short +notice like this when it starts in an interactive mode: + + {project} Copyright (C) {year} {fullname} + This program comes with ABSOLUTELY NO WARRANTY; for details type 'show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type 'show c' for details. + +The hypothetical commands 'show w' and 'show c' should show the appropriate +parts of the General Public License. Of course, your program's commands +might be different; for a GUI interface, you would use an "about box". + + You should also get your employer (if you work as a programmer) or school, +if any, to sign a "copyright disclaimer" for the program, if necessary. +For more information on this, and how to apply and follow the GNU GPL, see +. + + The GNU General Public License does not permit incorporating your program +into proprietary programs. If your program is a subroutine library, you +may consider it more useful to permit linking proprietary applications with +the library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. But first, please read +. diff --git a/docs/CODE_OF_CONDUCT.md b/docs/CODE_OF_CONDUCT.md new file mode 100644 index 0000000..43aeed4 --- /dev/null +++ b/docs/CODE_OF_CONDUCT.md @@ -0,0 +1,64 @@ +# Code Of Conduct + +## Our Pledge + +In the interest of fostering an open and welcoming environment, we as contributors and leaders pledge to making participation in our project and our community a harassment-free experience for everyone, regardless of age, body size, disability, ethnicity, gender identity and expression, level or type of experience, education, socio-economic status, nationality, personal appearance, race, religion, or sexual identity and orientation. +Note, however, that religion, political party, or other ideological affiliation provide no exemptions for the behavior we outline as unacceptable in this Code of Conduct. + +## Our Standards + +We are committed to providing a friendly, safe and welcoming environment for all. + +Examples of behavior that contributes to creating a positive environment include: + +- Be kind and courteous to others +- Using welcoming and inclusive language +- Being respectful of differing viewpoints and experiences +- Collaborating with other community members +- Gracefully accepting constructive criticism +- Focusing on what is best for the community +- Showing empathy towards other community members + +Examples of unacceptable behavior by participants include: + +- The use of sexualized language or imagery and sexual attention or advances +- The use of inappropriate images, including in a community member's avatar +- The use of inappropriate language, including in a community member's nickname +- Any spamming, flaming, baiting or other attention-stealing behavior +- Excessive or unwelcome helping; answering outside the scope of the question asked +- Trolling, insulting/derogatory comments, and personal or political attacks +- Public or private harassment +- Publishing others' private information, such as a physical or electronic address, without explicit permission +- Other conduct which could reasonably be considered inappropriate + +The goal of the standards and moderation guidelines outlined here is to build and maintain a respectful community. We ask that you don’t just aim to be "technically unimpeachable", but rather try to be your best self. + +We value many things beyond technical expertise, including collaboration and supporting others within our community. Providing a positive experience for other community members can have a much more significant impact than simply providing the correct answer. + +## Our Responsibilities + +Project leaders are responsible for clarifying the standards of acceptable behavior and are expected to take appropriate and fair corrective action in response to any instances of unacceptable behavior. + +Project leaders respect all people who contribute through reporting issues, posting feature requests, updating documentation, metadata, artwork, manuals, videos, submitting pull requests or patches, and other activities. But also have the right and responsibility to remove, edit, or reject messages, comments, commits, code, issues, and other contributions that are not aligned to this Code of Conduct, or to ban temporarily or permanently any community member for other behaviors that they deem inappropriate, threatening, offensive, or harmful. + +## Scope + +This Code of Conduct and the enforcement policies listed above apply to all Rætro Community venues. This includes but is not limited to any community spaces (both public and private), the entire Rætro Discord server, and all Rætro associated GitHub repositories. Examples of Rætro Community spaces include but are not limited to meet-ups, audio chats on the Rætro Discord, or interaction at a conference. + +This Code of Conduct applies both within project spaces and in public spaces when an individual is representing the project or its community. As a community member, you are representing our community, and are expected to behave accordingly. + +## Enforcement + +Instances of abusive, harassing, or otherwise unacceptable behavior may be reported by contacting the project team at or contact [community@raetro.org][conduct-email]. +All complaints will be reviewed and investigated and will result in a response that is deemed necessary and appropriate to the circumstances. +The project team is obligated to maintain confidentiality with regard to the reporter of an incident. +Further details of specific enforcement policies may be posted separately. + +Project maintainers who do not follow or enforce the Code of Conduct in good faith may face temporary or permanent repercussions as determined by other members of the project's leadership. + +## Attribution + +This Code of Conduct is adapted from the [Contributor Covenant][homepage], version 1.4, available at https://www.contributor-covenant.org/version/1/4/code-of-conduct.html, and the Rust Code of Conduct, available at https://www.rust-lang.org/en-US/conduct.html and the Adafruit Community Code of Conduct, available at https://github.com/adafruit/Adafruit_Community_Code_of_Conduct. + +[homepage]: https://www.contributor-covenant.org +[conduct-email]: mailto:community@raetro.org diff --git a/docs/Dig_Dug.svg b/docs/Dig_Dug.svg new file mode 100644 index 0000000..054754e --- /dev/null +++ b/docs/Dig_Dug.svg @@ -0,0 +1,106 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/docs/README.md b/docs/README.md new file mode 100644 index 0000000..553e0f7 --- /dev/null +++ b/docs/README.md @@ -0,0 +1,113 @@ +[![Dig Dug Logo](digdug-logo.png)](#) + +--- + +[![Active Development](https://img.shields.io/badge/Maintenance%20Level-Actively%20Developed-brightgreen.svg)](#status-of-features) +[![Build](https://github.com/opengateware/arcade-digdug/actions/workflows/build-pocket.yml/badge.svg?branch=master&event=push)](https://github.com/opengateware/arcade-digdug/actions/workflows/build-pocket.yml) +[![release](https://img.shields.io/github/release/opengateware/arcade-digdug.svg)](https://github.com/opengateware/arcade-digdug/releases) +[![license](https://img.shields.io/github/license/opengateware/arcade-digdug.svg?label=License&color=yellow)](#legal-notices) +[![issues](https://img.shields.io/github/issues/opengateware/arcade-digdug.svg?label=Issues&color=red)](https://github.com/opengateware/arcade-digdug/issues) +[![stars](https://img.shields.io/github/stars/opengateware/arcade-digdug.svg?label=Project%20Stars)](https://github.com/opengateware/arcade-digdug/stargazers) +[![discord](https://img.shields.io/discord/676418475635507210.svg?logo=discord&logoColor=white&label=Discord&color=5865F2)](https://chat.raetro.org) +[![Twitter Follow](https://img.shields.io/twitter/follow/marcusjordan?style=social)](https://twitter.com/marcusjordan) + +## Namco [Dig Dug] Compatible Gateware IP Core + +This Implementation of a compatible Dig Dug arcade hardware in HDL is the work of [MiSTer-X]. + +## Overview + +Dig Dug is single screen action game in which the player must dig horizontal and vertical tunnels to reach and eliminate the underground-dwelling monsters living there. This is achieved by either inflating them with an air pump until they explode, or by dropping rocks onto them. + +## Technical specifications + +- **Main CPU:** Zilog Z80 @ 3.072 MHz +- **Graphics CPU:** Zilog Z80 @ 3.072 MHz +- **Sound CPU:** Zilog Z80 @ 3.072 MHz +- **Sound Chip:** Namco 3-channel WSG +- **Resolution:** 288×224, 16 colors +- **Display Box:** 384×264 @ 6.144 MHz +- **Aspect Ratio:** 9:7 +- **Orientation:** Vertical (90º) + +## Compatible Platforms + +- Analogue Pocket + +## Compatible Games + +> **ROMs NOT INCLUDED:** By using this gateware you agree to provide your own roms. + +| **Game** | Region | Status | +| :------------------------------ | :----: | :----: | +| Dig Dug (Rev 2) | JPN | ✅ | +| **Alternatives** | | | +| Dig Dug (Rev 1) | JPN | ✅ | +| Dig Dug (Atari, Rev 1) | USA | ✅ | +| Dig Dug (Atari, Rev 2) | USA | ✅ | +| Dig Dug (Manufactured by Sidam) | ITA | ✅ | + +### ROM Instructions + +1. Download and Install [ORCA](https://github.com/opengateware/tools-orca/releases/latest) (Open ROM Conversion Assistant) +2. Download the [ROM Recipes](https://github.com/opengateware/arcade-digdug/releases/latest) and extract to your computer. +3. Copy the required MAME `.zip` file(s) into the `roms` folder. +4. Inside the `tools` folder execute the script related to your system. + 1. **Windows:** right click `make_roms.ps1` and select `Run with Powershell`. + 2. **Linux and MacOS:** run script `make_roms.sh`. +5. After the conversion is completed, copy the `Assets` folder to the Root of your SD Card. +6. **Optional:** an `.md5` file is included to verify if the hash of the ROMs are valid. (eg: `md5sum -c checklist.md5`) + +> **Note:** Make sure your `.rom` files are in the `Assets/digdug/common` directory. + +## Status of Features + +> **WARNING**: This repository is in active development. There are no guarantees about stability. Breaking changes might occur until a stable release is made and announced. + +- [ ] Dip Switches + - [x] Reset Core + - [x] Enter Service Mode + - [ ] Change Difficulty + - [ ] Change Number of Lives + - [ ] Change Score for Bonus Life +- [ ] Pause +- [ ] Hi-Score Save + + +## Credits and acknowledgment + +- [Alan Steremberg] +- [Jim Gregory] +- [Matt McConnell] +- [MiSTer-X] + +## Powered by Open-Source Software + +This project borrowed and use code from several other projects. A great thanks to their efforts! + +| Modules | Copyright/Developer | +| :----------------------------- | :---------------------- | +| [Data Loader] | 2022 (c) Adam Gastineau | +| [Dig Dug RTL] | 2017 (c) MiSTer-X | +| [Generic Dual-Port RAM module] | 2021 (c) Jim Gregory | +| [Pause Handler] | 2021 (c) Jim Gregory | +| [TV80] | 2004 (c) Guy Hutchison | + +## Legal Notices + +Dig Dug © 1982 NAMCO LTD. All rights reserved. Dig Dug is a trademark of BANDAI NAMCO ENTERTAINMENT INC. +All other trademarks, logos, and copyrights are property of their respective owners. + +The authors and contributors or any of its maintainers are in no way associated with or endorsed by Bandai Namco Entertainment Inc. + +[Data Loader]: https://github.com/agg23/analogue-pocket-utils +[Dig Dug RTL]: https://github.com/MiSTer-devel/Arcade-DigDug_MiSTer/tree/master/rtl +[TV80]: https://github.com/hutch31/tv80 +[Pause Handler]: https://github.com/JimmyStones/Pause_MiSTer +[Dig Dug]: https://en.wikipedia.org/wiki/Dig_Dug +[Generic Dual-Port RAM module]: https://github.com/JimmyStones + +[Alan Steremberg]: https://github.com/alanswx +[Jim Gregory]: https://github.com/JimmyStones +[Matt McConnell]: https://github.com/mattmcwru +[MiSTer-X]: https://github.com/MrX-8B diff --git a/docs/digdug-logo.png b/docs/digdug-logo.png new file mode 100644 index 0000000..16b35a6 Binary files /dev/null and b/docs/digdug-logo.png differ diff --git a/docs/dip-switch.md b/docs/dip-switch.md new file mode 100644 index 0000000..4bd6a05 --- /dev/null +++ b/docs/dip-switch.md @@ -0,0 +1,57 @@ +# Dip Switch + +## SWA + +| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | Function | Option | +| ---- | ---- | ---- | ---- | ---- | ---- | ---- | ---- | ---------- | ----------------------- | +| Off | On | On | | | | | | Coin B | 1 Coin/1 Credit* | +| On | Off | Off | | | | | | | 1 Coin/2 Credits | +| On | Off | On | | | | | | | 1 Coin/3 Credits | +| On | On | Off | | | | | | | 1 Coin/6 Credits | +| On | On | On | | | | | | | 1 Coin/7 Credits | +| Off | Off | On | | | | | | | 2 Coins/1 Credit | +| Off | On | Off | | | | | | | 2 Coins/3 Credits | +| Off | Off | Off | | | | | | | 3 Coins/1 Credit | +| | | | | | | | | | When Lives not set to 5 | +| | | | Off | On | Off | | | Bonus Life | 10K and 40K Only | +| | | | Off | Off | Off | | | | 10K Only | +| | | | On | On | Off | | | | 10K, 40K, Every 40K | +| | | | On | Off | On | | | | 10K, 50K, Every 50K | +| | | | Off | Off | On | | | | 20K and 60K Only* | +| | | | On | Off | Off | | | | 20K, 60K, Every 60K | +| | | | Off | On | On | | | | 20K, 70K, Every 70K | +| | | | On | On | On | | | | None | +| | | | | | | | | | When Lives set to 5 | +| | | | On | Off | Off | | | | 20K and 50K Only | +| | | | Off | On | On | | | | 20K and 60K Only | +| | | | Off | Off | On | | | | 20K Only* | +| | | | On | On | Off | | | | 20K, 60K, Every 60K | +| | | | Off | On | Off | | | | 30K and 70K Only | +| | | | Off | Off | Off | | | | 30K Only | +| | | | On | Off | On | | | | 30K, 80K, Every 80K | +| | | | On | On | On | | | | None | +| | | | | | | On | On | Lives | 1 | +| | | | | | | Off | On | | 2 | +| | | | | | | On | Off | | 3* | +| | | | | | | Off | Off | | 5 | + +## SWB + +| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | Function | Option | +| ---- | ---- | ---- | ---- | ---- | ---- | ---- | ---- | -------------- | ----------------- | +| On | On | | | | | | | Coin A | 1 Coin/1 Credit* | +| Off | On | | | | | | | | 1 Coin/2 Credits | +| On | Off | | | | | | | | 2 Coins/1 Credit | +| Off | Off | | | | | | | | 2 Coins/3 Credits | +| | | Off | | | | | | Freeze | Off* | +| | | On | | | | | | | On | +| | | | Off | | | | | Demo Sounds | Off | +| | | | On | | | | | | On* | +| | | | | Off | | | | Allow Continue | No | +| | | | | On | | | | | Yes* | +| | | | | | On | | | Cabinet | Cocktail | +| | | | | | Off | | | | Upright* | +| | | | | | | On | On | Difficulty | Easy* | +| | | | | | | On | Off | | Hard | +| | | | | | | Off | Off | | Hardest | +| | | | | | | Off | On | | Medium | diff --git a/docs/git-social.jpg b/docs/git-social.jpg new file mode 100644 index 0000000..2fd2de9 Binary files /dev/null and b/docs/git-social.jpg differ diff --git a/docs/print/digdug.png b/docs/print/digdug.png new file mode 100644 index 0000000..94f74ab Binary files /dev/null and b/docs/print/digdug.png differ diff --git a/docs/print/digduga1.png b/docs/print/digduga1.png new file mode 100644 index 0000000..a733fa4 Binary files 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[English].pdf new file mode 100644 index 0000000..ea42435 Binary files /dev/null and b/docs/schematics/Dig Dug [Backdoor Sheet] [English].pdf differ diff --git a/gateware.json b/gateware.json new file mode 100644 index 0000000..e51a0cc --- /dev/null +++ b/gateware.json @@ -0,0 +1,37 @@ +{ + "name": "digdug", + "displayName": "Dig Dug", + "description": "Namco Dig Dug Compatible Gateware IP Core for FPGA", + "author": "boogermann", + "version": "0.1.0", + "license": "GPL-3.0-or-later", + "repository": "https://github.com/opengateware/arcade-digdug", + "keywords": [ + "namco", + "digdug", + "vertical", + "arcade", + "1982", + "ecosystem:gateman" + ], + "scripts": { + "verilator": "echo \"Error: no simulation specified\" && exit 1" + }, + "hardware": { + "id": "digdug", + "name": "Dig Dug", + "year": 1982, + "manufacturer": "Namco" + }, + "platforms": { + "pocket": "1.1.0" + }, + "modules": { + "arcade-highscore": "0.1.4", + "dataloader-pocket": "1.0.0", + "generic-dpram": "1.0.0", + "generic-pause": "0.2.0", + "mb88xx": "0.3.0", + "tv80": "1.0.0" + } +} \ No newline at end of file diff --git a/modules/TV80/index.qip b/modules/TV80/index.qip new file mode 100644 index 0000000..10942d1 --- /dev/null +++ b/modules/TV80/index.qip @@ -0,0 +1,6 @@ +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "tv80_core.v"] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "tv80_alu.v"] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "tv80_mcode.v"] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "tv80_reg.v"] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "tv80n.v"] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "tv80s.v"] \ No newline at end of file diff --git a/modules/TV80/tv80_alu.v b/modules/TV80/tv80_alu.v new file mode 100644 index 0000000..f90bc70 --- /dev/null +++ b/modules/TV80/tv80_alu.v @@ -0,0 +1,442 @@ +// +// TV80 8-Bit Microprocessor Core +// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) +// +// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +module tv80_alu (/*AUTOARG*/ + // Outputs + Q, F_Out, + // Inputs + Arith16, Z16, ALU_Op, IR, ISet, BusA, BusB, F_In + ); + + parameter Mode = 0; + parameter Flag_C = 0; + parameter Flag_N = 1; + parameter Flag_P = 2; + parameter Flag_X = 3; + parameter Flag_H = 4; + parameter Flag_Y = 5; + parameter Flag_Z = 6; + parameter Flag_S = 7; + + input Arith16; + input Z16; + input [3:0] ALU_Op ; + input [5:0] IR; + input [1:0] ISet; + input [7:0] BusA; + input [7:0] BusB; + input [7:0] F_In; + output [7:0] Q; + output [7:0] F_Out; + reg [7:0] Q; + reg [7:0] F_Out; + + function [4:0] AddSub4; + input [3:0] A; + input [3:0] B; + input Sub; + input Carry_In; + begin + AddSub4 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {4'h0,Carry_In}; + end + endfunction // AddSub4 + + function [3:0] AddSub3; + input [2:0] A; + input [2:0] B; + input Sub; + input Carry_In; + begin + AddSub3 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {3'h0,Carry_In}; + end + endfunction // AddSub4 + + function [1:0] AddSub1; + input A; + input B; + input Sub; + input Carry_In; + begin + AddSub1 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {1'h0,Carry_In}; + end + endfunction // AddSub4 + + // AddSub variables (temporary signals) + reg UseCarry; + reg Carry7_v; + reg OverFlow_v; + reg HalfCarry_v; + reg Carry_v; + reg [7:0] Q_v; + + reg [7:0] BitMask; + + + always @(/*AUTOSENSE*/ALU_Op or BusA or BusB or F_In or IR) + begin + case (IR[5:3]) + 3'b000 : BitMask = 8'b00000001; + 3'b001 : BitMask = 8'b00000010; + 3'b010 : BitMask = 8'b00000100; + 3'b011 : BitMask = 8'b00001000; + 3'b100 : BitMask = 8'b00010000; + 3'b101 : BitMask = 8'b00100000; + 3'b110 : BitMask = 8'b01000000; + default: BitMask = 8'b10000000; + endcase // case(IR[5:3]) + + UseCarry = ~ ALU_Op[2] && ALU_Op[0]; + { HalfCarry_v, Q_v[3:0] } = AddSub4(BusA[3:0], BusB[3:0], ALU_Op[1], ALU_Op[1] ^ (UseCarry && F_In[Flag_C]) ); + { Carry7_v, Q_v[6:4] } = AddSub3(BusA[6:4], BusB[6:4], ALU_Op[1], HalfCarry_v); + { Carry_v, Q_v[7] } = AddSub1(BusA[7], BusB[7], ALU_Op[1], Carry7_v); + OverFlow_v = Carry_v ^ Carry7_v; + end // always @ * + + reg [7:0] Q_t; + reg [8:0] DAA_Q; + + always @ (/*AUTOSENSE*/ALU_Op or Arith16 or BitMask or BusA or BusB + or Carry_v or F_In or HalfCarry_v or IR or ISet + or OverFlow_v or Q_v or Z16) + begin + Q_t = 8'hxx; + DAA_Q = {9{1'bx}}; + + F_Out = F_In; + case (ALU_Op) + 4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111 : + begin + F_Out[Flag_N] = 1'b0; + F_Out[Flag_C] = 1'b0; + + case (ALU_Op[2:0]) + + 3'b000, 3'b001 : // ADD, ADC + begin + Q_t = Q_v; + F_Out[Flag_C] = Carry_v; + F_Out[Flag_H] = HalfCarry_v; + F_Out[Flag_P] = OverFlow_v; + end + + 3'b010, 3'b011, 3'b111 : // SUB, SBC, CP + begin + Q_t = Q_v; + F_Out[Flag_N] = 1'b1; + F_Out[Flag_C] = ~ Carry_v; + F_Out[Flag_H] = ~ HalfCarry_v; + F_Out[Flag_P] = OverFlow_v; + end + + 3'b100 : // AND + begin + Q_t[7:0] = BusA & BusB; + F_Out[Flag_H] = 1'b1; + end + + 3'b101 : // XOR + begin + Q_t[7:0] = BusA ^ BusB; + F_Out[Flag_H] = 1'b0; + end + + default : // OR 3'b110 + begin + Q_t[7:0] = BusA | BusB; + F_Out[Flag_H] = 1'b0; + end + + endcase // case(ALU_OP[2:0]) + + if (ALU_Op[2:0] == 3'b111 ) + begin // CP + F_Out[Flag_X] = BusB[3]; + F_Out[Flag_Y] = BusB[5]; + end + else + begin + F_Out[Flag_X] = Q_t[3]; + F_Out[Flag_Y] = Q_t[5]; + end + + if (Q_t[7:0] == 8'b00000000 ) + begin + F_Out[Flag_Z] = 1'b1; + if (Z16 == 1'b1 ) + begin + F_Out[Flag_Z] = F_In[Flag_Z]; // 16 bit ADC,SBC + end + end + else + begin + F_Out[Flag_Z] = 1'b0; + end // else: !if(Q_t[7:0] == 8'b00000000 ) + + F_Out[Flag_S] = Q_t[7]; + case (ALU_Op[2:0]) + 3'b000, 3'b001, 3'b010, 3'b011, 3'b111 : // ADD, ADC, SUB, SBC, CP + ; + + default : + F_Out[Flag_P] = ~(^Q_t); + endcase // case(ALU_Op[2:0]) + + if (Arith16 == 1'b1 ) + begin + F_Out[Flag_S] = F_In[Flag_S]; + F_Out[Flag_Z] = F_In[Flag_Z]; + F_Out[Flag_P] = F_In[Flag_P]; + end + end // case: 4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111 + + 4'b1100 : + begin + // DAA + F_Out[Flag_H] = F_In[Flag_H]; + F_Out[Flag_C] = F_In[Flag_C]; + DAA_Q[7:0] = BusA; + DAA_Q[8] = 1'b0; + if (F_In[Flag_N] == 1'b0 ) + begin + // After addition + // Alow > 9 || H == 1 + if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 ) + begin + if ((DAA_Q[3:0] > 9) ) + begin + F_Out[Flag_H] = 1'b1; + end + else + begin + F_Out[Flag_H] = 1'b0; + end + DAA_Q = DAA_Q + 6; + end // if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 ) + + // new Ahigh > 9 || C == 1 + if (DAA_Q[8:4] > 9 || F_In[Flag_C] == 1'b1 ) + begin + DAA_Q = DAA_Q + 96; // 0x60 + end + end + else + begin + // After subtraction + if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 ) + begin + if (DAA_Q[3:0] > 5 ) + begin + F_Out[Flag_H] = 1'b0; + end + DAA_Q[7:0] = DAA_Q[7:0] - 6; + end + if (BusA > 153 || F_In[Flag_C] == 1'b1 ) + begin + DAA_Q = DAA_Q - 352; // 0x160 + end + end // else: !if(F_In[Flag_N] == 1'b0 ) + + F_Out[Flag_X] = DAA_Q[3]; + F_Out[Flag_Y] = DAA_Q[5]; + F_Out[Flag_C] = F_In[Flag_C] || DAA_Q[8]; + Q_t = DAA_Q[7:0]; + + if (DAA_Q[7:0] == 8'b00000000 ) + begin + F_Out[Flag_Z] = 1'b1; + end + else + begin + F_Out[Flag_Z] = 1'b0; + end + + F_Out[Flag_S] = DAA_Q[7]; + F_Out[Flag_P] = ~ (^DAA_Q); + end // case: 4'b1100 + + 4'b1101, 4'b1110 : + begin + // RLD, RRD + Q_t[7:4] = BusA[7:4]; + if (ALU_Op[0] == 1'b1 ) + begin + Q_t[3:0] = BusB[7:4]; + end + else + begin + Q_t[3:0] = BusB[3:0]; + end + F_Out[Flag_H] = 1'b0; + F_Out[Flag_N] = 1'b0; + F_Out[Flag_X] = Q_t[3]; + F_Out[Flag_Y] = Q_t[5]; + if (Q_t[7:0] == 8'b00000000 ) + begin + F_Out[Flag_Z] = 1'b1; + end + else + begin + F_Out[Flag_Z] = 1'b0; + end + F_Out[Flag_S] = Q_t[7]; + F_Out[Flag_P] = ~(^Q_t); + end // case: when 4'b1101, 4'b1110 + + 4'b1001 : + begin + // BIT + Q_t[7:0] = BusB & BitMask; + F_Out[Flag_S] = Q_t[7]; + if (Q_t[7:0] == 8'b00000000 ) + begin + F_Out[Flag_Z] = 1'b1; + F_Out[Flag_P] = 1'b1; + end + else + begin + F_Out[Flag_Z] = 1'b0; + F_Out[Flag_P] = 1'b0; + end + F_Out[Flag_H] = 1'b1; + F_Out[Flag_N] = 1'b0; + F_Out[Flag_X] = 1'b0; + F_Out[Flag_Y] = 1'b0; + if (IR[2:0] != 3'b110 ) + begin + F_Out[Flag_X] = BusB[3]; + F_Out[Flag_Y] = BusB[5]; + end + end // case: when 4'b1001 + + 4'b1010 : + // SET + Q_t[7:0] = BusB | BitMask; + + 4'b1011 : + // RES + Q_t[7:0] = BusB & ~ BitMask; + + 4'b1000 : + begin + // ROT + case (IR[5:3]) + 3'b000 : // RLC + begin + Q_t[7:1] = BusA[6:0]; + Q_t[0] = BusA[7]; + F_Out[Flag_C] = BusA[7]; + end + + 3'b010 : // RL + begin + Q_t[7:1] = BusA[6:0]; + Q_t[0] = F_In[Flag_C]; + F_Out[Flag_C] = BusA[7]; + end + + 3'b001 : // RRC + begin + Q_t[6:0] = BusA[7:1]; + Q_t[7] = BusA[0]; + F_Out[Flag_C] = BusA[0]; + end + + 3'b011 : // RR + begin + Q_t[6:0] = BusA[7:1]; + Q_t[7] = F_In[Flag_C]; + F_Out[Flag_C] = BusA[0]; + end + + 3'b100 : // SLA + begin + Q_t[7:1] = BusA[6:0]; + Q_t[0] = 1'b0; + F_Out[Flag_C] = BusA[7]; + end + + 3'b110 : // SLL (Undocumented) / SWAP + begin + if (Mode == 3 ) + begin + Q_t[7:4] = BusA[3:0]; + Q_t[3:0] = BusA[7:4]; + F_Out[Flag_C] = 1'b0; + end + else + begin + Q_t[7:1] = BusA[6:0]; + Q_t[0] = 1'b1; + F_Out[Flag_C] = BusA[7]; + end // else: !if(Mode == 3 ) + end // case: 3'b110 + + 3'b101 : // SRA + begin + Q_t[6:0] = BusA[7:1]; + Q_t[7] = BusA[7]; + F_Out[Flag_C] = BusA[0]; + end + + default : // SRL + begin + Q_t[6:0] = BusA[7:1]; + Q_t[7] = 1'b0; + F_Out[Flag_C] = BusA[0]; + end + endcase // case(IR[5:3]) + + F_Out[Flag_H] = 1'b0; + F_Out[Flag_N] = 1'b0; + F_Out[Flag_X] = Q_t[3]; + F_Out[Flag_Y] = Q_t[5]; + F_Out[Flag_S] = Q_t[7]; + if (Q_t[7:0] == 8'b00000000 ) + begin + F_Out[Flag_Z] = 1'b1; + end + else + begin + F_Out[Flag_Z] = 1'b0; + end + F_Out[Flag_P] = ~(^Q_t); + + if (ISet == 2'b00 ) + begin + F_Out[Flag_P] = F_In[Flag_P]; + F_Out[Flag_S] = F_In[Flag_S]; + F_Out[Flag_Z] = F_In[Flag_Z]; + end + end // case: 4'b1000 + + + default : + ; + + endcase // case(ALU_Op) + + Q = Q_t; + end // always @ (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + +endmodule // T80_ALU diff --git a/modules/TV80/tv80_core.v b/modules/TV80/tv80_core.v new file mode 100644 index 0000000..e3f7d24 --- /dev/null +++ b/modules/TV80/tv80_core.v @@ -0,0 +1,1389 @@ +// +// TV80 8-Bit Microprocessor Core +// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) +// +// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +module tv80_core (/*AUTOARG*/ + // Outputs + m1_n, iorq, no_read, write, rfsh_n, halt_n, busak_n, A, dout, mc, + ts, intcycle_n, IntE, stop, + // Inputs + reset_n, clk, cen, wait_n, int_n, nmi_n, busrq_n, dinst, di + ); + // Beginning of automatic inputs (from unused autoinst inputs) + // End of automatics + + parameter Mode = 1; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle + parameter Flag_C = 0; + parameter Flag_N = 1; + parameter Flag_P = 2; + parameter Flag_X = 3; + parameter Flag_H = 4; + parameter Flag_Y = 5; + parameter Flag_Z = 6; + parameter Flag_S = 7; + + input reset_n; + input clk; + input cen; + input wait_n; + input int_n; + input nmi_n; + input busrq_n; + output m1_n; + output iorq; + output no_read; + output write; + output rfsh_n; + output halt_n; + output busak_n; + output [15:0] A; + input [7:0] dinst; + input [7:0] di; + output [7:0] dout; + output [6:0] mc; + output [6:0] ts; + output intcycle_n; + output IntE; + output stop; + + reg m1_n; + reg iorq; +`ifdef TV80_REFRESH + reg rfsh_n; +`endif + reg halt_n; + reg busak_n; + reg [15:0] A; + reg [7:0] dout; + reg [6:0] mc; + reg [6:0] ts; + reg intcycle_n; + reg IntE; + reg stop; + + parameter aNone = 3'b111; + parameter aBC = 3'b000; + parameter aDE = 3'b001; + parameter aXY = 3'b010; + parameter aIOA = 3'b100; + parameter aSP = 3'b101; + parameter aZI = 3'b110; + + // Registers + reg [7:0] ACC, F; + reg [7:0] Ap, Fp; + reg [7:0] I; +`ifdef TV80_REFRESH + reg [7:0] R; +`endif + reg [15:0] SP, PC; + reg [7:0] RegDIH; + reg [7:0] RegDIL; + wire [15:0] RegBusA; + wire [15:0] RegBusB; + wire [15:0] RegBusC; + reg [2:0] RegAddrA_r; + reg [2:0] RegAddrA; + reg [2:0] RegAddrB_r; + reg [2:0] RegAddrB; + reg [2:0] RegAddrC; + reg RegWEH; + reg RegWEL; + reg Alternate; + + // Help Registers + reg [15:0] TmpAddr; // Temporary address register + reg [7:0] IR; // Instruction register + reg [1:0] ISet; // Instruction set selector + reg [15:0] RegBusA_r; + + reg [15:0] ID16; + reg [7:0] Save_Mux; + + reg [6:0] tstate; + reg [6:0] mcycle; + reg last_mcycle, last_tstate; + reg IntE_FF1; + reg IntE_FF2; + reg Halt_FF; + reg BusReq_s; + reg BusAck; + reg ClkEn; + reg NMI_s; + reg INT_s; + reg [1:0] IStatus; + + reg [7:0] DI_Reg; + reg T_Res; + reg [1:0] XY_State; + reg [2:0] Pre_XY_F_M; + reg NextIs_XY_Fetch; + reg XY_Ind; + reg No_BTR; + reg BTR_r; + reg Auto_Wait; + reg Auto_Wait_t1; + reg Auto_Wait_t2; + reg IncDecZ; + + // ALU signals + reg [7:0] BusB; + reg [7:0] BusA; + wire [7:0] ALU_Q; + wire [7:0] F_Out; + + // Registered micro code outputs + reg [4:0] Read_To_Reg_r; + reg Arith16_r; + reg Z16_r; + reg [3:0] ALU_Op_r; + reg Save_ALU_r; + reg PreserveC_r; + reg [2:0] mcycles; + + // Micro code outputs + wire [2:0] mcycles_d; + wire [2:0] tstates; + reg IntCycle; + reg NMICycle; + wire Inc_PC; + wire Inc_WZ; + wire [3:0] IncDec_16; + wire [1:0] Prefix; + wire Read_To_Acc; + wire Read_To_Reg; + wire [3:0] Set_BusB_To; + wire [3:0] Set_BusA_To; + wire [3:0] ALU_Op; + wire Save_ALU; + wire PreserveC; + wire Arith16; + wire [2:0] Set_Addr_To; + wire Jump; + wire JumpE; + wire JumpXY; + wire Call; + wire RstP; + wire LDZ; + wire LDW; + wire LDSPHL; + wire iorq_i; + wire [2:0] Special_LD; + wire ExchangeDH; + wire ExchangeRp; + wire ExchangeAF; + wire ExchangeRS; + wire I_DJNZ; + wire I_CPL; + wire I_CCF; + wire I_SCF; + wire I_RETN; + wire I_BT; + wire I_BC; + wire I_BTR; + wire I_RLD; + wire I_RRD; + wire I_INRC; + wire SetDI; + wire SetEI; + wire [1:0] IMode; + wire Halt; + + reg [15:0] PC16; + reg [15:0] PC16_B; + reg [15:0] SP16, SP16_A, SP16_B; + reg [15:0] ID16_B; + reg Oldnmi_n; + + tv80_mcode #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_mcode + ( + .IR (IR), + .ISet (ISet), + .MCycle (mcycle), + .F (F), + .NMICycle (NMICycle), + .IntCycle (IntCycle), + .MCycles (mcycles_d), + .TStates (tstates), + .Prefix (Prefix), + .Inc_PC (Inc_PC), + .Inc_WZ (Inc_WZ), + .IncDec_16 (IncDec_16), + .Read_To_Acc (Read_To_Acc), + .Read_To_Reg (Read_To_Reg), + .Set_BusB_To (Set_BusB_To), + .Set_BusA_To (Set_BusA_To), + .ALU_Op (ALU_Op), + .Save_ALU (Save_ALU), + .PreserveC (PreserveC), + .Arith16 (Arith16), + .Set_Addr_To (Set_Addr_To), + .IORQ (iorq_i), + .Jump (Jump), + .JumpE (JumpE), + .JumpXY (JumpXY), + .Call (Call), + .RstP (RstP), + .LDZ (LDZ), + .LDW (LDW), + .LDSPHL (LDSPHL), + .Special_LD (Special_LD), + .ExchangeDH (ExchangeDH), + .ExchangeRp (ExchangeRp), + .ExchangeAF (ExchangeAF), + .ExchangeRS (ExchangeRS), + .I_DJNZ (I_DJNZ), + .I_CPL (I_CPL), + .I_CCF (I_CCF), + .I_SCF (I_SCF), + .I_RETN (I_RETN), + .I_BT (I_BT), + .I_BC (I_BC), + .I_BTR (I_BTR), + .I_RLD (I_RLD), + .I_RRD (I_RRD), + .I_INRC (I_INRC), + .SetDI (SetDI), + .SetEI (SetEI), + .IMode (IMode), + .Halt (Halt), + .NoRead (no_read), + .Write (write) + ); + + tv80_alu #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_alu + ( + .Arith16 (Arith16_r), + .Z16 (Z16_r), + .ALU_Op (ALU_Op_r), + .IR (IR[5:0]), + .ISet (ISet), + .BusA (BusA), + .BusB (BusB), + .F_In (F), + .Q (ALU_Q), + .F_Out (F_Out) + ); + + function [6:0] number_to_bitvec; + input [2:0] num; + begin + case (num) + 1 : number_to_bitvec = 7'b0000001; + 2 : number_to_bitvec = 7'b0000010; + 3 : number_to_bitvec = 7'b0000100; + 4 : number_to_bitvec = 7'b0001000; + 5 : number_to_bitvec = 7'b0010000; + 6 : number_to_bitvec = 7'b0100000; + 7 : number_to_bitvec = 7'b1000000; + default : number_to_bitvec = 7'bx; + endcase // case(num) + end + endfunction // number_to_bitvec + + function [2:0] mcyc_to_number; + input [6:0] mcyc; + begin + casez (mcyc) + 7'b1zzzzzz : mcyc_to_number = 3'h7; + 7'b01zzzzz : mcyc_to_number = 3'h6; + 7'b001zzzz : mcyc_to_number = 3'h5; + 7'b0001zzz : mcyc_to_number = 3'h4; + 7'b00001zz : mcyc_to_number = 3'h3; + 7'b000001z : mcyc_to_number = 3'h2; + 7'b0000001 : mcyc_to_number = 3'h1; + default : mcyc_to_number = 3'h1; + endcase + end + endfunction + + always @(/*AUTOSENSE*/mcycle or mcycles or tstate or tstates) + begin + case (mcycles) + 1 : last_mcycle = mcycle[0]; + 2 : last_mcycle = mcycle[1]; + 3 : last_mcycle = mcycle[2]; + 4 : last_mcycle = mcycle[3]; + 5 : last_mcycle = mcycle[4]; + 6 : last_mcycle = mcycle[5]; + 7 : last_mcycle = mcycle[6]; + default : last_mcycle = 1'bx; + endcase // case(mcycles) + + case (tstates) + 0 : last_tstate = tstate[0]; + 1 : last_tstate = tstate[1]; + 2 : last_tstate = tstate[2]; + 3 : last_tstate = tstate[3]; + 4 : last_tstate = tstate[4]; + 5 : last_tstate = tstate[5]; + 6 : last_tstate = tstate[6]; + default : last_tstate = 1'bx; + endcase + end // always @ (... + + + always @(/*AUTOSENSE*/ALU_Q or BusAck or BusB or DI_Reg + or ExchangeRp or IR or Save_ALU_r or Set_Addr_To or XY_Ind + or XY_State or cen or last_tstate or mcycle) + begin + ClkEn = cen && ~ BusAck; + + if (last_tstate) + T_Res = 1'b1; + else T_Res = 1'b0; + + if (XY_State != 2'b00 && XY_Ind == 1'b0 && + ((Set_Addr_To == aXY) || + (mcycle[0] && IR == 8'b11001011) || + (mcycle[0] && IR == 8'b00110110))) + NextIs_XY_Fetch = 1'b1; + else + NextIs_XY_Fetch = 1'b0; + + if (ExchangeRp) + Save_Mux = BusB; + else if (!Save_ALU_r) + Save_Mux = DI_Reg; + else + Save_Mux = ALU_Q; + end // always @ * + + always @ (posedge clk or negedge reset_n) + begin + if (reset_n == 1'b0 ) + begin + PC <= #1 0; // Program Counter + A <= #1 0; + TmpAddr <= #1 0; + IR <= #1 8'b00000000; + ISet <= #1 2'b00; + XY_State <= #1 2'b00; + IStatus <= #1 2'b00; + mcycles <= #1 3'b000; + dout <= #1 8'b00000000; + + ACC <= #1 8'hFF; + F <= #1 8'hFF; + Ap <= #1 8'hFF; + Fp <= #1 8'hFF; + I <= #1 0; + `ifdef TV80_REFRESH + R <= #1 0; + `endif + SP <= #1 16'hFFFF; + Alternate <= #1 1'b0; + + Read_To_Reg_r <= #1 5'b00000; + Arith16_r <= #1 1'b0; + BTR_r <= #1 1'b0; + Z16_r <= #1 1'b0; + ALU_Op_r <= #1 4'b0000; + Save_ALU_r <= #1 1'b0; + PreserveC_r <= #1 1'b0; + XY_Ind <= #1 1'b0; + end + else + begin + + if (ClkEn == 1'b1 ) + begin + + ALU_Op_r <= #1 4'b0000; + Save_ALU_r <= #1 1'b0; + Read_To_Reg_r <= #1 5'b00000; + + mcycles <= #1 mcycles_d; + + if (IMode != 2'b11 ) + begin + IStatus <= #1 IMode; + end + + Arith16_r <= #1 Arith16; + PreserveC_r <= #1 PreserveC; + if (ISet == 2'b10 && ALU_Op[2] == 1'b0 && ALU_Op[0] == 1'b1 && mcycle[2] ) + begin + Z16_r <= #1 1'b1; + end + else + begin + Z16_r <= #1 1'b0; + end + + if (mcycle[0] && (tstate[1] | tstate[2] | tstate[3] )) + begin + // mcycle == 1 && tstate == 1, 2, || 3 + if (tstate[2] && wait_n == 1'b1 ) + begin + `ifdef TV80_REFRESH + if (Mode < 2 ) + begin + A[7:0] <= #1 R; + A[15:8] <= #1 I; + R[6:0] <= #1 R[6:0] + 1; + end + `endif + if (Jump == 1'b0 && Call == 1'b0 && NMICycle == 1'b0 && IntCycle == 1'b0 && ~ (Halt_FF == 1'b1 || Halt == 1'b1) ) + begin + PC <= #1 PC16; + end + + if (IntCycle == 1'b1 && IStatus == 2'b01 ) + begin + IR <= #1 8'b11111111; + end + else if (Halt_FF == 1'b1 || (IntCycle == 1'b1 && IStatus == 2'b10) || NMICycle == 1'b1 ) + begin + IR <= #1 8'b00000000; + TmpAddr[7:0] <= #1 dinst; // Special M1 vector fetch + end + else + begin + IR <= #1 dinst; + end + + ISet <= #1 2'b00; + if (Prefix != 2'b00 ) + begin + if (Prefix == 2'b11 ) + begin + if (IR[5] == 1'b1 ) + begin + XY_State <= #1 2'b10; + end + else + begin + XY_State <= #1 2'b01; + end + end + else + begin + if (Prefix == 2'b10 ) + begin + XY_State <= #1 2'b00; + XY_Ind <= #1 1'b0; + end + ISet <= #1 Prefix; + end + end + else + begin + XY_State <= #1 2'b00; + XY_Ind <= #1 1'b0; + end + end // if (tstate == 2 && wait_n == 1'b1 ) + + + end + else + begin + // either (mcycle > 1) OR (mcycle == 1 AND tstate > 3) + + if (mcycle[5] ) + begin + XY_Ind <= #1 1'b1; + if (Prefix == 2'b01 ) + begin + ISet <= #1 2'b01; + end + end + + if (T_Res == 1'b1 ) + begin + BTR_r <= #1 (I_BT || I_BC || I_BTR) && ~ No_BTR; + if (Jump == 1'b1 ) + begin + A[15:8] <= #1 DI_Reg; + A[7:0] <= #1 TmpAddr[7:0]; + PC[15:8] <= #1 DI_Reg; + PC[7:0] <= #1 TmpAddr[7:0]; + end + else if (JumpXY == 1'b1 ) + begin + A <= #1 RegBusC; + PC <= #1 RegBusC; + end else if (Call == 1'b1 || RstP == 1'b1 ) + begin + A <= #1 TmpAddr; + PC <= #1 TmpAddr; + end + else if (last_mcycle && NMICycle == 1'b1 ) + begin + A <= #1 16'b0000000001100110; + PC <= #1 16'b0000000001100110; + end + else if (mcycle[2] && IntCycle == 1'b1 && IStatus == 2'b10 ) + begin + A[15:8] <= #1 I; + A[7:0] <= #1 TmpAddr[7:0]; + PC[15:8] <= #1 I; + PC[7:0] <= #1 TmpAddr[7:0]; + end + else + begin + case (Set_Addr_To) + aXY : + begin + if (XY_State == 2'b00 ) + begin + A <= #1 RegBusC; + end + else + begin + if (NextIs_XY_Fetch == 1'b1 ) + begin + A <= #1 PC; + end + else + begin + A <= #1 TmpAddr; + end + end // else: !if(XY_State == 2'b00 ) + end // case: aXY + + aIOA : + begin + if (Mode == 3 ) + begin + // Memory map I/O on GBZ80 + A[15:8] <= #1 8'hFF; + end + else if (Mode == 2 ) + begin + // Duplicate I/O address on 8080 + A[15:8] <= #1 DI_Reg; + end + else + begin + A[15:8] <= #1 ACC; + end + A[7:0] <= #1 DI_Reg; + end // case: aIOA + + + aSP : + begin + A <= #1 SP; + end + + aBC : + begin + if (Mode == 3 && iorq_i == 1'b1 ) + begin + // Memory map I/O on GBZ80 + A[15:8] <= #1 8'hFF; + A[7:0] <= #1 RegBusC[7:0]; + end + else + begin + A <= #1 RegBusC; + end + end // case: aBC + + aDE : + begin + A <= #1 RegBusC; + end + + aZI : + begin + if (Inc_WZ == 1'b1 ) + begin + A <= #1 TmpAddr + 1; + end + else + begin + A[15:8] <= #1 DI_Reg; + A[7:0] <= #1 TmpAddr[7:0]; + end + end // case: aZI + + default : + begin + A <= #1 PC; + end + endcase // case(Set_Addr_To) + + end // else: !if(mcycle[2] && IntCycle == 1'b1 && IStatus == 2'b10 ) + + + Save_ALU_r <= #1 Save_ALU; + ALU_Op_r <= #1 ALU_Op; + + if (I_CPL == 1'b1 ) + begin + // CPL + ACC <= #1 ~ ACC; + F[Flag_Y] <= #1 ~ ACC[5]; + F[Flag_H] <= #1 1'b1; + F[Flag_X] <= #1 ~ ACC[3]; + F[Flag_N] <= #1 1'b1; + end + if (I_CCF == 1'b1 ) + begin + // CCF + F[Flag_C] <= #1 ~ F[Flag_C]; + F[Flag_Y] <= #1 ACC[5]; + F[Flag_H] <= #1 F[Flag_C]; + F[Flag_X] <= #1 ACC[3]; + F[Flag_N] <= #1 1'b0; + end + if (I_SCF == 1'b1 ) + begin + // SCF + F[Flag_C] <= #1 1'b1; + F[Flag_Y] <= #1 ACC[5]; + F[Flag_H] <= #1 1'b0; + F[Flag_X] <= #1 ACC[3]; + F[Flag_N] <= #1 1'b0; + end + end // if (T_Res == 1'b1 ) + + + if (tstate[2] && wait_n == 1'b1 ) + begin + if (ISet == 2'b01 && mcycle[6] ) + begin + IR <= #1 dinst; + end + if (JumpE == 1'b1 ) + begin + PC <= #1 PC16; + end + else if (Inc_PC == 1'b1 ) + begin + //PC <= #1 PC + 1; + PC <= #1 PC16; + end + if (BTR_r == 1'b1 ) + begin + //PC <= #1 PC - 2; + PC <= #1 PC16; + end + if (RstP == 1'b1 ) + begin + TmpAddr <= #1 { 10'h0, IR[5:3], 3'h0 }; + //TmpAddr <= #1 (others =>1'b0); + //TmpAddr[5:3] <= #1 IR[5:3]; + end + end + if (tstate[3] && mcycle[5] ) + begin + TmpAddr <= #1 SP16; + end + + if ((tstate[2] && wait_n == 1'b1) || (tstate[4] && mcycle[0]) ) + begin + if (IncDec_16[2:0] == 3'b111 ) + begin + SP <= #1 SP16; + end + end + + if (LDSPHL == 1'b1 ) + begin + SP <= #1 RegBusC; + end + if (ExchangeAF == 1'b1 ) + begin + Ap <= #1 ACC; + ACC <= #1 Ap; + Fp <= #1 F; + F <= #1 Fp; + end + if (ExchangeRS == 1'b1 ) + begin + Alternate <= #1 ~ Alternate; + end + end // else: !if(mcycle == 3'b001 && tstate(2) == 1'b0 ) + + + if (tstate[3] ) + begin + if (LDZ == 1'b1 ) + begin + TmpAddr[7:0] <= #1 DI_Reg; + end + if (LDW == 1'b1 ) + begin + TmpAddr[15:8] <= #1 DI_Reg; + end + + if (Special_LD[2] == 1'b1 ) + begin + case (Special_LD[1:0]) + 2'b00 : + begin + ACC <= #1 I; + F[Flag_P] <= #1 IntE_FF2; + F[Flag_Z] <= (I == 0); + F[Flag_S] <= I[7]; + F[Flag_H] <= 0; + F[Flag_N] <= 0; + end + + 2'b01 : + begin + `ifdef TV80_REFRESH + ACC <= #1 R; + `else + ACC <= #1 0; + `endif + F[Flag_P] <= #1 IntE_FF2; + F[Flag_Z] <= (I == 0); + F[Flag_S] <= I[7]; + F[Flag_H] <= 0; + F[Flag_N] <= 0; + end + + 2'b10 : + I <= #1 ACC; + + `ifdef TV80_REFRESH + default : + R <= #1 ACC; + `else + default : ; + `endif + endcase + end + end // if (tstate == 3 ) + + + if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) || ALU_Op_r == 4'b1001 ) + begin + if (Mode == 3 ) + begin + F[6] <= #1 F_Out[6]; + F[5] <= #1 F_Out[5]; + F[7] <= #1 F_Out[7]; + if (PreserveC_r == 1'b0 ) + begin + F[4] <= #1 F_Out[4]; + end + end + else + begin + F[7:1] <= #1 F_Out[7:1]; + if (PreserveC_r == 1'b0 ) + begin + F[Flag_C] <= #1 F_Out[0]; + end + end + end // if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) || ALU_Op_r == 4'b1001 ) + + if (T_Res == 1'b1 && I_INRC == 1'b1 ) + begin + F[Flag_H] <= #1 1'b0; + F[Flag_N] <= #1 1'b0; + if (DI_Reg[7:0] == 8'b00000000 ) + begin + F[Flag_Z] <= #1 1'b1; + end + else + begin + F[Flag_Z] <= #1 1'b0; + end + F[Flag_S] <= #1 DI_Reg[7]; + F[Flag_P] <= #1 ~ (^DI_Reg[7:0]); + end // if (T_Res == 1'b1 && I_INRC == 1'b1 ) + + + if (tstate[1] && Auto_Wait_t1 == 1'b0 ) + begin + dout <= #1 BusB; + if (I_RLD == 1'b1 ) + begin + dout[3:0] <= #1 BusA[3:0]; + dout[7:4] <= #1 BusB[3:0]; + end + if (I_RRD == 1'b1 ) + begin + dout[3:0] <= #1 BusB[7:4]; + dout[7:4] <= #1 BusA[3:0]; + end + end + + if (T_Res == 1'b1 ) + begin + Read_To_Reg_r[3:0] <= #1 Set_BusA_To; + Read_To_Reg_r[4] <= #1 Read_To_Reg; + if (Read_To_Acc == 1'b1 ) + begin + Read_To_Reg_r[3:0] <= #1 4'b0111; + Read_To_Reg_r[4] <= #1 1'b1; + end + end + + if (tstate[1] && I_BT == 1'b1 ) + begin + F[Flag_X] <= #1 ALU_Q[3]; + F[Flag_Y] <= #1 ALU_Q[1]; + F[Flag_H] <= #1 1'b0; + F[Flag_N] <= #1 1'b0; + end + if (I_BC == 1'b1 || I_BT == 1'b1 ) + begin + F[Flag_P] <= #1 IncDecZ; + end + + if ((tstate[1] && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) || + (Save_ALU_r == 1'b1 && ALU_Op_r != 4'b0111) ) + begin + case (Read_To_Reg_r) + 5'b10111 : + ACC <= #1 Save_Mux; + 5'b10110 : + dout <= #1 Save_Mux; + 5'b11000 : + SP[7:0] <= #1 Save_Mux; + 5'b11001 : + SP[15:8] <= #1 Save_Mux; + 5'b11011 : + F <= #1 Save_Mux; + default : ; + endcase + end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||... + end // if (ClkEn == 1'b1 ) + end // else: !if(reset_n == 1'b0 ) + end + + + //------------------------------------------------------------------------- + // + // BC('), DE('), HL('), IX && IY + // + //------------------------------------------------------------------------- + always @ (posedge clk) + begin + if (ClkEn == 1'b1 ) + begin + // Bus A / Write + RegAddrA_r <= #1 { Alternate, Set_BusA_To[2:1] }; + if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusA_To[2:1] == 2'b10 ) + begin + RegAddrA_r <= #1 { XY_State[1], 2'b11 }; + end + + // Bus B + RegAddrB_r <= #1 { Alternate, Set_BusB_To[2:1] }; + if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusB_To[2:1] == 2'b10 ) + begin + RegAddrB_r <= #1 { XY_State[1], 2'b11 }; + end + + // Address from register + RegAddrC <= #1 { Alternate, Set_Addr_To[1:0] }; + // Jump (HL), LD SP,HL + if ((JumpXY == 1'b1 || LDSPHL == 1'b1) ) + begin + RegAddrC <= #1 { Alternate, 2'b10 }; + end + if (((JumpXY == 1'b1 || LDSPHL == 1'b1) && XY_State != 2'b00) || (mcycle[5]) ) + begin + RegAddrC <= #1 { XY_State[1], 2'b11 }; + end + + if (I_DJNZ == 1'b1 && Save_ALU_r == 1'b1 && Mode < 2 ) + begin + IncDecZ <= #1 F_Out[Flag_Z]; + end + if ((tstate[2] || (tstate[3] && mcycle[0])) && IncDec_16[2:0] == 3'b100 ) + begin + if (ID16 == 0 ) + begin + IncDecZ <= #1 1'b0; + end + else + begin + IncDecZ <= #1 1'b1; + end + end + + RegBusA_r <= #1 RegBusA; + end + + end // always @ (posedge clk) + + + always @(/*AUTOSENSE*/Alternate or ExchangeDH or IncDec_16 + or RegAddrA_r or RegAddrB_r or XY_State or mcycle or tstate) + begin + if ((tstate[2] || (tstate[3] && mcycle[0] && IncDec_16[2] == 1'b1)) && XY_State == 2'b00) + RegAddrA = { Alternate, IncDec_16[1:0] }; + else if ((tstate[2] || (tstate[3] && mcycle[0] && IncDec_16[2] == 1'b1)) && IncDec_16[1:0] == 2'b10) + RegAddrA = { XY_State[1], 2'b11 }; + else if (ExchangeDH == 1'b1 && tstate[3]) + RegAddrA = { Alternate, 2'b10 }; + else if (ExchangeDH == 1'b1 && tstate[4]) + RegAddrA = { Alternate, 2'b01 }; + else + RegAddrA = RegAddrA_r; + + if (ExchangeDH == 1'b1 && tstate[3]) + RegAddrB = { Alternate, 2'b01 }; + else + RegAddrB = RegAddrB_r; + end // always @ * + + + always @(/*AUTOSENSE*/ALU_Op_r or Auto_Wait_t1 or ExchangeDH + or IncDec_16 or Read_To_Reg_r or Save_ALU_r or mcycle + or tstate or wait_n) + begin + RegWEH = 1'b0; + RegWEL = 1'b0; + if ((tstate[1] && ~Save_ALU_r && ~Auto_Wait_t1) || + (Save_ALU_r && (ALU_Op_r != 4'b0111)) ) + begin + case (Read_To_Reg_r) + 5'b10000 , 5'b10001 , 5'b10010 , 5'b10011 , 5'b10100 , 5'b10101 : + begin + RegWEH = ~ Read_To_Reg_r[0]; + RegWEL = Read_To_Reg_r[0]; + end // UNMATCHED !! + default : ; + endcase // case(Read_To_Reg_r) + + end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||... + + + if (ExchangeDH && (tstate[3] || tstate[4]) ) + begin + RegWEH = 1'b1; + RegWEL = 1'b1; + end + + if (IncDec_16[2] && ((tstate[2] && wait_n && ~mcycle[0]) || (tstate[3] && mcycle[0])) ) + begin + case (IncDec_16[1:0]) + 2'b00 , 2'b01 , 2'b10 : + begin + RegWEH = 1'b1; + RegWEL = 1'b1; + end // UNMATCHED !! + default : ; + endcase + end + end // always @ * + + + always @(/*AUTOSENSE*/ExchangeDH or ID16 or IncDec_16 or RegBusA_r + or RegBusB or Save_Mux or mcycle or tstate) + begin + RegDIH = Save_Mux; + RegDIL = Save_Mux; + + if (ExchangeDH == 1'b1 && tstate[3] ) + begin + RegDIH = RegBusB[15:8]; + RegDIL = RegBusB[7:0]; + end + else if (ExchangeDH == 1'b1 && tstate[4] ) + begin + RegDIH = RegBusA_r[15:8]; + RegDIL = RegBusA_r[7:0]; + end + else if (IncDec_16[2] == 1'b1 && ((tstate[2] && ~mcycle[0]) || (tstate[3] && mcycle[0])) ) + begin + RegDIH = ID16[15:8]; + RegDIL = ID16[7:0]; + end + end + + tv80_reg i_reg + ( + .clk (clk), + .CEN (ClkEn), + .WEH (RegWEH), + .WEL (RegWEL), + .AddrA (RegAddrA), + .AddrB (RegAddrB), + .AddrC (RegAddrC), + .DIH (RegDIH), + .DIL (RegDIL), + .DOAH (RegBusA[15:8]), + .DOAL (RegBusA[7:0]), + .DOBH (RegBusB[15:8]), + .DOBL (RegBusB[7:0]), + .DOCH (RegBusC[15:8]), + .DOCL (RegBusC[7:0]) + ); + + //------------------------------------------------------------------------- + // + // Buses + // + //------------------------------------------------------------------------- + + always @ (posedge clk) + begin + if (ClkEn == 1'b1 ) + begin + case (Set_BusB_To) + 4'b0111 : + BusB <= #1 ACC; + 4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 : + begin + if (Set_BusB_To[0] == 1'b1 ) + begin + BusB <= #1 RegBusB[7:0]; + end + else + begin + BusB <= #1 RegBusB[15:8]; + end + end + 4'b0110 : + BusB <= #1 DI_Reg; + 4'b1000 : + BusB <= #1 SP[7:0]; + 4'b1001 : + BusB <= #1 SP[15:8]; + 4'b1010 : + BusB <= #1 8'b00000001; + 4'b1011 : + BusB <= #1 F; + 4'b1100 : + BusB <= #1 PC[7:0]; + 4'b1101 : + BusB <= #1 PC[15:8]; + 4'b1110 : + BusB <= #1 8'b00000000; + default : + BusB <= #1 8'h0; + endcase + + case (Set_BusA_To) + 4'b0111 : + BusA <= #1 ACC; + 4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 : + begin + if (Set_BusA_To[0] == 1'b1 ) + begin + BusA <= #1 RegBusA[7:0]; + end + else + begin + BusA <= #1 RegBusA[15:8]; + end + end + 4'b0110 : + BusA <= #1 DI_Reg; + 4'b1000 : + BusA <= #1 SP[7:0]; + 4'b1001 : + BusA <= #1 SP[15:8]; + 4'b1010 : + BusA <= #1 8'b00000000; + default : + BusA <= #1 8'h0; + endcase + end + end + + //------------------------------------------------------------------------- + // + // Generate external control signals + // + //------------------------------------------------------------------------- +`ifdef TV80_REFRESH + always @ (posedge clk or negedge reset_n) + begin + if (reset_n == 1'b0 ) + begin + rfsh_n <= #1 1'b1; + end + else + begin + if (cen == 1'b1 ) + begin + if (mcycle[0] && ((tstate[2] && wait_n == 1'b1) || tstate[3]) ) + begin + rfsh_n <= #1 1'b0; + end + else + begin + rfsh_n <= #1 1'b1; + end + end + end + end // always @ (posedge clk or negedge reset_n) +`else // !`ifdef TV80_REFRESH + assign rfsh_n = 1'b1; +`endif + + always @(/*AUTOSENSE*/BusAck or Halt_FF or I_DJNZ or IntCycle + or IntE_FF1 or di or iorq_i or mcycle or tstate) + begin + mc = mcycle; + ts = tstate; + DI_Reg = di; + halt_n = ~ Halt_FF; + busak_n = ~ BusAck; + intcycle_n = ~ IntCycle; + IntE = IntE_FF1; + iorq = iorq_i; + stop = I_DJNZ; + end + + //----------------------------------------------------------------------- + // + // Syncronise inputs + // + //----------------------------------------------------------------------- + + always @ (posedge clk or negedge reset_n) + begin : sync_inputs + if (~reset_n) + begin + BusReq_s <= #1 1'b0; + INT_s <= #1 1'b0; + NMI_s <= #1 1'b0; + Oldnmi_n <= #1 1'b0; + end + else + begin + if (cen == 1'b1 ) + begin + BusReq_s <= #1 ~ busrq_n; + INT_s <= #1 ~ int_n; + if (NMICycle == 1'b1 ) + begin + NMI_s <= #1 1'b0; + end + else if (nmi_n == 1'b0 && Oldnmi_n == 1'b1 ) + begin + NMI_s <= #1 1'b1; + end + Oldnmi_n <= #1 nmi_n; + end + end + end + + //----------------------------------------------------------------------- + // + // Main state machine + // + //----------------------------------------------------------------------- + + always @ (posedge clk or negedge reset_n) + begin + if (reset_n == 1'b0 ) + begin + mcycle <= #1 7'b0000001; + tstate <= #1 7'b0000001; + Pre_XY_F_M <= #1 3'b000; + Halt_FF <= #1 1'b0; + BusAck <= #1 1'b0; + NMICycle <= #1 1'b0; + IntCycle <= #1 1'b0; + IntE_FF1 <= #1 1'b0; + IntE_FF2 <= #1 1'b0; + No_BTR <= #1 1'b0; + Auto_Wait_t1 <= #1 1'b0; + Auto_Wait_t2 <= #1 1'b0; + m1_n <= #1 1'b1; + end + else + begin + if (cen == 1'b1 ) + begin + if (T_Res == 1'b1 ) + begin + Auto_Wait_t1 <= #1 1'b0; + end + else + begin + Auto_Wait_t1 <= #1 Auto_Wait || (iorq_i & ~Auto_Wait_t2); + end + Auto_Wait_t2 <= #1 Auto_Wait_t1 & !T_Res; + No_BTR <= #1 (I_BT && (~ IR[4] || ~ F[Flag_P])) || + (I_BC && (~ IR[4] || F[Flag_Z] || ~ F[Flag_P])) || + (I_BTR && (~ IR[4] || F[Flag_Z])); + if (tstate[2] ) + begin + if (SetEI == 1'b1 ) + begin + if (!NMICycle) + IntE_FF1 <= #1 1'b1; + IntE_FF2 <= #1 1'b1; + end + if (I_RETN == 1'b1 ) + begin + IntE_FF1 <= #1 IntE_FF2; + end + end + if (tstate[3] ) + begin + if (SetDI == 1'b1 ) + begin + IntE_FF1 <= #1 1'b0; + IntE_FF2 <= #1 1'b0; + end + end + if (IntCycle == 1'b1 || NMICycle == 1'b1 ) + begin + Halt_FF <= #1 1'b0; + end + if (mcycle[0] && tstate[2] && wait_n == 1'b1 ) + begin + m1_n <= #1 1'b1; + end + if (BusReq_s == 1'b1 && BusAck == 1'b1 ) + begin + end + else + begin + BusAck <= #1 1'b0; + if (tstate[2] && wait_n == 1'b0 ) + begin + end + else if (T_Res == 1'b1 ) + begin + if (Halt == 1'b1 ) + begin + Halt_FF <= #1 1'b1; + end + if (BusReq_s == 1'b1 ) + begin + BusAck <= #1 1'b1; + end + else + begin + tstate <= #1 7'b0000010; + if (NextIs_XY_Fetch == 1'b1 ) + begin + mcycle <= #1 7'b0100000; + Pre_XY_F_M <= #1 mcyc_to_number(mcycle); + if (IR == 8'b00110110 && Mode == 0 ) + begin + Pre_XY_F_M <= #1 3'b010; + end + end + else if ((mcycle[6]) || (mcycle[5] && Mode == 1 && ISet != 2'b01) ) + begin + mcycle <= #1 number_to_bitvec(Pre_XY_F_M + 1); + end + else if ((last_mcycle) || + No_BTR == 1'b1 || + (mcycle[1] && I_DJNZ == 1'b1 && IncDecZ == 1'b1) ) + begin + m1_n <= #1 1'b0; + mcycle <= #1 7'b0000001; + IntCycle <= #1 1'b0; + NMICycle <= #1 1'b0; + if (NMI_s == 1'b1 && Prefix == 2'b00 ) + begin + NMICycle <= #1 1'b1; + IntE_FF1 <= #1 1'b0; + end + else if ((IntE_FF1 == 1'b1 && INT_s == 1'b1) && Prefix == 2'b00 && SetEI == 1'b0 ) + begin + IntCycle <= #1 1'b1; + IntE_FF1 <= #1 1'b0; + IntE_FF2 <= #1 1'b0; + end + end + else + begin + mcycle <= #1 { mcycle[5:0], mcycle[6] }; + end + end + end + else + begin // verilog has no "nor" operator + if ( ~(Auto_Wait == 1'b1 && Auto_Wait_t2 == 1'b0) && + ~(IOWait == 1 && iorq_i == 1'b1 && Auto_Wait_t1 == 1'b0) ) + begin + tstate <= #1 { tstate[5:0], tstate[6] }; + end + end + end + if (tstate[0]) + begin + m1_n <= #1 1'b0; + end + end + end + end + + always @(/*AUTOSENSE*/BTR_r or DI_Reg or IncDec_16 or JumpE or PC + or RegBusA or RegBusC or SP or tstate) + begin + if (JumpE == 1'b1 ) + begin + PC16_B = { {8{DI_Reg[7]}}, DI_Reg }; + end + else if (BTR_r == 1'b1 ) + begin + PC16_B = -2; + end + else + begin + PC16_B = 1; + end + + if (tstate[3]) + begin + SP16_A = RegBusC; + SP16_B = { {8{DI_Reg[7]}}, DI_Reg }; + end + else + begin + // suspect that ID16 and SP16 could be shared + SP16_A = SP; + + if (IncDec_16[3] == 1'b1) + SP16_B = -1; + else + SP16_B = 1; + end + + if (IncDec_16[3]) + ID16_B = -1; + else + ID16_B = 1; + + ID16 = RegBusA + ID16_B; + PC16 = PC + PC16_B; + SP16 = SP16_A + SP16_B; + end // always @ * + + + always @(/*AUTOSENSE*/IntCycle or NMICycle or mcycle) + begin + Auto_Wait = 1'b0; + if (IntCycle == 1'b1 || NMICycle == 1'b1 ) + begin + if (mcycle[0] ) + begin + Auto_Wait = 1'b1; + end + end + end // always @ * + +endmodule // T80 + diff --git a/modules/TV80/tv80_mcode.v b/modules/TV80/tv80_mcode.v new file mode 100644 index 0000000..40622d2 --- /dev/null +++ b/modules/TV80/tv80_mcode.v @@ -0,0 +1,2650 @@ +// +// TV80 8-Bit Microprocessor Core +// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) +// +// Copyright (c) 2004,2007 Guy Hutchison (ghutchis@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +module tv80_mcode + (/*AUTOARG*/ + // Outputs + MCycles, TStates, Prefix, Inc_PC, Inc_WZ, IncDec_16, Read_To_Reg, + Read_To_Acc, Set_BusA_To, Set_BusB_To, ALU_Op, Save_ALU, PreserveC, + Arith16, Set_Addr_To, IORQ, Jump, JumpE, JumpXY, Call, RstP, LDZ, + LDW, LDSPHL, Special_LD, ExchangeDH, ExchangeRp, ExchangeAF, + ExchangeRS, I_DJNZ, I_CPL, I_CCF, I_SCF, I_RETN, I_BT, I_BC, I_BTR, + I_RLD, I_RRD, I_INRC, SetDI, SetEI, IMode, Halt, NoRead, Write, + // Inputs + IR, ISet, MCycle, F, NMICycle, IntCycle + ); + + parameter Mode = 0; + parameter Flag_C = 0; + parameter Flag_N = 1; + parameter Flag_P = 2; + parameter Flag_X = 3; + parameter Flag_H = 4; + parameter Flag_Y = 5; + parameter Flag_Z = 6; + parameter Flag_S = 7; + + input [7:0] IR; + input [1:0] ISet ; + input [6:0] MCycle ; + input [7:0] F ; + input NMICycle ; + input IntCycle ; + output [2:0] MCycles ; + output [2:0] TStates ; + output [1:0] Prefix ; // None,BC,ED,DD/FD + output Inc_PC ; + output Inc_WZ ; + output [3:0] IncDec_16 ; // BC,DE,HL,SP 0 is inc + output Read_To_Reg ; + output Read_To_Acc ; + output [3:0] Set_BusA_To ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + output [3:0] Set_BusB_To ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + output [3:0] ALU_Op ; + output Save_ALU ; + output PreserveC ; + output Arith16 ; + output [2:0] Set_Addr_To ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI + output IORQ ; + output Jump ; + output JumpE ; + output JumpXY ; + output Call ; + output RstP ; + output LDZ ; + output LDW ; + output LDSPHL ; + output [2:0] Special_LD ; // A,I;A,R;I,A;R,A;None + output ExchangeDH ; + output ExchangeRp ; + output ExchangeAF ; + output ExchangeRS ; + output I_DJNZ ; + output I_CPL ; + output I_CCF ; + output I_SCF ; + output I_RETN ; + output I_BT ; + output I_BC ; + output I_BTR ; + output I_RLD ; + output I_RRD ; + output I_INRC ; + output SetDI ; + output SetEI ; + output [1:0] IMode ; + output Halt ; + output NoRead ; + output Write ; + + // regs + reg [2:0] MCycles ; + reg [2:0] TStates ; + reg [1:0] Prefix ; // None,BC,ED,DD/FD + reg Inc_PC ; + reg Inc_WZ ; + reg [3:0] IncDec_16 ; // BC,DE,HL,SP 0 is inc + reg Read_To_Reg ; + reg Read_To_Acc ; + reg [3:0] Set_BusA_To ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + reg [3:0] Set_BusB_To ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + reg [3:0] ALU_Op ; + reg Save_ALU ; + reg PreserveC ; + reg Arith16 ; + reg [2:0] Set_Addr_To ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI + reg IORQ ; + reg Jump ; + reg JumpE ; + reg JumpXY ; + reg Call ; + reg RstP ; + reg LDZ ; + reg LDW ; + reg LDSPHL ; + reg [2:0] Special_LD ; // A,I;A,R;I,A;R,A;None + reg ExchangeDH ; + reg ExchangeRp ; + reg ExchangeAF ; + reg ExchangeRS ; + reg I_DJNZ ; + reg I_CPL ; + reg I_CCF ; + reg I_SCF ; + reg I_RETN ; + reg I_BT ; + reg I_BC ; + reg I_BTR ; + reg I_RLD ; + reg I_RRD ; + reg I_INRC ; + reg SetDI ; + reg SetEI ; + reg [1:0] IMode ; + reg Halt ; + reg NoRead ; + reg Write ; + + parameter aNone = 3'b111; + parameter aBC = 3'b000; + parameter aDE = 3'b001; + parameter aXY = 3'b010; + parameter aIOA = 3'b100; + parameter aSP = 3'b101; + parameter aZI = 3'b110; + // constant aNone : std_logic_vector[2:0] = 3'b000; + // constant aXY : std_logic_vector[2:0] = 3'b001; + // constant aIOA : std_logic_vector[2:0] = 3'b010; + // constant aSP : std_logic_vector[2:0] = 3'b011; + // constant aBC : std_logic_vector[2:0] = 3'b100; + // constant aDE : std_logic_vector[2:0] = 3'b101; + // constant aZI : std_logic_vector[2:0] = 3'b110; + + function is_cc_true; + input [7:0] FF; + input [2:0] cc; + begin + if (Mode == 3 ) + begin + case (cc) + 3'b000 : is_cc_true = FF[7] == 1'b0; // NZ + 3'b001 : is_cc_true = FF[7] == 1'b1; // Z + 3'b010 : is_cc_true = FF[4] == 1'b0; // NC + 3'b011 : is_cc_true = FF[4] == 1'b1; // C + 3'b100 : is_cc_true = 0; + 3'b101 : is_cc_true = 0; + 3'b110 : is_cc_true = 0; + 3'b111 : is_cc_true = 0; + endcase + end + else + begin + case (cc) + 3'b000 : is_cc_true = FF[6] == 1'b0; // NZ + 3'b001 : is_cc_true = FF[6] == 1'b1; // Z + 3'b010 : is_cc_true = FF[0] == 1'b0; // NC + 3'b011 : is_cc_true = FF[0] == 1'b1; // C + 3'b100 : is_cc_true = FF[2] == 1'b0; // PO + 3'b101 : is_cc_true = FF[2] == 1'b1; // PE + 3'b110 : is_cc_true = FF[7] == 1'b0; // P + 3'b111 : is_cc_true = FF[7] == 1'b1; // M + endcase + end + end + endfunction // is_cc_true + + + reg [2:0] DDD; + reg [2:0] SSS; + reg [1:0] DPAIR; + + always @ (/*AUTOSENSE*/F or IR or ISet or IntCycle or MCycle + or NMICycle) + begin + DDD = IR[5:3]; + SSS = IR[2:0]; + DPAIR = IR[5:4]; + + MCycles = 3'b001; + if (MCycle[0] ) + begin + TStates = 3'b100; + end + else + begin + TStates = 3'b011; + end + Prefix = 2'b00; + Inc_PC = 1'b0; + Inc_WZ = 1'b0; + IncDec_16 = 4'b0000; + Read_To_Acc = 1'b0; + Read_To_Reg = 1'b0; + Set_BusB_To = 4'b0000; + Set_BusA_To = 4'b0000; + ALU_Op = { 1'b0, IR[5:3] }; + Save_ALU = 1'b0; + PreserveC = 1'b0; + Arith16 = 1'b0; + IORQ = 1'b0; + Set_Addr_To = aNone; + Jump = 1'b0; + JumpE = 1'b0; + JumpXY = 1'b0; + Call = 1'b0; + RstP = 1'b0; + LDZ = 1'b0; + LDW = 1'b0; + LDSPHL = 1'b0; + Special_LD = 3'b000; + ExchangeDH = 1'b0; + ExchangeRp = 1'b0; + ExchangeAF = 1'b0; + ExchangeRS = 1'b0; + I_DJNZ = 1'b0; + I_CPL = 1'b0; + I_CCF = 1'b0; + I_SCF = 1'b0; + I_RETN = 1'b0; + I_BT = 1'b0; + I_BC = 1'b0; + I_BTR = 1'b0; + I_RLD = 1'b0; + I_RRD = 1'b0; + I_INRC = 1'b0; + SetDI = 1'b0; + SetEI = 1'b0; + IMode = 2'b11; + Halt = 1'b0; + NoRead = 1'b0; + Write = 1'b0; + + case (ISet) + 2'b00 : + begin + + //---------------------------------------------------------------------------- + // + // Unprefixed instructions + // + //---------------------------------------------------------------------------- + + casez (IR) + // 8 BIT LOAD GROUP + 8'b01zzzzzz : + begin + if (IR[5:0] == 6'b110110) + Halt = 1'b1; + else if (IR[2:0] == 3'b110) + begin + // LD r,(HL) + MCycles = 3'b010; + if (MCycle[0]) + Set_Addr_To = aXY; + if (MCycle[1]) + begin + Set_BusA_To[2:0] = DDD; + Read_To_Reg = 1'b1; + end + end // if (IR[2:0] == 3'b110) + else if (IR[5:3] == 3'b110) + begin + // LD (HL),r + MCycles = 3'b010; + if (MCycle[0]) + begin + Set_Addr_To = aXY; + Set_BusB_To[2:0] = SSS; + Set_BusB_To[3] = 1'b0; + end + if (MCycle[1]) + Write = 1'b1; + end // if (IR[5:3] == 3'b110) + else + begin + Set_BusB_To[2:0] = SSS; + ExchangeRp = 1'b1; + Set_BusA_To[2:0] = DDD; + Read_To_Reg = 1'b1; + end // else: !if(IR[5:3] == 3'b110) + end // case: 8'b01zzzzzz + + 8'b00zzz110 : + begin + if (IR[5:3] == 3'b110) + begin + // LD (HL),n + MCycles = 3'b011; + if (MCycle[1]) + begin + Inc_PC = 1'b1; + Set_Addr_To = aXY; + Set_BusB_To[2:0] = SSS; + Set_BusB_To[3] = 1'b0; + end + if (MCycle[2]) + Write = 1'b1; + end // if (IR[5:3] == 3'b110) + else + begin + // LD r,n + MCycles = 3'b010; + if (MCycle[1]) + begin + Inc_PC = 1'b1; + Set_BusA_To[2:0] = DDD; + Read_To_Reg = 1'b1; + end + end + end + + 8'b00001010 : + begin + // LD A,(BC) + MCycles = 3'b010; + if (MCycle[0]) + Set_Addr_To = aBC; + if (MCycle[1]) + Read_To_Acc = 1'b1; + end // case: 8'b00001010 + + 8'b00011010 : + begin + // LD A,(DE) + MCycles = 3'b010; + if (MCycle[0]) + Set_Addr_To = aDE; + if (MCycle[1]) + Read_To_Acc = 1'b1; + end // case: 8'b00011010 + + 8'b00111010 : + begin + if (Mode == 3 ) + begin + // LDD A,(HL) + MCycles = 3'b010; + if (MCycle[0]) + Set_Addr_To = aXY; + if (MCycle[1]) + begin + Read_To_Acc = 1'b1; + IncDec_16 = 4'b1110; + end + end + else + begin + // LD A,(nn) + MCycles = 3'b100; + if (MCycle[1]) + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + if (MCycle[2]) + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + end + if (MCycle[3]) + begin + Read_To_Acc = 1'b1; + end + end // else: !if(Mode == 3 ) + end // case: 8'b00111010 + + 8'b00000010 : + begin + // LD (BC),A + MCycles = 3'b010; + if (MCycle[0]) + begin + Set_Addr_To = aBC; + Set_BusB_To = 4'b0111; + end + if (MCycle[1]) + begin + Write = 1'b1; + end + end // case: 8'b00000010 + + 8'b00010010 : + begin + // LD (DE),A + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0] : + begin + Set_Addr_To = aDE; + Set_BusB_To = 4'b0111; + end + MCycle[1] : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b00010010 + + 8'b00110010 : + begin + if (Mode == 3 ) + begin + // LDD (HL),A + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0] : + begin + Set_Addr_To = aXY; + Set_BusB_To = 4'b0111; + end + MCycle[1] : + begin + Write = 1'b1; + IncDec_16 = 4'b1110; + end + default :; + endcase // case(MCycle) + + end + else + begin + // LD (nn),A + MCycles = 3'b100; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + MCycle[2] : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + Set_BusB_To = 4'b0111; + end + MCycle[3] : + begin + Write = 1'b1; + end + default :; + endcase + end // else: !if(Mode == 3 ) + end // case: 8'b00110010 + + + // 16 BIT LOAD GROUP + 8'b00000001,8'b00010001,8'b00100001,8'b00110001 : + begin + // LD dd,nn + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + Read_To_Reg = 1'b1; + if (DPAIR == 2'b11 ) + begin + Set_BusA_To[3:0] = 4'b1000; + end + else + begin + Set_BusA_To[2:1] = DPAIR; + Set_BusA_To[0] = 1'b1; + end + end // case: 2 + + MCycle[2] : + begin + Inc_PC = 1'b1; + Read_To_Reg = 1'b1; + if (DPAIR == 2'b11 ) + begin + Set_BusA_To[3:0] = 4'b1001; + end + else + begin + Set_BusA_To[2:1] = DPAIR; + Set_BusA_To[0] = 1'b0; + end + end // case: 3 + + default :; + endcase // case(MCycle) + end // case: 8'b00000001,8'b00010001,8'b00100001,8'b00110001 + + 8'b00101010 : + begin + if (Mode == 3 ) + begin + // LDI A,(HL) + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aXY; + MCycle[1] : + begin + Read_To_Acc = 1'b1; + IncDec_16 = 4'b0110; + end + + default :; + endcase + end + else + begin + // LD HL,(nn) + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + MCycle[2] : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + LDW = 1'b1; + end + MCycle[3] : + begin + Set_BusA_To[2:0] = 3'b101; // L + Read_To_Reg = 1'b1; + Inc_WZ = 1'b1; + Set_Addr_To = aZI; + end + MCycle[4] : + begin + Set_BusA_To[2:0] = 3'b100; // H + Read_To_Reg = 1'b1; + end + default :; + endcase + end // else: !if(Mode == 3 ) + end // case: 8'b00101010 + + 8'b00100010 : + begin + if (Mode == 3 ) + begin + // LDI (HL),A + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0] : + begin + Set_Addr_To = aXY; + Set_BusB_To = 4'b0111; + end + MCycle[1] : + begin + Write = 1'b1; + IncDec_16 = 4'b0110; + end + default :; + endcase + end + else + begin + // LD (nn),HL + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + MCycle[2] : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + LDW = 1'b1; + Set_BusB_To = 4'b0101; // L + end + + MCycle[3] : + begin + Inc_WZ = 1'b1; + Set_Addr_To = aZI; + Write = 1'b1; + Set_BusB_To = 4'b0100; // H + end + MCycle[4] : + Write = 1'b1; + default :; + endcase + end // else: !if(Mode == 3 ) + end // case: 8'b00100010 + + 8'b11111001 : + begin + // LD SP,HL + TStates = 3'b110; + LDSPHL = 1'b1; + end + + 8'b11zz0101 : + begin + // PUSH qq + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + begin + TStates = 3'b101; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + if (DPAIR == 2'b11 ) + begin + Set_BusB_To = 4'b0111; + end + else + begin + Set_BusB_To[2:1] = DPAIR; + Set_BusB_To[0] = 1'b0; + Set_BusB_To[3] = 1'b0; + end + end // case: 1 + + MCycle[1] : + begin + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + if (DPAIR == 2'b11 ) + begin + Set_BusB_To = 4'b1011; + end + else + begin + Set_BusB_To[2:1] = DPAIR; + Set_BusB_To[0] = 1'b1; + Set_BusB_To[3] = 1'b0; + end + Write = 1'b1; + end // case: 2 + + MCycle[2] : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b11000101,8'b11010101,8'b11100101,8'b11110101 + + 8'b11zz0001 : + begin + // POP qq + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aSP; + MCycle[1] : + begin + IncDec_16 = 4'b0111; + Set_Addr_To = aSP; + Read_To_Reg = 1'b1; + if (DPAIR == 2'b11 ) + begin + Set_BusA_To[3:0] = 4'b1011; + end + else + begin + Set_BusA_To[2:1] = DPAIR; + Set_BusA_To[0] = 1'b1; + end + end // case: 2 + + MCycle[2] : + begin + IncDec_16 = 4'b0111; + Read_To_Reg = 1'b1; + if (DPAIR == 2'b11 ) + begin + Set_BusA_To[3:0] = 4'b0111; + end + else + begin + Set_BusA_To[2:1] = DPAIR; + Set_BusA_To[0] = 1'b0; + end + end // case: 3 + + default :; + endcase // case(MCycle) + end // case: 8'b11000001,8'b11010001,8'b11100001,8'b11110001 + + + // EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + 8'b11101011 : + begin + if (Mode != 3 ) + begin + // EX DE,HL + ExchangeDH = 1'b1; + end + end + + 8'b00001000 : + begin + if (Mode == 3 ) + begin + // LD (nn),SP + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + MCycle[2] : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + LDW = 1'b1; + Set_BusB_To = 4'b1000; + end + + MCycle[3] : + begin + Inc_WZ = 1'b1; + Set_Addr_To = aZI; + Write = 1'b1; + Set_BusB_To = 4'b1001; + end + + MCycle[4] : + Write = 1'b1; + default :; + endcase + end + else if (Mode < 2 ) + begin + // EX AF,AF' + ExchangeAF = 1'b1; + end + end // case: 8'b00001000 + + 8'b11011001 : + begin + if (Mode == 3 ) + begin + // RETI + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aSP; + MCycle[1] : + begin + IncDec_16 = 4'b0111; + Set_Addr_To = aSP; + LDZ = 1'b1; + end + + MCycle[2] : + begin + Jump = 1'b1; + IncDec_16 = 4'b0111; + I_RETN = 1'b1; + SetEI = 1'b1; + end + default :; + endcase + end + else if (Mode < 2 ) + begin + // EXX + ExchangeRS = 1'b1; + end + end // case: 8'b11011001 + + 8'b11100011 : + begin + if (Mode != 3 ) + begin + // EX (SP),HL + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aSP; + MCycle[1] : + begin + Read_To_Reg = 1'b1; + Set_BusA_To = 4'b0101; + Set_BusB_To = 4'b0101; + Set_Addr_To = aSP; + end + MCycle[2] : + begin + IncDec_16 = 4'b0111; + Set_Addr_To = aSP; + TStates = 3'b100; + Write = 1'b1; + end + MCycle[3] : + begin + Read_To_Reg = 1'b1; + Set_BusA_To = 4'b0100; + Set_BusB_To = 4'b0100; + Set_Addr_To = aSP; + end + MCycle[4] : + begin + IncDec_16 = 4'b1111; + TStates = 3'b101; + Write = 1'b1; + end + + default :; + endcase + end // if (Mode != 3 ) + end // case: 8'b11100011 + + + // 8 BIT ARITHMETIC AND LOGICAL GROUP + 8'b10zzzzzz : + begin + if (IR[2:0] == 3'b110) + begin + // ADD A,(HL) + // ADC A,(HL) + // SUB A,(HL) + // SBC A,(HL) + // AND A,(HL) + // OR A,(HL) + // XOR A,(HL) + // CP A,(HL) + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aXY; + MCycle[1] : + begin + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_BusB_To[2:0] = SSS; + Set_BusA_To[2:0] = 3'b111; + end + + default :; + endcase // case(MCycle) + end // if (IR[2:0] == 3'b110) + else + begin + // ADD A,r + // ADC A,r + // SUB A,r + // SBC A,r + // AND A,r + // OR A,r + // XOR A,r + // CP A,r + Set_BusB_To[2:0] = SSS; + Set_BusA_To[2:0] = 3'b111; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + end // else: !if(IR[2:0] == 3'b110) + end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,... + + 8'b11zzz110 : + begin + // ADD A,n + // ADC A,n + // SUB A,n + // SBC A,n + // AND A,n + // OR A,n + // XOR A,n + // CP A,n + MCycles = 3'b010; + if (MCycle[1] ) + begin + Inc_PC = 1'b1; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_BusB_To[2:0] = SSS; + Set_BusA_To[2:0] = 3'b111; + end + end + + 8'b00zzz100 : + begin + if (IR[5:3] == 3'b110) + begin + // INC (HL) + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aXY; + MCycle[1] : + begin + TStates = 3'b100; + Set_Addr_To = aXY; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + PreserveC = 1'b1; + ALU_Op = 4'b0000; + Set_BusB_To = 4'b1010; + Set_BusA_To[2:0] = DDD; + end // case: 2 + + MCycle[2] : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b00110100 + else + begin + // INC r + Set_BusB_To = 4'b1010; + Set_BusA_To[2:0] = DDD; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + PreserveC = 1'b1; + ALU_Op = 4'b0000; + end + end + + 8'b00zzz101 : + begin + if (IR[5:3] == 3'b110) + begin + // DEC (HL) + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aXY; + MCycle[1] : + begin + TStates = 3'b100; + Set_Addr_To = aXY; + ALU_Op = 4'b0010; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + PreserveC = 1'b1; + Set_BusB_To = 4'b1010; + Set_BusA_To[2:0] = DDD; + end // case: 2 + + MCycle[2] : + Write = 1'b1; + default :; + endcase // case(MCycle) + end + else + begin + // DEC r + Set_BusB_To = 4'b1010; + Set_BusA_To[2:0] = DDD; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + PreserveC = 1'b1; + ALU_Op = 4'b0010; + end + end + + // GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + 8'b00100111 : + begin + // DAA + Set_BusA_To[2:0] = 3'b111; + Read_To_Reg = 1'b1; + ALU_Op = 4'b1100; + Save_ALU = 1'b1; + end + + 8'b00101111 : + // CPL + I_CPL = 1'b1; + + 8'b00111111 : + // CCF + I_CCF = 1'b1; + + 8'b00110111 : + // SCF + I_SCF = 1'b1; + + 8'b00000000 : + begin + if (NMICycle == 1'b1 ) + begin + // NMI + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + begin + TStates = 3'b101; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1101; + end + + MCycle[1] : + begin + TStates = 3'b100; + Write = 1'b1; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1100; + end + + MCycle[2] : + begin + TStates = 3'b100; + Write = 1'b1; + end + + default :; + endcase // case(MCycle) + + end + else if (IntCycle == 1'b1 ) + begin + // INT (IM 2) + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[0] : + begin + LDZ = 1'b1; + TStates = 3'b101; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1101; + end + + MCycle[1] : + begin + TStates = 3'b100; + Write = 1'b1; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1100; + end + + MCycle[2] : + begin + TStates = 3'b100; + Write = 1'b1; + end + + MCycle[3] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + MCycle[4] : + Jump = 1'b1; + default :; + endcase + end + end // case: 8'b00000000 + + 8'b11110011 : + // DI + SetDI = 1'b1; + + 8'b11111011 : + // EI + SetEI = 1'b1; + + // 16 BIT ARITHMETIC GROUP + 8'b00zz1001 : + begin + // ADD HL,ss + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + NoRead = 1'b1; + ALU_Op = 4'b0000; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_BusA_To[2:0] = 3'b101; + case (IR[5:4]) + 0,1,2 : + begin + Set_BusB_To[2:1] = IR[5:4]; + Set_BusB_To[0] = 1'b1; + end + + default : + Set_BusB_To = 4'b1000; + endcase // case(IR[5:4]) + + TStates = 3'b100; + Arith16 = 1'b1; + end // case: 2 + + MCycle[2] : + begin + NoRead = 1'b1; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + ALU_Op = 4'b0001; + Set_BusA_To[2:0] = 3'b100; + case (IR[5:4]) + 0,1,2 : + Set_BusB_To[2:1] = IR[5:4]; + default : + Set_BusB_To = 4'b1001; + endcase + Arith16 = 1'b1; + end // case: 3 + + default :; + endcase // case(MCycle) + end // case: 8'b00001001,8'b00011001,8'b00101001,8'b00111001 + + 8'b00zz0011 : + begin + // INC ss + TStates = 3'b110; + IncDec_16[3:2] = 2'b01; + IncDec_16[1:0] = DPAIR; + end + + 8'b00zz1011 : + begin + // DEC ss + TStates = 3'b110; + IncDec_16[3:2] = 2'b11; + IncDec_16[1:0] = DPAIR; + end + + // ROTATE AND SHIFT GROUP + 8'b00000111, + // RLCA + 8'b00010111, + // RLA + 8'b00001111, + // RRCA + 8'b00011111 : + // RRA + begin + Set_BusA_To[2:0] = 3'b111; + ALU_Op = 4'b1000; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + end // case: 8'b00000111,... + + + // JUMP GROUP + 8'b11000011 : + begin + // JP nn + MCycles = 3'b011; + if (MCycle[1]) + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + if (MCycle[2]) + begin + Inc_PC = 1'b1; + Jump = 1'b1; + end + + end // case: 8'b11000011 + + 8'b11zzz010 : + begin + if (IR[5] == 1'b1 && Mode == 3 ) + begin + case (IR[4:3]) + 2'b00 : + begin + // LD ($FF00+C),A + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0] : + begin + Set_Addr_To = aBC; + Set_BusB_To = 4'b0111; + end + MCycle[1] : + begin + Write = 1'b1; + IORQ = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 2'b00 + + 2'b01 : + begin + // LD (nn),A + MCycles = 3'b100; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + MCycle[2] : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + Set_BusB_To = 4'b0111; + end + + MCycle[3] : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: default :... + + 2'b10 : + begin + // LD A,($FF00+C) + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aBC; + MCycle[1] : + begin + Read_To_Acc = 1'b1; + IORQ = 1'b1; + end + default :; + endcase // case(MCycle) + end // case: 2'b10 + + 2'b11 : + begin + // LD A,(nn) + MCycles = 3'b100; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + MCycle[2] : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + end + MCycle[3] : + Read_To_Acc = 1'b1; + default :; + endcase // case(MCycle) + end + endcase + end + else + begin + // JP cc,nn + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + MCycle[2] : + begin + Inc_PC = 1'b1; + if (is_cc_true(F, IR[5:3]) ) + begin + Jump = 1'b1; + end + end + + default :; + endcase + end // else: !if(DPAIR == 2'b11 ) + end // case: 8'b11000010,8'b11001010,8'b11010010,8'b11011010,8'b11100010,8'b11101010,8'b11110010,8'b11111010 + + 8'b00011000 : + begin + if (Mode != 2 ) + begin + // JR e + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + Inc_PC = 1'b1; + MCycle[2] : + begin + NoRead = 1'b1; + JumpE = 1'b1; + TStates = 3'b101; + end + default :; + endcase + end // if (Mode != 2 ) + end // case: 8'b00011000 + + // Conditional relative jumps (JR [C/NC/Z/NZ], e) + 8'b001zz000 : + begin + if (Mode != 2 ) + begin + MCycles = 3'd3; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + + case (IR[4:3]) + 0 : MCycles = (F[Flag_Z]) ? 3'd2 : 3'd3; + 1 : MCycles = (!F[Flag_Z]) ? 3'd2 : 3'd3; + 2 : MCycles = (F[Flag_C]) ? 3'd2 : 3'd3; + 3 : MCycles = (!F[Flag_C]) ? 3'd2 : 3'd3; + endcase + end + + MCycle[2] : + begin + NoRead = 1'b1; + JumpE = 1'b1; + TStates = 3'd5; + end + default :; + endcase + end // if (Mode != 2 ) + end // case: 8'b00111000 + + 8'b11101001 : + // JP (HL) + JumpXY = 1'b1; + + 8'b00010000 : + begin + if (Mode == 3 ) + begin + I_DJNZ = 1'b1; + end + else if (Mode < 2 ) + begin + // DJNZ,e + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + begin + TStates = 3'b101; + I_DJNZ = 1'b1; + Set_BusB_To = 4'b1010; + Set_BusA_To[2:0] = 3'b000; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + ALU_Op = 4'b0010; + end + MCycle[1] : + begin + I_DJNZ = 1'b1; + Inc_PC = 1'b1; + end + MCycle[2] : + begin + NoRead = 1'b1; + JumpE = 1'b1; + TStates = 3'b101; + end + default :; + endcase + end // if (Mode < 2 ) + end // case: 8'b00010000 + + + // CALL AND RETURN GROUP + 8'b11001101 : + begin + // CALL nn + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + MCycle[2] : + begin + IncDec_16 = 4'b1111; + Inc_PC = 1'b1; + TStates = 3'b100; + Set_Addr_To = aSP; + LDW = 1'b1; + Set_BusB_To = 4'b1101; + end + MCycle[3] : + begin + Write = 1'b1; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1100; + end + MCycle[4] : + begin + Write = 1'b1; + Call = 1'b1; + end + default :; + endcase // case(MCycle) + end // case: 8'b11001101 + + 8'b11zzz100 : + begin + if (IR[5] == 1'b0 || Mode != 3 ) + begin + // CALL cc,nn + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + MCycle[2] : + begin + Inc_PC = 1'b1; + LDW = 1'b1; + if (is_cc_true(F, IR[5:3]) ) + begin + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + TStates = 3'b100; + Set_BusB_To = 4'b1101; + end + else + begin + MCycles = 3'b011; + end // else: !if(is_cc_true(F, IR[5:3]) ) + end // case: 3 + + MCycle[3] : + begin + Write = 1'b1; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1100; + end + + MCycle[4] : + begin + Write = 1'b1; + Call = 1'b1; + end + + default :; + endcase + end // if (IR[5] == 1'b0 || Mode != 3 ) + end // case: 8'b11000100,8'b11001100,8'b11010100,8'b11011100,8'b11100100,8'b11101100,8'b11110100,8'b11111100 + + 8'b11001001 : + begin + // RET + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + begin + TStates = 3'b101; + Set_Addr_To = aSP; + end + + MCycle[1] : + begin + IncDec_16 = 4'b0111; + Set_Addr_To = aSP; + LDZ = 1'b1; + end + + MCycle[2] : + begin + Jump = 1'b1; + IncDec_16 = 4'b0111; + end + + default :; + endcase // case(MCycle) + end // case: 8'b11001001 + + 8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000 : + begin + if (IR[5] == 1'b1 && Mode == 3 ) + begin + case (IR[4:3]) + 2'b00 : + begin + // LD ($FF00+nn),A + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + Set_Addr_To = aIOA; + Set_BusB_To = 4'b0111; + end + + MCycle[2] : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 2'b00 + + 2'b01 : + begin + // ADD SP,n + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + ALU_Op = 4'b0000; + Inc_PC = 1'b1; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_BusA_To = 4'b1000; + Set_BusB_To = 4'b0110; + end + + MCycle[2] : + begin + NoRead = 1'b1; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + ALU_Op = 4'b0001; + Set_BusA_To = 4'b1001; + Set_BusB_To = 4'b1110; // Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + end + + default :; + endcase // case(MCycle) + end // case: 2'b01 + + 2'b10 : + begin + // LD A,($FF00+nn) + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + Set_Addr_To = aIOA; + end + + MCycle[2] : + Read_To_Acc = 1'b1; + default :; + endcase // case(MCycle) + end // case: 2'b10 + + 2'b11 : + begin + // LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + MCycle[2] : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + LDW = 1'b1; + end + + MCycle[3] : + begin + Set_BusA_To[2:0] = 3'b101; // L + Read_To_Reg = 1'b1; + Inc_WZ = 1'b1; + Set_Addr_To = aZI; + end + + MCycle[4] : + begin + Set_BusA_To[2:0] = 3'b100; // H + Read_To_Reg = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 2'b11 + + endcase // case(IR[4:3]) + + end + else + begin + // RET cc + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + begin + if (is_cc_true(F, IR[5:3]) ) + begin + Set_Addr_To = aSP; + end + else + begin + MCycles = 3'b001; + end + TStates = 3'b101; + end // case: 1 + + MCycle[1] : + begin + IncDec_16 = 4'b0111; + Set_Addr_To = aSP; + LDZ = 1'b1; + end + MCycle[2] : + begin + Jump = 1'b1; + IncDec_16 = 4'b0111; + end + default :; + endcase + end // else: !if(IR[5] == 1'b1 && Mode == 3 ) + end // case: 8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000 + + 8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111 : + begin + // RST p + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + begin + TStates = 3'b101; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1101; + end + + MCycle[1] : + begin + Write = 1'b1; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1100; + end + + MCycle[2] : + begin + Write = 1'b1; + RstP = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111 + + // INPUT AND OUTPUT GROUP + 8'b11011011 : + begin + if (Mode != 3 ) + begin + // IN A,(n) + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + Set_Addr_To = aIOA; + end + + MCycle[2] : + begin + Read_To_Acc = 1'b1; + IORQ = 1'b1; + end + + default :; + endcase + end // if (Mode != 3 ) + end // case: 8'b11011011 + + 8'b11010011 : + begin + if (Mode != 3 ) + begin + // OUT (n),A + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + Set_Addr_To = aIOA; + Set_BusB_To = 4'b0111; + end + + MCycle[2] : + begin + Write = 1'b1; + IORQ = 1'b1; + end + + default :; + endcase + end // if (Mode != 3 ) + end // case: 8'b11010011 + + + //---------------------------------------------------------------------------- + //---------------------------------------------------------------------------- + // MULTIBYTE INSTRUCTIONS + //---------------------------------------------------------------------------- + //---------------------------------------------------------------------------- + + 8'b11001011 : + begin + if (Mode != 2 ) + begin + Prefix = 2'b01; + end + end + + 8'b11101101 : + begin + if (Mode < 2 ) + begin + Prefix = 2'b10; + end + end + + 8'b11011101,8'b11111101 : + begin + if (Mode < 2 ) + begin + Prefix = 2'b11; + end + end + + endcase // case(IR) + end // case: 2'b00 + + + 2'b01 : + begin + + + //---------------------------------------------------------------------------- + // + // CB prefixed instructions + // + //---------------------------------------------------------------------------- + + Set_BusA_To[2:0] = IR[2:0]; + Set_BusB_To[2:0] = IR[2:0]; + + casez (IR) + 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111, + 8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010111, + 8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001111, + 8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011111, + 8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100111, + 8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101111, + 8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110111, + 8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111111 : + begin + // RLC r + // RL r + // RRC r + // RR r + // SLA r + // SRA r + // SRL r + // SLL r (Undocumented) / SWAP r + if (MCycle[0] ) begin + ALU_Op = 4'b1000; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + end + end // case: 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,... + + 8'b00zzz110 : + begin + // RLC (HL) + // RL (HL) + // RRC (HL) + // RR (HL) + // SRA (HL) + // SRL (HL) + // SLA (HL) + // SLL (HL) (Undocumented) / SWAP (HL) + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0], MCycle[6] : + Set_Addr_To = aXY; + MCycle[1] : + begin + ALU_Op = 4'b1000; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_Addr_To = aXY; + TStates = 3'b100; + end + + MCycle[2] : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b00000110,8'b00010110,8'b00001110,8'b00011110,8'b00101110,8'b00111110,8'b00100110,8'b00110110 + + 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111, + 8'b01001000,8'b01001001,8'b01001010,8'b01001011,8'b01001100,8'b01001101,8'b01001111, + 8'b01010000,8'b01010001,8'b01010010,8'b01010011,8'b01010100,8'b01010101,8'b01010111, + 8'b01011000,8'b01011001,8'b01011010,8'b01011011,8'b01011100,8'b01011101,8'b01011111, + 8'b01100000,8'b01100001,8'b01100010,8'b01100011,8'b01100100,8'b01100101,8'b01100111, + 8'b01101000,8'b01101001,8'b01101010,8'b01101011,8'b01101100,8'b01101101,8'b01101111, + 8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111, + 8'b01111000,8'b01111001,8'b01111010,8'b01111011,8'b01111100,8'b01111101,8'b01111111 : + begin + // BIT b,r + if (MCycle[0] ) + begin + Set_BusB_To[2:0] = IR[2:0]; + ALU_Op = 4'b1001; + end + end // case: 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,... + + 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110 : + begin + // BIT b,(HL) + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0], MCycle[6] : + Set_Addr_To = aXY; + MCycle[1] : + begin + ALU_Op = 4'b1001; + TStates = 3'b100; + end + + default :; + endcase // case(MCycle) + end // case: 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110 + + 8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111, + 8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001111, + 8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010111, + 8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011111, + 8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100111, + 8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101111, + 8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110111, + 8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111111 : + begin + // SET b,r + if (MCycle[0] ) + begin + ALU_Op = 4'b1010; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + end + end // case: 8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111,... + + 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110 : + begin + // SET b,(HL) + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0], MCycle[6] : + Set_Addr_To = aXY; + MCycle[1] : + begin + ALU_Op = 4'b1010; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_Addr_To = aXY; + TStates = 3'b100; + end + MCycle[2] : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110 + + 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111, + 8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001111, + 8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010111, + 8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011111, + 8'b10100000,8'b10100001,8'b10100010,8'b10100011,8'b10100100,8'b10100101,8'b10100111, + 8'b10101000,8'b10101001,8'b10101010,8'b10101011,8'b10101100,8'b10101101,8'b10101111, + 8'b10110000,8'b10110001,8'b10110010,8'b10110011,8'b10110100,8'b10110101,8'b10110111, + 8'b10111000,8'b10111001,8'b10111010,8'b10111011,8'b10111100,8'b10111101,8'b10111111 : + begin + // RES b,r + if (MCycle[0] ) + begin + ALU_Op = 4'b1011; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + end + end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,... + + 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110 : + begin + // RES b,(HL) + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0], MCycle[6] : + Set_Addr_To = aXY; + MCycle[1] : + begin + ALU_Op = 4'b1011; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_Addr_To = aXY; + TStates = 3'b100; + end + + MCycle[2] : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110 + + endcase // case(IR) + end // case: 2'b01 + + + default : + begin : default_ed_block + + //---------------------------------------------------------------------------- + // + // ED prefixed instructions + // + //---------------------------------------------------------------------------- + + casez (IR) + /* + * Undocumented NOP instructions commented out to reduce size of mcode + * + 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000110,8'b00000111 + ,8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001110,8'b00001111 + ,8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010110,8'b00010111 + ,8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011110,8'b00011111 + ,8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100110,8'b00100111 + ,8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101110,8'b00101111 + ,8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110110,8'b00110111 + ,8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111110,8'b00111111 + + + ,8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000110,8'b10000111 + ,8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001110,8'b10001111 + ,8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010110,8'b10010111 + ,8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011110,8'b10011111 + , 8'b10100100,8'b10100101,8'b10100110,8'b10100111 + , 8'b10101100,8'b10101101,8'b10101110,8'b10101111 + , 8'b10110100,8'b10110101,8'b10110110,8'b10110111 + , 8'b10111100,8'b10111101,8'b10111110,8'b10111111 + ,8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000110,8'b11000111 + ,8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001110,8'b11001111 + ,8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010110,8'b11010111 + ,8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011110,8'b11011111 + ,8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100110,8'b11100111 + ,8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101110,8'b11101111 + ,8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110110,8'b11110111 + ,8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111110,8'b11111111 : + ; // NOP, undocumented + + 8'b01111110,8'b01111111 : + // NOP, undocumented + ; + */ + + // 8 BIT LOAD GROUP + 8'b01010111 : + begin + // LD A,I + Special_LD = 3'b100; + TStates = 3'b101; + end + + 8'b01011111 : + begin + // LD A,R + Special_LD = 3'b101; + TStates = 3'b101; + end + + 8'b01000111 : + begin + // LD I,A + Special_LD = 3'b110; + TStates = 3'b101; + end + + 8'b01001111 : + begin + // LD R,A + Special_LD = 3'b111; + TStates = 3'b101; + end + + // 16 BIT LOAD GROUP + 8'b01001011,8'b01011011,8'b01101011,8'b01111011 : + begin + // LD dd,(nn) + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + MCycle[2] : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + LDW = 1'b1; + end + + MCycle[3] : + begin + Read_To_Reg = 1'b1; + if (IR[5:4] == 2'b11 ) + begin + Set_BusA_To = 4'b1000; + end + else + begin + Set_BusA_To[2:1] = IR[5:4]; + Set_BusA_To[0] = 1'b1; + end + Inc_WZ = 1'b1; + Set_Addr_To = aZI; + end // case: 4 + + MCycle[4] : + begin + Read_To_Reg = 1'b1; + if (IR[5:4] == 2'b11 ) + begin + Set_BusA_To = 4'b1001; + end + else + begin + Set_BusA_To[2:1] = IR[5:4]; + Set_BusA_To[0] = 1'b0; + end + end // case: 5 + + default :; + endcase // case(MCycle) + end // case: 8'b01001011,8'b01011011,8'b01101011,8'b01111011 + + + 8'b01000011,8'b01010011,8'b01100011,8'b01110011 : + begin + // LD (nn),dd + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + MCycle[2] : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + LDW = 1'b1; + if (IR[5:4] == 2'b11 ) + begin + Set_BusB_To = 4'b1000; + end + else + begin + Set_BusB_To[2:1] = IR[5:4]; + Set_BusB_To[0] = 1'b1; + Set_BusB_To[3] = 1'b0; + end + end // case: 3 + + MCycle[3] : + begin + Inc_WZ = 1'b1; + Set_Addr_To = aZI; + Write = 1'b1; + if (IR[5:4] == 2'b11 ) + begin + Set_BusB_To = 4'b1001; + end + else + begin + Set_BusB_To[2:1] = IR[5:4]; + Set_BusB_To[0] = 1'b0; + Set_BusB_To[3] = 1'b0; + end + end // case: 4 + + MCycle[4] : + begin + Write = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b01000011,8'b01010011,8'b01100011,8'b01110011 + + 8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000 : + begin + // LDI, LDD, LDIR, LDDR + MCycles = 3'b100; + case (1'b1) // MCycle + MCycle[0] : + begin + Set_Addr_To = aXY; + IncDec_16 = 4'b1100; // BC + end + + MCycle[1] : + begin + Set_BusB_To = 4'b0110; + Set_BusA_To[2:0] = 3'b111; + ALU_Op = 4'b0000; + Set_Addr_To = aDE; + if (IR[3] == 1'b0 ) + begin + IncDec_16 = 4'b0110; // IX + end + else + begin + IncDec_16 = 4'b1110; + end + end // case: 2 + + MCycle[2] : + begin + I_BT = 1'b1; + TStates = 3'b101; + Write = 1'b1; + if (IR[3] == 1'b0 ) + begin + IncDec_16 = 4'b0101; // DE + end + else + begin + IncDec_16 = 4'b1101; + end + end // case: 3 + + MCycle[3] : + begin + NoRead = 1'b1; + TStates = 3'b101; + end + + default :; + endcase // case(MCycle) + end // case: 8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000 + + 8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001 : + begin + // CPI, CPD, CPIR, CPDR + MCycles = 3'b100; + case (1'b1) // MCycle + MCycle[0] : + begin + Set_Addr_To = aXY; + IncDec_16 = 4'b1100; // BC + end + + MCycle[1] : + begin + Set_BusB_To = 4'b0110; + Set_BusA_To[2:0] = 3'b111; + ALU_Op = 4'b0111; + Save_ALU = 1'b1; + PreserveC = 1'b1; + if (IR[3] == 1'b0 ) + begin + IncDec_16 = 4'b0110; + end + else + begin + IncDec_16 = 4'b1110; + end + end // case: 2 + + MCycle[2] : + begin + NoRead = 1'b1; + I_BC = 1'b1; + TStates = 3'b101; + end + + MCycle[3] : + begin + NoRead = 1'b1; + TStates = 3'b101; + end + + default :; + endcase // case(MCycle) + end // case: 8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001 + + 8'b01000100,8'b01001100,8'b01010100,8'b01011100,8'b01100100,8'b01101100,8'b01110100,8'b01111100 : + begin + // NEG + ALU_Op = 4'b0010; + Set_BusB_To = 4'b0111; + Set_BusA_To = 4'b1010; + Read_To_Acc = 1'b1; + Save_ALU = 1'b1; + end + + 8'b01000110,8'b01001110,8'b01100110,8'b01101110 : + begin + // IM 0 + IMode = 2'b00; + end + + 8'b01010110,8'b01110110 : + // IM 1 + IMode = 2'b01; + + 8'b01011110,8'b01110111 : + // IM 2 + IMode = 2'b10; + + // 16 bit arithmetic + 8'b01001010,8'b01011010,8'b01101010,8'b01111010 : + begin + // ADC HL,ss + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + NoRead = 1'b1; + ALU_Op = 4'b0001; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_BusA_To[2:0] = 3'b101; + case (IR[5:4]) + 0,1,2 : + begin + Set_BusB_To[2:1] = IR[5:4]; + Set_BusB_To[0] = 1'b1; + end + default : + Set_BusB_To = 4'b1000; + endcase + TStates = 3'b100; + end // case: 2 + + MCycle[2] : + begin + NoRead = 1'b1; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + ALU_Op = 4'b0001; + Set_BusA_To[2:0] = 3'b100; + case (IR[5:4]) + 0,1,2 : + begin + Set_BusB_To[2:1] = IR[5:4]; + Set_BusB_To[0] = 1'b0; + end + default : + Set_BusB_To = 4'b1001; + endcase // case(IR[5:4]) + end // case: 3 + + default :; + endcase // case(MCycle) + end // case: 8'b01001010,8'b01011010,8'b01101010,8'b01111010 + + 8'b01000010,8'b01010010,8'b01100010,8'b01110010 : + begin + // SBC HL,ss + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + NoRead = 1'b1; + ALU_Op = 4'b0011; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_BusA_To[2:0] = 3'b101; + case (IR[5:4]) + 0,1,2 : + begin + Set_BusB_To[2:1] = IR[5:4]; + Set_BusB_To[0] = 1'b1; + end + default : + Set_BusB_To = 4'b1000; + endcase + TStates = 3'b100; + end // case: 2 + + MCycle[2] : + begin + NoRead = 1'b1; + ALU_Op = 4'b0011; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_BusA_To[2:0] = 3'b100; + case (IR[5:4]) + 0,1,2 : + Set_BusB_To[2:1] = IR[5:4]; + default : + Set_BusB_To = 4'b1001; + endcase + end // case: 3 + + default :; + + endcase // case(MCycle) + end // case: 8'b01000010,8'b01010010,8'b01100010,8'b01110010 + + 8'b01101111 : + begin + // RLD + MCycles = 3'b100; + case (1'b1) // MCycle + MCycle[1] : + begin + NoRead = 1'b1; + Set_Addr_To = aXY; + end + + MCycle[2] : + begin + Read_To_Reg = 1'b1; + Set_BusB_To[2:0] = 3'b110; + Set_BusA_To[2:0] = 3'b111; + ALU_Op = 4'b1101; + TStates = 3'b100; + Set_Addr_To = aXY; + Save_ALU = 1'b1; + end + + MCycle[3] : + begin + I_RLD = 1'b1; + Write = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b01101111 + + 8'b01100111 : + begin + // RRD + MCycles = 3'b100; + case (1'b1) // MCycle + MCycle[1] : + Set_Addr_To = aXY; + MCycle[2] : + begin + Read_To_Reg = 1'b1; + Set_BusB_To[2:0] = 3'b110; + Set_BusA_To[2:0] = 3'b111; + ALU_Op = 4'b1110; + TStates = 3'b100; + Set_Addr_To = aXY; + Save_ALU = 1'b1; + end + + MCycle[3] : + begin + I_RRD = 1'b1; + Write = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b01100111 + + 8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101 : + begin + // RETI, RETN + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aSP; + + MCycle[1] : + begin + IncDec_16 = 4'b0111; + Set_Addr_To = aSP; + LDZ = 1'b1; + end + + MCycle[2] : + begin + Jump = 1'b1; + IncDec_16 = 4'b0111; + I_RETN = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101 + + 8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000 : + begin + // IN r,(C) + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aBC; + + MCycle[1] : + begin + IORQ = 1'b1; + if (IR[5:3] != 3'b110 ) + begin + Read_To_Reg = 1'b1; + Set_BusA_To[2:0] = IR[5:3]; + end + I_INRC = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000 + + 8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001 : + begin + // OUT (C),r + // OUT (C),0 + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0] : + begin + Set_Addr_To = aBC; + Set_BusB_To[2:0] = IR[5:3]; + if (IR[5:3] == 3'b110 ) + begin + Set_BusB_To[3] = 1'b1; + end + end + + MCycle[1] : + begin + Write = 1'b1; + IORQ = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001 + + 8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010 : + begin + // INI, IND, INIR, INDR + MCycles = 3'b100; + case (1'b1) // MCycle + MCycle[0] : + begin + Set_Addr_To = aBC; + Set_BusB_To = 4'b1010; + Set_BusA_To = 4'b0000; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + ALU_Op = 4'b0010; + end + + MCycle[1] : + begin + IORQ = 1'b1; + Set_BusB_To = 4'b0110; + Set_Addr_To = aXY; + end + + MCycle[2] : + begin + if (IR[3] == 1'b0 ) + begin + IncDec_16 = 4'b0110; + end + else + begin + IncDec_16 = 4'b1110; + end + TStates = 3'b100; + Write = 1'b1; + I_BTR = 1'b1; + end // case: 3 + + MCycle[3] : + begin + NoRead = 1'b1; + TStates = 3'b101; + end + + default :; + endcase // case(MCycle) + end // case: 8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010 + + 8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011 : + begin + // OUTI, OUTD, OTIR, OTDR + MCycles = 3'b100; + case (1'b1) // MCycle + MCycle[0] : + begin + TStates = 3'b101; + Set_Addr_To = aXY; + Set_BusB_To = 4'b1010; + Set_BusA_To = 4'b0000; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + ALU_Op = 4'b0010; + end + + MCycle[1] : + begin + Set_BusB_To = 4'b0110; + Set_Addr_To = aBC; + if (IR[3] == 1'b0 ) + begin + IncDec_16 = 4'b0110; + end + else + begin + IncDec_16 = 4'b1110; + end + end + + MCycle[2] : + begin + if (IR[3] == 1'b0 ) + begin + IncDec_16 = 4'b0010; + end + else + begin + IncDec_16 = 4'b1010; + end + IORQ = 1'b1; + Write = 1'b1; + I_BTR = 1'b1; + end // case: 3 + + MCycle[3] : + begin + NoRead = 1'b1; + TStates = 3'b101; + end + + default :; + endcase // case(MCycle) + end // case: 8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011 + + default : ; + + endcase // case(IR) + end // block: default_ed_block + endcase // case(ISet) + + if (Mode == 1 ) + begin + if (MCycle[0] ) + begin + //TStates = 3'b100; + end + else + begin + TStates = 3'b011; + end + end + + if (Mode == 3 ) + begin + if (MCycle[0] ) + begin + //TStates = 3'b100; + end + else + begin + TStates = 3'b100; + end + end + + if (Mode < 2 ) + begin + if (MCycle[5] ) + begin + Inc_PC = 1'b1; + if (Mode == 1 ) + begin + Set_Addr_To = aXY; + TStates = 3'b100; + Set_BusB_To[2:0] = SSS; + Set_BusB_To[3] = 1'b0; + end + if (IR == 8'b00110110 || IR == 8'b11001011 ) + begin + Set_Addr_To = aNone; + end + end + if (MCycle[6] ) + begin + if (Mode == 0 ) + begin + TStates = 3'b101; + end + if (ISet != 2'b01 ) + begin + Set_Addr_To = aXY; + end + Set_BusB_To[2:0] = SSS; + Set_BusB_To[3] = 1'b0; + if (IR == 8'b00110110 || ISet == 2'b01 ) + begin + // LD (HL),n + Inc_PC = 1'b1; + end + else + begin + NoRead = 1'b1; + end + end + end // if (Mode < 2 ) + + end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle) +endmodule // T80_MCode diff --git a/modules/TV80/tv80_reg.v b/modules/TV80/tv80_reg.v new file mode 100644 index 0000000..889766c --- /dev/null +++ b/modules/TV80/tv80_reg.v @@ -0,0 +1,77 @@ +// +// TV80 8-Bit Microprocessor Core +// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) +// +// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +module tv80_reg (/*AUTOARG*/ + // Outputs + DOBH, DOAL, DOCL, DOBL, DOCH, DOAH, + // Inputs + AddrC, AddrA, AddrB, DIH, DIL, clk, CEN, WEH, WEL + ); + input [2:0] AddrC; + output [7:0] DOBH; + input [2:0] AddrA; + input [2:0] AddrB; + input [7:0] DIH; + output [7:0] DOAL; + output [7:0] DOCL; + input [7:0] DIL; + output [7:0] DOBL; + output [7:0] DOCH; + output [7:0] DOAH; + input clk, CEN, WEH, WEL; + + reg [7:0] RegsH [0:7]; + reg [7:0] RegsL [0:7]; + + always @(posedge clk) + begin + if (CEN) + begin + if (WEH) RegsH[AddrA] <= DIH; + if (WEL) RegsL[AddrA] <= DIL; + end + end + + assign DOAH = RegsH[AddrA]; + assign DOAL = RegsL[AddrA]; + assign DOBH = RegsH[AddrB]; + assign DOBL = RegsL[AddrB]; + assign DOCH = RegsH[AddrC]; + assign DOCL = RegsL[AddrC]; + + // break out ram bits for waveform debug +// synopsys translate_off + wire [7:0] B = RegsH[0]; + wire [7:0] C = RegsL[0]; + wire [7:0] D = RegsH[1]; + wire [7:0] E = RegsL[1]; + wire [7:0] H = RegsH[2]; + wire [7:0] L = RegsL[2]; + + wire [15:0] IX = { RegsH[3], RegsL[3] }; + wire [15:0] IY = { RegsH[7], RegsL[7] }; +// synopsys translate_on + +endmodule + diff --git a/modules/TV80/tv80n.v b/modules/TV80/tv80n.v new file mode 100644 index 0000000..d672608 --- /dev/null +++ b/modules/TV80/tv80n.v @@ -0,0 +1,182 @@ +// +// TV80 8-Bit Microprocessor Core +// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) +// +// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +// Negative-edge based wrapper allows memory wait_n signal to work +// correctly without resorting to asynchronous logic. + +module tv80n (/*AUTOARG*/ + // Outputs + m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout, + // Inputs + reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di + ); + + parameter Mode = 0; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + parameter T2Write = 0; // 0 => wr_n active in T3, /=0 => wr_n active in T2 + parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle + + + input reset_n; + input clk; + input wait_n; + input int_n; + input nmi_n; + input busrq_n; + output m1_n; + output mreq_n; + output iorq_n; + output rd_n; + output wr_n; + output rfsh_n; + output halt_n; + output busak_n; + output [15:0] A; + input [7:0] di; + output [7:0] dout; + + reg mreq_n; + reg iorq_n; + reg rd_n; + reg wr_n; + reg nxt_mreq_n; + reg nxt_iorq_n; + reg nxt_rd_n; + reg nxt_wr_n; + + wire cen; + wire intcycle_n; + wire no_read; + wire write; + wire iorq; + reg [7:0] di_reg; + wire [6:0] mcycle; + wire [6:0] tstate; + + assign cen = 1; + + tv80_core #(Mode, IOWait) i_tv80_core + ( + .cen (cen), + .m1_n (m1_n), + .iorq (iorq), + .no_read (no_read), + .write (write), + .rfsh_n (rfsh_n), + .halt_n (halt_n), + .wait_n (wait_n), + .int_n (int_n), + .nmi_n (nmi_n), + .reset_n (reset_n), + .busrq_n (busrq_n), + .busak_n (busak_n), + .clk (clk), + .IntE (), + .stop (), + .A (A), + .dinst (di), + .di (di_reg), + .dout (dout), + .mc (mcycle), + .ts (tstate), + .intcycle_n (intcycle_n) + ); + + always @* + begin + nxt_mreq_n = 1; + nxt_rd_n = 1; + nxt_iorq_n = 1; + nxt_wr_n = 1; + + if (mcycle[0]) + begin + if (tstate[1] || tstate[2]) + begin + nxt_rd_n = ~ intcycle_n; + nxt_mreq_n = ~ intcycle_n; + nxt_iorq_n = intcycle_n; + end + end // if (mcycle[0]) + else + begin + if ((tstate[1] || tstate[2]) && !no_read && !write) + begin + nxt_rd_n = 1'b0; + nxt_iorq_n = ~ iorq; + nxt_mreq_n = iorq; + end + if (T2Write == 0) + begin + if (tstate[2] && write) + begin + nxt_wr_n = 1'b0; + nxt_iorq_n = ~ iorq; + nxt_mreq_n = iorq; + end + end + else + begin + if ((tstate[1] || (tstate[2] && !wait_n)) && write) + begin + nxt_wr_n = 1'b0; + nxt_iorq_n = ~ iorq; + nxt_mreq_n = iorq; + end + end // else: !if(T2write == 0) + end // else: !if(mcycle[0]) + end // always @ * + + always @(negedge clk) + begin + if (!reset_n) + begin + rd_n <= #1 1'b1; + wr_n <= #1 1'b1; + iorq_n <= #1 1'b1; + mreq_n <= #1 1'b1; + end + else + begin + rd_n <= #1 nxt_rd_n; + wr_n <= #1 nxt_wr_n; + iorq_n <= #1 nxt_iorq_n; + mreq_n <= #1 nxt_mreq_n; + end // else: !if(!reset_n) + end // always @ (posedge clk or negedge reset_n) + + always @(posedge clk) + begin + if (!reset_n) + begin + di_reg <= #1 0; + end + else + begin + if (tstate[2] && wait_n == 1'b1) + di_reg <= #1 di; + end // else: !if(!reset_n) + end // always @ (posedge clk) + +endmodule // t80n + diff --git a/modules/TV80/tv80s.v b/modules/TV80/tv80s.v new file mode 100644 index 0000000..3d825cb --- /dev/null +++ b/modules/TV80/tv80s.v @@ -0,0 +1,162 @@ +// +// TV80 8-Bit Microprocessor Core +// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) +// +// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +module tv80s (/*AUTOARG*/ + // Outputs + m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout, + // Inputs + reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di + ); + + parameter Mode = 0; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + parameter T2Write = 1; // 0 => wr_n active in T3, /=0 => wr_n active in T2 + parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle + + + input reset_n; + input clk; + input wait_n; + input int_n; + input nmi_n; + input busrq_n; + output m1_n; + output mreq_n; + output iorq_n; + output rd_n; + output wr_n; + output rfsh_n; + output halt_n; + output busak_n; + output [15:0] A; + input [7:0] di; + output [7:0] dout; + + reg mreq_n; + reg iorq_n; + reg rd_n; + reg wr_n; + + wire cen; + wire intcycle_n; + wire no_read; + wire write; + wire iorq; + reg [7:0] di_reg; + wire [6:0] mcycle; + wire [6:0] tstate; + + assign cen = 1; + + tv80_core #(Mode, IOWait) i_tv80_core + ( + .cen (cen), + .m1_n (m1_n), + .iorq (iorq), + .no_read (no_read), + .write (write), + .rfsh_n (rfsh_n), + .halt_n (halt_n), + .wait_n (wait_n), + .int_n (int_n), + .nmi_n (nmi_n), + .reset_n (reset_n), + .busrq_n (busrq_n), + .busak_n (busak_n), + .clk (clk), + .IntE (), + .stop (), + .A (A), + .dinst (di), + .di (di_reg), + .dout (dout), + .mc (mcycle), + .ts (tstate), + .intcycle_n (intcycle_n) + ); + + always @(posedge clk or negedge reset_n) + begin + if (!reset_n) + begin + rd_n <= #1 1'b1; + wr_n <= #1 1'b1; + iorq_n <= #1 1'b1; + mreq_n <= #1 1'b1; + di_reg <= #1 0; + end + else + begin + rd_n <= #1 1'b1; + wr_n <= #1 1'b1; + iorq_n <= #1 1'b1; + mreq_n <= #1 1'b1; + if (mcycle[0]) + begin + if (tstate[1] || (tstate[2] && wait_n == 1'b0)) + begin + rd_n <= #1 ~ intcycle_n; + mreq_n <= #1 ~ intcycle_n; + iorq_n <= #1 intcycle_n; + end + `ifdef TV80_REFRESH + if (tstate[3]) + mreq_n <= #1 1'b0; + `endif + end // if (mcycle[0]) + else + begin + if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && no_read == 1'b0 && write == 1'b0) + begin + rd_n <= #1 1'b0; + iorq_n <= #1 ~ iorq; + mreq_n <= #1 iorq; + end + if (T2Write == 0) + begin + if (tstate[2] && write == 1'b1) + begin + wr_n <= #1 1'b0; + iorq_n <= #1 ~ iorq; + mreq_n <= #1 iorq; + end + end + else + begin + if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && write == 1'b1) + begin + wr_n <= #1 1'b0; + iorq_n <= #1 ~ iorq; + mreq_n <= #1 iorq; + end + end // else: !if(T2write == 0) + + end // else: !if(mcycle[0]) + + if (tstate[2] && wait_n == 1'b1) + di_reg <= #1 di; + end // else: !if(!reset_n) + end // always @ (posedge clk or negedge reset_n) + +endmodule // t80s + diff --git a/modules/arcade-hiscore/hiscore.v b/modules/arcade-hiscore/hiscore.v new file mode 100644 index 0000000..36f88f9 --- /dev/null +++ b/modules/arcade-hiscore/hiscore.v @@ -0,0 +1,818 @@ +//============================================================================ +// MAME hiscore.dat support for MiSTer arcade cores. +// +// https://github.com/JimmyStones/Hiscores_MiSTer +// +// Copyright (c) 2021 Alan Steremberg +// Copyright (c) 2021 Jim Gregory +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 3 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ +/* + Version history: + 0001 - 2021-03-06 - First marked release + 0002 - 2021-03-06 - Added HS_DUMPFORMAT localparam to identify dump version (for future use) + Add HS_CONFIGINDEX and HS_DUMPINDEX parameters to configure ioctl_indexes + 0003 - 2021-03-10 - Added WRITE_REPEATCOUNT and WRITE_REPEATWAIT to handle tricky write situations + 0004 - 2021-03-15 - Fix ram_access assignment + 0005 - 2021-03-18 - Add configurable score table width, clean up some stupid mistakes + 0006 - 2021-03-27 - Move 'tweakable' parameters into MRA data header + 0007 - 2021-04-15 - Improve state machine maintainability, add new 'pause padding' states + 0008 - 2021-05-12 - Feed back core-level pause to halt startup timer + 0009 - 2021-07-31 - Split hiscore extraction from upload (updates hiscore buffer on OSD open) + 0010 - 2021-08-03 - Add hiscore buffer and change detection (ready for autosave!) + 0011 - 2021-08-07 - Optional auto-save on OSD open + 0012 - 2021-08-17 - Add variable length change detection mask + 0013 - 2021-09-01 - Output configured signal for autosave option menu masking + 0014 - 2021-09-09 - Fix turning on autosave w/o core reload +============================================================================ +*/ + +`timescale 1 ps / 1 ps + +module hiscore +#( + parameter HS_ADDRESSWIDTH=10, // Max size of game RAM address for highscores + parameter HS_SCOREWIDTH=8, // Max size of capture RAM For highscore data (default 8 = 256 bytes max) + parameter HS_CONFIGINDEX=3, // ioctl_index for config transfer + parameter HS_DUMPINDEX=4, // ioctl_index for dump transfer + parameter CFG_ADDRESSWIDTH=4, // Max size of RAM address for highscore.dat entries (default 4 = 16 entries max) + parameter CFG_LENGTHWIDTH=1 // Max size of length for each highscore.dat entries (default 1 = 256 bytes max) +) +( + input clk, + input paused, // Signal from core confirming CPU is paused + input reset, + input autosave, // Auto-save enabled (active high) + + input ioctl_upload, + output reg ioctl_upload_req, + input ioctl_download, + input ioctl_wr, + input [24:0] ioctl_addr, + input [7:0] ioctl_index, + input OSD_STATUS, + + input [7:0] data_from_hps, // Incoming data from HPS ioctl_dout + input [7:0] data_from_ram, // Incoming data from game RAM + output [HS_ADDRESSWIDTH-1:0] ram_address, // Address in game RAM to read/write score data + output [7:0] data_to_hps, // Data to send to HPS ioctl_din + output [7:0] data_to_ram, // Data to send to game RAM + output reg ram_write, // Write to game RAM (active high) + output ram_intent_read, // RAM read required (active high) + output ram_intent_write, // RAM write required (active high) + output reg pause_cpu, // Pause core CPU to prepare for/relax after RAM access + output configured // Hiscore module has valid configuration (active high) +); + +// Parameters read from config header +reg [31:0] START_WAIT =32'd0; // Delay before beginning check process +reg [15:0] CHECK_WAIT =16'hFF; // Delay between start/end check attempts +reg [15:0] CHECK_HOLD =16'd2; // Hold time for start/end check reads +reg [15:0] WRITE_HOLD =16'd2; // Hold time for game RAM writes +reg [15:0] WRITE_REPEATCOUNT =16'b1; // Number of times to write score to game RAM +reg [15:0] WRITE_REPEATWAIT =16'b1111; // Delay between subsequent write attempts to game RAM +reg [7:0] ACCESS_PAUSEPAD =8'd4; // Cycles to wait with paused CPU before and after RAM access +reg [7:0] CHANGEMASK =1'b0; // Length of change mask + +// State machine constants +localparam SM_STATEWIDTH = 5; // Width of state machine net + +localparam SM_INIT_RESTORE = 0; +localparam SM_TIMER = 1; + +localparam SM_CHECKPREP = 2; +localparam SM_CHECKBEGIN = 3; +localparam SM_CHECKSTARTVAL = 4; +localparam SM_CHECKENDVAL = 5; +localparam SM_CHECKCANCEL = 6; + +localparam SM_WRITEPREP = 7; +localparam SM_WRITEBEGIN = 8; +localparam SM_WRITEREADY = 9; +localparam SM_WRITEDONE = 10; +localparam SM_WRITECOMPLETE = 11; +localparam SM_WRITERETRY = 12; + +localparam SM_COMPAREINIT = 16; +localparam SM_COMPAREBEGIN = 17; +localparam SM_COMPAREREADY = 18; +localparam SM_COMPAREREAD = 19; +localparam SM_COMPAREDONE = 20; +localparam SM_COMPARECOMPLETE = 21; + +localparam SM_EXTRACTINIT = 22; +localparam SM_EXTRACT = 23; +localparam SM_EXTRACTSAVE = 24; +localparam SM_EXTRACTCOMPLETE = 25; + +localparam SM_STOPPED = 30; + +/* +Hiscore config data structure (version 1) +----------------------------------------- +[16 byte header] +[8 byte * no. of entries] + +- Header format +00 00 FF FF 00 FF 00 02 00 02 00 01 11 11 00 00 +[ SW ] [ CW] [ CH] [ WH] [WRC] [WRW] [PAD] +4 byte START_WAIT +2 byte CHECK_WAIT +2 byte CHECK_HOLD +2 byte WRITE_HOLD +2 byte WRITE_REPEATCOUNT +2 byte WRITE_REPEATWAIT +1 byte ACCESS_PAUSEPAD +1 byte CHANGEMASK + +- Entry format (when CFG_LENGTHWIDTH=1) +00 00 43 0b 0f 10 01 00 +00 00 40 23 02 04 12 00 +[ ADDR ] LEN START END PAD + +4 bytes Address of ram entry (in core memory map) +1 byte Length of ram entry in bytes +1 byte Start value to check for at start of address range before proceeding +1 byte End value to check for at end of address range before proceeding +1 byte (padding) + +- Entry format (when CFG_LENGTHWIDTH=2) +00 00 43 0b 00 0f 10 01 +00 00 40 23 00 02 04 12 +[ ADDR ] [LEN ] START END + +4 bytes Address of ram entry (in core memory map) +2 bytes Length of ram entry in bytes +1 byte Start value to check for at start of address range before proceeding +1 byte End value to check for at end of address range before proceeding + +*/ + +localparam HS_VERSION =14; // Version identifier for module +localparam HS_DUMPFORMAT =1; // Version identifier for dump format +localparam HS_HEADERLENGTH =16; // Size of header chunk (default=16 bytes) + +// HS_DUMPFORMAT = 1 --> No header, just the extracted hiscore data + +// Hiscore config tracking +wire downloading_config; // Is hiscore configuration currently being loaded from HPS? +reg downloaded_config = 1'b0; // Has hiscore configuration been loaded successfully +wire parsing_header; // Is hiscore configuration header currently being parsed? +wire parsing_mask; // Is hiscore configuration change mask currently being parsed? (optional 2nd line of config) + +// Hiscore data tracking +wire downloading_dump; // Is hiscore data currently being loaded from HPS? +reg downloaded_dump = 1'b0; // Has hiscore data been loaded successfully +wire uploading_dump; // Is hiscore data currently being sent to HPS? +reg extracting_dump = 1'b0; // Is hiscore data currently being extracted from game RAM? +reg restoring_dump = 1'b0; // Is hiscore data currently being (or waiting to) restore to game RAM + +reg checking_scores = 1'b0; // Is state machine currently checking game RAM for highscore restore readiness +reg reading_scores = 1'b0; // Is state machine currently reading game RAM for highscore dump +reg writing_scores = 1'b0; // Is state machine currently restoring hiscore data to game RAM + +reg [3:0] initialised; // Number of times state machine has been initialised (debug only) + +assign configured = downloaded_config; +assign downloading_config = ioctl_download && (ioctl_index==HS_CONFIGINDEX); +assign parsing_header = downloading_config && (ioctl_addr 8'b0) && (ioctl_addr < HS_HEADERLENGTH + CHANGEMASK); +assign downloading_dump = ioctl_download && (ioctl_index==HS_DUMPINDEX); +assign uploading_dump = ioctl_upload && (ioctl_index==HS_DUMPINDEX); +assign ram_intent_read = reading_scores | checking_scores; +assign ram_intent_write = writing_scores; +assign ram_address = ram_addr[HS_ADDRESSWIDTH-1:0]; + +reg [(SM_STATEWIDTH-1):0] state = SM_INIT_RESTORE; // Current state machine index +reg [(SM_STATEWIDTH-1):0] next_state = SM_INIT_RESTORE; // Next state machine index to move to after wait timer expires +reg [31:0] wait_timer; // Wait timer for inital/read/write delays + +reg [CFG_ADDRESSWIDTH-1:0] counter = 1'b0; // Index for current config table entry +reg [CFG_ADDRESSWIDTH-1:0] total_entries = 1'b0; // Total count of config table entries +reg reset_last = 1'b0; // Last cycle reset +reg [7:0] write_counter = 1'b0; // Index of current game RAM write attempt + +reg [255:0] change_mask; // Bit mask for dump change check + +reg [7:0] last_ioctl_index; // Last cycle HPS IO index +reg last_ioctl_download = 0;// Last cycle HPS IO download +reg [7:0] last_data_from_hps; // Last cycle HPS IO data out +reg [7:0] last_data_from_hps2; // Last cycle +1 HPS IO data out +reg [7:0] last_data_from_hps3; // Last cycle +2 HPS IO data out +reg last_OSD_STATUS; // Last cycle OSD status + +reg [24:0] ram_addr; // Target RAM address for hiscore read/write +reg [24:0] base_io_addr; +wire [23:0] addr_base /* synthesis keep */; +wire [(CFG_LENGTHWIDTH*8)-1:0] length; +wire [24:0] end_addr = (addr_base + length - 1'b1); +reg [HS_SCOREWIDTH-1:0] data_addr; +reg [HS_SCOREWIDTH-1:0] buffer_addr; +wire [7:0] start_val /* synthesis keep */; +wire [7:0] end_val /* synthesis keep */; + +wire [7:0] hiscore_data_out /* synthesis keep */; +reg dump_write = 1'b0; +wire [7:0] hiscore_buffer_out /* synthesis keep */; +reg buffer_write = 1'b0; +reg [19:0] compare_length = 1'b0; +reg compare_nonzero = 1'b1; // High after extract and compare if any byte returned is non-zero +reg compare_changed = 1'b1; // High after extract and compare if any byte is different to current hiscore data +wire check_mask = change_mask[compare_length]/* synthesis keep */; +reg dump_dirty = 1'b0; // High if dump has changed since last save (or first load if no save has occurred) + +wire [23:0] address_data_in; +wire [(CFG_LENGTHWIDTH*8)-1:0] length_data_in; + +assign address_data_in = {last_data_from_hps2, last_data_from_hps, data_from_hps}; +assign length_data_in = (CFG_LENGTHWIDTH == 1'b1) ? data_from_hps : {last_data_from_hps, data_from_hps}; + +wire parsing_config = ~(parsing_header | parsing_mask); // Hiscore config lines are being parsed + +wire [CFG_ADDRESSWIDTH-1:0] config_upload_addr = ioctl_addr[CFG_ADDRESSWIDTH+2:3] - (9'd2 + CHANGEMASK[7:3]) /* synthesis keep */; + +wire address_we = downloading_config & parsing_config & (ioctl_addr[2:0] == 3'd3); +wire length_we = downloading_config & parsing_config & (ioctl_addr[2:0] == 3'd3 + CFG_LENGTHWIDTH); +wire startdata_we = downloading_config & parsing_config & (ioctl_addr[2:0] == 3'd4 + CFG_LENGTHWIDTH); +wire enddata_we = downloading_config & parsing_config & (ioctl_addr[2:0] == 3'd5 + CFG_LENGTHWIDTH); + +// RAM chunks used to store configuration data +// - Address table +dpram_hs #(.aWidth(CFG_ADDRESSWIDTH),.dWidth(24)) +address_table( + .clk(clk), + .addr_a(config_upload_addr), + .we_a(address_we & ioctl_wr), + .d_a(address_data_in), + .addr_b(counter), + .q_b(addr_base) +); +// Length table - variable width depending on CFG_LENGTHWIDTH +dpram_hs #(.aWidth(CFG_ADDRESSWIDTH),.dWidth(CFG_LENGTHWIDTH*8)) +length_table( + .clk(clk), + .addr_a(config_upload_addr), + .we_a(length_we & ioctl_wr), + .d_a(length_data_in), + .addr_b(counter), + .q_b(length) +); +// - Start data table +dpram_hs #(.aWidth(CFG_ADDRESSWIDTH),.dWidth(8)) +startdata_table( + .clk(clk), + .addr_a(config_upload_addr), + .we_a(startdata_we & ioctl_wr), + .d_a(data_from_hps), + .addr_b(counter), + .q_b(start_val) +); +// - End data table +dpram_hs #(.aWidth(CFG_ADDRESSWIDTH),.dWidth(8)) +enddata_table( + .clk(clk), + .addr_a(config_upload_addr), + .we_a(enddata_we & ioctl_wr), + .d_a(data_from_hps), + .addr_b(counter), + .q_b(end_val) +); + +// RAM chunk used to store valid hiscore data +dpram_hs #(.aWidth(HS_SCOREWIDTH),.dWidth(8)) +hiscore_data ( + .clk(clk), + .addr_a(ioctl_addr[(HS_SCOREWIDTH-1):0]), + .we_a(downloading_dump), + .d_a(data_from_hps), + .addr_b(data_addr), + .we_b(dump_write), + .d_b(hiscore_buffer_out), + .q_b(hiscore_data_out) +); +// RAM chunk used to store temporary high score data +dpram_hs #(.aWidth(HS_SCOREWIDTH),.dWidth(8)) +hiscore_buffer ( + .clk(clk), + .addr_a(buffer_addr), + .we_a(buffer_write), + .d_a(data_from_ram), + .q_a(hiscore_buffer_out) +); + +assign data_to_ram = hiscore_data_out; +assign data_to_hps = hiscore_data_out; + +wire [3:0] header_chunk = ioctl_addr[3:0]; +wire [7:0] mask_chunk = ioctl_addr[7:0] - 5'd16; +wire [255:0] mask_load_index = mask_chunk * 8; + +always @(posedge clk) +begin + + if (downloading_config) + begin + // Get header chunk data + if(parsing_header) + begin + if(ioctl_wr) + begin + if(header_chunk == 4'd3) START_WAIT <= { last_data_from_hps3, last_data_from_hps2, last_data_from_hps, data_from_hps }; + if(header_chunk == 4'd5) CHECK_WAIT <= { last_data_from_hps, data_from_hps }; + if(header_chunk == 4'd7) CHECK_HOLD <= { last_data_from_hps, data_from_hps }; + if(header_chunk == 4'd9) WRITE_HOLD <= { last_data_from_hps, data_from_hps }; + if(header_chunk == 4'd11) WRITE_REPEATCOUNT <= { last_data_from_hps, data_from_hps }; + if(header_chunk == 4'd13) WRITE_REPEATWAIT <= { last_data_from_hps, data_from_hps }; + if(header_chunk == 4'd14) ACCESS_PAUSEPAD <= data_from_hps; + if(header_chunk == 4'd15) CHANGEMASK <= data_from_hps; + end + end + else + if(parsing_mask) + begin + if(ioctl_wr == 1'b1) change_mask[mask_load_index +: 8] <= data_from_hps; + end + else + begin + // Keep track of the largest entry during config download + total_entries <= config_upload_addr; + end + end + + // Track completion of configuration and dump download + if ((last_ioctl_download != ioctl_download) && (ioctl_download == 1'b0)) + begin + if (last_ioctl_index==HS_CONFIGINDEX) downloaded_config <= 1'b1; + if (last_ioctl_index==HS_DUMPINDEX) downloaded_dump <= 1'b1; + end + + // Track last cycle values + last_ioctl_download <= ioctl_download; + last_ioctl_index <= ioctl_index; + last_OSD_STATUS <= OSD_STATUS; + + // Cascade incoming data bytes from HPS + if(ioctl_download && ioctl_wr) + begin + last_data_from_hps3 = last_data_from_hps2; + last_data_from_hps2 = last_data_from_hps; + last_data_from_hps = data_from_hps; + end + + // If we have a valid configuration then enable the hiscore system + if(downloaded_config) + begin + + // Check for end of core reset to initialise state machine for restore + reset_last <= reset; + if (downloaded_dump == 1'b1 && reset_last == 1'b1 && reset == 1'b0) + begin + wait_timer <= START_WAIT; + next_state <= SM_INIT_RESTORE; + state <= SM_TIMER; + counter <= 1'b0; + initialised <= initialised + 1'b1; + restoring_dump <= 1'b1; + end + else + begin + // Upload scores if requested by HPS + // - Data is now sent from the hiscore data buffer rather than game RAM as in previous versions + if (uploading_dump == 1'b1) + begin + // Set local address to read from hiscore data based on ioctl_address + data_addr <= ioctl_addr[HS_SCOREWIDTH-1:0]; + // Clear dump dirty flag + dump_dirty <= 1'b0; + end + + // Trigger hiscore extraction when OSD is opened + if(last_OSD_STATUS==1'b0 && OSD_STATUS==1'b1 && extracting_dump==1'b0 && uploading_dump==1'b0 && restoring_dump==1'b0) + begin + extracting_dump <= 1'b1; + state <= SM_COMPAREINIT; + end + + // Extract hiscore data from game RAM and save in hiscore data buffer + if (extracting_dump == 1'b1) + begin + case (state) + // Compare process states + SM_COMPAREINIT: // Initialise state machine for comparison + begin + // Setup addresses and comparison flags + buffer_addr <= 0; + data_addr <= 0; + counter <= 0; + compare_nonzero <= 1'b0; + compare_changed <= 1'b0; + compare_length <= 1'b0; + // Pause cpu and wait for next state + pause_cpu <= 1'b1; + state <= SM_TIMER; + next_state <= SM_COMPAREBEGIN; + wait_timer <= ACCESS_PAUSEPAD; + end + SM_COMPAREBEGIN: + begin + // Get ready to read next line (wait until addr_base is updated) + reading_scores <= 1'b1; + state <= SM_COMPAREREADY; + end + SM_COMPAREREADY: + begin + // Set ram address and wait for it to return correctly + ram_addr <= addr_base; + if(ram_addr == addr_base) + begin + state <= SM_COMPAREREAD; + end + end + SM_COMPAREREAD: + begin + // Setup next address and signal write enable to hiscore buffer + buffer_write <= 1'b1; + state <= SM_COMPAREDONE; + end + SM_COMPAREDONE: + begin + // If RAM data has changed since last dump and there is either no mask or a 1 in the mask for this address + if (data_from_ram != hiscore_data_out && (CHANGEMASK==8'b0 || check_mask==1)) + begin + // Hiscore data changed + compare_changed <= 1'b1; + end + if (data_from_ram != 8'b0) + begin + // Hiscore data is not blank + compare_nonzero <= 1'b1; + end + compare_length <= compare_length + 20'b1; + // Move to next entry when last address is reached + if (ram_addr == end_addr) + begin + // If this was the last entry then we are done + if (counter == total_entries) + begin + state <= SM_TIMER; + reading_scores <= 1'b0; + next_state <= SM_COMPARECOMPLETE; + wait_timer <= ACCESS_PAUSEPAD; + end + else + begin + // Next config line + counter <= counter + 1'b1; + state <= SM_COMPAREBEGIN; + end + end + else + begin + // Keep extracting this section + state <= SM_COMPAREREAD; + ram_addr <= ram_addr + 1'b1; + end + // Always stop writing to hiscore dump ram and increment local address + buffer_addr <= buffer_addr + 1'b1; + data_addr <= data_addr + 1'b1; + buffer_write <= 1'b0; + end + SM_COMPARECOMPLETE: + begin + pause_cpu <= 1'b0; + reading_scores <= 1'b0; + if (compare_changed == 1'b1 && compare_nonzero == 1'b1) + begin + // If high scores have changed and are not blank, update the hiscore data from extract buffer + dump_dirty <= 1'b1; + state <= SM_EXTRACTINIT; + end + else + begin + // If no change or scores are invalid leave the existing hiscore data in place + if(dump_dirty == 1'b1 && autosave == 1'b1) + begin + state <= SM_EXTRACTSAVE; + end + else + begin + extracting_dump <= 1'b0; + state <= SM_STOPPED; + end + end + end + SM_EXTRACTINIT: + begin + // Setup address and counter + data_addr <= 0; + buffer_addr <= 0; + state <= SM_EXTRACT; + dump_write <= 1'b1; + end + SM_EXTRACT: + begin + // Keep writing until end of buffer + if (buffer_addr == compare_length) + begin + dump_write <= 1'b0; + state <= SM_EXTRACTSAVE; + end + // Increment buffer address and set data address to one behind + data_addr <= buffer_addr; + buffer_addr <= buffer_addr + 1'b1; + end + SM_EXTRACTSAVE: + begin + if(autosave == 1'b1) + begin + ioctl_upload_req <= 1'b1; + state <= SM_TIMER; + next_state <= SM_EXTRACTCOMPLETE; + wait_timer <= 4'd4; + end + else + begin + extracting_dump <= 1'b0; + state <= SM_STOPPED; + end + end + SM_EXTRACTCOMPLETE: + begin + ioctl_upload_req <= 1'b0; + extracting_dump <= 1'b0; + state <= SM_STOPPED; + end + endcase + end + + // If we are not uploading or resetting and valid hiscore data is available then start the state machine to write data to game RAM + if (uploading_dump == 1'b0 && downloaded_dump == 1'b1 && reset == 1'b0) + begin + // State machine to write data to game RAM + case (state) + SM_INIT_RESTORE: // Start state machine + begin + // Setup base addresses + data_addr <= 0; + base_io_addr <= 25'b0; + // Reset entry counter and states + counter <= 0; + writing_scores <= 1'b0; + checking_scores <= 1'b0; + pause_cpu <= 1'b0; + state <= SM_CHECKPREP; + end + + // Start/end check states + // ---------------------- + SM_CHECKPREP: // Prepare start/end check run - pause CPU in readiness for RAM access + begin + state <= SM_TIMER; + next_state <= SM_CHECKBEGIN; + pause_cpu <= 1'b1; + wait_timer <= ACCESS_PAUSEPAD; + end + + SM_CHECKBEGIN: // Begin start/end check run - enable RAM access + begin + checking_scores <= 1'b1; + ram_addr <= {1'b0, addr_base}; + state <= SM_CHECKSTARTVAL; + wait_timer <= CHECK_HOLD; + end + + SM_CHECKSTARTVAL: // Start check + begin + // Check for matching start value + if(wait_timer != CHECK_HOLD && data_from_ram == start_val) + begin + // Prepare end check + ram_addr <= end_addr; + state <= SM_CHECKENDVAL; + wait_timer <= CHECK_HOLD; + end + else + begin + ram_addr <= {1'b0, addr_base}; + if (wait_timer > 1'b0) + begin + wait_timer <= wait_timer - 1'b1; + end + else + begin + // - If no match after read wait then stop check run and schedule restart of state machine + next_state <= SM_CHECKCANCEL; + state <= SM_TIMER; + checking_scores <= 1'b0; + wait_timer <= ACCESS_PAUSEPAD; + end + end + end + + SM_CHECKENDVAL: // End check + begin + // Check for matching end value + if (wait_timer != CHECK_HOLD & data_from_ram == end_val) + begin + if (counter == total_entries) + begin + // If this was the last entry then move on to writing scores to game ram + checking_scores <= 1'b0; + state <= SM_WRITEBEGIN; // Bypass SM_WRITEPREP as we are already paused + counter <= 1'b0; + write_counter <= 1'b0; + ram_write <= 1'b0; + ram_addr <= {1'b0, addr_base}; + end + else + begin + // Increment counter and restart state machine to check next entry + counter <= counter + 1'b1; + state <= SM_CHECKBEGIN; + end + end + else + begin + ram_addr <= end_addr; + if (wait_timer > 1'b0) + begin + wait_timer <= wait_timer - 1'b1; + end + else + begin + // - If no match after read wait then stop check run and schedule restart of state machine + next_state <= SM_CHECKCANCEL; + state <= SM_TIMER; + checking_scores <= 1'b0; + wait_timer <= ACCESS_PAUSEPAD; + end + end + end + + SM_CHECKCANCEL: // Cancel start/end check run - disable RAM access and keep CPU paused + begin + pause_cpu <= 1'b0; + next_state <= SM_INIT_RESTORE; + state <= SM_TIMER; + wait_timer <= CHECK_WAIT; + end + + // Write to game RAM states + // ---------------------- + SM_WRITEPREP: // Prepare to write scores - pause CPU in readiness for RAM access (only used on subsequent write attempts) + begin + state <= SM_TIMER; + next_state <= SM_WRITEBEGIN; + pause_cpu <= 1'b1; + wait_timer <= ACCESS_PAUSEPAD; + end + + SM_WRITEBEGIN: // Writing scores to game RAM begins + begin + writing_scores <= 1'b1; // Enable muxes if necessary + write_counter <= write_counter + 1'b1; + state <= SM_WRITEREADY; + end + + SM_WRITEREADY: // local ram should be correct, start write to game RAM + begin + ram_addr <= addr_base + (data_addr - base_io_addr); + state <= SM_TIMER; + next_state <= SM_WRITEDONE; + wait_timer <= WRITE_HOLD; + ram_write <= 1'b1; + end + + SM_WRITEDONE: + begin + data_addr <= data_addr + 1'b1; // Increment to next byte of entry + if (ram_addr == end_addr) + begin + // End of entry reached + if (counter == total_entries) + begin + state <= SM_WRITECOMPLETE; + end + else + begin + // Move to next entry + counter <= counter + 1'b1; + write_counter <= 1'b0; + base_io_addr <= data_addr + 1'b1; + state <= SM_WRITEBEGIN; + end + end + else + begin + state <= SM_WRITEREADY; + end + ram_write <= 1'b0; + end + + SM_WRITECOMPLETE: // Hiscore write to RAM completed + begin + ram_write <= 1'b0; + writing_scores <= 1'b0; + restoring_dump <= 1'b0; + state <= SM_TIMER; + if(write_counter < WRITE_REPEATCOUNT) + begin + // Schedule next write + next_state <= SM_WRITERETRY; + data_addr <= 0; + wait_timer <= WRITE_REPEATWAIT; + end + else + begin + next_state <= SM_STOPPED; + wait_timer <= ACCESS_PAUSEPAD; + end + end + + SM_WRITERETRY: // Stop pause and schedule next write + begin + pause_cpu <= 1'b0; + state <= SM_TIMER; + next_state <= SM_WRITEPREP; + wait_timer <= WRITE_REPEATWAIT; + end + + SM_STOPPED: + begin + pause_cpu <= 1'b0; + end + endcase + end + + if(state == SM_TIMER) // timer wait state + begin + // Do not progress timer if CPU is paused by source other than this module + // - Stops initial hiscore load delay being foiled by user pausing/entering OSD + if (paused == 1'b0 || pause_cpu == 1'b1) + begin + if (wait_timer > 1'b0) + wait_timer <= wait_timer - 1'b1; + else + state <= next_state; + end + end + end + end +end + +endmodule + +// Simple dual-port RAM module used by hiscore module +module dpram_hs #( + parameter dWidth=8, + parameter aWidth=8 +)( + input clk, + + input [aWidth-1:0] addr_a, + input [dWidth-1:0] d_a, + input we_a, + output reg [dWidth-1:0] q_a, + + input [aWidth-1:0] addr_b, + input [dWidth-1:0] d_b, + input we_b, + output reg [dWidth-1:0] q_b +); + +reg [dWidth-1:0] ram [2**aWidth-1:0]; + +always @(posedge clk) begin + if (we_a) begin + ram[addr_a] <= d_a; + q_a <= d_a; + end + else + begin + q_a <= ram[addr_a]; + end + + if (we_b) begin + ram[addr_b] <= d_b; + q_b <= d_b; + end + else + begin + q_b <= ram[addr_b]; + end +end + +endmodule diff --git a/modules/arcade-hiscore/index.qip b/modules/arcade-hiscore/index.qip new file mode 100644 index 0000000..d453b96 --- /dev/null +++ b/modules/arcade-hiscore/index.qip @@ -0,0 +1 @@ +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "hiscore.v"] diff --git a/modules/dataloader-pocket/data_loader.sv b/modules/dataloader-pocket/data_loader.sv new file mode 100644 index 0000000..ea181fa --- /dev/null +++ b/modules/dataloader-pocket/data_loader.sv @@ -0,0 +1,223 @@ +// MIT License + +// Copyright (c) 2022 Adam Gastineau + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +// SOFTWARE. +// +//////////////////////////////////////////////////////////////////////////////// + +// A data loader for consuming APF bridge writes and directing them to some storage medium +// +// This takes the 32 bit words from APF, and splits it into four / OUTPUT_WORD_SIZE words (4 separate bytes, or 2 16-bit words). +// You can configure the cycle delay by setting WRITE_MEM_CLOCK_DELAY +module data_loader #( + // Upper 4 bits of address + parameter ADDRESS_MASK_UPPER_4 = 0, + parameter ADDRESS_SIZE = 14, + + // Number of clk_memory cycles to delay each write output + // Min 4. Component will assert this value is within the valid range + // Be aware that APF sends data every ~75 74MHz cycles, so you cannot send data slower than this + parameter WRITE_MEM_CLOCK_DELAY = 4, + + // Number of clk_memory cycles to hold the write_en signal high + // Min 1. Component will assert this value is within the valid range + parameter WRITE_MEM_EN_CYCLE_LENGTH = 1, + + // Word size in number of bytes. Can either be 1 (output 8 bits), or 2 (output 16 bits) + // Component will assert this value is within the valid range + parameter OUTPUT_WORD_SIZE = 1 +) ( + input wire clk_74a, + input wire clk_memory, + + input wire bridge_wr, + input wire bridge_endian_little, + input wire [31:0] bridge_addr, + input wire [31:0] bridge_wr_data, + + // These outputs are synced to the memory clock + output reg write_en = 0, + output reg [ADDRESS_SIZE:0] write_addr = 0, + output reg [8 * OUTPUT_WORD_SIZE - 1:0] write_data = 0 +); + + `define MAX(x, y) ((x > y) ? x : y) + + localparam WORD_SIZE = 8 * OUTPUT_WORD_SIZE; + + // Only use the lower 28 bits of the address + localparam FIFO_SIZE = WORD_SIZE + 28; + + wire mem_empty; + + wire [FIFO_SIZE - 1:0] fifo_out; + + reg read_req = 0; + reg write_req = 0; + reg [31:0] shift_data; + reg [27:0] buff_bridge_addr; + + wire [FIFO_SIZE - 1:0] fifo_in = {shift_data[WORD_SIZE-1:0], buff_bridge_addr[27:0]}; + + dcfifo dcfifo_component ( + .data(fifo_in), + .rdclk(clk_memory), + .rdreq(read_req), + .wrclk(clk_74a), + .wrreq(write_req), + .q(fifo_out), + .rdempty(mem_empty) + // .wrempty(), + // .aclr(), + // .eccstatus(), + // .rdfull(), + // .rdusedw(), + // .wrfull(), + // .wrusedw() + ); + defparam dcfifo_component.clocks_are_synchronized = "FALSE", + dcfifo_component.intended_device_family = "Cyclone V", dcfifo_component.lpm_numwords = 4, + dcfifo_component.lpm_showahead = "OFF", dcfifo_component.lpm_type = "dcfifo", + dcfifo_component.lpm_width = FIFO_SIZE, dcfifo_component.lpm_widthu = 2, + dcfifo_component.overflow_checking = "OFF", dcfifo_component.rdsync_delaypipe = 5, + dcfifo_component.underflow_checking = "OFF", dcfifo_component.use_eab = "OFF", + dcfifo_component.wrsync_delaypipe = 5; + + /// APF to Mem clock + + reg prev_bridge_wr = 0; + reg [2:0] write_count = 0; + reg [2:0] write_state = 0; + + localparam WRITE_START = 1; + localparam WRITE_REQ_SHIFT = 2; + + // Receive APF writes and buffer them into the memory clock domain + always @(posedge clk_74a) begin + prev_bridge_wr <= bridge_wr; + + if (~prev_bridge_wr && bridge_wr && bridge_addr[31:28] == ADDRESS_MASK_UPPER_4) begin + // Beginning APF write to core + write_state <= WRITE_REQ_SHIFT; + write_req <= 1; + write_count <= 0; + + shift_data <= bridge_endian_little ? bridge_wr_data : { + bridge_wr_data[7:0], bridge_wr_data[15:8], bridge_wr_data[23:16], bridge_wr_data[31:24] + }; + + buff_bridge_addr <= bridge_addr[27:0]; + end + + case (write_state) + WRITE_START: begin + write_req <= 1; + + write_state <= WRITE_REQ_SHIFT; + end + WRITE_REQ_SHIFT: begin + write_req <= 0; + + // We will be writing again in the next cycle + shift_data <= {8'h0, shift_data[31:WORD_SIZE]}; + buff_bridge_addr <= buff_bridge_addr + OUTPUT_WORD_SIZE; + + write_count <= write_count + 1; + + if (write_count == (4 / OUTPUT_WORD_SIZE) - 1) begin + // Finished write + write_state <= 0; + end else begin + write_state <= WRITE_START; + end + end + endcase + end + + /// Mem clock to core + + reg [5:0] read_state = 0; + + localparam READ_DELAY = 1; + localparam READ_WRITE = 2; + localparam READ_WRITE_EN_CYCLE_OFF = READ_WRITE + WRITE_MEM_EN_CYCLE_LENGTH; + localparam READ_WRITE_END_DEFAULT = WRITE_MEM_CLOCK_DELAY - 1; + // Must use max to prevent READ_WRITE_END from being the same as READ_WRITE_EN_CYCLE_OFF + localparam READ_WRITE_END = + `MAX(READ_WRITE_END_DEFAULT, READ_WRITE_EN_CYCLE_OFF + 1); + localparam HAS_DELAY = READ_WRITE_END_DEFAULT > READ_WRITE_EN_CYCLE_OFF; + + always @(posedge clk_memory) begin + if (read_state != 0) begin + read_state <= read_state + 1; + end else if (~mem_empty) begin + // Start read + read_state <= READ_DELAY; + read_req <= 1; + end + + case (read_state) + READ_DELAY: begin + read_req <= 0; + write_en <= 0; + end + READ_WRITE: begin + // Read data is available + write_en <= 1; + + // Lowest 28 bits are the address + write_addr <= fifo_out[27:0]; + + write_data <= fifo_out[WORD_SIZE+27:28]; + + read_req <= 0; + end + READ_WRITE_EN_CYCLE_OFF: begin + write_en <= 0; + + if (!HAS_DELAY) begin + // No extra delay, immediately go back to start + read_state <= 0; + end + end + READ_WRITE_END: begin + read_state <= 0; + end + endcase + end + + initial begin + // Verify parameters + if (WRITE_MEM_CLOCK_DELAY < 4) begin + $error("WRITE_MEM_CLOCK_DELAY has a minimum value of 4. Received %d", WRITE_MEM_CLOCK_DELAY); + end + + if (WRITE_MEM_EN_CYCLE_LENGTH < 1 || WRITE_MEM_EN_CYCLE_LENGTH >= WRITE_MEM_CLOCK_DELAY - 2) begin + $error( + "WRITE_MEM_EN_CYCLE_LENGTH must be between 1 and %d (inclusive, based off of WRITE_MEM_CLOCK_DELAY). Received %d", + WRITE_MEM_CLOCK_DELAY - 2 - 1, WRITE_MEM_EN_CYCLE_LENGTH); + end + + if (OUTPUT_WORD_SIZE < 1 || OUTPUT_WORD_SIZE > 2) begin + $error("OUTPUT_WORD_SIZE must be 1 or 2. Received %d", OUTPUT_WORD_SIZE); + end + end + +endmodule \ No newline at end of file diff --git a/modules/dataloader-pocket/index.qip b/modules/dataloader-pocket/index.qip new file mode 100644 index 0000000..9f277f4 --- /dev/null +++ b/modules/dataloader-pocket/index.qip @@ -0,0 +1 @@ +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "data_loader.sv"] diff --git a/modules/generic-dpram/dpram.v b/modules/generic-dpram/dpram.v new file mode 100644 index 0000000..4afceca --- /dev/null +++ b/modules/generic-dpram/dpram.v @@ -0,0 +1,66 @@ +/*============================================================================ + Generic dual-port RAM module + + Author: Jim Gregory - https://github.com/JimmyStones/ + Version: 1.0 + Date: 2021-07-03 + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program. If not, see . +===========================================================================*/ + +`timescale 1 ps / 1 ps + +module dpram #( + parameter address_width = 10, + parameter data_width = 8, + parameter init_file= "" + ) ( + input wire clock_a, + input wire wren_a, + input wire [address_width-1:0] address_a, + input wire [data_width-1:0] data_a, + output reg [data_width-1:0] q_a, + + input wire clock_b, + input wire wren_b, + input wire [address_width-1:0] address_b, + input wire [data_width-1:0] data_b, + output reg [data_width-1:0] q_b + ); + + localparam ramLength = (2**address_width); + reg [data_width-1:0] mem [ramLength-1:0]; + + initial begin + if (init_file>0) + $readmemh(init_file, mem); + end + + always @(posedge clock_a) begin + q_a <= mem[address_a]; + if(wren_a) begin + q_a <= data_a; + mem[address_a] <= data_a; + end + end + + always @(posedge clock_b) begin + q_b <= mem[address_b]; + if(wren_b) begin + q_b <= data_b; + mem[address_b] <= data_b; + end + end + +endmodule diff --git a/modules/generic-dpram/index.qip b/modules/generic-dpram/index.qip new file mode 100644 index 0000000..0af70d1 --- /dev/null +++ b/modules/generic-dpram/index.qip @@ -0,0 +1 @@ +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "dpram.v"] diff --git a/modules/generic-pause/index.qip b/modules/generic-pause/index.qip new file mode 100644 index 0000000..16c1ad8 --- /dev/null +++ b/modules/generic-pause/index.qip @@ -0,0 +1 @@ +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pause.v"] diff --git a/modules/generic-pause/pause.v b/modules/generic-pause/pause.v new file mode 100644 index 0000000..7e61b60 --- /dev/null +++ b/modules/generic-pause/pause.v @@ -0,0 +1,97 @@ +/******************************************************************************* + * SPDX-License-Identifier: GPL-3.0-or-later + * SPDX-FileType: SOURCE + * SPDX-FileCopyrightText: (c) 2021 Jim Gregory + ******************************************************************************* + * Generic pause handling for MiSTer cores. + * Copyright (c) 2021 Jim Gregory + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 3 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + ******************************************************************************/ + +/** + * Features: + * - Pause can be triggered by user input, hiscore module or OSD opening (optionally controlled by setting in OSD) + * - When paused the RGB outputs will be halved after 10 seconds to reduce burn-in (optionally controlled by setting in OSD) + * - Reset signal will cancel user triggered pause + * + * Version history: + * 0001 - 2021-03-15 - First marked release + * 0002 - 2021-08-28 - Add optional output of dim_video signal (currently used by Galaga) + */ +module pause # + ( + parameter RW = 8, //! Width of red channel + parameter GW = 8, //! Width of green channel + parameter BW = 8, //! Width of blue channel + parameter CLKSPD = 12 //! Main clock speed in MHz + ) ( + input clk_sys, //! Core system clock (should match HPS module) + input reset, //! CPU reset signal (active-high) + input user_button, //! User pause button signal (active-high) + input pause_request, //! Pause requested by other code (active-high) + input [1:0] options, //! Pause options from OSD - [0] = pause in OSD (active-high) - [1] = dim video (active-high) + input OSD_STATUS, //! OSD is open (active-high) + input [(RW-1):0] r, //! Red channel + input [(GW-1):0] g, //! Green channel + input [(BW-1):0] b, //! Blue channel + output pause_cpu, //! Pause signal to CPU (active-high) +`ifdef PAUSE_OUTPUT_DIM + output dim_video, //! Dim video requested (active-high) +`endif + output [(RW+GW+BW-1):0] rgb_out //! RGB output to arcade_video module + + ); + + // Option constants + localparam pause_in_osd = 1'b0; + localparam dim_video_timer = 1'b1; + + reg pause_toggle = 1'b0; //! User paused (active-high) + reg [31:0] pause_timer = 1'b0; //! Time since pause + reg [31:0] dim_timeout = (CLKSPD*10000000); //! Time until video output dim (10 seconds @ CLKSPD Mhz) +`ifndef PAUSE_OUTPUT_DIM + wire dim_video; //! Dim video requested (active-high) +`endif + + assign pause_cpu = (pause_request | pause_toggle | (OSD_STATUS & options[pause_in_osd])) & !reset; + assign dim_video = (pause_timer >= dim_timeout); + + always @(posedge clk_sys) begin + + // Track user pause button down + reg user_button_last; + user_button_last <= user_button; + if(!user_button_last & user_button) + pause_toggle <= ~pause_toggle; + + // Clear user pause on reset + if(pause_toggle & reset) + pause_toggle <= 0; + + if(pause_cpu & options[dim_video_timer]) begin + // Track pause duration for video dim + if((pause_timer> 1,g >> 1, b >> 1} : {r,g,b}; + +endmodule diff --git a/modules/pocket-i2s/index.qip b/modules/pocket-i2s/index.qip new file mode 100644 index 0000000..fb19ba9 --- /dev/null +++ b/modules/pocket-i2s/index.qip @@ -0,0 +1 @@ +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pocket_i2s.v"] diff --git a/modules/pocket-i2s/pocket_i2s.v b/modules/pocket-i2s/pocket_i2s.v new file mode 100644 index 0000000..512e515 --- /dev/null +++ b/modules/pocket-i2s/pocket_i2s.v @@ -0,0 +1,80 @@ +//------------------------------------------------------------------------------ +// Generic I2S audio interface for the Analogue Pocket +//------------------------------------------------------------------------------ +module pocket_i2s + ( + input iCLK_74, + input [15:0] AUDIO_L, + input [15:0] AUDIO_R, + + output wire I2S_MCLK, + output wire I2S_DAC, + output wire I2S_LRCK + ); + + parameter AUDIO_S = 0; + localparam [20:0] CYCLE_48KHZ = 21'd122880 * 2; + + assign I2S_MCLK = audio_mclk; + assign I2S_DAC = audio_dac; + assign I2S_LRCK = audio_lrck; + + // Generate MCLK = 12.288mhz with fractional accumulator + reg [21:0] audio_accum; + reg audio_mclk; + always @(posedge iCLK_74) begin + audio_accum <= audio_accum + CYCLE_48KHZ; + if(audio_accum >= 21'd742500) begin + audio_mclk <= ~audio_mclk; + audio_accum <= audio_accum - 21'd742500 + CYCLE_48KHZ; + end + end + + // Generate SCLK = 3.072mhz by dividing MCLK by 4 + reg [1:0] aud_mclk_divider; + wire audio_sclk = aud_mclk_divider[1] /* synthesis keep*/; + reg audio_lrck_1; + always @(posedge audio_mclk) begin + aud_mclk_divider <= aud_mclk_divider + 1'b1; + end + + // Synchronize audio samples coming from the core + wire [31:0] audio_sampledata_s; + synch_3 #(.WIDTH(32)) sync_snd({AUDIO_L, AUDIO_R} ,audio_sampledata_s, audio_sclk); + + reg [31:0] audio_sampshift; + reg [4:0] audio_lrck_cnt; + reg audio_lrck; + reg audio_dac; + reg audio_nextsamp; + always @(negedge audio_sclk) begin + audio_nextsamp <= 0; + // Output the next bit + audio_dac <= audio_sampshift[31]; + // 48khz * 64 + audio_lrck_cnt <= audio_lrck_cnt + 1'b1; + if(audio_lrck_cnt == 31) begin + // Switch channels + audio_lrck <= ~audio_lrck; + if(AUDIO_S && audio_lrck) begin + // Load new sample + audio_nextsamp <= 1; + // Data is stored as 16bit little endian signed, so byteswap 16-bit + audio_sampshift <= {audio_sampledata_s}; + end + else begin + if(~audio_lrck) begin + // Reload sample shifter + audio_sampshift <= audio_sampledata_s; + end + end + end + else begin + // Only shift for 16 clocks per channel + if(audio_lrck_cnt < 16) begin + audio_sampshift <= {audio_sampshift[30:0], 1'b0}; + end + end + end + +endmodule diff --git a/modules/pocket-joypad/index.qip b/modules/pocket-joypad/index.qip new file mode 100644 index 0000000..05c286c --- /dev/null +++ b/modules/pocket-joypad/index.qip @@ -0,0 +1 @@ +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "joypad.v"] diff --git a/modules/pocket-joypad/joypad.v b/modules/pocket-joypad/joypad.v new file mode 100644 index 0000000..11f8276 --- /dev/null +++ b/modules/pocket-joypad/joypad.v @@ -0,0 +1,67 @@ +//------------------------------------------------------------------------------ +// SPDX-License-Identifier: MPL-2.0 +// SPDX-FileType: SOURCE +// SPDX-FileCopyrightText: (c) 2022 Marcus Andrade +//------------------------------------------------------------------------------ +// Generic Gamepad interface for the Analogue Pocket +//------------------------------------------------------------------------------ + +`timescale 1 ps / 1 ps + +module pocket_gamepad + ( + input iCLK, + input [15:0] iJOY, + + output wire PAD_U, + output wire PAD_D, + output wire PAD_L, + output wire PAD_R, + + output wire BTN_A, + output wire BTN_B, + output wire BTN_X, + output wire BTN_Y, + + output wire BTN_L1, + output wire BTN_L2, + output wire BTN_L3, + + output wire BTN_R1, + output wire BTN_R2, + output wire BTN_R3, + + output wire BTN_SE, + output wire BTN_ST + ); + + assign PAD_U = joy_keys_s[0]; + assign PAD_D = joy_keys_s[1]; + assign PAD_L = joy_keys_s[2]; + assign PAD_R = joy_keys_s[3]; + + assign BTN_A = joy_keys_s[4]; + assign BTN_B = joy_keys_s[5]; + assign BTN_X = joy_keys_s[6]; + assign BTN_Y = joy_keys_s[7]; + + assign BTN_L1 = joy_keys_s[8]; + assign BTN_R1 = joy_keys_s[9]; + + assign BTN_L2 = joy_keys_s[10]; + assign BTN_R2 = joy_keys_s[11]; + + assign BTN_L3 = joy_keys_s[12]; + assign BTN_R3 = joy_keys_s[13]; + + assign BTN_SE = joy_keys_s[14]; + assign BTN_ST = joy_keys_s[15]; + + reg [15:0] joy_keys_s; + + // Sync Joystick to Core Clock + always @ (posedge iCLK) begin + joy_keys_s <= iJOY; + end + +endmodule diff --git a/pkg/pocket/Assets/digdug/boogermann.digdug/Alternatives/Dig Dug (Atari, Rev 1).json b/pkg/pocket/Assets/digdug/boogermann.digdug/Alternatives/Dig Dug (Atari, Rev 1).json new file mode 100644 index 0000000..22a7bf7 --- /dev/null +++ b/pkg/pocket/Assets/digdug/boogermann.digdug/Alternatives/Dig Dug (Atari, Rev 1).json @@ -0,0 +1,21 @@ +{ + "instance": { + "magic": "APF_VER_1", + "variant_select": { + "id": 777, + "select": false + }, + "data_slots": [ + { + "id": 1, + "filename": "digduat1.rom" + } + ], + "memory_writes": [ + { + "address": "0xFEEDC0DE", + "data": 0 + } + ] + } +} \ No newline at end of file diff --git a/pkg/pocket/Assets/digdug/boogermann.digdug/Alternatives/Dig Dug (Atari, Rev 2).json b/pkg/pocket/Assets/digdug/boogermann.digdug/Alternatives/Dig Dug (Atari, Rev 2).json new file mode 100644 index 0000000..d1ee2d0 --- /dev/null +++ b/pkg/pocket/Assets/digdug/boogermann.digdug/Alternatives/Dig Dug (Atari, Rev 2).json @@ -0,0 +1,21 @@ +{ + "instance": { + "magic": "APF_VER_1", + "variant_select": { + "id": 777, + "select": false + }, + "data_slots": [ + { + "id": 1, + "filename": "digdugat.rom" + } + ], + "memory_writes": [ + { + "address": "0xFEEDC0DE", + "data": 0 + } + ] + } +} \ No newline at end of file diff --git a/pkg/pocket/Assets/digdug/boogermann.digdug/Alternatives/Dig Dug (Manufactured by Sidam).json b/pkg/pocket/Assets/digdug/boogermann.digdug/Alternatives/Dig Dug (Manufactured by Sidam).json new file mode 100644 index 0000000..59ecb87 --- /dev/null +++ b/pkg/pocket/Assets/digdug/boogermann.digdug/Alternatives/Dig Dug (Manufactured by Sidam).json @@ -0,0 +1,21 @@ +{ + "instance": { + "magic": "APF_VER_1", + "variant_select": { + "id": 777, + "select": false + }, + "data_slots": [ + { + "id": 1, + "filename": "digsid.rom" + } + ], + "memory_writes": [ + { + "address": "0xFEEDC0DE", + "data": 0 + } + ] + } +} \ No newline at end of file diff --git a/pkg/pocket/Assets/digdug/boogermann.digdug/Alternatives/Dig Dug (Rev 1).json b/pkg/pocket/Assets/digdug/boogermann.digdug/Alternatives/Dig Dug (Rev 1).json new file mode 100644 index 0000000..8dac15c --- /dev/null +++ b/pkg/pocket/Assets/digdug/boogermann.digdug/Alternatives/Dig Dug (Rev 1).json @@ -0,0 +1,21 @@ +{ + "instance": { + "magic": "APF_VER_1", + "variant_select": { + "id": 777, + "select": false + }, + "data_slots": [ + { + "id": 1, + "filename": "digdug1.rom" + } + ], + "memory_writes": [ + { + "address": "0xFEEDC0DE", + "data": 0 + } + ] + } +} \ No newline at end of file diff --git a/pkg/pocket/Assets/digdug/boogermann.digdug/Dig Dug (Rev 2).json b/pkg/pocket/Assets/digdug/boogermann.digdug/Dig Dug (Rev 2).json new file mode 100644 index 0000000..b9d9938 --- /dev/null +++ b/pkg/pocket/Assets/digdug/boogermann.digdug/Dig Dug (Rev 2).json @@ -0,0 +1,21 @@ +{ + "instance": { + "magic": "APF_VER_1", + "variant_select": { + "id": 777, + "select": false + }, + "data_slots": [ + { + "id": 1, + "filename": "digdug.rom" + } + ], + "memory_writes": [ + { + "address": "0xFEEDC0DE", + "data": 0 + } + ] + } +} \ No newline at end of file diff --git a/pkg/pocket/Assets/digdug/common/checklist.md5 b/pkg/pocket/Assets/digdug/common/checklist.md5 new file mode 100644 index 0000000..f91eb4c --- /dev/null +++ b/pkg/pocket/Assets/digdug/common/checklist.md5 @@ -0,0 +1,5 @@ +121e5ccc5fa5b4b93ee5564f7933e80c digduat1.rom +d6790fb2893b2290b4ac74544e4d78e6 digdug.rom +2cec9f1428c97de2af61dfc25bd3ac55 digdug1.rom +1ec940262e97efe4c32a59877a775a0e digdugat.rom +446407cafe972619809aa05418584b1a digsid.rom diff --git a/pkg/pocket/Cores/boogermann.digdug/audio.json b/pkg/pocket/Cores/boogermann.digdug/audio.json new file mode 100644 index 0000000..ea8e2f4 --- /dev/null +++ b/pkg/pocket/Cores/boogermann.digdug/audio.json @@ -0,0 +1,5 @@ +{ + "audio": { + "magic": "APF_VER_1" + } +} \ No newline at end of file diff --git a/pkg/pocket/Cores/boogermann.digdug/core.json b/pkg/pocket/Cores/boogermann.digdug/core.json new file mode 100644 index 0000000..639d4e9 --- /dev/null +++ b/pkg/pocket/Cores/boogermann.digdug/core.json @@ -0,0 +1,36 @@ +{ + "core": { + "magic": "APF_VER_1", + "metadata": { + "platform_ids": [ + "digdug" + ], + "shortname": "digdug", + "description": "Namco Dig Dug Compatible Gateware IP Core for FPGA", + "author": "boogermann", + "url": "https://github.com/opengateware/arcade-digdug", + "version": "<%- VERSION %>", + "date_release": "<%- RELEASE_DATE %>" + }, + "framework": { + "target_product": "Analogue Pocket", + "version_required": "1.1", + "sleep_supported": false, + "dock": { + "supported": true, + "analog_output": false + }, + "hardware": { + "link_port": false, + "cartridge_adapter": -1 + } + }, + "cores": [ + { + "name": "default", + "id": 0, + "filename": "bitstream.rbf_r" + } + ] + } +} \ No newline at end of file diff --git a/pkg/pocket/Cores/boogermann.digdug/data.json b/pkg/pocket/Cores/boogermann.digdug/data.json new file mode 100644 index 0000000..b44e178 --- /dev/null +++ b/pkg/pocket/Cores/boogermann.digdug/data.json @@ -0,0 +1,26 @@ +{ + "data": { + "magic": "APF_VER_1", + "data_slots": [ + { + "name": "Load Game Definition File", + "id": 0, + "required": true, + "parameters": "0x12", + "extensions": [ + "json" + ] + }, + { + "name": "ROM", + "id": 1, + "required": true, + "parameters": 0, + "extensions": [ + "rom" + ], + "address": "0x00000000" + } + ] + } +} \ No newline at end of file diff --git a/pkg/pocket/Cores/boogermann.digdug/icon.bin b/pkg/pocket/Cores/boogermann.digdug/icon.bin new file mode 100644 index 0000000..cb4e46d Binary files /dev/null and b/pkg/pocket/Cores/boogermann.digdug/icon.bin differ diff --git a/pkg/pocket/Cores/boogermann.digdug/icon.png b/pkg/pocket/Cores/boogermann.digdug/icon.png new file mode 100644 index 0000000..255e6ec Binary files /dev/null and b/pkg/pocket/Cores/boogermann.digdug/icon.png differ diff --git a/pkg/pocket/Cores/boogermann.digdug/info.txt b/pkg/pocket/Cores/boogermann.digdug/info.txt new file mode 100644 index 0000000..73b7085 --- /dev/null +++ b/pkg/pocket/Cores/boogermann.digdug/info.txt @@ -0,0 +1,32 @@ +Dig Dug is a maze arcade game developed by Namco. The player controls Dig Dug to defeat all enemies per stage, by either inflating them to bursting or crushing them underneath rocks. + +Note: You must provide your own roms to use this core. + +Developer(s) + Namco +Publisher(s) + JP/EU: Namco + NA: Atari, Inc. +Designer(s) + Masahisa Ikegami + Shigeru Yokoyama +Programmer(s) + Shouichi Fukatani + Toshio Sakai +Artist(s) + Hiroshi Ono[6] +Composer(s) + Yuriko Keino +Release + JP: February 20, 1982 + NA: April 1982 + EU: April 19, 1982 + +This Implementation of a compatible Dig Dug arcade hardware in HDL is the work of MiSTer-X + +Analogue Pocket port by Marcus Andrade (Boogermann) + +Dig Dug © 1982 NAMCO LTD. All rights reserved. Dig Dug is a trademark of BANDAI NAMCO ENTERTAINMENT INC. +All other trademarks, logos, and copyrights are property of their respective owners. + +The authors and contributors or any of its maintainers are in no way associated with or endorsed by Bandai Namco Entertainment Inc. diff --git a/pkg/pocket/Cores/boogermann.digdug/input.json b/pkg/pocket/Cores/boogermann.digdug/input.json new file mode 100644 index 0000000..f8a81b4 --- /dev/null +++ b/pkg/pocket/Cores/boogermann.digdug/input.json @@ -0,0 +1,52 @@ +{ + "input": { + "magic": "APF_VER_1", + "controllers": [ + { + "type": "default", + "mappings": [ + { + "id": 0, + "name": "Coin", + "key": "pad_btn_select" + }, + { + "id": 1, + "name": "Start Player 1", + "key": "pad_btn_start" + }, + { + "id": 2, + "name": "Start Player 2", + "key": "pad_trig_l" + }, + { + "id": 3, + "name": "Fire", + "key": "pad_btn_a" + }, + { + "id": 4, + "name": "Fire", + "key": "pad_btn_b" + }, + { + "id": 5, + "name": "Fire", + "key": "pad_btn_x" + }, + { + "id": 6, + "name": "Fire", + "key": "pad_btn_y" + }, + { + "id": 7, + "name": "Pause", + "key": "pad_trig_r" + } + ] + } + ] + } +} \ No newline at end of file diff --git a/pkg/pocket/Cores/boogermann.digdug/interact.json b/pkg/pocket/Cores/boogermann.digdug/interact.json new file mode 100644 index 0000000..3a6022c --- /dev/null +++ b/pkg/pocket/Cores/boogermann.digdug/interact.json @@ -0,0 +1,115 @@ +{ + "interact": { + "magic": "APF_VER_1", + "variables": [ + { + "name": "Reset Core", + "id": 1, + "type": "action", + "enabled": true, + "address": "0x10000000", + "value": 1 + }, + { + "name": "Service Mode", + "id": 2, + "type": "check", + "enabled": true, + "address": "0x10010000", + "defaultval": 0, + "value": 1 + }, + { + "name": "Easy *", + "id": 3, + "type": "radio", + "group": 100, + "enabled": true, + "persist": true, + "address": "0x10020000", + "defaultval": 0, + "value": 0, + "mask": "0xFFFFFF00" + }, + { + "name": "Medium", + "id": 4, + "type": "radio", + "group": 100, + "enabled": true, + "persist": true, + "address": "0x10020000", + "value": "0x2", + "mask": "0xFFFFFF00" + }, + { + "name": "Hard", + "id": 5, + "type": "radio", + "group": 100, + "enabled": true, + "persist": true, + "address": "0x10020000", + "value": "0x1", + "mask": "0xFFFFFF00" + }, + { + "name": "Hardest", + "id": 6, + "type": "radio", + "group": 100, + "enabled": true, + "persist": true, + "address": "0x10020000", + "value": "0x3", + "mask": "0xFFFFFF00" + }, + { + "name": "3 Lives *", + "id": 9, + "type": "radio", + "group": 101, + "enabled": true, + "persist": true, + "address": "0x10030000", + "defaultval": "0x1", + "value": "0x1", + "mask": "0xFFFFFF00" + }, + { + "name": "1 Live", + "id": 7, + "type": "radio", + "group": 101, + "enabled": true, + "persist": true, + "address": "0x10030000", + "value": "0x0", + "mask": "0xFFFFFF00" + }, + { + "name": "2 Lives", + "id": 8, + "type": "radio", + "group": 101, + "enabled": true, + "persist": true, + "address": "0x10030000", + "value": "0x2", + "mask": "0xFFFFFF00" + }, + { + "name": "5 Lives", + "id": 10, + "type": "radio", + "group": 101, + "enabled": true, + "persist": true, + "address": "0x10030000", + "value": "0x3", + "mask": "0xFFFFFF00" + } + ], + "messages": [] + } +} \ No newline at end of file diff --git a/pkg/pocket/Cores/boogermann.digdug/variants.json b/pkg/pocket/Cores/boogermann.digdug/variants.json new file mode 100644 index 0000000..c2dbd41 --- /dev/null +++ b/pkg/pocket/Cores/boogermann.digdug/variants.json @@ -0,0 +1,6 @@ +{ + "variants": { + "magic": "APF_VER_1", + "variant_list": [] + } +} \ No newline at end of file diff --git a/pkg/pocket/Cores/boogermann.digdug/video.json b/pkg/pocket/Cores/boogermann.digdug/video.json new file mode 100644 index 0000000..0b18170 --- /dev/null +++ b/pkg/pocket/Cores/boogermann.digdug/video.json @@ -0,0 +1,15 @@ +{ + "video": { + "magic": "APF_VER_1", + "scaler_modes": [ + { + "width": 288, + "height": 224, + "aspect_w": 9, + "aspect_h": 7, + "rotation": 90, + "mirror": 0 + } + ] + } +} \ No newline at end of file diff --git a/pkg/pocket/Platforms/_images/digdug.bin b/pkg/pocket/Platforms/_images/digdug.bin new file mode 100644 index 0000000..dfe194c Binary files /dev/null and b/pkg/pocket/Platforms/_images/digdug.bin differ diff --git a/pkg/pocket/Platforms/_images/digdug.png b/pkg/pocket/Platforms/_images/digdug.png new file mode 100644 index 0000000..6fea341 Binary files /dev/null and b/pkg/pocket/Platforms/_images/digdug.png differ diff --git a/pkg/pocket/Platforms/digdug.json b/pkg/pocket/Platforms/digdug.json new file mode 100644 index 0000000..b8dde5c --- /dev/null +++ b/pkg/pocket/Platforms/digdug.json @@ -0,0 +1,8 @@ +{ + "platform": { + "category": "Arcade", + "name": "Dig Dug", + "manufacturer": "Namco", + "year": 1982 + } +} \ No newline at end of file diff --git a/pkg/rom-recipes/Assets/digdug/common/checklist.md5 b/pkg/rom-recipes/Assets/digdug/common/checklist.md5 new file mode 100644 index 0000000..f91eb4c --- /dev/null +++ b/pkg/rom-recipes/Assets/digdug/common/checklist.md5 @@ -0,0 +1,5 @@ +121e5ccc5fa5b4b93ee5564f7933e80c digduat1.rom +d6790fb2893b2290b4ac74544e4d78e6 digdug.rom +2cec9f1428c97de2af61dfc25bd3ac55 digdug1.rom +1ec940262e97efe4c32a59877a775a0e digdugat.rom +446407cafe972619809aa05418584b1a digsid.rom diff --git a/pkg/rom-recipes/roms/_PUT_YOUR_ROMS_HERE b/pkg/rom-recipes/roms/_PUT_YOUR_ROMS_HERE new file mode 100644 index 0000000..e69de29 diff --git a/pkg/rom-recipes/tools/make_roms.ps1 b/pkg/rom-recipes/tools/make_roms.ps1 new file mode 100644 index 0000000..39e0fec --- /dev/null +++ b/pkg/rom-recipes/tools/make_roms.ps1 @@ -0,0 +1,23 @@ +#!/usr/bin/pwsh -Command + +$coreName = "digdug" +$currentPath = $(Get-Item $($MyInvocation.MyCommand.Path)).DirectoryName +$fileNames = Get-ChildItem -Path "$currentPath\..\xml" -Recurse -Include *.mra + +try { + foreach ($f in $fileNames){ + $outfile = $f.FullName + Write-Host "Converting $outfile ..." + orca.exe -z ..\roms -O ..\Assets\$coreName\common $outfile + } +} catch { + Write-Host "Error: $($_.Exception.Message)" + exit 1 +} finally { + Write-Host "Done." + Write-Host "Copy your rom files to Assets/$coreName/common" + Write-Host "Enjoy!" + timeout /t 10 +} + +exit 0 diff --git a/pkg/rom-recipes/tools/make_roms.sh b/pkg/rom-recipes/tools/make_roms.sh new file mode 100644 index 0000000..9c87902 --- /dev/null +++ b/pkg/rom-recipes/tools/make_roms.sh @@ -0,0 +1,14 @@ +#!/usr/bin/env bash + +CORE=digdug +PARENT=$(dirname $PWD) +XML=$PARENT/xml +ROMS=$PARENT/roms +ASSETS=$PARENT/Assets/$CORE/common + +find ${XML} -name '*.mra' | while read line; do + echo "Processing file '$line'" + orca -z ${ROMS} -O ${ASSETS} "$line" +done + +exit 0 \ No newline at end of file diff --git a/pkg/rom-recipes/xml/Alternatives/Dig Dug (Atari, Rev 1).mra b/pkg/rom-recipes/xml/Alternatives/Dig Dug (Atari, Rev 1).mra new file mode 100644 index 0000000..a498a62 --- /dev/null +++ b/pkg/rom-recipes/xml/Alternatives/Dig Dug (Atari, Rev 1).mra @@ -0,0 +1,26 @@ + + digdugat1 + no + no + 0240 + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/pkg/rom-recipes/xml/Alternatives/Dig Dug (Atari, Rev 2).mra b/pkg/rom-recipes/xml/Alternatives/Dig Dug (Atari, Rev 2).mra new file mode 100644 index 0000000..a7529c0 --- /dev/null +++ b/pkg/rom-recipes/xml/Alternatives/Dig Dug (Atari, Rev 2).mra @@ -0,0 +1,26 @@ + + digdugat + no + no + 0240 + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/pkg/rom-recipes/xml/Alternatives/Dig Dug (Manufactured by Sidam).mra b/pkg/rom-recipes/xml/Alternatives/Dig Dug (Manufactured by Sidam).mra new file mode 100644 index 0000000..948c3b0 --- /dev/null +++ b/pkg/rom-recipes/xml/Alternatives/Dig Dug (Manufactured by Sidam).mra @@ -0,0 +1,26 @@ + + digsid + no + no + 0240 + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/pkg/rom-recipes/xml/Alternatives/Dig Dug (Rev 1).mra b/pkg/rom-recipes/xml/Alternatives/Dig Dug (Rev 1).mra new file mode 100644 index 0000000..902d381 --- /dev/null +++ b/pkg/rom-recipes/xml/Alternatives/Dig Dug (Rev 1).mra @@ -0,0 +1,26 @@ + + digdug1 + no + no + 0240 + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/pkg/rom-recipes/xml/Dig Dug (Rev 2).mra b/pkg/rom-recipes/xml/Dig Dug (Rev 2).mra new file mode 100644 index 0000000..9472899 --- /dev/null +++ b/pkg/rom-recipes/xml/Dig Dug (Rev 2).mra @@ -0,0 +1,33 @@ + + digdug + no + no + 0240 + + + + + + + + + + + + + + + + + + + + + + + + 10 00 00 00 00 FF 00 04 00 04 00 08 00 FF 02 00 00 00 89 A0 00 25 01 01 + + + + \ No newline at end of file diff --git a/platform/pocket/apf.qip b/platform/pocket/apf.qip new file mode 100644 index 0000000..2fd9aea --- /dev/null +++ b/platform/pocket/apf.qip @@ -0,0 +1,7 @@ +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "apf_top.v"] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "common.v"] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "io_bridge_peripheral.v"] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "io_pad_controller.v"] +set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) "apf_constraints.sdc"] +set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "mf_ddio_bidir_12.qip"] +set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "mf_datatable.qip"] diff --git a/platform/pocket/apf_constraints.sdc b/platform/pocket/apf_constraints.sdc new file mode 100644 index 0000000..b168b55 --- /dev/null +++ b/platform/pocket/apf_constraints.sdc @@ -0,0 +1,12 @@ +# +# APF constraints +# Do not edit this file. +# +# Add your own constraints in the \core_constraints.sdc in the core directory, which will also be loaded. + +create_clock -name clk_74a -period 13.468 [get_ports clk_74a] +create_clock -name clk_74b -period 13.468 [get_ports clk_74b] +create_clock -name bridge_spiclk -period 13.468 [get_ports bridge_spiclk] + +# autogenerate PLL clock names for use down below +derive_pll_clocks diff --git a/platform/pocket/apf_top.v b/platform/pocket/apf_top.v new file mode 100644 index 0000000..43f9021 --- /dev/null +++ b/platform/pocket/apf_top.v @@ -0,0 +1,471 @@ +// Software License Agreement + +// The software supplied herewith by Analogue Enterprises Limited (the "Company”), +// the Analogue Pocket Framework (“APF”), is provided and licensed to you, the +// Company's customer, solely for use in designing, testing and creating +// applications for use with Company's Products or Services. The software is +// owned by the Company and/or its licensors, and is protected under applicable +// laws, including, but not limited to, U.S. copyright law. All rights are +// reserved. By using the APF code you are agreeing to the terms of the End User +// License Agreement (“EULA”) located at [https://www.analogue.link/pocket-eula] +// and incorporated herein by reference. + +// THE SOFTWARE IS PROVIDED "AS-IS" AND WE EXPRESSLY DISCLAIM ANY IMPLIED +// WARRANTIES TO THE FULLEST EXTENT PROVIDED BY LAW, INCLUDING BUT NOT LIMITED TO, +// ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE OR +// NON-INFRINGEMENT. TO THE EXTENT APPLICABLE LAWS PROHIBIT TERMS OF USE FROM +// DISCLAIMING ANY IMPLIED WARRANTY, SUCH IMPLIED WARRANTY SHALL BE LIMITED TO THE +// MINIMUM WARRANTY PERIOD REQUIRED BY LAW, AND IF NO SUCH PERIOD IS REQUIRED, +// THEN THIRTY (30) DAYS FROM FIRST USE OF THE SOFTWARE. WE CANNOT GUARANTEE AND +// DO NOT PROMISE ANY SPECIFIC RESULTS FROM USE OF THE SOFTWARE. WITHOUT LIMITING +// THE FOREGOING, WE DO NOT WARRANT THAT THE SOFTWARE WILL BE UNINTERRUPTED OR +// ERROR-FREE. IN NO EVENT WILL WE BE LIABLE TO YOU OR ANY OTHER PERSON FOR ANY +// INDIRECT, CONSEQUENTIAL, EXEMPLARY, INCIDENTAL, SPECIAL OR PUNITIVE DAMAGES, +// INCLUDING BUT NOT LIMITED TO, LOST PROFITS ARISING OUT OF YOUR USE, OR +// INABILITY TO USE, THE SOFTWARE, EVEN IF WE HAVE BEEN ADVISED OF THE POSSIBILITY +// OF SUCH DAMAGES. UNDER NO CIRCUMSTANCES SHALL OUR LIABILITY TO YOU FOR ANY +// CLAIM OR CAUSE OF ACTION WHATSOEVER, AND REGARDLESS OF THE FORM OF THE ACTION, +// WHETHER ARISING IN CONTRACT, TORT OR OTHERWISE, EXCEED THE AMOUNT PAID BY YOU +// TO US, IF ANY, DURING THE 90 DAY PERIOD IMMEDIATELY PRECEDING THE DATE ON WHICH +// YOU FIRST ASSERT ANY SUCH CLAIM. THE FOREGOING LIMITATIONS SHALL APPLY TO THE +// FULLEST EXTENT PERMITTED BY APPLICABLE LAW. +// +// 6515C - Analogue Pocket main unit +// SOCRATES FPGA +// +// 2022-06-28 Analogue + +`default_nettype none + +module apf_top ( +/////////////////////////////////////////////////// +// clock inputs 74.25mhz. not phase aligned, so treat these domains as asynchronous + +input wire clk_74a, // mainclk1 +input wire clk_74b, // mainclk1 + +/////////////////////////////////////////////////// +// cartridge interface +// switches between 3.3v and 5v mechanically +// output enable for multibit translators controlled by PIC32 + +// GBA AD[15:8] +inout wire [7:0] cart_tran_bank2, +output wire cart_tran_bank2_dir, + +// GBA AD[7:0] +inout wire [7:0] cart_tran_bank3, +output wire cart_tran_bank3_dir, + +// GBA A[23:16] +inout wire [7:0] cart_tran_bank1, +output wire cart_tran_bank1_dir, + +// GBA [7] PHI# +// GBA [6] WR# +// GBA [5] RD# +// GBA [4] CS1#/CS# +// [3:0] unwired +inout wire [7:4] cart_tran_bank0, +output wire cart_tran_bank0_dir, + +// GBA CS2#/RES# +inout wire cart_tran_pin30, +output wire cart_tran_pin30_dir, +// when GBC cart is inserted, this signal when low or weak will pull GBC /RES low with a special circuit +// the goal is that when unconfigured, the FPGA weak pullups won't interfere. +// thus, if GBC cart is inserted, FPGA must drive this high in order to let the level translators +// and general IO drive this pin. +output wire cart_pin30_pwroff_reset, + +// GBA IRQ/DRQ +inout wire cart_tran_pin31, +output wire cart_tran_pin31_dir, + +// infrared +// avoid driving the TX LED with DC or leaving it stuck on. pulsed usage is fine +input wire port_ir_rx, +output wire port_ir_tx, +output wire port_ir_rx_disable, + +// GBA link port +inout wire port_tran_si, +output wire port_tran_si_dir, +inout wire port_tran_so, +output wire port_tran_so_dir, +inout wire port_tran_sck, +output wire port_tran_sck_dir, +inout wire port_tran_sd, +output wire port_tran_sd_dir, + +/////////////////////////////////////////////////// +// video output to the scaler + +inout wire [11:0] scal_vid, +inout wire scal_clk, +inout wire scal_de, +inout wire scal_skip, +inout wire scal_vs, +inout wire scal_hs, + +output wire scal_audmclk, +input wire scal_audadc, +output wire scal_auddac, +output wire scal_audlrck, + +/////////////////////////////////////////////////// +// communication between main and scaler (aristotle) fpga. +// spi bus with aristotle as controller. + +inout wire bridge_spimosi, +inout wire bridge_spimiso, +inout wire bridge_spiclk, +input wire bridge_spiss, +inout wire bridge_1wire, + +/////////////////////////////////////////////////// +// cellular psram 0 and 1, two chips (64mbit x2 dual die per chip) + +output wire [21:16] cram0_a, +inout wire [15:0] cram0_dq, +input wire cram0_wait, +output wire cram0_clk, +output wire cram0_adv_n, +output wire cram0_cre, +output wire cram0_ce0_n, +output wire cram0_ce1_n, +output wire cram0_oe_n, +output wire cram0_we_n, +output wire cram0_ub_n, +output wire cram0_lb_n, + +output wire [21:16] cram1_a, +inout wire [15:0] cram1_dq, +input wire cram1_wait, +output wire cram1_clk, +output wire cram1_adv_n, +output wire cram1_cre, +output wire cram1_ce0_n, +output wire cram1_ce1_n, +output wire cram1_oe_n, +output wire cram1_we_n, +output wire cram1_ub_n, +output wire cram1_lb_n, + +/////////////////////////////////////////////////// +// sdram, 512mbit x16 + +output wire [12:0] dram_a, +output wire [1:0] dram_ba, +inout wire [15:0] dram_dq, +output wire [1:0] dram_dqm, +output wire dram_clk, +output wire dram_cke, +output wire dram_ras_n, +output wire dram_cas_n, +output wire dram_we_n, + +/////////////////////////////////////////////////// +// sram, 1mbit x16 + +output wire [16:0] sram_a, +inout wire [15:0] sram_dq, +output wire sram_oe_n, +output wire sram_we_n, +output wire sram_ub_n, +output wire sram_lb_n, + +/////////////////////////////////////////////////// +// vblank output to scaler + +input wire vblank, + +/////////////////////////////////////////////////// +// i/o to 6515D breakout usb uart + +output wire dbg_tx, +input wire dbg_rx, + +/////////////////////////////////////////////////// +// i/o pads near jtag connector user can solder to + +output wire user1, +input wire user2, + +/////////////////////////////////////////////////// +// powerup self test, do not use + +inout wire bist, +output wire vpll_feed, + +/////////////////////////////////////////////////// +// RFU internal i2c bus (DNU) + +inout wire aux_sda, +output wire aux_scl + +); + +assign bist = 1'bZ; + +// reset generation + + reg [24:0] count; + reg reset_n; + +initial begin + count <= 0; + reset_n <= 0; +end +always @(posedge clk_74a) begin + count <= count + 1'b1; + + if(count[15]) begin + // exit reset + reset_n <= 1; + end + +end + + + + +// convert 24-bit rgb data to 12-bit DDR for ARISTOTLE + + wire [23:0] video_rgb; + wire video_rgb_clock; + wire video_rgb_clock_90; + wire video_de; + wire video_skip; + wire video_vs; + wire video_hs; + +mf_ddio_bidir_12 isco ( + .oe ( 1'b1 ), + .datain_h ( video_rgb[23:12] ), + .datain_l ( video_rgb[11: 0] ), + .outclock ( video_rgb_clock ), + .padio ( scal_ddio_12 ) +); + +wire [11:0] scal_ddio_12; +assign scal_vid = scal_ddio_12; + +mf_ddio_bidir_12 iscc ( + .oe ( 1'b1 ), + .datain_h ( {video_vs, video_hs, video_de, video_skip} ), + .datain_l ( {video_vs, video_hs, video_de, video_skip} ), + .outclock ( video_rgb_clock ), + .padio ( scal_ddio_ctrl ) +); + +wire [3:0] scal_ddio_ctrl; +assign scal_vs = scal_ddio_ctrl[3]; +assign scal_hs = scal_ddio_ctrl[2]; +assign scal_de = scal_ddio_ctrl[1]; +assign scal_skip = scal_ddio_ctrl[0]; + +mf_ddio_bidir_12 isclk( + .oe ( 1'b1 ), + .datain_h ( 1'b1 ), + .datain_l ( 1'b0 ), + .outclock ( video_rgb_clock_90 ), + .padio ( scal_clk ) +); + + + +// controller data (pad) controller. + wire [15:0] cont1_key; + wire [15:0] cont2_key; + wire [15:0] cont3_key; + wire [15:0] cont4_key; + wire [31:0] cont1_joy; + wire [31:0] cont2_joy; + wire [31:0] cont3_joy; + wire [31:0] cont4_joy; + wire [15:0] cont1_trig; + wire [15:0] cont2_trig; + wire [15:0] cont3_trig; + wire [15:0] cont4_trig; + +io_pad_controller ipm ( + .clk ( clk_74a ), + .reset_n ( reset_n ), + + .pad_1wire ( bridge_1wire ), + + .cont1_key ( cont1_key ), + .cont2_key ( cont2_key ), + .cont3_key ( cont3_key ), + .cont4_key ( cont4_key ), + .cont1_joy ( cont1_joy ), + .cont2_joy ( cont2_joy ), + .cont3_joy ( cont3_joy ), + .cont4_joy ( cont4_joy ), + .cont1_trig ( cont1_trig ), + .cont2_trig ( cont2_trig ), + .cont3_trig ( cont3_trig ), + .cont4_trig ( cont4_trig ) +); + + +// virtual pmp bridge + wire bridge_endian_little; + wire [31:0] bridge_addr; + wire bridge_rd; + wire [31:0] bridge_rd_data; + wire bridge_wr; + wire [31:0] bridge_wr_data; + +io_bridge_peripheral ibs ( + + .clk ( clk_74a ), + .reset_n ( reset_n ), + + .endian_little ( bridge_endian_little ), + + .pmp_addr ( bridge_addr ), + .pmp_rd ( bridge_rd ), + .pmp_rd_data ( bridge_rd_data ), + .pmp_wr ( bridge_wr ), + .pmp_wr_data ( bridge_wr_data ), + + .phy_spimosi ( bridge_spimosi ), + .phy_spimiso ( bridge_spimiso ), + .phy_spiclk ( bridge_spiclk ), + .phy_spiss ( bridge_spiss ) + +); + + +/////////////////////////////////////////////////// +// instantiate the user core top-level + +core_top ic ( + + // physical connections + // + .clk_74a ( clk_74a ), + .clk_74b ( clk_74b ), + + .cart_tran_bank2 ( cart_tran_bank2 ), + .cart_tran_bank2_dir ( cart_tran_bank2_dir ), + .cart_tran_bank3 ( cart_tran_bank3 ), + .cart_tran_bank3_dir ( cart_tran_bank3_dir ), + .cart_tran_bank1 ( cart_tran_bank1 ), + .cart_tran_bank1_dir ( cart_tran_bank1_dir ), + .cart_tran_bank0 ( cart_tran_bank0 ), + .cart_tran_bank0_dir ( cart_tran_bank0_dir ), + .cart_tran_pin30 ( cart_tran_pin30 ), + .cart_tran_pin30_dir ( cart_tran_pin30_dir ), + .cart_pin30_pwroff_reset ( cart_pin30_pwroff_reset ), + .cart_tran_pin31 ( cart_tran_pin31 ), + .cart_tran_pin31_dir ( cart_tran_pin31_dir ), + + .port_ir_rx ( port_ir_rx ), + .port_ir_tx ( port_ir_tx ), + .port_ir_rx_disable ( port_ir_rx_disable ), + + .port_tran_si ( port_tran_si ), + .port_tran_si_dir ( port_tran_si_dir ), + .port_tran_so ( port_tran_so ), + .port_tran_so_dir ( port_tran_so_dir ), + .port_tran_sck ( port_tran_sck ), + .port_tran_sck_dir ( port_tran_sck_dir ), + .port_tran_sd ( port_tran_sd ), + .port_tran_sd_dir ( port_tran_sd_dir ), + + .cram0_a ( cram0_a ), + .cram0_dq ( cram0_dq ), + .cram0_wait ( cram0_wait ), + .cram0_clk ( cram0_clk ), + .cram0_adv_n ( cram0_adv_n ), + .cram0_cre ( cram0_cre ), + .cram0_ce0_n ( cram0_ce0_n ), + .cram0_ce1_n ( cram0_ce1_n ), + .cram0_oe_n ( cram0_oe_n ), + .cram0_we_n ( cram0_we_n ), + .cram0_ub_n ( cram0_ub_n ), + .cram0_lb_n ( cram0_lb_n ), + .cram1_a ( cram1_a ), + .cram1_dq ( cram1_dq ), + .cram1_wait ( cram1_wait ), + .cram1_clk ( cram1_clk ), + .cram1_adv_n ( cram1_adv_n ), + .cram1_cre ( cram1_cre ), + .cram1_ce0_n ( cram1_ce0_n ), + .cram1_ce1_n ( cram1_ce1_n ), + .cram1_oe_n ( cram1_oe_n ), + .cram1_we_n ( cram1_we_n ), + .cram1_ub_n ( cram1_ub_n ), + .cram1_lb_n ( cram1_lb_n ), + + .dram_a ( dram_a ), + .dram_ba ( dram_ba ), + .dram_dq ( dram_dq ), + .dram_dqm ( dram_dqm ), + .dram_clk ( dram_clk ), + .dram_cke ( dram_cke ), + .dram_ras_n ( dram_ras_n ), + .dram_cas_n ( dram_cas_n ), + .dram_we_n ( dram_we_n ), + + .sram_a ( sram_a ), + .sram_dq ( sram_dq ), + .sram_oe_n ( sram_oe_n ), + .sram_we_n ( sram_we_n ), + .sram_ub_n ( sram_ub_n ), + .sram_lb_n ( sram_lb_n ), + + .vblank ( vblank ), + .vpll_feed ( vpll_feed ), + + .dbg_tx ( dbg_tx ), + .dbg_rx ( dbg_rx ), + .user1 ( user1 ), + .user2 ( user2 ), + + .aux_sda ( aux_sda ), + .aux_scl ( aux_scl ), + + + // logical connections with user core + // + .video_rgb ( video_rgb ), + .video_rgb_clock ( video_rgb_clock ), + .video_rgb_clock_90 ( video_rgb_clock_90 ), + .video_de ( video_de ), + .video_skip ( video_skip ), + .video_vs ( video_vs ), + .video_hs ( video_hs ), + + .audio_mclk ( scal_audmclk ), + .audio_adc ( scal_audadc ), + .audio_dac ( scal_auddac ), + .audio_lrck ( scal_audlrck ), + + .bridge_endian_little ( bridge_endian_little ), + .bridge_addr ( bridge_addr ), + .bridge_rd ( bridge_rd ), + .bridge_rd_data ( bridge_rd_data ), + .bridge_wr ( bridge_wr ), + .bridge_wr_data ( bridge_wr_data ), + + .cont1_key ( cont1_key ), + .cont2_key ( cont2_key ), + .cont3_key ( cont3_key ), + .cont4_key ( cont4_key ), + .cont1_joy ( cont1_joy ), + .cont2_joy ( cont2_joy ), + .cont3_joy ( cont3_joy ), + .cont4_joy ( cont4_joy ), + .cont1_trig ( cont1_trig ), + .cont2_trig ( cont2_trig ), + .cont3_trig ( cont3_trig ), + .cont4_trig ( cont4_trig ) + +); + +endmodule + diff --git a/platform/pocket/build_cdf.tcl b/platform/pocket/build_cdf.tcl new file mode 100644 index 0000000..ec99b5d --- /dev/null +++ b/platform/pocket/build_cdf.tcl @@ -0,0 +1,48 @@ +# ============================================================================== +# SPDX-License-Identifier: CC0-1.0 +# SPDX-FileType: SOURCE +# SPDX-FileCopyrightText: (c) 2022, OpenGateware authors and contributors +# ============================================================================== +# @file: build_cd.h +# @brief: Generate a JTAG Chain Description File. +# Create a .cdf file to be used with Quartus Prime Programmer +# ============================================================================== +proc createChainDescriptionFile {revision device outpath project_name} { + set outputFileName "$project_name.cdf" + set outputFile [open $outputFileName "w"] + + puts $outputFile "JedecChain;" + puts $outputFile " FileRevision(JESD32A);" + puts $outputFile " DefaultMfr(6E);" + puts $outputFile "" + puts $outputFile " P ActionCode(Cfg)" + puts $outputFile " Device PartName($device) Path(\"$outpath/\") File(\"$revision.sof\") MfrSpec(OpMask(1));" + puts $outputFile "ChainEnd;" + puts $outputFile "" + puts $outputFile "AlteraBegin;" + puts $outputFile " ChainType(JTAG);" + puts $outputFile "AlteraEnd;" +} + +set project_name [lindex $quartus(args) 1] +set revision [lindex $quartus(args) 2] + +if {[project_exists $project_name]} { + if {[string equal "" $revision]} { + project_open $project_name -revision [get_current_revision $project_name] + } else { + project_open $project_name -revision $revision + } +} else { + post_message -type error "Project $project_name does not exist" + exit +} + +set device [get_global_assignment -name DEVICE] +set outpath [get_global_assignment -name PROJECT_OUTPUT_DIRECTORY] + +if [is_project_open] { + project_close +} + +createChainDescriptionFile $revision $device $outpath $project_name diff --git a/platform/pocket/build_id_gen.tcl b/platform/pocket/build_id_gen.tcl new file mode 100644 index 0000000..91b0627 --- /dev/null +++ b/platform/pocket/build_id_gen.tcl @@ -0,0 +1,171 @@ +# ================================================================================ +# (c) 2011 Altera Corporation. All rights reserved. +# Altera products are protected under numerous U.S. and foreign patents, maskwork +# rights, copyrights and other intellectual property laws. +# +# This reference design file, and your use thereof, is subject to and governed +# by the terms and conditions of the applicable Altera Reference Design License +# Agreement (either as signed by you, agreed by you upon download or as a +# "click-through" agreement upon installation andor found at www.altera.com). +# By using this reference design file, you indicate your acceptance of such terms +# and conditions between you and Altera Corporation. In the event that you do +# not agree with such terms and conditions, you may not use the reference design +# file and please promptly destroy any copies you have made. +# +# This reference design file is being provided on an "as-is" basis and as an +# accommodation and therefore all warranties, representations or guarantees of +# any kind (whether express, implied or statutory) including, without limitation, +# warranties of merchantability, non-infringement, or fitness for a particular +# purpose, are specifically disclaimed. By making this reference design file +# available, Altera expressly does not recommend, suggest or require that this +# reference design file be used in combination with any other product not +# provided by Altera. +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, physical address, and host name +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# The format for each value is as follows: +# Date - 32-bit decimal number of the format mmddyyyy +# Time - 32-bit decimal number of the format hhmmss +# Phyiscal Address - 48-bit hexadecimal number +# Host name - 120-bit hexadecimal number with pairs of digits equal to the +# hexadecimal code for the first 15 ASCII characters of the host +# name. For added clarity, host names that have fewer than 30 +# hexadecimal digits (15 characters) are padded on the left with +# zeros. +# +# Usage: +# +# To manually execute this script, source this file using the following Tcl commands: +# source build_id_verilog.tcl +# +# To have this script automatically execute each time your project is built, use the +# following command (see: http://www.altera.com/support/examples/tcl/auto_processing.html): +# set_global_assignment -name PRE_FLOW_SCRIPT_FILE quartus_sh:build_id_verilog.tcl +# +# Comment out the last line to prevent the process from automatically executing when +# the file is sourced. The process can then be executed with the following command: +# generateBuildID_Verilog +# +# +# For more information, see "build_identification.pdf" +# +# ================================================================================ +# +# 2021-01-21 Analogue +# +# Only care about generating build date/time, so the rest was removed. +# The original can be downloaded from the Intel resource page +# + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %Y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "../platform/pocket/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "// Build ID Verilog Module" + puts $outputFile "//" + puts $outputFile "// Note - these are stored as binary coded decimal" + puts $outputFile "// Date: $buildDate" + puts $outputFile "// Time: $buildTime" + puts $outputFile "" + puts $outputFile "module build_id" + puts $outputFile "(" + puts $outputFile " output \[31:0\] build_date," + puts $outputFile " output \[31:0\] build_time" + puts $outputFile ");" + puts $outputFile "" + puts $outputFile " assign build_date = 32'h$buildDate;" + puts $outputFile " assign build_time = 32'h$buildTime;" + puts $outputFile "" + puts $outputFile "endmodule" + close $outputFile + + + + # Send confirmation message to the Messages window + #post_message "APF core build date/time generated: [pwd]/$outputFileName" + #post_message "Date: $buildDate" + #post_message "Time: $buildTime" +} + + +proc generateBuildID_MIF {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %Y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + set buildUnique [expr {int(rand()*(4294967295))}] + + set buildDateNoLeadingZeros [string trimleft $buildDate "0"] + set buildTimeNoLeadingZeros [string trimleft $buildTime "0"] + set buildDate4Byte [format "%08d" $buildDateNoLeadingZeros] + set buildTime4Byte [format "%08d" $buildTimeNoLeadingZeros] + set buildUnique4Byte [format "%08x" $buildUnique] + + #set buildDate4Byte \ + [concat [string range $buildDate 0 1] \ + [string range $buildDate 2 3] \ + [string range $buildDate 4 5] \ + [string range $buildDate 6 7] ] + + + set buildDateNumBytes 4 + set buildTimeNumBytes 4 + + # Calculate depth of the memory (8-bit) words + set memoryDepth [expr $buildDateNumBytes + $buildTimeNumBytes] + + # Create a Memory Initialization File for output + set outputFileName "../platform/pocket/build_id.mif" + set outputFile [open $outputFileName "w"] + + # Output the MIF header (see: http://quartushelp.altera.com/current/mergedProjects/reference/glossary/def_mif.htm) + puts $outputFile "-- Build ID Memory Initialization File" + puts $outputFile "--" + puts $outputFile "" + puts $outputFile "DEPTH = 256;" + puts $outputFile "WIDTH = 32;" + puts $outputFile "ADDRESS_RADIX = HEX;" + puts $outputFile "DATA_RADIX = HEX;" + puts $outputFile "" + puts $outputFile "CONTENT" + puts $outputFile "BEGIN" + puts $outputFile "" + puts $outputFile " 0E0 : $buildDate4Byte;" + puts $outputFile " 0E1 : $buildTime4Byte;" + puts $outputFile " 0E2 : $buildUnique4Byte;" + puts $outputFile "" + puts $outputFile "END;" + + # Close file to complete write + close $outputFile + + # Send confirmation message to the Messages window + post_message "APF core build date/time generated: [pwd]/$outputFileName" +} + +generateBuildID_MIF + +# 2021-01-21 Analogue +# +# There are some circumstances where you want all parts of a FPGA flow to be deterministic, especially +# when trying to hash out timing issues. +# You should comment this line out and temporarily bypass buildid generation so that synthesis/par +# have consistent working input. MIF bram contents like above won't affect the random seed or trigger +# recompilation. +# Don't forget to re-enable before you release. +# +# generateBuildID_Verilog diff --git a/platform/pocket/common.v b/platform/pocket/common.v new file mode 100644 index 0000000..6c8c0f2 --- /dev/null +++ b/platform/pocket/common.v @@ -0,0 +1,152 @@ +// Software License Agreement + +// The software supplied herewith by Analogue Enterprises Limited (the "Company”), +// the Analogue Pocket Framework (“APF”), is provided and licensed to you, the +// Company's customer, solely for use in designing, testing and creating +// applications for use with Company's Products or Services. The software is +// owned by the Company and/or its licensors, and is protected under applicable +// laws, including, but not limited to, U.S. copyright law. All rights are +// reserved. By using the APF code you are agreeing to the terms of the End User +// License Agreement (“EULA”) located at [https://www.analogue.link/pocket-eula] +// and incorporated herein by reference. + +// THE SOFTWARE IS PROVIDED "AS-IS" AND WE EXPRESSLY DISCLAIM ANY IMPLIED +// WARRANTIES TO THE FULLEST EXTENT PROVIDED BY LAW, INCLUDING BUT NOT LIMITED TO, +// ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE OR +// NON-INFRINGEMENT. TO THE EXTENT APPLICABLE LAWS PROHIBIT TERMS OF USE FROM +// DISCLAIMING ANY IMPLIED WARRANTY, SUCH IMPLIED WARRANTY SHALL BE LIMITED TO THE +// MINIMUM WARRANTY PERIOD REQUIRED BY LAW, AND IF NO SUCH PERIOD IS REQUIRED, +// THEN THIRTY (30) DAYS FROM FIRST USE OF THE SOFTWARE. WE CANNOT GUARANTEE AND +// DO NOT PROMISE ANY SPECIFIC RESULTS FROM USE OF THE SOFTWARE. WITHOUT LIMITING +// THE FOREGOING, WE DO NOT WARRANT THAT THE SOFTWARE WILL BE UNINTERRUPTED OR +// ERROR-FREE. IN NO EVENT WILL WE BE LIABLE TO YOU OR ANY OTHER PERSON FOR ANY +// INDIRECT, CONSEQUENTIAL, EXEMPLARY, INCIDENTAL, SPECIAL OR PUNITIVE DAMAGES, +// INCLUDING BUT NOT LIMITED TO, LOST PROFITS ARISING OUT OF YOUR USE, OR +// INABILITY TO USE, THE SOFTWARE, EVEN IF WE HAVE BEEN ADVISED OF THE POSSIBILITY +// OF SUCH DAMAGES. UNDER NO CIRCUMSTANCES SHALL OUR LIABILITY TO YOU FOR ANY +// CLAIM OR CAUSE OF ACTION WHATSOEVER, AND REGARDLESS OF THE FORM OF THE ACTION, +// WHETHER ARISING IN CONTRACT, TORT OR OTHERWISE, EXCEED THE AMOUNT PAID BY YOU +// TO US, IF ANY, DURING THE 90 DAY PERIOD IMMEDIATELY PRECEDING THE DATE ON WHICH +// YOU FIRST ASSERT ANY SUCH CLAIM. THE FOREGOING LIMITATIONS SHALL APPLY TO THE +// FULLEST EXTENT PERMITTED BY APPLICABLE LAW. +// +// 2-stage synchronizer +// +module synch_2 #(parameter WIDTH = 1) ( + input wire [WIDTH-1:0] i, // input signal + output reg [WIDTH-1:0] o, // synchronized output + input wire clk, // clock to synchronize on + output wire rise, // one-cycle rising edge pulse + output wire fall // one-cycle falling edge pulse +); + +reg [WIDTH-1:0] stage_1; +reg [WIDTH-1:0] stage_2; +reg [WIDTH-1:0] stage_3; + +assign rise = (WIDTH == 1) ? (o & ~stage_2) : 1'b0; +assign fall = (WIDTH == 1) ? (~o & stage_2) : 1'b0; +always @(posedge clk) + {stage_2, o, stage_1} <= {o, stage_1, i}; + +endmodule + + +// +// 3-stage synchronizer +// +module synch_3 #(parameter WIDTH = 1) ( + input wire [WIDTH-1:0] i, // input signal + output reg [WIDTH-1:0] o, // synchronized output + input wire clk, // clock to synchronize on + output wire rise, // one-cycle rising edge pulse + output wire fall // one-cycle falling edge pulse +); + +reg [WIDTH-1:0] stage_1; +reg [WIDTH-1:0] stage_2; +reg [WIDTH-1:0] stage_3; + +assign rise = (WIDTH == 1) ? (o & ~stage_3) : 1'b0; +assign fall = (WIDTH == 1) ? (~o & stage_3) : 1'b0; +always @(posedge clk) + {stage_3, o, stage_2, stage_1} <= {o, stage_2, stage_1, i}; + +endmodule + + +module bram_block_dp #( + parameter DATA = 32, + parameter ADDR = 7 +) ( + input wire a_clk, + input wire a_wr, + input wire [ADDR-1:0] a_addr, + input wire [DATA-1:0] a_din, + output reg [DATA-1:0] a_dout, + + input wire b_clk, + input wire b_wr, + input wire [ADDR-1:0] b_addr, + input wire [DATA-1:0] b_din, + output reg [DATA-1:0] b_dout +); + +reg [DATA-1:0] mem [(2**ADDR)-1:0]; + +always @(posedge a_clk) begin + if(a_wr) begin + a_dout <= a_din; + mem[a_addr] <= a_din; + end else + a_dout <= mem[a_addr]; +end + +always @(posedge b_clk) begin + if(b_wr) begin + b_dout <= b_din; + mem[b_addr] <= b_din; + end else + b_dout <= mem[b_addr]; +end + +endmodule + + +module bram_block_dp_nonstd #( + parameter DATA = 32, + parameter ADDR = 7, + parameter DEPTH = 128 +) ( + input wire a_clk, + input wire a_wr, + input wire [ADDR-1:0] a_addr, + input wire [DATA-1:0] a_din, + output reg [DATA-1:0] a_dout, + + input wire b_clk, + input wire b_wr, + input wire [ADDR-1:0] b_addr, + input wire [DATA-1:0] b_din, + output reg [DATA-1:0] b_dout +); + +reg [DATA-1:0] mem [DEPTH-1:0]; + +always @(posedge a_clk) begin + if(a_wr) begin + a_dout <= a_din; + mem[a_addr] <= a_din; + end else + a_dout <= mem[a_addr]; +end + +always @(posedge b_clk) begin + if(b_wr) begin + b_dout <= b_din; + mem[b_addr] <= b_din; + end else + b_dout <= mem[b_addr]; +end + +endmodule diff --git a/platform/pocket/io_bridge_peripheral.v b/platform/pocket/io_bridge_peripheral.v new file mode 100644 index 0000000..7e0467c --- /dev/null +++ b/platform/pocket/io_bridge_peripheral.v @@ -0,0 +1,331 @@ +// Software License Agreement + +// The software supplied herewith by Analogue Enterprises Limited (the "Company”), +// the Analogue Pocket Framework (“APF”), is provided and licensed to you, the +// Company's customer, solely for use in designing, testing and creating +// applications for use with Company's Products or Services. The software is +// owned by the Company and/or its licensors, and is protected under applicable +// laws, including, but not limited to, U.S. copyright law. All rights are +// reserved. By using the APF code you are agreeing to the terms of the End User +// License Agreement (“EULA”) located at [https://www.analogue.link/pocket-eula] +// and incorporated herein by reference. + +// THE SOFTWARE IS PROVIDED "AS-IS" AND WE EXPRESSLY DISCLAIM ANY IMPLIED +// WARRANTIES TO THE FULLEST EXTENT PROVIDED BY LAW, INCLUDING BUT NOT LIMITED TO, +// ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE OR +// NON-INFRINGEMENT. TO THE EXTENT APPLICABLE LAWS PROHIBIT TERMS OF USE FROM +// DISCLAIMING ANY IMPLIED WARRANTY, SUCH IMPLIED WARRANTY SHALL BE LIMITED TO THE +// MINIMUM WARRANTY PERIOD REQUIRED BY LAW, AND IF NO SUCH PERIOD IS REQUIRED, +// THEN THIRTY (30) DAYS FROM FIRST USE OF THE SOFTWARE. WE CANNOT GUARANTEE AND +// DO NOT PROMISE ANY SPECIFIC RESULTS FROM USE OF THE SOFTWARE. WITHOUT LIMITING +// THE FOREGOING, WE DO NOT WARRANT THAT THE SOFTWARE WILL BE UNINTERRUPTED OR +// ERROR-FREE. IN NO EVENT WILL WE BE LIABLE TO YOU OR ANY OTHER PERSON FOR ANY +// INDIRECT, CONSEQUENTIAL, EXEMPLARY, INCIDENTAL, SPECIAL OR PUNITIVE DAMAGES, +// INCLUDING BUT NOT LIMITED TO, LOST PROFITS ARISING OUT OF YOUR USE, OR +// INABILITY TO USE, THE SOFTWARE, EVEN IF WE HAVE BEEN ADVISED OF THE POSSIBILITY +// OF SUCH DAMAGES. UNDER NO CIRCUMSTANCES SHALL OUR LIABILITY TO YOU FOR ANY +// CLAIM OR CAUSE OF ACTION WHATSOEVER, AND REGARDLESS OF THE FORM OF THE ACTION, +// WHETHER ARISING IN CONTRACT, TORT OR OTHERWISE, EXCEED THE AMOUNT PAID BY YOU +// TO US, IF ANY, DURING THE 90 DAY PERIOD IMMEDIATELY PRECEDING THE DATE ON WHICH +// YOU FIRST ASSERT ANY SUCH CLAIM. THE FOREGOING LIMITATIONS SHALL APPLY TO THE +// FULLEST EXTENT PERMITTED BY APPLICABLE LAW. +// +// bridge peripheral for socrates PMP bridge to heraclitus+aristotle +// 2020-2022 Analogue +// +// please note that while writes are immediate, +// reads are buffered by 1 word. this is necessary to maintain +// data throughput while reading from slower data sources like +// sdram. +// reads should always return the current bus value, and kickstart +// into the next read immediately. this way, you have the entire +// next word time to retrieve the data, instead of just a few +// cycles. +// +// the worst-case read/write timing is every 88 cycles @ 74.25mhz +// which is about 1180ns. + +module io_bridge_peripheral ( + +input wire clk, +input wire reset_n, + +input wire endian_little, + +output reg [31:0] pmp_addr, +output reg pmp_addr_valid, +output reg pmp_rd, +input wire [31:0] pmp_rd_data, +output reg pmp_wr, +output reg [31:0] pmp_wr_data, + +inout reg phy_spimosi, +inout reg phy_spimiso, +inout reg phy_spiclk, +input wire phy_spiss + +); + +// +// clock domain: clk (74.25mhz) rising edge +// + wire reset_n_s; +synch_3 s00(reset_n, reset_n_s, clk); + + wire endian_little_s; +synch_3 s01(endian_little, endian_little_s, clk); + + wire phy_spiss_s, phy_spiss_r, phy_spiss_f; +synch_3 s02(phy_spiss, phy_spiss_s, clk, phy_spiss_r, phy_spiss_f); + + + reg [4:0] state; + localparam ST_RESET = 'd0; + localparam ST_IDLE = 'd1; + localparam ST_READ_0 = 'd2; + localparam ST_READ_1 = 'd3; + localparam ST_READ_2 = 'd4; + localparam ST_READ_3 = 'd5; + localparam ST_WRITE_0 = 'd6; + localparam ST_WRITE_1 = 'd7; + localparam ST_WRITE_2 = 'd8; + localparam ST_ADDR_0 = 'd9; + + reg [1:0] addr_cnt; + reg [1:0] data_cnt; + reg [6:0] read_cnt; + + // synchronize rd byte flag's rising edge into clk + wire rx_byte_done_s, rx_byte_done_r; +synch_3 s03(rx_byte_done, rx_byte_done_s, clk, rx_byte_done_r); + + + reg [4:0] spis; + localparam ST_SIDLE = 'd1; + localparam ST_SEND_N = 'd6; + localparam ST_SEND_0 = 'd2; + localparam ST_SEND_1 = 'd3; + localparam ST_SEND_2 = 'd4; + localparam ST_SEND_3 = 'd5; + reg spis_tx; + reg [31:0] spis_word_tx; + reg [31:0] spis_word; + reg [4:0] spis_count; + reg spis_done; + + reg rx_byte_done_r_1, rx_byte_done_r_2; + reg [7:0] rx_byte_1, rx_byte_2; + + // handle reversing endianness on both ports + reg [31:0] pmp_wr_data_latch; + reg [31:0] pmp_rd_data_e; // asynchronous + reg [31:0] pmp_rd_data_buf; // buffer the last word for immediate response +always @(*) begin + pmp_wr_data <= endian_little_s ? { pmp_wr_data_latch[7:0], + pmp_wr_data_latch[15:8], + pmp_wr_data_latch[23:16], + pmp_wr_data_latch[31:24] + } : pmp_wr_data_latch; + + pmp_rd_data_e <= endian_little_s ? {pmp_rd_data[7:0], + pmp_rd_data[15:8], + pmp_rd_data[23:16], + pmp_rd_data[31:24] + } : pmp_rd_data; +end + +always @(posedge clk) begin + + rx_byte_2 <= rx_byte_1; + rx_byte_1 <= rx_byte; + + rx_byte_done_r_1 <= rx_byte_done_r; + rx_byte_done_r_2 <= rx_byte_done_r_1; + + case(state) + ST_RESET: begin + addr_cnt <= 0; + data_cnt <= 0; + pmp_wr <= 0; + pmp_rd <= 0; + pmp_addr_valid <= 0; + spis_tx <= 0; + + state <= ST_ADDR_0; + end + ST_ADDR_0: begin + // transaction has started + + if(rx_byte_done_r_2) begin + case(addr_cnt) + 0: pmp_addr[31:24] <= rx_byte_2; + 1: pmp_addr[23:16] <= rx_byte_2; + 2: pmp_addr[15: 8] <= rx_byte_2; + 3: begin + pmp_addr[ 7: 0] <= {rx_byte_2[7:2], 2'b00}; + // address is latched + if( rx_byte_2[0] ) begin + data_cnt <= 0; + state <= ST_WRITE_0; + end else begin + data_cnt <= 0; + read_cnt <= 0; + state <= ST_READ_0; + end + end + endcase + + addr_cnt <= addr_cnt + 1'b1; + end + end + ST_WRITE_0: begin + // give notice, address has become valid + pmp_addr_valid <= 1; + + if(rx_byte_done_r_2) begin + case(data_cnt) + 0: pmp_wr_data_latch[31:24] <= rx_byte_2; + 1: pmp_wr_data_latch[23:16] <= rx_byte_2; + 2: pmp_wr_data_latch[15: 8] <= rx_byte_2; + 3: begin + pmp_wr_data_latch[ 7: 0] <= rx_byte_2; + state <= ST_WRITE_1; + end + endcase + data_cnt <= data_cnt + 1'b1; + end + end + ST_WRITE_1: begin + pmp_wr <= 1; + state <= ST_WRITE_2; + end + ST_WRITE_2: begin + // exited upon new transaction + pmp_wr <= 0; + end + ST_READ_0: begin + pmp_addr_valid <= 1; + + // delay a few cycles + read_cnt <= read_cnt + 1'b1; + if(read_cnt == 4-1) begin + // load the buffer with the current data + // and give the current buffer contents to bridge + spis_word_tx <= pmp_rd_data_e; + spis_tx <= 1; + + state <= ST_READ_1; + end + end + ST_READ_1: begin + pmp_rd <= 1; + state <= ST_READ_2; + end + ST_READ_2: begin + pmp_rd <= 0; + if(spis_done) begin + spis_tx <= 0; + state <= ST_READ_3; + end + end + ST_READ_3: begin + // exited upon new transaction + end + endcase + + + + + // + // word transmit + // + spis_done <= 0; + case(spis) + ST_SIDLE: begin + spis_count <= 0; + + phy_spiclk <= 1'bZ; + phy_spimosi <= 1'bZ; + phy_spimiso <= 1'bZ; + + if(spis_tx) begin + spis_word <= spis_word_tx; + spis <= ST_SEND_N; + end + end + // drive high first + ST_SEND_N: begin + phy_spiclk <= 1'b1; + phy_spimosi <= 1'b1; + phy_spimiso <= 1'b1; + spis <= ST_SEND_0; + end + // tx, shift out bits + ST_SEND_0: begin + phy_spiclk <= 0; + spis <= ST_SEND_1; + phy_spimosi <= spis_word[31]; + phy_spimiso <= spis_word[30]; + spis_word <= {spis_word[29:0], 2'b00}; + end + ST_SEND_1: begin + phy_spiclk <= 1; + spis <= ST_SEND_0; + spis_count <= spis_count + 1'b1; + if(spis_count == 15) spis <= ST_SEND_2; + end + ST_SEND_2: begin + phy_spiclk <= 1'b1; + phy_spimosi <= 1'b1; + phy_spimiso <= 1'b1; + spis <= ST_SEND_3; + spis_done <= 1; + end + ST_SEND_3: begin + spis <= ST_SIDLE; + end + endcase + + if(phy_spiss_s) begin + // select is high, go back to reset + state <= ST_RESET; + spis <= ST_SIDLE; + end + +end + + +// +// clock domain: phy_spiclk rising edge +// + reg [1:0] rx_latch_idx; + reg [7:0] rx_dat; + reg [7:0] rx_byte; // latched by clk, but upon a synchronized trigger + reg rx_byte_done; + +always @(posedge phy_spiclk or posedge phy_spiss) begin + + if(phy_spiss) begin + // reset + rx_byte_done <= 0; + rx_latch_idx <= 0; + + end else begin + // spiclk rising edge, latch data + rx_byte_done <= 0; + + case(rx_latch_idx) + 0: begin rx_dat[7:6] <= {phy_spimosi, phy_spimiso}; rx_latch_idx <= 1; end + 1: begin rx_dat[5:4] <= {phy_spimosi, phy_spimiso}; rx_latch_idx <= 2; end + 2: begin rx_dat[3:2] <= {phy_spimosi, phy_spimiso}; rx_latch_idx <= 3; end + 3: begin + // last bit of the byte + rx_byte <= {rx_dat[7:2], phy_spimosi, phy_spimiso}; + rx_latch_idx <= 0; + rx_byte_done <= 1; + end + endcase + end +end + +endmodule diff --git a/platform/pocket/io_pad_controller.v b/platform/pocket/io_pad_controller.v new file mode 100644 index 0000000..26e4c2e --- /dev/null +++ b/platform/pocket/io_pad_controller.v @@ -0,0 +1,324 @@ +// Software License Agreement + +// The software supplied herewith by Analogue Enterprises Limited (the "Company”), +// the Analogue Pocket Framework (“APF”), is provided and licensed to you, the +// Company's customer, solely for use in designing, testing and creating +// applications for use with Company's Products or Services. The software is +// owned by the Company and/or its licensors, and is protected under applicable +// laws, including, but not limited to, U.S. copyright law. All rights are +// reserved. By using the APF code you are agreeing to the terms of the End User +// License Agreement (“EULA”) located at [https://www.analogue.link/pocket-eula] +// and incorporated herein by reference. + +// THE SOFTWARE IS PROVIDED "AS-IS" AND WE EXPRESSLY DISCLAIM ANY IMPLIED +// WARRANTIES TO THE FULLEST EXTENT PROVIDED BY LAW, INCLUDING BUT NOT LIMITED TO, +// ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE OR +// NON-INFRINGEMENT. TO THE EXTENT APPLICABLE LAWS PROHIBIT TERMS OF USE FROM +// DISCLAIMING ANY IMPLIED WARRANTY, SUCH IMPLIED WARRANTY SHALL BE LIMITED TO THE +// MINIMUM WARRANTY PERIOD REQUIRED BY LAW, AND IF NO SUCH PERIOD IS REQUIRED, +// THEN THIRTY (30) DAYS FROM FIRST USE OF THE SOFTWARE. WE CANNOT GUARANTEE AND +// DO NOT PROMISE ANY SPECIFIC RESULTS FROM USE OF THE SOFTWARE. WITHOUT LIMITING +// THE FOREGOING, WE DO NOT WARRANT THAT THE SOFTWARE WILL BE UNINTERRUPTED OR +// ERROR-FREE. IN NO EVENT WILL WE BE LIABLE TO YOU OR ANY OTHER PERSON FOR ANY +// INDIRECT, CONSEQUENTIAL, EXEMPLARY, INCIDENTAL, SPECIAL OR PUNITIVE DAMAGES, +// INCLUDING BUT NOT LIMITED TO, LOST PROFITS ARISING OUT OF YOUR USE, OR +// INABILITY TO USE, THE SOFTWARE, EVEN IF WE HAVE BEEN ADVISED OF THE POSSIBILITY +// OF SUCH DAMAGES. UNDER NO CIRCUMSTANCES SHALL OUR LIABILITY TO YOU FOR ANY +// CLAIM OR CAUSE OF ACTION WHATSOEVER, AND REGARDLESS OF THE FORM OF THE ACTION, +// WHETHER ARISING IN CONTRACT, TORT OR OTHERWISE, EXCEED THE AMOUNT PAID BY YOU +// TO US, IF ANY, DURING THE 90 DAY PERIOD IMMEDIATELY PRECEDING THE DATE ON WHICH +// YOU FIRST ASSERT ANY SUCH CLAIM. THE FOREGOING LIMITATIONS SHALL APPLY TO THE +// FULLEST EXTENT PERMITTED BY APPLICABLE LAW. +// +// pad controller +// 2020-08-10 Analogue - started +// + +module io_pad_controller ( + +input wire clk, +input wire reset_n, + +inout reg pad_1wire, + +output reg [15:0] cont1_key, +output reg [15:0] cont2_key, +output reg [15:0] cont3_key, +output reg [15:0] cont4_key, +output reg [31:0] cont1_joy, +output reg [31:0] cont2_joy, +output reg [31:0] cont3_joy, +output reg [31:0] cont4_joy, +output reg [15:0] cont1_trig, +output reg [15:0] cont2_trig, +output reg [15:0] cont3_trig, +output reg [15:0] cont4_trig, + +output reg rx_timed_out +); + + wire reset_n_s; +synch_3 s00(reset_n, reset_n_s, clk); + + wire pad_1wire_s, pad_1wire_r, pad_1wire_f; +synch_3 s01(pad_1wire, pad_1wire_s, clk, pad_1wire_r, pad_1wire_f); + + +// +// protocol fsm +// + + reg [20:0] rx_timeout; // ~28ms + + reg [15:0] auto_poll_cnt; // 882us + reg auto_poll_queue; + + reg [18:0] heartbeat_cnt; // 7ms + reg heartbeat_queue; + + + localparam ST_RESET = 'd0; + localparam ST_IDLE = 'd1; + localparam ST_RX_BUTTON_1 = 'd2; + localparam ST_RX_BUTTON_2 = 'd3; + localparam ST_TX_SCALER = 'd4; + localparam ST_END_TX = 'd5; + + reg [3:0] state; + reg [3:0] cnt; + +always @(posedge clk) begin + tx_word_start <= 0; + + auto_poll_cnt <= auto_poll_cnt + 1'b1; + heartbeat_cnt <= heartbeat_cnt + 1'b1; + + // increment rx timeout, override and reset when idle below + rx_timeout <= rx_timeout + 1'b1; + + case(state) + ST_RESET: begin + reset_tr_n <= 0; + rx_timed_out <= 0; + + if(&rx_timeout[19:0]) begin + state <= ST_IDLE; + end + end + ST_IDLE: begin + // idle state + reset_tr_n <= 1; + rx_timeout <= 0; + cnt <= 0; + if(auto_poll_queue) begin + auto_poll_queue <= 0; + + tx_word_start <= 1; + tx_word <= 32'h4A10000C; + + state <= ST_RX_BUTTON_1; + end else if(heartbeat_queue) begin + heartbeat_queue <= 0; + + tx_word_start <= 1; + tx_word <= 32'h4AFE0000; + + state <= ST_END_TX; + end + end + // receive button words + ST_RX_BUTTON_1: begin + if(tx_word_done) begin + state <= ST_RX_BUTTON_2; + end + end + ST_RX_BUTTON_2: begin + if(rx_word_done) begin + cnt <= cnt + 1'b1; + case(cnt) + 0: cont1_key <= rx_word; + 1: cont1_joy <= rx_word; + 2: cont1_trig <= rx_word; + + 3: cont2_key <= rx_word; + 4: cont2_joy <= rx_word; + 5: cont2_trig <= rx_word; + + 6: cont3_key <= rx_word; + 7: cont3_joy <= rx_word; + 8: cont3_trig <= rx_word; + + 9: cont4_key <= rx_word; + 10: cont4_joy <= rx_word; + 11: begin + cont4_trig <= rx_word; + state <= ST_IDLE; + end + endcase + end + end + // do nothing + ST_END_TX: begin + // done sending, idle again + if(tx_word_done) begin + state <= ST_IDLE; + end + end + endcase + + + if(&auto_poll_cnt) begin + auto_poll_queue <= 1; + end + if(&heartbeat_cnt) begin + heartbeat_queue <= 1; + end + + if(&rx_timeout) begin + // reset protocol FSM which will also reset t/r engine + rx_timed_out <= 1; + rx_timeout <= 0; + state <= ST_RESET; + end + + if(~reset_n_s) begin + state <= ST_RESET; + end +end + + + + + +// +// word receive/transmit engine +// + reg reset_tr_n; + localparam BITLEN = 60; + + reg rx_word_done; + reg [31:0] rx_word_shift; + reg [31:0] rx_word; + + reg tx_word_start, tx_word_start_1; + reg tx_word_done; + reg [31:0] tx_word; + reg [31:0] tx_word_shift; + + reg [7:0] tr_cnt; + reg [5:0] tr_bit; + + localparam TR_IDLE = 'd1; + localparam TR_TX_START = 'd2; + localparam TR_TX_CONTINUE = 'd3; + localparam TR_TX_DONE = 'd4; + localparam TR_RX_START = 'd5; + localparam TR_RX_WAITEDGE = 'd6; + localparam TR_RX_DONE = 'd7; + + reg [3:0] tr_state; + +always @(posedge clk) begin + + rx_word_done <= 0; + tx_word_done <= 0; + + tx_word_start_1 <= tx_word_start; + + case(tr_state) + TR_IDLE: begin + tr_bit <= 0; + tr_cnt <= 0; + + pad_1wire <= 1'bZ; + + if(tx_word_start & ~tx_word_start_1) begin + // transmit word + tx_word_shift <= tx_word; + tr_state <= TR_TX_START; + end + + if(pad_1wire_f) begin + // receive word + tr_state <= TR_RX_START; + end + end + + // transmit 32bit + TR_TX_START: begin + // insert delay + tr_cnt <= tr_cnt + 1'b1; + if(&tr_cnt) begin + // drive from tristate(high) to explicitly high to prevent glitching + pad_1wire <= 1'b1; + tr_state <= TR_TX_CONTINUE; + end + end + TR_TX_CONTINUE: begin + tr_cnt <= tr_cnt + 1'b1; + case(tr_cnt) + 0: begin + pad_1wire <= 1'b0; + end + (BITLEN/3): begin + pad_1wire <= tx_word_shift[31]; + end + (BITLEN*2/3): begin + pad_1wire <= 1'b1; + end + (BITLEN-1): begin + tr_cnt <= 0; + tx_word_shift <= {tx_word_shift[30:0], 1'b1}; + + tr_bit <= tr_bit + 1'b1; + if(tr_bit == 31) begin + tr_state <= TR_TX_DONE; + end + end + endcase + end + TR_TX_DONE: begin + tx_word_done <= 1; + tr_state <= TR_IDLE; + end + + // receive 32bit + TR_RX_START: begin + tr_cnt <= tr_cnt + 1'b1; + case(tr_cnt) + (BITLEN/2-4): begin + rx_word_shift <= {rx_word_shift[30:0], pad_1wire_s}; + end + (BITLEN*5/6): begin + tr_cnt <= 0; + + // wait for next falling edge + tr_state <= TR_RX_WAITEDGE; + tr_bit <= tr_bit + 1'b1; + if(tr_bit == 31) begin + // if this is bit32, don't wait and finish + tr_state <= TR_RX_DONE; + end + end + endcase + end + TR_RX_WAITEDGE: begin + if(pad_1wire_f) begin + tr_state <= TR_RX_START; + end + end + TR_RX_DONE: begin + rx_word <= rx_word_shift; + rx_word_done <= 1; + tr_state <= TR_IDLE; + end + + default: begin + tr_state <= TR_IDLE; + end + endcase + + if(~reset_n_s | ~reset_tr_n) tr_state <= TR_IDLE; +end + +endmodule diff --git a/platform/pocket/mf_datatable.qip b/platform/pocket/mf_datatable.qip new file mode 100644 index 0000000..9c3a0f7 --- /dev/null +++ b/platform/pocket/mf_datatable.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" +set_global_assignment -name IP_TOOL_VERSION "18.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "mf_datatable.v"] diff --git a/platform/pocket/mf_datatable.v b/platform/pocket/mf_datatable.v new file mode 100644 index 0000000..33c26be --- /dev/null +++ b/platform/pocket/mf_datatable.v @@ -0,0 +1,247 @@ +// megafunction wizard: %RAM: 2-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: mf_datatable.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.1.1 Build 646 04/11/2019 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2019 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details, at +//https://fpgasoftware.intel.com/eula. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module mf_datatable ( + address_a, + address_b, + clock_a, + clock_b, + data_a, + data_b, + wren_a, + wren_b, + q_a, + q_b); + + input [7:0] address_a; + input [7:0] address_b; + input clock_a; + input clock_b; + input [31:0] data_a; + input [31:0] data_b; + input wren_a; + input wren_b; + output [31:0] q_a; + output [31:0] q_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock_a; + tri0 wren_a; + tri0 wren_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [31:0] sub_wire0; + wire [31:0] sub_wire1; + wire [31:0] q_a = sub_wire0[31:0]; + wire [31:0] q_b = sub_wire1[31:0]; + + altsyncram altsyncram_component ( + .address_a (address_a), + .address_b (address_b), + .clock0 (clock_a), + .clock1 (clock_b), + .data_a (data_a), + .data_b (data_b), + .wren_a (wren_a), + .wren_b (wren_b), + .q_a (sub_wire0), + .q_b (sub_wire1), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .eccstatus (), + .rden_a (1'b1), + .rden_b (1'b1)); + defparam + altsyncram_component.address_reg_b = "CLOCK1", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.indata_reg_b = "CLOCK1", + altsyncram_component.init_file = "./apf/build_id.mif", + altsyncram_component.intended_device_family = "Cyclone V", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 256, + altsyncram_component.numwords_b = 256, + altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_a = "CLOCK0", + altsyncram_component.outdata_reg_b = "CLOCK1", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 8, + altsyncram_component.widthad_b = 8, + altsyncram_component.width_a = 32, + altsyncram_component.width_b = 32, + altsyncram_component.width_byteena_a = 1, + altsyncram_component.width_byteena_b = 1, + altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLRdata NUMERIC "0" +// Retrieval info: PRIVATE: CLRq NUMERIC "0" +// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRrren NUMERIC "0" +// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRwren NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "5" +// Retrieval info: PRIVATE: Clock_A NUMERIC "0" +// Retrieval info: PRIVATE: Clock_B NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192" +// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "./apf/build_id.mif" +// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" +// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +// Retrieval info: PRIVATE: REGdata NUMERIC "1" +// Retrieval info: PRIVATE: REGq NUMERIC "1" +// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: REGrren NUMERIC "0" +// Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +// Retrieval info: PRIVATE: REGwren NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +// Retrieval info: PRIVATE: VarWidth NUMERIC "0" +// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32" +// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32" +// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32" +// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32" +// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: enable NUMERIC "0" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1" +// Retrieval info: CONSTANT: INIT_FILE STRING "./apf/build_id.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" +// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" +// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1" +// Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL "address_a[7..0]" +// Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL "address_b[7..0]" +// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a" +// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b" +// Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]" +// Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]" +// Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]" +// Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]" +// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" +// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" +// Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0 +// Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0 +// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0 +// Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 +// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 +// Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0 +// Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_datatable.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_datatable.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_datatable.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_datatable.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_datatable_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_datatable_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/platform/pocket/mf_ddio_bidir_12.qip b/platform/pocket/mf_ddio_bidir_12.qip new file mode 100644 index 0000000..40c4266 --- /dev/null +++ b/platform/pocket/mf_ddio_bidir_12.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_BIDIR" +set_global_assignment -name IP_TOOL_VERSION "18.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "mf_ddio_bidir_12.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mf_ddio_bidir_12.ppf"] diff --git a/platform/pocket/mf_ddio_bidir_12.v b/platform/pocket/mf_ddio_bidir_12.v new file mode 100644 index 0000000..6bac1ab --- /dev/null +++ b/platform/pocket/mf_ddio_bidir_12.v @@ -0,0 +1,134 @@ +// megafunction wizard: %ALTDDIO_BIDIR% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_BIDIR + +// ============================================================ +// File Name: mf_ddio_bidir_12.v +// Megafunction Name(s): +// ALTDDIO_BIDIR +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.1.1 Build 646 04/11/2019 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2019 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details, at +//https://fpgasoftware.intel.com/eula. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module mf_ddio_bidir_12 ( + datain_h, + datain_l, + inclock, + oe, + outclock, + dataout_h, + dataout_l, + padio); + + input [11:0] datain_h; + input [11:0] datain_l; + input inclock; + input oe; + input outclock; + output [11:0] dataout_h; + output [11:0] dataout_l; + inout [11:0] padio; + + wire [11:0] sub_wire0; + wire [11:0] sub_wire1; + wire [11:0] dataout_h = sub_wire0[11:0]; + wire [11:0] dataout_l = sub_wire1[11:0]; + + altddio_bidir ALTDDIO_BIDIR_component ( + .datain_h (datain_h), + .datain_l (datain_l), + .inclock (inclock), + .oe (oe), + .outclock (outclock), + .padio (padio), + .dataout_h (sub_wire0), + .dataout_l (sub_wire1), + .aclr (1'b0), + .aset (1'b0), + .combout (), + .dqsundelayedout (), + .inclocken (1'b1), + .oe_out (), + .outclocken (1'b1), + .sclr (1'b0), + .sset (1'b0)); + defparam + ALTDDIO_BIDIR_component.extend_oe_disable = "OFF", + ALTDDIO_BIDIR_component.implement_input_in_lcell = "OFF", + ALTDDIO_BIDIR_component.intended_device_family = "Cyclone V", + ALTDDIO_BIDIR_component.invert_output = "OFF", + ALTDDIO_BIDIR_component.lpm_hint = "UNUSED", + ALTDDIO_BIDIR_component.lpm_type = "altddio_bidir", + ALTDDIO_BIDIR_component.oe_reg = "UNREGISTERED", + ALTDDIO_BIDIR_component.power_up_high = "OFF", + ALTDDIO_BIDIR_component.width = 12; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF" +// Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir" +// Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +// Retrieval info: CONSTANT: WIDTH NUMERIC "12" +// Retrieval info: USED_PORT: datain_h 0 0 12 0 INPUT NODEFVAL "datain_h[11..0]" +// Retrieval info: CONNECT: @datain_h 0 0 12 0 datain_h 0 0 12 0 +// Retrieval info: USED_PORT: datain_l 0 0 12 0 INPUT NODEFVAL "datain_l[11..0]" +// Retrieval info: CONNECT: @datain_l 0 0 12 0 datain_l 0 0 12 0 +// Retrieval info: USED_PORT: dataout_h 0 0 12 0 OUTPUT NODEFVAL "dataout_h[11..0]" +// Retrieval info: CONNECT: dataout_h 0 0 12 0 @dataout_h 0 0 12 0 +// Retrieval info: USED_PORT: dataout_l 0 0 12 0 OUTPUT NODEFVAL "dataout_l[11..0]" +// Retrieval info: CONNECT: dataout_l 0 0 12 0 @dataout_l 0 0 12 0 +// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock" +// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 +// Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe" +// Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0 +// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" +// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +// Retrieval info: USED_PORT: padio 0 0 12 0 BIDIR NODEFVAL "padio[11..0]" +// Retrieval info: CONNECT: padio 0 0 12 0 @padio 0 0 12 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.bsf FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12_inst.v FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12_bb.v FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.inc FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.cmp FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.ppf TRUE FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/platform/pocket/pocket.tcl b/platform/pocket/pocket.tcl new file mode 100644 index 0000000..ec49478 --- /dev/null +++ b/platform/pocket/pocket.tcl @@ -0,0 +1,714 @@ +# ============================================================================== +# SPDX-License-Identifier: CC0-1.0 +# SPDX-FileType: SOURCE +# SPDX-FileCopyrightText: (c) 2022, OpenGateware authors and contributors +# ============================================================================== +# +# Platform Global/Location/Instance Assignments +# +# ============================================================================== +# Hardware Information +# ============================================================================== +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CEBA4F23C8 +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 + +# ============================================================================== +# Classic Timing Assignments +# ============================================================================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON + +# ============================================================================== +# Assembler Assignments +# ============================================================================== +set_global_assignment -name ENABLE_OCT_DONE OFF +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name GENERATE_RBF_FILE ON + +# ============================================================================== +# Power Estimation Assignments +# ============================================================================== +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# ============================================================================== +# Signal Tap Assignments +# ============================================================================== +set_global_assignment -name ENABLE_SIGNALTAP ON + +# ============================================================================== +# Pin & Location Assignments +# ============================================================================== +set_location_assignment PIN_V15 -to clk_74a +set_location_assignment PIN_H16 -to clk_74b +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk_74a +set_instance_assignment -name IO_STANDARD "1.8 V" -to clk_74b + +# ============================================================================== +# SPI bus with Aristotle +# ============================================================================== +set_location_assignment PIN_T17 -to bridge_spiclk +set_location_assignment PIN_M21 -to bridge_spimiso +set_location_assignment PIN_M20 -to bridge_spimosi +set_location_assignment PIN_L19 -to bridge_1wire +set_location_assignment PIN_H14 -to bridge_spiss +set_instance_assignment -name IO_STANDARD "1.8 V" -to bridge_spiclk +set_instance_assignment -name IO_STANDARD "1.8 V" -to bridge_spimiso +set_instance_assignment -name IO_STANDARD "1.8 V" -to bridge_spimosi +set_instance_assignment -name IO_STANDARD "1.8 V" -to bridge_1wire +set_instance_assignment -name IO_STANDARD "1.8 V" -to bridge_spiss +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to bridge_spiclk +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to bridge_spimiso +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to bridge_spimosi +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to bridge_1wire + +# ============================================================================== +# Cartridge interface +# ============================================================================== +set_location_assignment PIN_AA9 -to cart_tran_bank0[7] +set_location_assignment PIN_AB8 -to cart_tran_bank0[6] +set_location_assignment PIN_AA8 -to cart_tran_bank0[5] +set_location_assignment PIN_AB7 -to cart_tran_bank0[4] +set_location_assignment PIN_AB6 -to cart_tran_bank0_dir +set_location_assignment PIN_AA10 -to cart_tran_bank1[7] +set_location_assignment PIN_AB10 -to cart_tran_bank1[6] +set_location_assignment PIN_Y10 -to cart_tran_bank1[5] +set_location_assignment PIN_AB11 -to cart_tran_bank1[4] +set_location_assignment PIN_Y11 -to cart_tran_bank1[3] +set_location_assignment PIN_AB12 -to cart_tran_bank1[2] +set_location_assignment PIN_AA12 -to cart_tran_bank1[1] +set_location_assignment PIN_AB13 -to cart_tran_bank1[0] +set_location_assignment PIN_AA13 -to cart_tran_bank1_dir +set_location_assignment PIN_AB15 -to cart_tran_bank2[7] +set_location_assignment PIN_AA15 -to cart_tran_bank2[6] +set_location_assignment PIN_AB17 -to cart_tran_bank2[5] +set_location_assignment PIN_AA17 -to cart_tran_bank2[4] +set_location_assignment PIN_AB18 -to cart_tran_bank2[3] +set_location_assignment PIN_AB20 -to cart_tran_bank2[0] +set_location_assignment PIN_AA19 -to cart_tran_bank2[1] +set_location_assignment PIN_AA18 -to cart_tran_bank2[2] +set_location_assignment PIN_AA14 -to cart_tran_bank2_dir +set_location_assignment PIN_AA20 -to cart_tran_bank3[7] +set_location_assignment PIN_AB21 -to cart_tran_bank3[6] +set_location_assignment PIN_AB22 -to cart_tran_bank3[5] +set_location_assignment PIN_AA22 -to cart_tran_bank3[4] +set_location_assignment PIN_Y21 -to cart_tran_bank3[3] +set_location_assignment PIN_Y22 -to cart_tran_bank3[2] +set_location_assignment PIN_W21 -to cart_tran_bank3[1] +set_location_assignment PIN_W22 -to cart_tran_bank3[0] +set_location_assignment PIN_V21 -to cart_tran_bank3_dir +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank0[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank0_dir +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank1[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank1_dir +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank2[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank2[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank2[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank2[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank2[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank2[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank2[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank2_dir +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank3[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank3[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank3[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank3[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank3[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank3[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank3[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank3[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank3_dir + +# ============================================================================== +# GBA CS2#/RES# +# ============================================================================== +set_location_assignment PIN_AB5 -to cart_tran_pin30_dir +set_location_assignment PIN_L8 -to cart_tran_pin30 +set_location_assignment PIN_L17 -to cart_pin30_pwroff_reset +set_instance_assignment -name IO_STANDARD "1.8 V" -to cart_pin30_pwroff_reset +set_instance_assignment -name IO_STANDARD "1.8 V" -to cart_tran_pin30 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_pin30_dir +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cart_pin30_pwroff_reset +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cart_tran_pin30 + +# ============================================================================== +# GBA IRQ/DRQ +# ============================================================================== +set_location_assignment PIN_K9 -to cart_tran_pin31 +set_location_assignment PIN_U22 -to cart_tran_pin31_dir +set_instance_assignment -name IO_STANDARD "1.8 V" -to cart_tran_pin31 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_pin31_dir +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cart_tran_pin31 + +# ============================================================================== +# GBA link port +# ============================================================================== +set_location_assignment PIN_V10 -to port_tran_si +set_location_assignment PIN_V9 -to port_tran_si_dir +set_location_assignment PIN_J11 -to port_tran_so +set_location_assignment PIN_T13 -to port_tran_so_dir +set_location_assignment PIN_AA7 -to port_tran_sck +set_location_assignment PIN_Y9 -to port_tran_sck_dir +set_location_assignment PIN_R9 -to port_tran_sd +set_location_assignment PIN_T9 -to port_tran_sd_dir +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_tran_si +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_tran_si_dir +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_tran_so_dir +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_tran_sck +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_tran_sck_dir +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_tran_sd +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_tran_sd_dir +set_instance_assignment -name IO_STANDARD "1.8 V" -to port_tran_so +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to port_tran_so + +# ============================================================================== +# I/O to 6515D Breakout USB UART +# ============================================================================== +set_location_assignment PIN_K21 -to dbg_tx +set_location_assignment PIN_K22 -to dbg_rx +set_instance_assignment -name IO_STANDARD "1.8 V" -to dbg_rx +set_instance_assignment -name IO_STANDARD "1.8 V" -to dbg_tx +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to dbg_tx + +# ============================================================================== +# Infrared +# ============================================================================== +set_location_assignment PIN_H10 -to port_ir_rx +set_location_assignment PIN_H11 -to port_ir_tx +set_location_assignment PIN_L18 -to port_ir_rx_disable +set_instance_assignment -name IO_STANDARD "1.8 V" -to port_ir_tx +set_instance_assignment -name IO_STANDARD "1.8 V" -to port_ir_rx +set_instance_assignment -name IO_STANDARD "1.8 V" -to port_ir_rx_disable +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to port_ir_tx +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to port_ir_rx_disable +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to port_ir_rx + +# ============================================================================== +# RFU internal I2C bus (DNU) +# ============================================================================== +set_location_assignment PIN_M16 -to aux_scl +set_location_assignment PIN_M18 -to aux_sda +set_instance_assignment -name IO_STANDARD "1.8 V" -to aux_sda +set_instance_assignment -name IO_STANDARD "1.8 V" -to aux_scl +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to aux_sda +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to aux_scl + +# ============================================================================== +# I/O pads near jtag connector user can solder to +# ============================================================================== +set_location_assignment PIN_M22 -to user1 +set_location_assignment PIN_L22 -to user2 +set_instance_assignment -name IO_STANDARD "1.8 V" -to user1 +set_instance_assignment -name IO_STANDARD "1.8 V" -to user2 + +# ============================================================================== +# VBlank output to scaler +# ============================================================================== +set_location_assignment PIN_N19 -to vblank +set_instance_assignment -name IO_STANDARD "1.8 V" -to vblank + +# ============================================================================== +# Video output to the scaler +# ============================================================================== +set_location_assignment PIN_H15 -to scal_audadc +set_location_assignment PIN_K19 -to scal_auddac +set_location_assignment PIN_K17 -to scal_audlrck +set_location_assignment PIN_K16 -to scal_audmclk +set_location_assignment PIN_R17 -to scal_clk +set_location_assignment PIN_N20 -to scal_de +set_location_assignment PIN_P17 -to scal_hs +set_location_assignment PIN_N21 -to scal_skip +set_location_assignment PIN_T15 -to scal_vs +set_location_assignment PIN_R16 -to scal_vid[11] +set_location_assignment PIN_R15 -to scal_vid[10] +set_location_assignment PIN_R22 -to scal_vid[9] +set_location_assignment PIN_T22 -to scal_vid[8] +set_location_assignment PIN_T18 -to scal_vid[7] +set_location_assignment PIN_T19 -to scal_vid[6] +set_location_assignment PIN_T20 -to scal_vid[5] +set_location_assignment PIN_P19 -to scal_vid[4] +set_location_assignment PIN_P18 -to scal_vid[3] +set_location_assignment PIN_N16 -to scal_vid[2] +set_location_assignment PIN_P22 -to scal_vid[1] +set_location_assignment PIN_R21 -to scal_vid[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_audadc +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_auddac +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_audlrck +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_audmclk +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_clk +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_de +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_hs +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_skip +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[11] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vs +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_auddac +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_audlrck +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_audmclk +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_clk +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_de +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_hs +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_skip +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[10] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[11] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[4] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[5] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[6] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[7] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[8] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[9] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vs + +# ============================================================================== +# SDRAM, 512mbit x16 +# ============================================================================== +set_location_assignment PIN_J17 -to dram_a[12] +set_location_assignment PIN_F15 -to dram_a[11] +set_location_assignment PIN_C13 -to dram_a[10] +set_location_assignment PIN_G17 -to dram_a[9] +set_location_assignment PIN_J18 -to dram_a[8] +set_location_assignment PIN_F14 -to dram_a[7] +set_location_assignment PIN_E15 -to dram_a[6] +set_location_assignment PIN_E16 -to dram_a[5] +set_location_assignment PIN_F13 -to dram_a[4] +set_location_assignment PIN_E14 -to dram_a[3] +set_location_assignment PIN_F12 -to dram_a[2] +set_location_assignment PIN_D12 -to dram_a[1] +set_location_assignment PIN_D17 -to dram_a[0] +set_location_assignment PIN_E12 -to dram_ba[1] +set_location_assignment PIN_C16 -to dram_ba[0] +set_location_assignment PIN_K20 -to dram_dq[15] +set_location_assignment PIN_G11 -to dram_dq[14] +set_location_assignment PIN_J19 -to dram_dq[13] +set_location_assignment PIN_H13 -to dram_dq[12] +set_location_assignment PIN_G13 -to dram_dq[11] +set_location_assignment PIN_G16 -to dram_dq[10] +set_location_assignment PIN_G15 -to dram_dq[9] +set_location_assignment PIN_J13 -to dram_dq[8] +set_location_assignment PIN_A12 -to dram_dq[7] +set_location_assignment PIN_A13 -to dram_dq[6] +set_location_assignment PIN_B12 -to dram_dq[5] +set_location_assignment PIN_A14 -to dram_dq[4] +set_location_assignment PIN_B13 -to dram_dq[3] +set_location_assignment PIN_A15 -to dram_dq[2] +set_location_assignment PIN_B15 -to dram_dq[1] +set_location_assignment PIN_C15 -to dram_dq[0] +set_location_assignment PIN_D13 -to dram_dqm[0] +set_location_assignment PIN_H18 -to dram_dqm[1] +set_location_assignment PIN_B16 -to dram_cas_n +set_location_assignment PIN_G18 -to dram_cke +set_location_assignment PIN_G12 -to dram_clk +set_location_assignment PIN_B11 -to dram_ras_n +set_location_assignment PIN_C11 -to dram_we_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[11] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[12] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_ba[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_ba[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_cas_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_cke +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_clk +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[11] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[12] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[13] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[14] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[15] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dqm[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dqm[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_ras_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_we_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_ba[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_ba[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_cas_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_cke +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[13] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[14] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[15] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dqm[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dqm[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_ras_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_we_n +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to dram_clk + +# ============================================================================== +# Cellular PSRAM 0 - 64mbit x2 dual die per chip +# ============================================================================== +set_location_assignment PIN_H8 -to cram0_a[21] +set_location_assignment PIN_H9 -to cram0_a[20] +set_location_assignment PIN_B7 -to cram0_a[19] +set_location_assignment PIN_B6 -to cram0_a[18] +set_location_assignment PIN_C6 -to cram0_a[17] +set_location_assignment PIN_H6 -to cram0_a[16] +set_location_assignment PIN_J9 -to cram0_dq[15] +set_location_assignment PIN_L7 -to cram0_dq[14] +set_location_assignment PIN_F9 -to cram0_dq[13] +set_location_assignment PIN_E7 -to cram0_dq[12] +set_location_assignment PIN_A8 -to cram0_dq[11] +set_location_assignment PIN_D9 -to cram0_dq[10] +set_location_assignment PIN_A10 -to cram0_dq[9] +set_location_assignment PIN_C9 -to cram0_dq[8] +set_location_assignment PIN_J7 -to cram0_dq[7] +set_location_assignment PIN_G6 -to cram0_dq[6] +set_location_assignment PIN_F10 -to cram0_dq[5] +set_location_assignment PIN_E9 -to cram0_dq[4] +set_location_assignment PIN_D7 -to cram0_dq[3] +set_location_assignment PIN_A9 -to cram0_dq[2] +set_location_assignment PIN_C8 -to cram0_dq[1] +set_location_assignment PIN_B10 -to cram0_dq[0] +set_location_assignment PIN_J8 -to cram0_adv_n +set_location_assignment PIN_B5 -to cram0_ce0_n +set_location_assignment PIN_E10 -to cram0_ce1_n +set_location_assignment PIN_G10 -to cram0_clk +set_location_assignment PIN_F7 -to cram0_cre +set_location_assignment PIN_A5 -to cram0_lb_n +set_location_assignment PIN_D6 -to cram0_oe_n +set_location_assignment PIN_A7 -to cram0_ub_n +set_location_assignment PIN_K7 -to cram0_wait +set_location_assignment PIN_G8 -to cram0_we_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[11] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[12] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[13] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[14] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[15] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_a[16] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_a[17] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_a[18] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_a[19] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_a[20] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_a[21] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_adv_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_ce0_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_ce1_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_clk +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_cre +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_lb_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_oe_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_ub_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_wait +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_we_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[13] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[14] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[15] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_a[16] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_a[17] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_a[18] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_a[19] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_a[20] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_a[21] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_adv_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_ce0_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_ce1_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_cre +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_lb_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_oe_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_ub_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_wait +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_we_n +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to cram0_clk + +# ============================================================================== +# Cellular PSRAM 1 - 64mbit x2 dual die per chip +# ============================================================================== +set_location_assignment PIN_Y3 -to cram1_a[21] +set_location_assignment PIN_AA2 -to cram1_a[20] +set_location_assignment PIN_L2 -to cram1_a[19] +set_location_assignment PIN_N1 -to cram1_a[18] +set_location_assignment PIN_U1 -to cram1_a[17] +set_location_assignment PIN_U2 -to cram1_a[16] +set_location_assignment PIN_W8 -to cram1_dq[15] +set_location_assignment PIN_U6 -to cram1_dq[14] +set_location_assignment PIN_R7 -to cram1_dq[13] +set_location_assignment PIN_R6 -to cram1_dq[12] +set_location_assignment PIN_P7 -to cram1_dq[11] +set_location_assignment PIN_N6 -to cram1_dq[10] +set_location_assignment PIN_C2 -to cram1_dq[9] +set_location_assignment PIN_D3 -to cram1_dq[8] +set_location_assignment PIN_V6 -to cram1_dq[7] +set_location_assignment PIN_U7 -to cram1_dq[6] +set_location_assignment PIN_M6 -to cram1_dq[5] +set_location_assignment PIN_R5 -to cram1_dq[4] +set_location_assignment PIN_P6 -to cram1_dq[3] +set_location_assignment PIN_E2 -to cram1_dq[2] +set_location_assignment PIN_G2 -to cram1_dq[1] +set_location_assignment PIN_C1 -to cram1_dq[0] +set_location_assignment PIN_U8 -to cram1_adv_n +set_location_assignment PIN_N2 -to cram1_ce0_n +set_location_assignment PIN_T8 -to cram1_ce1_n +set_location_assignment PIN_W2 -to cram1_clk +set_location_assignment PIN_T7 -to cram1_cre +set_location_assignment PIN_L1 -to cram1_lb_n +set_location_assignment PIN_M7 -to cram1_oe_n +set_location_assignment PIN_G1 -to cram1_ub_n +set_location_assignment PIN_W9 -to cram1_wait +set_location_assignment PIN_AA1 -to cram1_we_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[11] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[12] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[13] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[14] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[15] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_a[16] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_a[17] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_a[18] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_a[19] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_a[20] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_a[21] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_adv_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_ce0_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_ce1_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_clk +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_cre +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_lb_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_oe_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_ub_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_wait +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_we_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[13] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[14] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[15] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_a[16] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_a[17] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_a[18] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_a[19] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_a[20] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_a[21] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_adv_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_ce0_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_ce1_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_cre +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_lb_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_oe_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_ub_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_wait +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_we_n +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to cram1_clk + +# ============================================================================== +# SRAM, 1mbit x16 +# ============================================================================== +set_location_assignment PIN_V16 -to sram_a[16] +set_location_assignment PIN_U12 -to sram_a[15] +set_location_assignment PIN_U15 -to sram_a[14] +set_location_assignment PIN_R10 -to sram_a[13] +set_location_assignment PIN_V14 -to sram_a[12] +set_location_assignment PIN_T10 -to sram_a[11] +set_location_assignment PIN_U11 -to sram_a[10] +set_location_assignment PIN_Y14 -to sram_a[9] +set_location_assignment PIN_U13 -to sram_a[8] +set_location_assignment PIN_Y19 -to sram_a[7] +set_location_assignment PIN_P8 -to sram_a[6] +set_location_assignment PIN_V19 -to sram_a[5] +set_location_assignment PIN_N9 -to sram_a[4] +set_location_assignment PIN_U21 -to sram_a[3] +set_location_assignment PIN_M8 -to sram_a[2] +set_location_assignment PIN_M9 -to sram_a[1] +set_location_assignment PIN_T14 -to sram_a[0] +set_location_assignment PIN_Y15 -to sram_dq[15] +set_location_assignment PIN_W16 -to sram_dq[14] +set_location_assignment PIN_Y16 -to sram_dq[13] +set_location_assignment PIN_Y17 -to sram_dq[12] +set_location_assignment PIN_V20 -to sram_dq[11] +set_location_assignment PIN_V18 -to sram_dq[10] +set_location_assignment PIN_U20 -to sram_dq[9] +set_location_assignment PIN_U16 -to sram_dq[8] +set_location_assignment PIN_R12 -to sram_dq[7] +set_location_assignment PIN_V13 -to sram_dq[6] +set_location_assignment PIN_T12 -to sram_dq[5] +set_location_assignment PIN_W19 -to sram_dq[4] +set_location_assignment PIN_Y20 -to sram_dq[3] +set_location_assignment PIN_P14 -to sram_dq[2] +set_location_assignment PIN_P9 -to sram_dq[1] +set_location_assignment PIN_N8 -to sram_dq[0] +set_location_assignment PIN_U17 -to sram_ub_n +set_location_assignment PIN_R11 -to sram_we_n +set_location_assignment PIN_R14 -to sram_oe_n +set_location_assignment PIN_P12 -to sram_lb_n +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_lb_n +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_oe_n +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_ub_n +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_we_n + +# ============================================================================== +# Powerup self test (DO NOT USE) +# ============================================================================== +set_location_assignment PIN_P16 -to vpll_feed +set_location_assignment PIN_U10 -to bist +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to bist +set_instance_assignment -name IO_STANDARD "1.8 V" -to vpll_feed +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to vpll_feed + +# ============================================================================== +# Advanced I/O Timing Assignments +# ============================================================================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ============================================================================== +# Scripts +# ============================================================================== +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:../platform/pocket/build_id_gen.tcl" +set_global_assignment -name POST_FLOW_SCRIPT_FILE "quartus_sh:../platform/pocket/build_cdf.tcl" + +# ============================================================================== +# Framework Files +# ============================================================================== +set_global_assignment -name QIP_FILE ../platform/pocket/apf.qip +set_global_assignment -name QIP_FILE ../target/pocket/core.qip diff --git a/projects/digdug_pocket.qpf b/projects/digdug_pocket.qpf new file mode 100644 index 0000000..99a1611 --- /dev/null +++ b/projects/digdug_pocket.qpf @@ -0,0 +1,11 @@ +# ============================================================================== +# Quartus Prime Project File +# Generated by OpenGateware - Gateman CLI v0.1.0 +# ============================================================================== + +QUARTUS_VERSION = "18.1" +DATE = "00:25:29 September 10, 2022" + +# Revisions + +PROJECT_REVISION = "digdug_pocket" diff --git a/projects/digdug_pocket.qsf b/projects/digdug_pocket.qsf new file mode 100644 index 0000000..1b7730b --- /dev/null +++ b/projects/digdug_pocket.qsf @@ -0,0 +1,62 @@ +# ============================================================================== +# Quartus Prime Settings File +# Generated by OpenGateware - Gateman CLI v0.1.0 +# ============================================================================== +# WARNING: DO NOT ADD FILES TO THE PROJECT VIA THE QUARTUS IDE! +# Add them manually to digdug_pocket.qip or Quartus will overwrite this file. +# ============================================================================== +# Project Assignments +# ============================================================================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.1 +set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Standard Edition" +set_global_assignment -name TOP_LEVEL_ENTITY apf_top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name SEED 1 +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON +set_global_assignment -name MUX_RESTRUCTURE OFF +set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON +set_global_assignment -name SAFE_STATE_MACHINE ON +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ +set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON +set_global_assignment -name ECO_OPTIMIZE_TIMING ON +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name FITTER_EFFORT "AUTO FIT" +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL" + +# ============================================================================== +# Macros +# ============================================================================== +# Don't use a clock divider to generate a pixel clock +set_global_assignment -name VERILOG_MACRO "DISABLE_VCLK_DIVIDER=1" + +# ============================================================================== +# Platform Specific Modules +# ============================================================================== +set_global_assignment -name QIP_FILE "../modules/pocket-i2s/index.qip" +set_global_assignment -name QIP_FILE "../modules/pocket-joypad/index.qip" + +# ============================================================================== +# File Assignments +# ============================================================================== +source ../platform/pocket/pocket.tcl +set_global_assignment -name QIP_FILE ../rtl/digdug.qip +set_global_assignment -name SDC_FILE digdug_pocket.sdc + + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/projects/digdug_pocket.sdc b/projects/digdug_pocket.sdc new file mode 100644 index 0000000..4b5d796 --- /dev/null +++ b/projects/digdug_pocket.sdc @@ -0,0 +1,61 @@ +# ============================================================================== +# Quartus Prime Synopsys Design Constraint File +# Generated by OpenGateware - Gateman CLI v0.1.0 +# ============================================================================== +# pocket SDC settings +# Users are recommended to modify this file to match users logic. +# Put your clock groups in here as well as any net assignments. +# ============================================================================== + +# ============================================================================== +# Time Information +# ============================================================================== + +# ============================================================================== +# Create Clock +# ============================================================================== + +# ============================================================================== +# Create Generated Clock +# ============================================================================== + +# ============================================================================== +# Set Clock Latency +# ============================================================================== + +# ============================================================================== +# Set Clock Uncertainty +# ============================================================================== + +# ============================================================================== +# Set Input Delay +# ============================================================================== + +# ============================================================================== +# Set Output Delay +# ============================================================================== + +# ============================================================================== +# Set Clock Groups +# ============================================================================== + +# ============================================================================== +# Set False Path +# ============================================================================== + +# ============================================================================== +# Set Multicycle Path +# ============================================================================== + +# ============================================================================== +# Set Maximum Delay +# ============================================================================== + +# ============================================================================== +# Set Minimum Delay +# ============================================================================== + +# ============================================================================== +# Set Input Transition +# ============================================================================== + diff --git a/rtl/DIGDUG_CORES.v b/rtl/DIGDUG_CORES.v new file mode 100644 index 0000000..5d8eeba --- /dev/null +++ b/rtl/DIGDUG_CORES.v @@ -0,0 +1,228 @@ +//------------------------------------------------------------------------------ +// SPDX-License-Identifier: GPL-3.0-or-later +// SPDX-FileType: SOURCE +// SPDX-FileCopyrightText: (c) 2017 MiSTer-X +//------------------------------------------------------------------------------ +// FPGA DigDug (CPU part) +//------------------------------------------------------------------------------ + +`timescale 1 ps / 1 ps + +module DIGDUG_CORES + ( + input MCLK, //! Clock (48.0MHz) + + input [2:0] RSTS, //! RESET [2:0] + input [2:0] IRQS, //! IRQ [2:0] + input [2:0] NMIS, //! NMI [2:0] + + output DEV_CL, //! I/O device Interface + output [15:0] DEV_AD, + output DEV_RD, + input DEV_DV, + input [7:0] DEV_DO, + output DEV_WR, + output [7:0] DEV_DI, + + + input ROMCL, //! Downloaded ROM image + input [15:0] ROMAD, + input [7:0] ROMDT, + input ROMEN, + + input PAUSE + ); + + //----------------------------------------------- + // CPU0 + //----------------------------------------------- + wire CPU0CL; + wire [15:0] CPU0AD; + wire CPU0RD; + wire CPU0DV; + wire [7:0] CPU0DI; + wire CPU0WR; + wire [7:0] CPU0DO; + + wire [7:0] CPU0IR; + DLROM #(14,8) rom0( DEV_CL, CPU0AD[13:0], CPU0IR, ROMCL,ROMAD[13:0],ROMDT,ROMEN & (ROMAD[15:14]==2'b00) ); + + wire NMI0; + CPUNMIACK n0( RSTS[0], CPU0CL, CPU0AD, NMIS[0], NMI0 ); + + CPUCORE cpu0 + ( + .RESET(RSTS[0]), + .CLK(CPU0CL), + .IRQ(IRQS[0]), + .NMI(NMI0), + .AD(CPU0AD), + .IR(CPU0IR), + .RD(CPU0RD), + .DV(CPU0DV), + .DI(CPU0DI), + .WR(CPU0WR), + .DO(CPU0DO), + .PAUSE(PAUSE) + ); + + + //----------------------------------------------- + // CPU1 + //----------------------------------------------- + wire CPU1CL; + wire [15:0] CPU1AD; + wire CPU1RD; + wire CPU1DV; + wire [7:0] CPU1DI; + wire CPU1WR; + wire [7:0] CPU1DO; + + wire [7:0] CPU1IR; + DLROM #(13,8) rom1( DEV_CL, CPU1AD[12:0], CPU1IR, ROMCL,ROMAD[12:0],ROMDT,ROMEN & (ROMAD[15:13]==3'b100) ); + + CPUCORE cpu1 + ( + .RESET(RSTS[1]), + .CLK(CPU1CL), + .IRQ(IRQS[1]), + .NMI(NMIS[1]), + .AD(CPU1AD), + .IR(CPU1IR), + .RD(CPU1RD), + .DV(CPU1DV), + .DI(CPU1DI), + .WR(CPU1WR), + .DO(CPU1DO), + .PAUSE(PAUSE) + ); + + + //----------------------------------------------- + // CPU2 + //----------------------------------------------- + wire CPU2CL; + wire [15:0] CPU2AD; + wire CPU2RD; + wire CPU2DV; + wire [7:0] CPU2DI; + wire CPU2WR; + wire [7:0] CPU2DO; + + wire [7:0] CPU2IR; + DLROM #(12,8) rom2( DEV_CL, CPU2AD[11:0], CPU2IR, ROMCL,ROMAD[11:0],ROMDT,ROMEN & (ROMAD[15:12]==4'hA) ); + + wire NMI2; + CPUNMIACK n2( RSTS[2], CPU2CL, CPU2AD, NMIS[2], NMI2 ); + + CPUCORE cpu2 + ( + .RESET(RSTS[2]), + .CLK(CPU2CL), + .IRQ(IRQS[2]), + .NMI(NMI2), + .AD(CPU2AD), + .IR(CPU2IR), + .RD(CPU2RD), + .DV(CPU2DV), + .DI(CPU2DI), + .WR(CPU2WR), + .DO(CPU2DO), + .PAUSE() + ); + + + //----------------------------------------------- + // CPU Access Arbiter + //----------------------------------------------- + CPUARB arb + ( + MCLK, + DEV_CL, DEV_AD, DEV_RD, DEV_DV, DEV_DO, DEV_WR, DEV_DI, + CPU0CL, CPU0AD, CPU0RD, CPU0DV, CPU0DI, CPU0WR, CPU0DO, + CPU1CL, CPU1AD, CPU1RD, CPU1DV, CPU1DI, CPU1WR, CPU1DO, + CPU2CL, CPU2AD, CPU2RD, CPU2DV, CPU2DI, CPU2WR, CPU2DO + ); + +endmodule + + +module CPUARB + ( + input CLK48M, + + output DEV_CL, + output [15:0] DEV_AD, + output DEV_RD, + input DEV_DV, + input [7:0] DEV_DO, + output DEV_WR, + output [7:0] DEV_DI, + + output CPU0CL, + input [15:0] CPU0AD, + input CPU0RD, + output CPU0DV, + output [7:0] CPU0DI, + input CPU0WR, + input [7:0] CPU0DO, + + output CPU1CL, + input [15:0] CPU1AD, + input CPU1RD, + output CPU1DV, + output [7:0] CPU1DI, + input CPU1WR, + input [7:0] CPU1DO, + + output CPU2CL, + input [15:0] CPU2AD, + input CPU2RD, + output CPU2DV, + output [7:0] CPU2DI, + input CPU2WR, + input [7:0] CPU2DO + ); + + reg [1:0] clkdiv; + always @( posedge CLK48M ) clkdiv <= clkdiv+1'b1; + wire CLK24M = clkdiv[0]; + wire CLK12M = clkdiv[1]; + + reg [3:0] CLKS = 4'b1000; + reg [3:0] BUSS = 4'b0001; + always @( posedge CLK12M ) CLKS <= {CLKS[2:0],CLKS[3]}; + always @( negedge CLK12M ) BUSS <= {BUSS[2:0],BUSS[3]}; + + assign CPU0CL = CLKS[0]; + assign CPU1CL = CLKS[1]; + assign CPU2CL = CLKS[2]; + + assign DEV_CL = CLK24M; + + assign DEV_AD = BUSS[0] ? CPU0AD : + BUSS[1] ? CPU1AD : + BUSS[2] ? CPU2AD : 16'd0000; + + assign DEV_RD = BUSS[0] ? CPU0RD : + BUSS[1] ? CPU1RD : + BUSS[2] ? CPU2RD : 1'b0; + + assign CPU0DV = BUSS[0] ? DEV_DV : 1'b0; + assign CPU1DV = BUSS[1] ? DEV_DV : 1'b0; + assign CPU2DV = BUSS[2] ? DEV_DV : 1'b0; + + assign CPU0DI = BUSS[0] ? DEV_DO : 8'h00; + assign CPU1DI = BUSS[1] ? DEV_DO : 8'h00; + assign CPU2DI = BUSS[2] ? DEV_DO : 8'h00; + + assign DEV_WR = BUSS[0] ? CPU0WR : + BUSS[1] ? CPU1WR : + BUSS[2] ? CPU2WR : 1'b0; + + assign DEV_DI = BUSS[0] ? CPU0DO : + BUSS[1] ? CPU1DO : + BUSS[2] ? CPU2DO : 8'h00; + +endmodule + diff --git a/rtl/DIGDUG_CUSIO.v b/rtl/DIGDUG_CUSIO.v new file mode 100644 index 0000000..176b3d1 --- /dev/null +++ b/rtl/DIGDUG_CUSIO.v @@ -0,0 +1,280 @@ +//------------------------------------------------------------------------------ +// SPDX-License-Identifier: GPL-3.0-or-later +// SPDX-FileType: SOURCE +// SPDX-FileCopyrightText: (c) 2017 MiSTer-X +//------------------------------------------------------------------------------ +// FPGA DigDug (Custom I/O chip emulation part) +//------------------------------------------------------------------------------ + +`timescale 1 ps / 1 ps + +module DIGDUG_CUSIO + ( + input RESET, + input VBLK, + + input [7:0] INP0, + input [7:0] INP1, + input [7:0] DSW0, + input [7:0] DSW1, + + input CL, + input CS, + input WR, + input [4:0] AD, + input [7:0] DI, + output [7:0] DO, + output NMI0 + ); + + reg MODE; + reg [7:0] COMMAND; + + reg [3:0] r2, r3, r4, r5; + reg [3:0] LCINPCRE, LCREPCIN, LCOINS; + reg [3:0] RCINPCRE, RCREPCIN, RCOINS; + reg CREDITAT; + reg [7:0] CREDITS; + + reg [11:0] CLK50uc; + reg CLK50u; + + always @( posedge CL ) begin + if (RESET) begin + CLK50u <= 0; + CLK50uc <= 0; + end + else begin + if ( CLK50uc == 2200 ) CLK50u <= 1'b1; + if ( CLK50uc == 2400 ) begin CLK50u <= 1'b0; CLK50uc <= 12'h000; end + else CLK50uc <= CLK50uc + 1'b1; + end + end + + reg NMI0EN = 1'b0; + assign NMI0 = NMI0EN & CLK50u; + + always @( posedge CL or posedge RESET ) begin + if (RESET) begin + NMI0EN <= 0; + MODE <= 1'b0; + COMMAND <= 0; + + LCINPCRE <= 0; + LCREPCIN <= 0; + RCINPCRE <= 0; + RCREPCIN <= 0; + CREDITAT <= 0; + end + else begin + if (CS&WR) begin + if (AD[4]) begin + // command write + COMMAND <= DI; + MODE <= (DI==8'hA1) ? 1'b1 : ((DI==8'hC1)|(DI==8'hE1)) ? 1'b0 : MODE; + NMI0EN <= (DI!=8'h10); + end + else begin + // data write + if (COMMAND == 8'hC1) + case (AD[3:0]) + 4'h2: r2 <= DI[3:0]; + 4'h3: r3 <= DI[3:0]; + 4'h4: r4 <= DI[3:0]; + 4'h5: r5 <= DI[3:0]; + 4'h8: begin + LCINPCRE <= r2; + LCREPCIN <= r3; + RCINPCRE <= r4; + RCREPCIN <= r5; + CREDITAT <= 1'b1; + end + default: + ; + endcase + end + end + end + end + + + // data read + wire [3:0] ADR = AD[3:0]; + wire [7:0] NONE = 8'hFF; + + reg [7:0] SW_CC; + reg [7:0] SW_P1; + reg [7:0] SW_P2; + + wire [7:0] ST_CC; + BCDCONV bcd( CREDITS, ST_CC[3:0], ST_CC[7:4] ); + + reg [7:0] ST_P1 = 8'hF8; + reg [7:0] ST_P2 = 8'hF8; + + wire [7:0] SWMODE = (ADR==0) ? (~SW_CC) : + (ADR==1) ? (~SW_P1) : + (ADR==2) ? (~SW_P2) : NONE; + + wire [7:0] STMODE = (ADR==0) ? ST_CC : + (ADR==1) ? ST_P1 : + (ADR==2) ? ST_P2 : NONE; + + wire [7:0] READh71 = MODE ? SWMODE : STMODE; + + wire [7:0] READhB1 = {8{~(ADR<=2)}}; + + wire [7:0] READhD2 = (ADR==0) ? DSW0 : + (ADR==1) ? DSW1 : NONE; + + wire [7:0] READDAT = (COMMAND == 8'h71) ? READh71 : + (COMMAND == 8'hB1) ? READhB1 : + (COMMAND == 8'hD2) ? READhD2 : NONE; + + assign DO = AD[4] ? COMMAND : READDAT; + + //------------------------------------------------------------ + + // INP0 = { SERVICE, 1'b0, m_coin2, m_coin1, m_start2, m_start1, m_pump2, m_pump1 }; + // INP1 = { m_left2, m_down2, m_right2, m_up2, m_left1, m_down1, m_right1, m_up1 }; + + reg [15:0] pINP,piINP,piINP0,piINP1,piINP2; + wire [15:0] nINP = {INP0,INP1}; + wire [15:0] iINP = (pINP^nINP) & nINP; + + function [3:0] stick; + input [3:0] stk; + stick = stk[0] ? 4'h0 : + stk[1] ? 4'h2 : + stk[2] ? 4'h4 : + stk[3] ? 4'h6 : 4'h8; + endfunction + + reg pVBLK = 1'b0; + + always @( posedge CL or posedge RESET ) begin + if (RESET) begin + LCOINS = 0; + RCOINS = 0; + CREDITS = 0; + + SW_CC <= 0; + SW_P1 <= 0; + SW_P2 <= 0; + ST_P1 <= 8'hF8; + ST_P2 <= 8'hF8; + + pINP <= 0; + piINP <= 0; + piINP0 <= 0; + piINP1 <= 0; + piINP2 <= 0; + + pVBLK <= 0; + end + else begin + if (VBLK & (VBLK^pVBLK)) begin + SW_CC <= {nINP[15],1'b0,piINP[11],piINP[10],2'b00,iINP[13],iINP[12]}; + SW_P1 <= {2'b00, pINP[8], iINP[8],nINP[3:0]}; + SW_P2 <= {2'b00, pINP[9], iINP[9],nINP[7:4]}; + ST_P1 <= {2'b11,~pINP[8],~iINP[8],stick(nINP[3:0])}; + ST_P2 <= {2'b11,~pINP[9],~iINP[9],stick(nINP[7:4])}; + + if (CREDITAT) begin + if ( LCINPCRE > 0 ) begin + if ( iINP[12] & ( CREDITS < 99 ) ) begin + LCOINS = LCOINS+1'b1; + if ( LCOINS >= LCINPCRE ) begin + CREDITS = CREDITS + LCREPCIN; + LCOINS = 0; + end + end + if ( iINP[13] & ( CREDITS < 99 ) ) begin + RCOINS = RCOINS+1'b1; + if ( RCOINS >= RCINPCRE ) begin + CREDITS = CREDITS + RCREPCIN; + RCOINS = 0; + end + end + end + else + CREDITS = 2; + if ( CREDITS > 99 ) + CREDITS = 99; + + if ( piINP[10] & (CREDITS >= 1) ) + CREDITS = CREDITS-1'b1; + if ( piINP[11] & (CREDITS >= 2) ) + CREDITS = CREDITS-2'd2; + end + + pINP <= nINP; + piINP0 <= iINP; + piINP1 <= piINP0; + piINP2 <= piINP1; + piINP <= piINP2; // delay start buttons + + end + pVBLK <= VBLK; + end + end + +endmodule + + + +//---------------------------------------- +// BCD Converter +//---------------------------------------- +module add3(in,out); + + input [3:0] in; + output [3:0] out; + reg [3:0] out; + + always @ (in) + case (in) + 4'b0000: out = 4'b0000; + 4'b0001: out = 4'b0001; + 4'b0010: out = 4'b0010; + 4'b0011: out = 4'b0011; + 4'b0100: out = 4'b0100; + 4'b0101: out = 4'b1000; + 4'b0110: out = 4'b1001; + 4'b0111: out = 4'b1010; + 4'b1000: out = 4'b1011; + 4'b1001: out = 4'b1100; + default: out = 4'b0000; + endcase + +endmodule + + +module BCDCONV(A,ONES,TENS); + + input [7:0] A; + output [3:0] ONES, TENS; + wire [3:0] c1,c2,c3,c4,c5,c6,c7; + wire [3:0] d1,d2,d3,d4,d5,d6,d7; + + assign d1 = {1'b0,A[7:5]}; + assign d2 = {c1[2:0],A[4]}; + assign d3 = {c2[2:0],A[3]}; + assign d4 = {c3[2:0],A[2]}; + assign d5 = {c4[2:0],A[1]}; + assign d6 = {1'b0,c1[3],c2[3],c3[3]}; + assign d7 = {c6[2:0],c4[3]}; + + add3 m1(d1,c1); + add3 m2(d2,c2); + add3 m3(d3,c3); + add3 m4(d4,c4); + add3 m5(d5,c5); + add3 m6(d6,c6); + add3 m7(d7,c7); + + assign ONES = {c5[2:0],A[0]}; + assign TENS = {c7[2:0],c5[3]}; + +endmodule + diff --git a/rtl/DIGDUG_IODEV.v b/rtl/DIGDUG_IODEV.v new file mode 100644 index 0000000..57c6cc1 --- /dev/null +++ b/rtl/DIGDUG_IODEV.v @@ -0,0 +1,219 @@ +//------------------------------------------------------------------------------ +// SPDX-License-Identifier: GPL-3.0-or-later +// SPDX-FileType: SOURCE +// SPDX-FileCopyrightText: (c) 2017 MiSTer-X +//------------------------------------------------------------------------------ +// FPGA DigDug (I/O device part) +//------------------------------------------------------------------------------ + +`timescale 1 ps / 1 ps + +module DIGDUG_IODEV + ( + input RESET, + + input [7:0] INP0, + input [7:0] INP1, + input [7:0] DSW0, + input [7:0] DSW1, + + input VBLK, //! V-BLANK + + input CL, //! CPU Interface + input [15:0] AD, + input WR, + input [7:0] DI, + input RD, + output DV, + output [7:0] DO, + + output [2:0] RSTS, //! CPU Reset Ctrl & Interrupt + output [2:0] IRQS, + output [2:0] NMIS, + + input CLK48M, + output PCMCLK, + output [7:0] PCMOUT, + + output WAVECL, //! Wave ROM + output [7:0] WAVEAD, + input [3:0] WAVEDT, + + input FGSCCL, //! FG VRAM + input [9:0] FGSCAD, + output [7:0] FGSCDT, + + input SPATCL, //! SP ARAM + input [6:0] SPATAD, + output [23:0] SPATDT, + + output [1:0] BG_SELECT, //! Video Ctrl. + output [1:0] BG_COLBNK, + output BG_CUTOFF, + output FG_CLMODE, + + input [10:0] hs_address, + output [7:0] hs_data_out, + input [7:0] hs_data_in, + input hs_write, + input hs_access + + ); + + // Work & Video Memory + wire CSM0 = (AD[15:11] == 5'b1000_0); //! $8000-$87FF + wire CSM1 = (AD[15:11] == 5'b1000_1); //! $8800-$8FFF + wire CSM2 = (AD[15:11] == 5'b1001_0); //! $9000-$97FF + wire CSM3 = (AD[15:11] == 5'b1001_1); //! $9800-$9FFF + + wire [10:0] MAD = AD[10:0]; + wire [7:0] DOM0, DOM1, DOM2, DOM3; + + // Hiscore mux into ram1 + wire [10:0] ram1_MAD = hs_access ? hs_address : MAD; + wire ram1_CSM1 = hs_access ? 1'b1 : CSM1; + wire ram1_WR = hs_access ? hs_write : WR; + wire [7:0] ram1_DI = hs_access ? hs_data_in : DI; + wire [7:0] ram1_DOM1; + assign hs_data_out = hs_access ? ram1_DOM1 : 8'b00000000; + assign DOM1 = ~hs_access ? ram1_DOM1 : 8'b00000000; + + DPR2KV ram0( CL, MAD, CSM0, WR, DI, DOM0, FGSCCL, {1'b0,FGSCAD}, FGSCDT ); //! (FGTX) $8000-$8300 + DPR2KV ram1( CL, ram1_MAD, ram1_CSM1, ram1_WR, ram1_DI, ram1_DOM1, SPATCL, {4'h7,SPATAD}, SPATDT[ 7: 0] ); //! (SPA0) $8B80-$8BFF + DPR2KV ram2( CL, MAD, CSM2, WR, DI, DOM2, SPATCL, {4'h7,SPATAD}, SPATDT[15: 8] ); //! (SPA1) $9380-$93FF + DPR2KV ram3( CL, MAD, CSM3, WR, DI, DOM3, SPATCL, {4'h7,SPATAD}, SPATDT[23:16] ); //! (SPA2) $9B80-$9BFF + + // NAMCO WSG + wire WSGWR =( AD[15:5] == 11'b0110_1000_000 ) & WR; //! $6800-$681F + WSG_3CH wsg( CLK48M, RESET, CL, AD[4:0], DI[3:0], WSGWR, WAVECL, WAVEAD, WAVEDT, PCMCLK, PCMOUT ); + + // NAMCO Custom I/O Chip + wire CSCUSIO = (AD[15:9] == 7'b0111_000); //! $70xx-$71xx + wire [7:0] DOCUSIO; + wire NMI0; + DIGDUG_CUSIO cusio( RESET, VBLK, INP0, INP1, DSW0, DSW1, CL, CSCUSIO, WR, {AD[8],AD[3:0]}, DI, DOCUSIO, NMI0 ); + + // Video Ctrl Latches + wire VLWR = (AD[15:3] == 13'b1010_0000_0000_0) & WR; //! $A000-$A007 + DIGDUG_VLATCH vlats( RESET, CL, AD[2:0], VLWR, DI[0], BG_SELECT, BG_COLBNK, BG_CUTOFF, FG_CLMODE ); + + // CPU Ctrl Latches + wire CLWR = (AD[15:3] == 13'b0110_1000_0010_0) & WR; //! $6820-$6827 + wire NMI2; + DIGDUG_CLATCH clats( RESET, CL, AD[2:0], CLWR, DI[0], VBLK, RSTS, IRQS, NMI2 ); + + // To CPU + assign DV = CSM0|CSM1|CSM2|CSM3|CSCUSIO; + assign DO = CSM0 ? DOM0 : CSM1 ? DOM1 : CSM2 ? DOM2 : CSM3 ? DOM3 : CSCUSIO ? DOCUSIO : 8'hFF; + assign NMIS = {NMI2,1'b0,NMI0}; + +endmodule + + +module DIGDUG_VLATCH + ( + input RESET, + input CL, + input [2:0] AD, + input WR, + input DI, + + output reg [1:0] BG_SELECT, + output reg [1:0] BG_COLBNK, + output reg BG_CUTOFF, + output reg FG_CLMODE + ); + + always @( posedge CL or posedge RESET ) begin + if (RESET) begin + BG_SELECT <= 2'b00; + BG_COLBNK <= 2'b00; + BG_CUTOFF <= 1'b0; + FG_CLMODE <= 1'b0; + end + else begin + if (WR) + case(AD) + 3'h0: BG_SELECT[0] <= DI; + 3'h1: BG_SELECT[1] <= DI; + 3'h2: FG_CLMODE <= DI; + 3'h3: BG_CUTOFF <= DI; + 3'h4: BG_COLBNK[0] <= DI; + 3'h5: BG_COLBNK[1] <= DI; + default: ; + endcase + end + end + +endmodule + + +module DIGDUG_CLATCH + ( + input RESET, + input CL, // 24MHz + input [2:0] AD, + input WR, + input DI, + + input VBLK, + output [2:0] RSTS, + output [2:0] IRQS, + output NMI2 + ); + + // OSC 120Hz +`define H120FLOW (12500) + reg [3:0] clkdiv; + always @( posedge CL ) clkdiv <= clkdiv+1'b1; + reg [13:0] H120CNT; + always @( posedge clkdiv[3] or posedge RESET ) begin + if (RESET) H120CNT <= 0; + else H120CNT <= (H120CNT==`H120FLOW) ? 14'd0 : (H120CNT+1'b1); + end + wire H120 = ( H120CNT >= (`H120FLOW-200) ) ? 1'b1 : 1'b0; + + reg IRQ0EN, IRQ0LC; + reg IRQ1EN, IRQ1LC; + reg NMI2EN, NMI2LC; + //reg NMI0LC; + + reg C12RST = 1'b1; + reg pH120; + + always @( posedge CL or posedge RESET ) begin + if (RESET) begin + IRQ0EN <= 1'b0; + IRQ0LC <= 1'b0; + IRQ1EN <= 1'b0; + IRQ1LC <= 1'b0; + NMI2EN <= 1'b0; + NMI2LC <= 1'b0; + C12RST <= 1'b1; //NMI0LC <= 1'b0; + pH120 <= 1'b0; + end + else begin + if (WR) begin + case(AD) + 3'h0: begin IRQ0EN <= DI; if (~DI) IRQ0LC <= 1'b0; end + 3'h1: begin IRQ1EN <= DI; if (~DI) IRQ1LC <= 1'b0; end + 3'h2: begin NMI2EN <=~DI; if ( DI) NMI2LC <= 1'b0; end + 3'h3: C12RST <= ~DI; + default:; + endcase + end + if (VBLK) begin + IRQ0LC <= 1'b1; + IRQ1LC <= 1'b1; + end + if ((pH120^H120)&H120) + NMI2LC <= 1'b1; + pH120 <= H120; + end + end + + assign RSTS = {{2{C12RST}},RESET}; + assign IRQS = {1'b0,(IRQ1EN & IRQ1LC),(IRQ0EN & IRQ0LC)}; + assign NMI2 = (NMI2EN & NMI2LC); + +endmodule diff --git a/rtl/DIGDUG_SPRITE.v b/rtl/DIGDUG_SPRITE.v new file mode 100644 index 0000000..38b8b0a --- /dev/null +++ b/rtl/DIGDUG_SPRITE.v @@ -0,0 +1,121 @@ +//------------------------------------------------------------------------------ +// SPDX-License-Identifier: GPL-3.0-or-later +// SPDX-FileType: SOURCE +// SPDX-FileCopyrightText: (c) 2017 MiSTer-X +//------------------------------------------------------------------------------ +// FPGA DigDug (Sprite part) +//------------------------------------------------------------------------------ + +`timescale 1 ps / 1 ps + +module DIGDUG_SPRITE + ( + input RCLK, //! Rendering Clock + input VCLK, //! Video Dot Clock + input VCLKx2, //! Video Dot Clockx2 + + input [8:0] POSH, + input [8:0] POSV, + + output SPATCL, + output [6:0] SPATAD, + input [23:0] SPATDT, + + output reg [4:0] SPCOL, + + input V_FLIP, + + input ROMCL, //! Downloaded ROM image + input [15:0] ROMAD, + input [7:0] ROMDT, + input ROMEN + ); + + wire [8:0] PH = POSH+9'd1; + wire [8:0] PV = V_FLIP ? (9'd221 - POSV) : POSV + 9'd2; + wire [8:0] TY; + + + reg [3:0] PHASE; + reg SIDE; + + reg [7:0] ADR; + reg [23:0] ATR0, ATR1; + + reg [8:0] WXP; + reg [8:0] WCN; + + + wire SZ = ATR0[7]; //! Size + wire [8:0] SS = SZ ? 9'd32 : 9'd16; //! Size (Pixels) + wire [5:0] SC = ATR1[5:0]; //! Color + wire [8:0] SX = {1'b0,ATR1[15:8]}-9'd39; //! Position X + wire [8:0] SY = (9'd256-TY); //! Position Y + wire [8:0] SU = (SS-WCN)^{9{ATR0[16]}}; //! Position U + wire [8:0] SV = (PV-SY )^{9{ATR0[17]}}; //! Position V + wire [7:0] SM = ATR0[7:0]; //! Code (for Normal) + wire [7:0] SL = {SM[7]|SM[5],SM[6]|SM[4],SM[3:0],SV[4],SU[4]}; //! Code (for Size) + wire [7:0] SN = SZ ? SL : SM; //! Code + wire SD = ATR1[17]|((PV=(SY+SS)); //! Visiblity (False:Visible) + + assign TY = ((({1'b0,ATR0[15:8]}+1'b1)+(SZ ? 9'd16 : 9'd0)) & 9'd255) + 9'd30; + + wire ABORT = (PH==288); + wire STANDBY = (PH!=289); + wire ATRTAIL = (ADR[7]); + wire DRAWING = (WCN!=1); + + assign SPATCL = ~RCLK; + assign SPATAD = ADR[6:0]; + + wire [8:0] WSX = {1'b0,SX[7:0]} + ((SX[7:0]<8'd16) ? 9'd256 : 9'd0); + + always @( posedge RCLK ) begin + if (ABORT) begin + PHASE <= 4'd0; + WCN <= 9'd0; + end + else + case (PHASE) + `define LOOP (PHASE) + `define NEXT (PHASE+1'b1) + `define NXTA (4'd1) + + 0: begin SIDE <= PV[0]; ADR <= 8'd0; WCN <= 9'd0; PHASE <= STANDBY ? `LOOP : `NEXT; end + 1: begin PHASE <= ATRTAIL ? `NXTA : `NEXT; end + 2: begin ATR0 <= SPATDT; ADR <= ADR+1'b1; PHASE <= `NEXT; end + 3: begin ATR1 <= SPATDT; ADR <= ADR+1'b1; PHASE <= `NEXT; end + 4: begin WXP <= WSX; WCN <= SS; PHASE <= SD ? `NXTA : `NEXT; end + // CHIP Read + 5: begin /* CLUT Read */ PHASE <= `NEXT; end + // LBUF Write + 6: begin WXP <= WXP+1'b1; WCN <= WCN-1'b1; PHASE <= DRAWING ? 4'd5 : `NXTA; end + default: ; + endcase + end + + wire [7:0] CHRD; + DLROMe #(14,8) spchip((PHASE==4'd5),~RCLK,{SN,SV[3],SU[3:2],SV[2:0]},CHRD, ROMCL,ROMAD[13:0],ROMDT,ROMEN & (ROMAD[15:14]==2'b01)); + wire [7:0] PIX = CHRD << (SU[1:0]); + + wire [7:0] WDT; + DLROMe #(8,8) spclut((PHASE==4'd5), RCLK,{SC,PIX[7],PIX[3]},WDT, ROMCL,ROMAD[7:0],ROMDT,ROMEN & (ROMAD[15:8]==8'hD9)); + + wire [4:0] LBOUT; + wire [2:0] unused; + wire [8:0] POSH_READ = V_FLIP ? 9'd287-PH : PH; + LBUF1K lbuf ( + ~RCLK, {SIDE,WXP}, (PHASE==4'd6) & (PIX[7]|PIX[3]), {4'h1,WDT[3:0]}, + VCLKx2, {~SIDE,POSH_READ}, (radr0==radr1), 8'h0, {unused, LBOUT} + ); + + reg [9:0] radr0=0,radr1=1; + always @(posedge VCLK) radr0 <= {~SIDE,PH}; + always @(negedge VCLK) begin + if (radr0!=radr1) + SPCOL <= LBOUT; + radr1 <= radr0; + end + +endmodule + diff --git a/rtl/DIGDUG_VIDEO.v b/rtl/DIGDUG_VIDEO.v new file mode 100644 index 0000000..46d57b7 --- /dev/null +++ b/rtl/DIGDUG_VIDEO.v @@ -0,0 +1,150 @@ +//------------------------------------------------------------------------------ +// SPDX-License-Identifier: GPL-3.0-or-later +// SPDX-FileType: SOURCE +// SPDX-FileCopyrightText: (c) 2017 MiSTer-X +//------------------------------------------------------------------------------ +// FPGA DigDug (Video part) +//------------------------------------------------------------------------------ + +`timescale 1 ps / 1 ps + +module DIGDUG_VIDEO + ( + input CLK48M, + input [8:0] POSH, + input [8:0] POSV, + + input [1:0] BG_SELECT, + input [1:0] BG_COLBNK, + input BG_CUTOFF, + input FG_CLMODE, + + output FGSCCL, + output [9:0] FGSCAD, + input [7:0] FGSCDT, + + output SPATCL, + output [6:0] SPATAD, + input [23:0] SPATDT, + + output VBLK, + output PCLK, + input iPCLK, + output [7:0] POUT, + + input V_FLIP, + + input ROMCL, // Downloaded ROM image + input [15:0] ROMAD, + input [7:0] ROMDT, + input ROMEN + ); + + //--------------------------------------- + // Clock Generator + //--------------------------------------- + reg [2:0] clkdiv; + always @( posedge CLK48M ) clkdiv <= clkdiv+1'b1; + wire VCLKx8 = CLK48M; + //wire VCLKx4 = clkdiv[0]; + wire VCLKx2 = clkdiv[1]; +`ifdef DISABLE_VCLK_DIVIDER + wire VCLK = iPCLK; +`else + wire VCLK = clkdiv[2]; +`endif + + + //--------------------------------------- + // Local Offset + //--------------------------------------- + reg [8:0] PH, PV; + reg [8:0] SPH, SPV; + always@( posedge VCLK ) begin + PH <= V_FLIP ? (9'd286 - POSH) : POSH + 9'd1; + PV <= V_FLIP ? (9'd223 - POSV) : POSV+(POSH>=9'd504); + SPH <= POSH; + SPV <= POSV+(POSH>=9'd504); + end + + //--------------------------------------- + // VRAM Scan Address Generator + //--------------------------------------- + wire [5:0] SCOL = PH[8:3]-2'd2; + wire [5:0] SROW = PV[8:3]+2'd2; + wire [9:0] VSAD = SCOL[5] ? {SCOL[4:0],SROW[4:0]} : {SROW[4:0],SCOL[4:0]}; + + + //--------------------------------------- + // Sprite ScanLine Generator + //--------------------------------------- + wire [4:0] SPCOL; + + DIGDUG_SPRITE + sprite + ( + .RCLK(VCLKx8), + .VCLK(VCLK), + .VCLKx2(VCLKx2), + .POSH(SPH), + .POSV(SPV), + .SPATCL(SPATCL), + .SPATAD(SPATAD), + .SPATDT(SPATDT), + + .SPCOL(SPCOL), + .V_FLIP(V_FLIP), + .ROMCL(ROMCL), + .ROMAD(ROMAD), + .ROMDT(ROMDT), + .ROMEN(ROMEN) + ); + + + //--------------------------------------- + // FG ScanLine Generator + //--------------------------------------- + + assign FGSCCL = VCLKx2; + assign FGSCAD = VSAD; + + reg [4:0] FGCOL; + wire [10:0] FGCHAD = {1'b0,FGSCDT[6:0],PV[2:0]}; + wire [7:0] FGCHDT; + DLROM #(11,8) fgchip(~VCLKx2,FGCHAD,FGCHDT, ROMCL,ROMAD[10:0],ROMDT,ROMEN & (ROMAD[15:11]=={4'hD,1'b0})); + wire [7:0] FGCHPX = FGCHDT >> (PH[2:0]); + + wire [3:0] FGCLUT = FG_CLMODE ? FGSCDT[3:0] : ({FGSCDT[7:5],1'b0}|{2'b00,FGSCDT[4],1'b0}); + always @( posedge VCLKx2 ) FGCOL <= {FGCHPX[0],FGCLUT}; + + + //--------------------------------------- + // BG ScanLine Generator + //--------------------------------------- + wire [3:0] BGCOL; + + wire [11:0] BGSCAD = {BG_SELECT,VSAD}; + wire [7:0] BGSCDT; + DLROM #(12,8) bgscrn(VCLKx2,BGSCAD,BGSCDT, ROMCL,ROMAD[11:0],ROMDT,ROMEN & (ROMAD[15:12]==4'hB)); + + wire [11:0] BGCHAD = {BGSCDT,~PH[2],PV[2:0]}; + wire [7:0] BGCHDT; + DLROM #(12,8) bgchip(~VCLKx2,BGCHAD,BGCHDT, ROMCL,ROMAD[11:0],ROMDT,ROMEN & (ROMAD[15:12]==4'hC)); + wire [7:0] BGCHPI = BGCHDT << (PH[1:0]); + wire [1:0] BGCHPX = {BGCHPI[7],BGCHPI[3]}; + + wire [7:0] BGCLAD = BG_CUTOFF ? {6'h0F,BGCHPX} : {BG_COLBNK,BGSCDT[7:4],BGCHPX}; + DLROM #(8,4) bgclut(VCLKx2,BGCLAD,BGCOL, ROMCL,ROMAD[7:0],ROMDT[3:0],ROMEN & (ROMAD[15:8]==8'hDA)); + + + //--------------------------------------- + // Color Mixer & Pixel Output + //--------------------------------------- + wire [4:0] CMIX = SPCOL[4] ? {1'b1,SPCOL[3:0]} : FGCOL[4] ? {1'b0,FGCOL[3:0]} : {1'b0,BGCOL}; + + DLROM #(5,8) palet( VCLK, CMIX, POUT, ROMCL,ROMAD[4:0],ROMDT,ROMEN & (ROMAD[15:5]=={8'hDB,3'b000}) ); + assign PCLK = ~VCLK; + assign VBLK = (PH<9'd64)&(PV==9'd224); + +endmodule + diff --git a/rtl/cpucore.v b/rtl/cpucore.v new file mode 100644 index 0000000..dab4af4 --- /dev/null +++ b/rtl/cpucore.v @@ -0,0 +1,104 @@ +//------------------------------------------------------------------------------ +// SPDX-License-Identifier: GPL-3.0-or-later +// SPDX-FileType: SOURCE +// SPDX-FileCopyrightText: (c) 2017 MiSTer-X +//------------------------------------------------------------------------------ +// FPGA DigDug (CPU Core) +//------------------------------------------------------------------------------ + +`timescale 1 ps / 1 ps + +module CPUCORE + ( + input RESET, + input CLK, + input IRQ, + input NMI, + output RD, + output WR, + output [15:0] AD, + input DV, + input [7:0] DI, + input [7:0] IR, + output [7:0] DO, + input PAUSE + ); + + wire [7:0] m_do; + wire [15:0] m_ad; + wire m_irq, m_nmi, m_me, m_ie, m_rd, m_wr; + + wire m_mx = (~m_me); + wire m_mr = (~m_rd) & m_mx; + wire m_mw = (~m_wr) & m_mx; + + wire cs_mrom = ( m_ad[15:14] == 2'b00 ); + wire cs_nodv = cs_mrom; + + wire [7:0] m_di = cs_mrom ? IR : DV ? DI : 8'hFF; + + assign m_irq = ~IRQ; + assign m_nmi = ~NMI; + + tv80s core + ( + .mreq_n(m_me), + .iorq_n(m_ie), + .rd_n(m_rd), + .wr_n(m_wr), + .A(m_ad), + .dout(m_do), + + .reset_n(~RESET), + .clk(CLK), + .wait_n(~PAUSE), + .int_n(m_irq), + .nmi_n(m_nmi), + .busrq_n(1'b1), + .di(m_di), + + .m1_n(), + .halt_n(), + .rfsh_n(), + .busak_n() + + ); + + assign RD = m_mr & ~cs_nodv; + assign WR = m_mw & ~cs_nodv; + assign AD = m_ad; + assign DO = m_do; + +endmodule + + +//----------------------------------------------- +// NMI Ack Control +//----------------------------------------------- +module CPUNMIACK + ( + input RST, + input CL, + input [15:0] AD, + input NMI, + output reg NMIo + ); + + reg pNMI = 1'b0; + wire NMIACK = ( AD == 16'h0066 ); + always @( negedge CL or posedge RST ) begin + if (RST) begin + pNMI <= 1'b0; + NMIo <= 1'b0; + end + else begin + if (NMIACK) + NMIo <= 0; + else if ((pNMI^NMI) & NMI) + NMIo <= 1'b1; + pNMI <= NMI; + end + end + +endmodule + diff --git a/rtl/digdug.qip b/rtl/digdug.qip new file mode 100644 index 0000000..e978258 --- /dev/null +++ b/rtl/digdug.qip @@ -0,0 +1,21 @@ +# ============================================================================== +# RTL +# ============================================================================== +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "digdug.v"] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "DIGDUG_CORES.v"] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "DIGDUG_CUSIO.v"] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "DIGDUG_IODEV.v"] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "DIGDUG_SPRITE.v"] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "DIGDUG_VIDEO.v"] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "cpucore.v"] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "dprams.v"] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "hvgen.v"] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "wsg.v"] + +# ============================================================================== +# MODULES +# ============================================================================== +set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "../modules/dataloader-pocket/index.qip"] +set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "../modules/generic-dpram/index.qip"] +set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "../modules/generic-pause/index.qip"] +set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "../modules/TV80/index.qip"] diff --git a/rtl/digdug.v b/rtl/digdug.v new file mode 100644 index 0000000..5178844 --- /dev/null +++ b/rtl/digdug.v @@ -0,0 +1,168 @@ +//------------------------------------------------------------------------------ +// SPDX-License-Identifier: GPL-3.0-or-later +// SPDX-FileType: SOURCE +// SPDX-FileCopyrightText: (c) 2017 MiSTer-X +//------------------------------------------------------------------------------ +// FPGA DigDug (Top module) +//------------------------------------------------------------------------------ + +`timescale 1 ps / 1 ps + +module FPGA_DIGDUG + ( + input RESET, //! RESET + input MCLK, //! Master Clock (48.0MHz) = VCLKx8 + + input [7:0] INP0, //! Control Panel + input [7:0] INP1, + input [7:0] DSW0, + input [7:0] DSW1, + + input [8:0] PH, //! PIXEL H + input [8:0] PV, //! PIXEL V + input iPCLK, //! PIXEL CLOCK [IN] (Don't use Clock Divider / DEFINED VIA VERILOG_MACRO) + output oPCLK, //! PIXEL CLOCK [OUT] + output [7:0] POUT, //! PIXEL OUT + + output reg [7:0] SOUT, //! SOUND OUT + + output [7:0] LED, //! LEDs (for Debug) + + input V_FLIP, //! Vertical flip video + + input ROMCL, //! Downloaded ROM image + input [15:0] ROMAD, + input [7:0] ROMDT, + input ROMEN, + + input PAUSE, + + input [10:0] hs_address, + output [7:0] hs_data_out, + input [7:0] hs_data_in, + input hs_write, + input hs_access + ); + + // Common I/O Device Bus + wire DEV_CL; + wire [15:0] DEV_AD; + wire DEV_RD; + wire DEV_DV; + wire [7:0] DEV_DO; + wire DEV_WR; + wire [7:0] DEV_DI; + + + //----------------------------------------------- + // CPUs + //----------------------------------------------- + wire [2:0] RSTS,IRQS,NMIS; + + DIGDUG_CORES cores + ( + .MCLK(MCLK), + .RSTS(RSTS),.IRQS(IRQS),.NMIS(NMIS), + + .DEV_CL(DEV_CL),.DEV_AD(DEV_AD), + .DEV_RD(DEV_RD),.DEV_DV(DEV_DV),.DEV_DO(DEV_DO), + .DEV_WR(DEV_WR),.DEV_DI(DEV_DI), + + .ROMCL(ROMCL),.ROMAD(ROMAD),.ROMDT(ROMDT),.ROMEN(ROMEN), + + .PAUSE(PAUSE) + ); + + assign LED = { RSTS, IRQS[1:0], 1'b0, NMIS[2],NMIS[0] }; + + + //----------------------------------------------- + // Sound wave ROM + //----------------------------------------------- + wire WAVECL; + wire [7:0] WAVEAD; + wire [3:0] WAVEDT; + + DLROM #(8,4) wave(WAVECL,WAVEAD,WAVEDT, ROMCL,ROMAD[7:0],ROMDT[3:0],ROMEN & (ROMAD[15:8]==8'hD8)); + + + //----------------------------------------------- + // Common I/O Device Module + //----------------------------------------------- + wire PCMCLK; + wire [7:0] PCMOUT; + always @(posedge PCMCLK) SOUT <= PCMOUT; + + wire FGSCCL; + wire [9:0] FGSCAD; + wire [7:0] FGSCDT; + + wire SPATCL; + wire [6:0] SPATAD; + wire [23:0] SPATDT; + + wire [1:0] BG_SELECT; + wire [1:0] BG_COLBNK; + wire BG_CUTOFF; + wire FG_CLMODE; + + wire VBLK; + + DIGDUG_IODEV iodev + ( + .RESET(RESET), + .VBLK(VBLK), + + .INP0(INP0), + .INP1(INP1), + .DSW0(DSW0), + .DSW1(DSW1), + + .CL(DEV_CL), // Access Clock: 24.0MHz + .AD(DEV_AD),.WR(DEV_WR),.DI(DEV_DI), + .RD(DEV_RD),.DV(DEV_DV),.DO(DEV_DO), + + .RSTS(RSTS),.IRQS(IRQS),.NMIS(NMIS), + + .CLK48M(MCLK),.PCMCLK(PCMCLK),.PCMOUT(PCMOUT), + + .WAVECL(WAVECL),.WAVEAD(WAVEAD),.WAVEDT(WAVEDT), + + .FGSCCL(FGSCCL),.FGSCAD(FGSCAD),.FGSCDT(FGSCDT), + .SPATCL(SPATCL),.SPATAD(SPATAD),.SPATDT(SPATDT), + + .BG_SELECT(BG_SELECT),.BG_COLBNK(BG_COLBNK),.BG_CUTOFF(BG_CUTOFF), + .FG_CLMODE(FG_CLMODE), + + .hs_address(hs_address), + .hs_data_in(hs_data_in), + .hs_data_out(hs_data_out), + .hs_write(hs_write), + .hs_access(hs_access) + ); + + + //----------------------------------------------- + // Video Module + //----------------------------------------------- + DIGDUG_VIDEO video + ( + .CLK48M(MCLK), + .POSH(PH),.POSV(PV), + + .BG_SELECT(BG_SELECT),.BG_COLBNK(BG_COLBNK),.BG_CUTOFF(BG_CUTOFF), + .FG_CLMODE(FG_CLMODE), + + .FGSCCL(FGSCCL),.FGSCAD(FGSCAD),.FGSCDT(FGSCDT), + .SPATCL(SPATCL),.SPATAD(SPATAD),.SPATDT(SPATDT), + + .VBLK(VBLK),.iPCLK(iPCLK),.PCLK(oPCLK),.POUT(POUT), + + .V_FLIP(V_FLIP), + + .ROMCL(ROMCL),.ROMAD(ROMAD),.ROMDT(ROMDT),.ROMEN(ROMEN) + ); + + +endmodule + diff --git a/rtl/dprams.v b/rtl/dprams.v new file mode 100644 index 0000000..280a787 --- /dev/null +++ b/rtl/dprams.v @@ -0,0 +1,144 @@ +//------------------------------------------------------------------------------ +// SPDX-License-Identifier: GPL-3.0-or-later +// SPDX-FileType: SOURCE +// SPDX-FileCopyrightText: (c) 2017 MiSTer-X +//------------------------------------------------------------------------------ +// FPGA DigDug (Dualport RAM modules) +//------------------------------------------------------------------------------ + +`timescale 1 ps / 1 ps + +module DPR2KV + ( + input CL0, + input [10:0] AD0, + input EN0, + input WR0, + input [7:0] DI0, + output [7:0] DO0, + + input CL1, + input [10:0] AD1, + output [7:0] DO1 + ); + + DPR2K ram( + CL0, AD0, EN0, WR0, DI0, DO0, + CL1, AD1, 1'b1, 1'b0, 8'h0, DO1 + ); + +endmodule + + +module DPR2K + ( + input CL0, + input [10:0] AD0, + input EN0, + input WR0, + input [7:0] DI0, + output reg [7:0] DO0, + + input CL1, + input [10:0] AD1, + input EN1, + input WR1, + input [7:0] DI1, + output reg [7:0] DO1 + ); + + reg [7:0] core[0:2047] /* synthesis ramstyle = "no_rw_check, M10K" */; + + always @( posedge CL0 ) begin + if (EN0) begin + DO0 <= core[AD0]; + if (WR0) + core[AD0] <= DI0; + end + end + + always @( posedge CL1 ) begin + if (EN1) begin + DO1 <= core[AD1]; + if (WR1) + core[AD1] <= DI1; + end + end + +endmodule + + +module LBUF1K + ( + input CL0, + input [9:0] AD0, + input WR0, + input [7:0] DI0, + + input CL1, + input [9:0] AD1, + input WR1, + input [7:0] DI1, + output [7:0] DO1 + ); + + dpram #(10,8) lbuf( + .clock_a(CL0), + .address_a(AD0), + .data_a(DI0), + .wren_a(WR0), + .q_a(), + + .clock_b(CL1), + .address_b(AD1), + .data_b(DI1), + .wren_b(WR1), + .q_b(DO1) + ); + +endmodule + + +module DLROM #(parameter AW,parameter DW) + ( + input CL0, + input [(AW-1):0] AD0, + output reg [(DW-1):0] DO0, + + input CL1, + input [(AW-1):0] AD1, + input [(DW-1):0] DI1, + input WE1 + ); + + reg [DW-1:0] core[0:((2**AW)-1)] /* synthesis ramstyle = "no_rw_check, M10K" */; + + always @(posedge CL0) DO0 <= core[AD0]; + always @(posedge CL1) if (WE1) + core[AD1] <= DI1; + +endmodule + + +module DLROMe #(parameter AW,parameter DW) + ( + input RE0, + input CL0, + input [(AW-1):0] AD0, + output reg [(DW-1):0] DO0, + + input CL1, + input [(AW-1):0] AD1, + input [(DW-1):0] DI1, + input WE1 + ); + + reg [DW-1:0] core[0:((2**AW)-1)] /* synthesis ramstyle = "no_rw_check, M10K" */; + + always @(posedge CL0) if (RE0) + DO0 <= core[AD0]; + always @(posedge CL1) if (WE1) + core[AD1] <= DI1; + +endmodule + diff --git a/rtl/hvgen.v b/rtl/hvgen.v new file mode 100644 index 0000000..9e4f921 --- /dev/null +++ b/rtl/hvgen.v @@ -0,0 +1,49 @@ +//------------------------------------------------------------------------------ +// SPDX-License-Identifier: GPL-3.0-or-later +// SPDX-FileType: SOURCE +// SPDX-FileCopyrightText: (c) 2017 MiSTer-X +//------------------------------------------------------------------------------ +// FPGA DigDug (Video timing part) +//------------------------------------------------------------------------------ + +`timescale 1 ps / 1 ps + +module hvgen + ( + input iPCLK, + output [8:0] oHPOS, + output [8:0] oVPOS, + + output reg oHBLK = 1, + output reg oVBLK = 1, + output reg oHSYN = 1, + output reg oVSYN = 1, + output reg oBLKN + ); + + reg [8:0] hcnt = 0; + reg [8:0] vcnt = 0; + + assign oHPOS = hcnt; + assign oVPOS = vcnt; + + always @(posedge iPCLK) begin + case (hcnt) + 288: begin oHBLK <= 1; hcnt <= hcnt + 1'b1; end + 311: begin oHSYN <= 0; hcnt <= hcnt + 1'b1; end + 342: begin oHSYN <= 1; hcnt <= 471; end + 511: begin oHBLK <= 0; hcnt <= 0; + case (vcnt) + 223: begin oVBLK <= 1; vcnt <= vcnt + 1'b1; end + 226: begin oVSYN <= 0; vcnt <= vcnt + 1'b1; end + 233: begin oVSYN <= 1; vcnt <= 483; end + 511: begin oVBLK <= 0; vcnt <= 0; end + default: vcnt <= vcnt + 1'b1; + endcase + end + default: hcnt <= hcnt + 1'b1; + endcase + oBLKN <= ~(oHBLK | oVBLK); + end + +endmodule diff --git a/rtl/wsg.v b/rtl/wsg.v new file mode 100644 index 0000000..0cb3adf --- /dev/null +++ b/rtl/wsg.v @@ -0,0 +1,256 @@ +//------------------------------------------------------------------------------ +// SPDX-License-Identifier: GPL-3.0-or-later +// SPDX-FileType: SOURCE +// SPDX-FileCopyrightText: (c) 2017 MiSTer-X +//------------------------------------------------------------------------------ +// FPGA DigDug (Wave-base Sound Generator [3ch]) +//------------------------------------------------------------------------------ + +`timescale 1 ps / 1 ps + +module WSG_3CH + ( + input CLK48M, + input RESET, + + input CPUCLK, + input [4:0] ADRS, + input [3:0] DATA, + input WR, + + output WROMCLK, + output [7:0] WROMADR, + input [3:0] WROMDAT, + + output PCMCLK, + output [7:0] PCMOUT + ); + + wire WSGCLKx4; + WSGCLKGEN cgen( CLK48M, WSGCLKx4 ); + + wire [2:0] W0, W1, W2; + wire [3:0] V0, V1, V2; + wire [19:0] F0; + wire [15:0] F1, F2; + + WSGREGS regs + ( + RESET, + CPUCLK, ADRS, WR, DATA, + + W0, W1, W2, + V0, V1, V2, + F0, F1, F2 + ); + + WSGCORE core + ( + RESET, WSGCLKx4, + WROMCLK, WROMADR, WROMDAT, + + W0, W1, W2, + V0, V1, V2, + F0, F1, F2, + + PCMCLK, PCMOUT + ); + +endmodule + + +module WSGREGS + ( + input RESET, + input CPUCLK, + input [4:0] ADRS, + input WR, + input [3:0] DATA, + + output reg [2:0] W0, + output reg [2:0] W1, + output reg [2:0] W2, + + output reg [3:0] V0, + output reg [3:0] V1, + output reg [3:0] V2, + + output reg [19:0] F0, + output reg [15:0] F1, + output reg [15:0] F2 + ); + + always @ ( posedge CPUCLK or posedge RESET ) begin + + if ( RESET ) begin + + W0 <= 0; + W1 <= 0; + W2 <= 0; + + F0 <= 0; + F1 <= 0; + F2 <= 0; + + V0 <= 0; + V1 <= 0; + V2 <= 0; + + end + else begin + + if ( WR ) + case ( ADRS ) + + 5'h05: W0 <= DATA[2:0]; + 5'h0A: W1 <= DATA[2:0]; + 5'h0F: W2 <= DATA[2:0]; + + 5'h15: V0 <= DATA; + 5'h1A: V1 <= DATA; + 5'h1F: V2 <= DATA; + + 5'h10: F0[3:0] <= DATA; + 5'h11: F0[7:4] <= DATA; + 5'h12: F0[11:8] <= DATA; + 5'h13: F0[15:12] <= DATA; + 5'h14: F0[19:16] <= DATA; + + 5'h16: F1[3:0] <= DATA; + 5'h17: F1[7:4] <= DATA; + 5'h18: F1[11:8] <= DATA; + 5'h19: F1[15:12] <= DATA; + + 5'h1B: F2[3:0] <= DATA; + 5'h1C: F2[7:4] <= DATA; + 5'h1D: F2[11:8] <= DATA; + 5'h1E: F2[15:12] <= DATA; + + default: ; + + endcase + + end + + end + +endmodule + + +module WSGCORE + ( + input RESET, + input WSGCLKx4, + + output WROMCLK, + output [7:0] WROMADR, + input [3:0] WROMDAT, + + input [2:0] W0, + input [2:0] W1, + input [2:0] W2, + + input [3:0] V0, + input [3:0] V1, + input [3:0] V2, + + input [19:0] F0, + input [15:0] F1, + input [15:0] F2, + + output reg outclk, + output reg [7:0] sndout + ); + + reg [7:0] waveadr, cc1, cc2; + + reg [19:0] c0; + reg [15:0] c1, c2; + + reg [3:0] wavevol; + wire [7:0] waveout = wavevol * WROMDAT; + + reg [9:0] sndmix; + wire [10:0] sndmixdown = { 1'b0, sndmix }; + + reg [1:0] phase; + always @ ( posedge WSGCLKx4 or posedge RESET ) begin + + if ( RESET ) begin + phase <= 2'h0; + sndout <= 8'h00; + outclk <= 1'b0; + cc1 <= 8'h00; + cc2 <= 8'h00; + end + else begin + + case ( phase ) + + 2'h0: begin + sndout <= ( sndmixdown[9:2] | {8{sndmixdown[10]}} ); + + cc1 <= {W1,c1[15:11]}; + cc2 <= {W2,c2[15:11]}; + + sndmix <= 10'h000; + waveadr <= {W0,c0[19:15]}; + wavevol <= (F0!=0) ? V0 : 4'h0; + end + + 2'h1: begin + outclk <= 1'b1; + sndmix <= sndmix + waveout; + + waveadr <= cc1; + wavevol <= (F1!=0) ? V1 : 4'h0; + end + + 2'h2: begin + sndmix <= sndmix + waveout; + + waveadr <= cc2; + wavevol <= (F2!=0) ? V2 : 4'h0; + end + + 2'h3: begin + outclk <= 1'b0; + sndmix <= sndmix + waveout; + end + + default: ; + + endcase + + phase <= phase+1'b1; + + c0 <= c0 + F0; + c1 <= c1 + F1; + c2 <= c2 + F2; + + end + + end + + assign WROMCLK = ~WSGCLKx4; + assign WROMADR = waveadr; + +endmodule + + +/** + * Clock Generator + * in: 48000000Hz -> out: 96000Hz + */ +module WSGCLKGEN( input in, output reg out ); + reg [7:0] count; + always @( posedge in ) begin + if (count > 8'd249) begin + count <= count - 8'd249; + out <= ~out; + end + else + count <= count + 8'd1; + end +endmodule + diff --git a/target/pocket/core.qip b/target/pocket/core.qip new file mode 100644 index 0000000..aa1025d --- /dev/null +++ b/target/pocket/core.qip @@ -0,0 +1,5 @@ +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "core_top.v"] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "core_bridge_cmd.v"] +set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) "core_constraints.sdc"] +set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "mf_pllbase.qip"] +set_global_assignment -name SIGNALTAP_FILE [file join $::quartus(qip_path) "stp1.stp"] diff --git a/target/pocket/core_bridge_cmd.v b/target/pocket/core_bridge_cmd.v new file mode 100644 index 0000000..7fc8a70 --- /dev/null +++ b/target/pocket/core_bridge_cmd.v @@ -0,0 +1,445 @@ +// +// bridge host/target command handler +// 2022 Analogue +// + +// mapped to 0xF8xxxxxx on bridge +// the spec is loose enough to allow implementation with either +// block rams and a soft CPU, or simply hard logic with some case statements. +// +// the implementation spec is documented, and depending on your application you +// may want to completely replace this module. this is only one of many +// possible ways to accomplish the host/target command system and data table. +// +// this module should always be clocked by a direct clock input and never a PLL, +// because it should report PLL lock status +// + +module core_bridge_cmd ( + +input wire clk, +output reg reset_n, + +input wire bridge_endian_little, +input wire [31:0] bridge_addr, +input wire bridge_rd, +output reg [31:0] bridge_rd_data, +input wire bridge_wr, +input wire [31:0] bridge_wr_data, + +// all these signals should be synchronous to clk +// add synchronizers if these need to be used in other clock domains +input wire status_boot_done, // assert when PLLs lock and logic is ready +input wire status_setup_done, // assert when core is happy with what's been loaded into it +input wire status_running, // assert when pocket's taken core out of reset and is running + +output reg dataslot_requestread, +output reg [15:0] dataslot_requestread_id, +input wire dataslot_requestread_ack, +input wire dataslot_requestread_ok, + +output reg dataslot_requestwrite, +output reg [15:0] dataslot_requestwrite_id, +input wire dataslot_requestwrite_ack, +input wire dataslot_requestwrite_ok, + +output reg dataslot_allcomplete, + +input wire savestate_supported, +input wire [31:0] savestate_addr, +input wire [31:0] savestate_size, +input wire [31:0] savestate_maxloadsize, + +output reg osnotify_inmenu, + +output reg savestate_start, // core should detect rising edge on this, +input wire savestate_start_ack, // and then assert ack for at least 1 cycle +input wire savestate_start_busy, // assert constantly while in progress after ack +input wire savestate_start_ok, // assert continuously when done, and clear when new process is started +input wire savestate_start_err, // assert continuously on error, and clear when new process is started + +output reg savestate_load, +input wire savestate_load_ack, +input wire savestate_load_busy, +input wire savestate_load_ok, +input wire savestate_load_err, + +input wire [9:0] datatable_addr, +input wire datatable_wren, +input wire [31:0] datatable_data, +output wire [31:0] datatable_q + +); + +// handle endianness + reg [31:0] bridge_wr_data_in; + reg [31:0] bridge_rd_data_out; + + wire endian_little_s; +synch_3 s01(bridge_endian_little, endian_little_s, clk); + +always @(*) begin + bridge_rd_data <= endian_little_s ? { + bridge_rd_data_out[7:0], + bridge_rd_data_out[15:8], + bridge_rd_data_out[23:16], + bridge_rd_data_out[31:24] + } : bridge_rd_data_out; + + bridge_wr_data_in <= endian_little_s ? { + bridge_wr_data[7:0], + bridge_wr_data[15:8], + bridge_wr_data[23:16], + bridge_wr_data[31:24] + } : bridge_wr_data; +end + + +// minimalistic approach here - +// keep the commonly used registers in logic, but data table in BRAM. +// implementation could be changed quite a bit for a more advanced use case + +// host + + reg [31:0] host_0; + reg [31:0] host_4 = 'h20; // host cmd parameter data at 0x20 + reg [31:0] host_8 = 'h40; // host cmd response data at 0x40 + + reg [31:0] host_20; // parameter data + reg [31:0] host_24; + reg [31:0] host_28; + reg [31:0] host_2C; + + reg [31:0] host_40; // response data + reg [31:0] host_44; + reg [31:0] host_48; + reg [31:0] host_4C; + + reg host_cmd_start; + reg [15:0] host_cmd_startval; + reg [15:0] host_cmd; + reg [15:0] host_resultcode; + +localparam [3:0] ST_IDLE = 'd0; +localparam [3:0] ST_PARSE = 'd1; +localparam [3:0] ST_WORK = 'd2; +localparam [3:0] ST_DONE_OK = 'd13; +localparam [3:0] ST_DONE_CODE = 'd14; +localparam [3:0] ST_DONE_ERR = 'd15; + reg [3:0] hstate; + +// target + + reg [31:0] target_0; + reg [31:0] target_4 = 'h20; + reg [31:0] target_8 = 'h40; + + reg [31:0] target_20; // parameter data + reg [31:0] target_24; + reg [31:0] target_28; + reg [31:0] target_2C; + + reg [31:0] target_40; // response data + reg [31:0] target_44; + reg [31:0] target_48; + reg [31:0] target_4C; + +localparam [3:0] TARG_ST_IDLE = 'd0; +localparam [3:0] TARG_ST_READYTORUN = 'd1; +localparam [3:0] TARG_ST_DISPMSG = 'd2; +localparam [3:0] TARG_ST_SLOTREAD = 'd3; +localparam [3:0] TARG_ST_SLOTRELOAD = 'd4; +localparam [3:0] TARG_ST_SLOTWRITE = 'd5; +localparam [3:0] TARG_ST_SLOTFLUSH = 'd6; +localparam [3:0] TARG_ST_WAITRESULT = 'd15; + reg [3:0] tstate; + + reg status_setup_done_1; + reg status_setup_done_queue; + + +initial begin + reset_n <= 0; + dataslot_requestread <= 0; + dataslot_requestwrite <= 0; + dataslot_allcomplete <= 0; + savestate_start <= 0; + savestate_load <= 0; + osnotify_inmenu <= 0; + status_setup_done_queue <= 0; +end + +always @(posedge clk) begin + + // detect a rising edge on the input signal + // and flag a queue that will be cleared later + status_setup_done_1 <= status_setup_done; + if(status_setup_done & ~status_setup_done_1) begin + status_setup_done_queue <= 1; + end + + b_datatable_wren <= 0; + b_datatable_addr <= bridge_addr >> 2; + + if(bridge_wr) begin + casex(bridge_addr) + 32'hF8xx00xx: begin + case(bridge_addr[7:0]) + 8'h0: begin + host_0 <= bridge_wr_data_in; // command/status + // check for command + if(bridge_wr_data_in[31:16] == 16'h434D) begin + // host wants us to do a command + host_cmd_startval <= bridge_wr_data_in[15:0]; + host_cmd_start <= 1; + end + end + 8'h20: host_20 <= bridge_wr_data_in; // parameter data regs + 8'h24: host_24 <= bridge_wr_data_in; + 8'h28: host_28 <= bridge_wr_data_in; + 8'h2C: host_2C <= bridge_wr_data_in; + endcase + end + 32'hF8xx10xx: begin + case(bridge_addr[7:0]) + 8'h0: target_0 <= bridge_wr_data_in; // command/status + 8'h4: target_4 <= bridge_wr_data_in; // parameter data pointer + 8'h8: target_8 <= bridge_wr_data_in; // response data pointer + 8'h40: target_40 <= bridge_wr_data_in; // response data regs + 8'h44: target_44 <= bridge_wr_data_in; + 8'h48: target_48 <= bridge_wr_data_in; + 8'h4C: target_4C <= bridge_wr_data_in; + endcase + end + 32'hF8xx2xxx: begin + b_datatable_wren <= 1; + end + endcase + end + if(bridge_rd) begin + casex(bridge_addr) + 32'hF8xx00xx: begin + case(bridge_addr[7:0]) + 8'h0: bridge_rd_data_out <= host_0; // command/status + 8'h4: bridge_rd_data_out <= host_4; // parameter data pointer + 8'h8: bridge_rd_data_out <= host_8; // response data pointer + 8'h40: bridge_rd_data_out <= host_40; // response data regs + 8'h44: bridge_rd_data_out <= host_44; + 8'h48: bridge_rd_data_out <= host_48; + 8'h4C: bridge_rd_data_out <= host_4C; + endcase + end + 32'hF8xx10xx: begin + case(bridge_addr[7:0]) + 8'h0: bridge_rd_data_out <= target_0; + 8'h4: bridge_rd_data_out <= target_4; + 8'h8: bridge_rd_data_out <= target_8; + 8'h20: bridge_rd_data_out <= target_20; // parameter data regs + 8'h24: bridge_rd_data_out <= target_24; + 8'h28: bridge_rd_data_out <= target_28; + 8'h2C: bridge_rd_data_out <= target_2C; + endcase + end + 32'hF8xx2xxx: begin + bridge_rd_data_out <= b_datatable_q; + + end + endcase + end + + + + + + // host > target command executer + case(hstate) + ST_IDLE: begin + + dataslot_requestread <= 0; + dataslot_requestwrite <= 0; + savestate_start <= 0; + savestate_load <= 0; + + // there is no queueing. pocket will always make sure any outstanding host + // commands are finished before starting another + if(host_cmd_start) begin + host_cmd_start <= 0; + // save the command in case it gets clobbered later + host_cmd <= host_cmd_startval; + hstate <= ST_PARSE; + end + + end + ST_PARSE: begin + // overwrite command semaphore with busy flag + host_0 <= {16'h4255, host_cmd}; + + case(host_cmd) + 16'h0000: begin + // Request Status + host_resultcode <= 1; // default: booting + if(status_boot_done) begin + host_resultcode <= 2; // setup + if(status_setup_done) begin + host_resultcode <= 3; // idle + end else if(status_running) begin + host_resultcode <= 4; // running + end + end + hstate <= ST_DONE_CODE; + end + 16'h0010: begin + // Reset Enter + reset_n <= 0; + hstate <= ST_DONE_OK; + end + 16'h0011: begin + // Reset Exit + reset_n <= 1; + hstate <= ST_DONE_OK; + end + 16'h0080: begin + // Data slot request read + dataslot_allcomplete <= 0; + dataslot_requestread <= 1; + dataslot_requestread_id <= host_20[15:0]; + if(dataslot_requestread_ack) begin + host_resultcode <= 0; + if(!dataslot_requestread_ok) host_resultcode <= 2; + hstate <= ST_DONE_CODE; + end + end + 16'h0082: begin + // Data slot request write + dataslot_allcomplete <= 0; + dataslot_requestwrite <= 1; + dataslot_requestwrite_id <= host_20[15:0]; + if(dataslot_requestwrite_ack) begin + host_resultcode <= 0; + if(!dataslot_requestwrite_ok) host_resultcode <= 2; + hstate <= ST_DONE_CODE; + end + end + 16'h008F: begin + // Data slot access all complete + dataslot_allcomplete <= 1; + hstate <= ST_DONE_OK; + end + 16'h00A0: begin + // Savestate: Start/Query + host_40 <= savestate_supported; + host_44 <= savestate_addr; + host_48 <= savestate_size; + + host_resultcode <= 0; + if(savestate_start_busy) host_resultcode <= 1; + if(savestate_start_ok) host_resultcode <= 2; + if(savestate_start_err) host_resultcode <= 3; + + if(host_20[0]) begin + // Request Start! + savestate_start <= 1; + // stay in this state until ack'd + if(savestate_start_ack) begin + hstate <= ST_DONE_CODE; + end + end else begin + hstate <= ST_DONE_CODE; + end + end + 16'h00A4: begin + // Savestate: Load/Query + host_40 <= savestate_supported; + host_44 <= savestate_addr; + host_48 <= savestate_maxloadsize; + + host_resultcode <= 0; + if(savestate_load_busy) host_resultcode <= 1; + if(savestate_load_ok) host_resultcode <= 2; + if(savestate_load_err) host_resultcode <= 3; + + if(host_20[0]) begin + // Request Load! + savestate_load <= 1; + // stay in this state until ack'd + if(savestate_load_ack) begin + hstate <= ST_DONE_CODE; + end + end else begin + hstate <= ST_DONE_CODE; + end + end + 16'h00B0: begin + // OS Notify: Menu State + osnotify_inmenu <= host_20[0]; + hstate <= ST_DONE_OK; + end + default: begin + hstate <= ST_DONE_ERR; + end + endcase + end + ST_WORK: begin + hstate <= ST_IDLE; + end + ST_DONE_OK: begin + host_0 <= 32'h4F4B0000; // result code 0 + hstate <= ST_IDLE; + end + ST_DONE_CODE: begin + host_0 <= {16'h4F4B, host_resultcode}; + hstate <= ST_IDLE; + end + ST_DONE_ERR: begin + host_0 <= 32'h4F4BFFFF; // result code FFFF = unknown command + hstate <= ST_IDLE; + end + endcase + + + + + // target > host command executer + case(tstate) + TARG_ST_IDLE: begin + if(status_setup_done_queue) begin + status_setup_done_queue <= 0; + tstate <= TARG_ST_READYTORUN; + end + + end + TARG_ST_READYTORUN: begin + target_0 <= 32'h636D_0140; + tstate <= TARG_ST_WAITRESULT; + end + TARG_ST_WAITRESULT: begin + if(target_0[31:16] == 16'h6F6B) begin + // done + tstate <= TARG_ST_IDLE; + end + + end + endcase + + +end + + wire [31:0] b_datatable_q; + reg [9:0] b_datatable_addr; + reg b_datatable_wren; + +mf_datatable idt ( + .address_a ( datatable_addr ), + .address_b ( b_datatable_addr ), + .clock_a ( clk ), + .clock_b ( clk ), + .data_a ( datatable_data ), + .data_b ( bridge_wr_data_in ), + .wren_a ( datatable_wren ), + .wren_b ( b_datatable_wren ), + .q_a ( datatable_q ), + .q_b ( b_datatable_q ) +); + + +endmodule diff --git a/target/pocket/core_constraints.sdc b/target/pocket/core_constraints.sdc new file mode 100644 index 0000000..198f17b --- /dev/null +++ b/target/pocket/core_constraints.sdc @@ -0,0 +1,14 @@ +# +# user core constraints +# +# put your clock groups in here as well as any net assignments +# + +set_clock_groups -asynchronous \ + -group { bridge_spiclk } \ + -group { clk_74a } \ + -group { clk_74b } \ + -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk } \ + -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk } \ + -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk } \ + -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk } diff --git a/target/pocket/core_top.v b/target/pocket/core_top.v new file mode 100644 index 0000000..7e891aa --- /dev/null +++ b/target/pocket/core_top.v @@ -0,0 +1,703 @@ +// +// User core top-level +// +// Instantiated by the real top-level: apf_top +// + +`default_nettype none + +module core_top ( + + // + // physical connections + // + + /////////////////////////////////////////////////// + // clock inputs 74.25mhz. not phase aligned, so treat these domains as asynchronous + + input wire clk_74a, // mainclk1 + input wire clk_74b, // mainclk1 + + /////////////////////////////////////////////////// + // cartridge interface + // switches between 3.3v and 5v mechanically + // output enable for multibit translators controlled by pic32 + + // GBA AD[15:8] + inout wire [7:0] cart_tran_bank2, + output wire cart_tran_bank2_dir, + + // GBA AD[7:0] + inout wire [7:0] cart_tran_bank3, + output wire cart_tran_bank3_dir, + + // GBA A[23:16] + inout wire [7:0] cart_tran_bank1, + output wire cart_tran_bank1_dir, + + // GBA [7] PHI# + // GBA [6] WR# + // GBA [5] RD# + // GBA [4] CS1#/CS# + // [3:0] unwired + inout wire [7:4] cart_tran_bank0, + output wire cart_tran_bank0_dir, + + // GBA CS2#/RES# + inout wire cart_tran_pin30, + output wire cart_tran_pin30_dir, + // when GBC cart is inserted, this signal when low or weak will pull GBC /RES low with a special circuit + // the goal is that when unconfigured, the FPGA weak pullups won't interfere. + // thus, if GBC cart is inserted, FPGA must drive this high in order to let the level translators + // and general IO drive this pin. + output wire cart_pin30_pwroff_reset, + + // GBA IRQ/DRQ + inout wire cart_tran_pin31, + output wire cart_tran_pin31_dir, + + // infrared + input wire port_ir_rx, + output wire port_ir_tx, + output wire port_ir_rx_disable, + + // GBA link port + inout wire port_tran_si, + output wire port_tran_si_dir, + inout wire port_tran_so, + output wire port_tran_so_dir, + inout wire port_tran_sck, + output wire port_tran_sck_dir, + inout wire port_tran_sd, + output wire port_tran_sd_dir, + + /////////////////////////////////////////////////// + // cellular psram 0 and 1, two chips (64mbit x2 dual die per chip) + + output wire [21:16] cram0_a, + inout wire [15:0] cram0_dq, + input wire cram0_wait, + output wire cram0_clk, + output wire cram0_adv_n, + output wire cram0_cre, + output wire cram0_ce0_n, + output wire cram0_ce1_n, + output wire cram0_oe_n, + output wire cram0_we_n, + output wire cram0_ub_n, + output wire cram0_lb_n, + + output wire [21:16] cram1_a, + inout wire [15:0] cram1_dq, + input wire cram1_wait, + output wire cram1_clk, + output wire cram1_adv_n, + output wire cram1_cre, + output wire cram1_ce0_n, + output wire cram1_ce1_n, + output wire cram1_oe_n, + output wire cram1_we_n, + output wire cram1_ub_n, + output wire cram1_lb_n, + + /////////////////////////////////////////////////// + // sdram, 512mbit 16bit + + output wire [12:0] dram_a, + output wire [1:0] dram_ba, + inout wire [15:0] dram_dq, + output wire [1:0] dram_dqm, + output wire dram_clk, + output wire dram_cke, + output wire dram_ras_n, + output wire dram_cas_n, + output wire dram_we_n, + + /////////////////////////////////////////////////// + // sram, 1mbit 16bit + + output wire [16:0] sram_a, + inout wire [15:0] sram_dq, + output wire sram_oe_n, + output wire sram_we_n, + output wire sram_ub_n, + output wire sram_lb_n, + + /////////////////////////////////////////////////// + // vblank driven by dock for sync in a certain mode + + input wire vblank, + + /////////////////////////////////////////////////// + // i/o to 6515D breakout usb uart + + output wire dbg_tx, + input wire dbg_rx, + + /////////////////////////////////////////////////// + // i/o pads near jtag connector user can solder to + + output wire user1, + input wire user2, + + /////////////////////////////////////////////////// + // RFU internal i2c bus + + inout wire aux_sda, + output wire aux_scl, + + /////////////////////////////////////////////////// + // RFU, do not use + output wire vpll_feed, + + // + // logical connections + // + /////////////////////////////////////////////////// + // video, audio output to scaler + output wire [23:0] video_rgb, + output wire video_rgb_clock, + output wire video_rgb_clock_90, + output wire video_de, + output wire video_skip, + output wire video_vs, + output wire video_hs, + + output wire audio_mclk, + input wire audio_adc, + output wire audio_dac, + output wire audio_lrck, + + /////////////////////////////////////////////////// + // bridge bus connection + // synchronous to clk_74a + output wire bridge_endian_little, + input wire [31:0] bridge_addr, + input wire bridge_rd, + output reg [31:0] bridge_rd_data, + input wire bridge_wr, + input wire [31:0] bridge_wr_data, + + /////////////////////////////////////////////////// + // controller data + // + // key bitmap: + // [0] dpad_up + // [1] dpad_down + // [2] dpad_left + // [3] dpad_right + // [4] face_a + // [5] face_b + // [6] face_x + // [7] face_y + // [8] trig_l1 + // [9] trig_r1 + // [10] trig_l2 + // [11] trig_r2 + // [12] trig_l3 + // [13] trig_r3 + // [14] face_select + // [15] face_start + // joy values - unsigned + // [ 7: 0] lstick_x + // [15: 8] lstick_y + // [23:16] rstick_x + // [31:24] rstick_y + // trigger values - unsigned + // [ 7: 0] ltrig + // [15: 8] rtrig + // + input wire [15:0] cont1_key, + input wire [15:0] cont2_key, + input wire [15:0] cont3_key, + input wire [15:0] cont4_key, + input wire [31:0] cont1_joy, + input wire [31:0] cont2_joy, + input wire [31:0] cont3_joy, + input wire [31:0] cont4_joy, + input wire [15:0] cont1_trig, + input wire [15:0] cont2_trig, + input wire [15:0] cont3_trig, + input wire [15:0] cont4_trig + + ); + + // not using the IR port, so turn off both the LED, and + // disable the receive circuit to save power + assign port_ir_tx = 0; + assign port_ir_rx_disable = 1; + + // bridge endianness + assign bridge_endian_little = 0; + + // cart is unused, so set all level translators accordingly + // directions are 0:IN, 1:OUT + assign cart_tran_bank3 = 8'hzz; + assign cart_tran_bank3_dir = 1'b0; + assign cart_tran_bank2 = 8'hzz; + assign cart_tran_bank2_dir = 1'b0; + assign cart_tran_bank1 = 8'hzz; + assign cart_tran_bank1_dir = 1'b0; + assign cart_tran_bank0 = 4'hf; + assign cart_tran_bank0_dir = 1'b1; + assign cart_tran_pin30 = 1'b0; // reset or cs2, we let the hw control it by itself + assign cart_tran_pin30_dir = 1'bz; + assign cart_pin30_pwroff_reset = 1'b0; // hardware can control this + assign cart_tran_pin31 = 1'bz; // input + assign cart_tran_pin31_dir = 1'b0; // input + + // link port is input only + assign port_tran_so = 1'bz; + assign port_tran_so_dir = 1'b0; // SO is output only + assign port_tran_si = 1'bz; + assign port_tran_si_dir = 1'b0; // SI is input only + assign port_tran_sck = 1'bz; + assign port_tran_sck_dir = 1'b0; // clock direction can change + assign port_tran_sd = 1'bz; + assign port_tran_sd_dir = 1'b0; // SD is input and not used + + // tie off the rest of the pins we are not using + assign cram0_a = 'h0; + assign cram0_dq = {16{1'bZ}}; + assign cram0_clk = 0; + assign cram0_adv_n = 1; + assign cram0_cre = 0; + assign cram0_ce0_n = 1; + assign cram0_ce1_n = 1; + assign cram0_oe_n = 1; + assign cram0_we_n = 1; + assign cram0_ub_n = 1; + assign cram0_lb_n = 1; + + assign cram1_a = 'h0; + assign cram1_dq = {16{1'bZ}}; + assign cram1_clk = 0; + assign cram1_adv_n = 1; + assign cram1_cre = 0; + assign cram1_ce0_n = 1; + assign cram1_ce1_n = 1; + assign cram1_oe_n = 1; + assign cram1_we_n = 1; + assign cram1_ub_n = 1; + assign cram1_lb_n = 1; + + assign dram_a = 'h0; + assign dram_ba = 'h0; + assign dram_dq = {16{1'bZ}}; + assign dram_dqm = 'h0; + assign dram_clk = 'h0; + assign dram_cke = 'h0; + assign dram_ras_n = 'h1; + assign dram_cas_n = 'h1; + assign dram_we_n = 'h1; + + assign sram_a = 'h0; + assign sram_dq = {16{1'bZ}}; + assign sram_oe_n = 1; + assign sram_we_n = 1; + assign sram_ub_n = 1; + assign sram_lb_n = 1; + + assign dbg_tx = 1'bZ; + assign user1 = 1'bZ; + assign aux_scl = 1'bZ; + assign vpll_feed = 1'bZ; + + // for bridge write data, we just broadcast it to all bus devices + // for bridge read data, we have to mux it + // add your own devices here + always @(*) begin + casex(bridge_addr) + 32'h10000000: begin + bridge_rd_data <= bridge_read_buffer; + end + 32'h10010000: begin + bridge_rd_data <= bridge_read_buffer; + end + // for core_bridge_cmd + 32'hF8xxxxxx: begin + bridge_rd_data <= cmd_bridge_rd_data; + end + default: begin + bridge_rd_data <= 0; + end + endcase + end + + // + // host/target command handler + // + wire reset_n; // driven by host commands, can be used as core-wide reset + wire [31:0] cmd_bridge_rd_data; + + // bridge host commands + // synchronous to clk_74a + wire status_boot_done = pll_core_locked; + wire status_setup_done = pll_core_locked; // rising edge triggers a target command + wire status_running = reset_n; // we are running as soon as reset_n goes high + + wire dataslot_requestread; + wire [15:0] dataslot_requestread_id; + wire dataslot_requestread_ack = 1; + wire dataslot_requestread_ok = 1; + + wire dataslot_requestwrite; + wire [15:0] dataslot_requestwrite_id; + wire dataslot_requestwrite_ack = 1; + wire dataslot_requestwrite_ok = 1; + + wire dataslot_allcomplete; + + wire savestate_supported; + wire [31:0] savestate_addr; + wire [31:0] savestate_size; + wire [31:0] savestate_maxloadsize; + + wire savestate_start; + wire savestate_start_ack; + wire savestate_start_busy; + wire savestate_start_ok; + wire savestate_start_err; + + wire savestate_load; + wire savestate_load_ack; + wire savestate_load_busy; + wire savestate_load_ok; + wire savestate_load_err; + + wire osnotify_inmenu; + // bridge target commands + // synchronous to clk_74a + + + // bridge data slot access + + wire [9:0] datatable_addr; + wire datatable_wren; + wire [31:0] datatable_data; + wire [31:0] datatable_q; + + core_bridge_cmd + icb ( + + .clk ( clk_74a ), + .reset_n ( reset_n ), + + .bridge_endian_little ( bridge_endian_little ), + .bridge_addr ( bridge_addr ), + .bridge_rd ( bridge_rd ), + .bridge_rd_data ( cmd_bridge_rd_data ), + .bridge_wr ( bridge_wr ), + .bridge_wr_data ( bridge_wr_data ), + + .status_boot_done ( status_boot_done ), + .status_setup_done ( status_setup_done ), + .status_running ( status_running ), + + .dataslot_requestread ( dataslot_requestread ), + .dataslot_requestread_id ( dataslot_requestread_id ), + .dataslot_requestread_ack ( dataslot_requestread_ack ), + .dataslot_requestread_ok ( dataslot_requestread_ok ), + + .dataslot_requestwrite ( dataslot_requestwrite ), + .dataslot_requestwrite_id ( dataslot_requestwrite_id ), + .dataslot_requestwrite_ack ( dataslot_requestwrite_ack ), + .dataslot_requestwrite_ok ( dataslot_requestwrite_ok ), + + .dataslot_allcomplete ( dataslot_allcomplete ), + + .savestate_supported ( savestate_supported ), + .savestate_addr ( savestate_addr ), + .savestate_size ( savestate_size ), + .savestate_maxloadsize ( savestate_maxloadsize ), + + .savestate_start ( savestate_start ), + .savestate_start_ack ( savestate_start_ack ), + .savestate_start_busy ( savestate_start_busy ), + .savestate_start_ok ( savestate_start_ok ), + .savestate_start_err ( savestate_start_err ), + + .savestate_load ( savestate_load ), + .savestate_load_ack ( savestate_load_ack ), + .savestate_load_busy ( savestate_load_busy ), + .savestate_load_ok ( savestate_load_ok ), + .savestate_load_err ( savestate_load_err ), + + .osnotify_inmenu ( osnotify_inmenu ), + + .datatable_addr ( datatable_addr ), + .datatable_wren ( datatable_wren ), + .datatable_data ( datatable_data ), + .datatable_q ( datatable_q ), + + ); + + //////////////////////////////////////////////////////////////////////////////////////// + + // + // Dig Dug IP Core + // + reg core_reset = 1; + reg core_reset_reg = 1; + wire core_reset_s; + + reg [31:0] reset_timer; + reg [31:0] bridge_addr_reg; + + reg service_mode_enable = 0; + reg temp_reset; + wire service_mode_enable_s; + reg [31:0] bridge_read_buffer; //! Buffer for the next read request + + always @(posedge clk_74a) begin + temp_reset <= 0; //! Always default this to zero + if(bridge_wr && bridge_addr == 32'h10000000) begin + temp_reset <= 1; //! Give the timer a tickle + end + if(bridge_wr && bridge_addr == 32'h10010000) begin + service_mode_enable <= bridge_wr_data[0]; + temp_reset <= 1; //! Give the timer a tickle + end + if(bridge_rd) begin //! Introduce a delay to the read as it is the second read that confirms this data. + casex(bridge_addr) + 32'h10000000: begin + bridge_read_buffer <= core_reset_reg; + end + 32'h10010000: begin + bridge_read_buffer <= service_mode_enable; + end + endcase + end + end + + always @(posedge clk_74a) begin + if(temp_reset) begin + reset_timer <= 32'd8000; + core_reset <= 0; + end + else begin + if (reset_timer == 32'h0) begin + core_reset <= 1; + end + else begin + reset_timer <= reset_timer - 1; + core_reset <= 0; + end + end + end + + synch_3 s4(core_reset, core_reset_s, clk_sys); + synch_3 s2(service_mode_enable, service_mode_enable_s, clk_sys); + + //! @DSW + //! SW1 + wire [1:0] COIA = 2'b00; //! 1 Coin/1 Credit* + wire FRZE = 1'b1; //! Freeze Off + wire DSND = 1'b0; //! Demo Sounds On + wire CONT = 1'b0; //! Allow Continue Yes + wire CABI = 1'b1; //! Cabinet Upright + wire [1:0] DIFC = 2'b00; //! Difficulty Easy + //! SW0 + wire [1:0] LIFE = 2'b01; //! Lives + wire [2:0] EXMD = 3'b011; //! Bonus Life + wire [2:0] COIB = 3'b001; //! 1coin/1credit + //! @end + + + //! @Data I/O + wire ioctl_wr; + wire [24:0] ioctl_addr; + wire [7:0] ioctl_dout; + + data_loader # + ( + .ADDRESS_SIZE(15) + ) + data_loader_dut ( + .clk_74a ( clk_74a ), + .clk_memory ( clk_sys ), + + .bridge_wr ( bridge_wr ), + .bridge_endian_little ( bridge_endian_little ), + .bridge_addr ( bridge_addr ), + .bridge_wr_data ( bridge_wr_data ), + + .write_en ( ioctl_wr ), + .write_addr ( ioctl_addr ), + .write_data ( ioctl_dout ) + ); + //! @end + + //////////////////////////////////////////////////////////////////////////////////////// + + wire [8:0] digdug_hpos; //! Horizontal Position + wire [8:0] digdug_vpos; //! Vertical Position + wire digdug_hs; //! Horizontal Sync + wire digdug_vs; //! Vertical Sync + wire [7:0] digdug_rgb; //! RGB 332 (8-bit Color) + wire digdug_hb; //! Horizontal Blank + wire digdug_vb; //! Vertical Blank + wire digdug_de; //! Data Enable + wire [7:0] digdug_sound; //! Core Audio + + //! @Gamepad + wire core_pause; + wire p1_coin; + wire p1_start, p2_start; + wire p1_up, p1_down, p1_left, p1_right; + wire p1_btn_a, p1_btn_b, p1_btn_x, p1_btn_y; + wire p1_btn_aio = ~(p1_btn_a | p1_btn_b | p1_btn_x | p1_btn_y); + pocket_gamepad + pocket_gamepad_dut ( + .iCLK ( clk_sys ), + .iJOY ( cont1_key ), + .PAD_U ( p1_up ), + .PAD_D ( p1_down ), + .PAD_L ( p1_left ), + .PAD_R ( p1_right ), + .BTN_A ( p1_btn_a ), + .BTN_B ( p1_btn_b ), + .BTN_X ( p1_btn_x ), + .BTN_Y ( p1_btn_y ), + .BTN_L1 ( p2_start ), + .BTN_R1 ( core_pause ), + .BTN_SE ( p1_coin ), + .BTN_ST ( p1_start ), + ); + //! @end + + //! @H/V Sync Generator + hvgen + hvgen_dut ( + .iPCLK ( clk_vid ), + .oHPOS ( digdug_hpos ), + .oVPOS ( digdug_vpos ), + .oHBLK ( digdug_hb ), + .oVBLK ( digdug_vb ), + .oHSYN ( digdug_hs ), + .oVSYN ( digdug_vs ), + .oBLKN ( digdug_de ) + ); + //! @end + + //! @Core + wire btn_reset = ~(reset_n && core_reset_s); + + FPGA_DIGDUG + FPGA_DIGDUG_dut( + .RESET ( btn_reset ), + .MCLK ( clk_sys ), + + .INP0 ( { + service_mode_enable_s, //! SERVICE + 1'b0, //! ---- + 1'b0, //! ---- + p1_coin, //! COIN + p2_start, //! START-P2 + p1_start, //! START-P1 + p1_btn_aio, //! FIRE-P2 + p1_btn_aio //! FIRE-P1 + } ), + .INP1 ( { + p1_left, //! LEFT-P2 + p1_down, //! DOWN-P2 + p1_right, //! RIGHT-P2 + p1_up, //! UP-P2 + p1_left, //! LEFT-P1 + p1_down, //! DOWN-P1 + p1_right, //! RIGHT-P1 + p1_up //! UP-P1 + } ), + + .DSW0 ( { LIFE, EXMD, COIB } ), + .DSW1 ( { COIA, FRZE, DSND, CONT, CABI, DIFC } ), + + .PH ( digdug_hpos ), + .PV ( digdug_vpos ), + .iPCLK ( clk_vid ), + .POUT ( digdug_rgb ), + .SOUT ( digdug_sound ), + + .ROMCL ( clk_sys ), + .ROMAD ( ioctl_addr[15:0] ), + .ROMDT ( ioctl_dout ), + .ROMEN ( ioctl_wr ) + ); + //! @end + + //////////////////////////////////////////////////////////////////////////////////////// + + //! @ Video + reg video_de_reg, video_hs_reg, video_vs_reg; + reg [23:0] video_rgb_reg; // R[23:16] G[15:8] B[7:0] + + reg de_prev, hs_prev, vs_prev; + reg [7:0] rgb_prev; + + assign video_de = video_de_reg; + assign video_hs = video_hs_reg; + assign video_vs = video_vs_reg; + assign video_rgb = video_rgb_reg; + + assign video_rgb_clock = clk_vid; + assign video_rgb_clock_90 = clk_vid_90deg; + + always @(posedge clk_vid) begin + video_de_reg <= 0; + video_rgb_reg <= 24'h0; + + if (de_prev) begin + video_de_reg <= 1; + video_rgb_reg <= {rgb_prev[2:0], 5'h0, rgb_prev[5:3], 5'h0, rgb_prev[7:6], 6'h0}; + end + + // Set HSync and VSync to be high for a single cycle on the rising edge of the HSync and VSync coming out of the core + video_hs_reg <= ~hs_prev && digdug_hs; + video_vs_reg <= ~vs_prev && digdug_vs; + hs_prev <= digdug_hs; + vs_prev <= digdug_vs; + de_prev <= digdug_de; + rgb_prev <= digdug_rgb; + end + //! @end + + //////////////////////////////////////////////////////////////////////////////////////// + + //! @Audio + wire [15:0] audio_left = {1'b0, digdug_sound, 7'h0}; + wire [15:0] audio_right = audio_left; + pocket_i2s + i2s ( + .iCLK_74 ( clk_74a ), + + .AUDIO_L ( audio_left ), + .AUDIO_R ( audio_right ), + + .I2S_MCLK ( audio_mclk ), + .I2S_DAC ( audio_dac ), + .I2S_LRCK ( audio_lrck ) + ); + //! @end + + //////////////////////////////////////////////////////////////////////////////////////// + + //! @Clocks + wire clk_sys; //! Core System Clock @ 48Mhz + wire clk_vid; //! Pixel clock: 288x224 @ 6Mhz + wire clk_vid_90deg; //! Pixel clock: 90º Phase Shift + wire pll_core_locked; + + mf_pllbase + mp1 ( + .refclk ( clk_74a ), + .rst ( 0 ), + + .outclk_0 ( clk_sys ), + .outclk_1 ( clk_vid ), + .outclk_2 ( clk_vid_90deg ), + + .locked ( pll_core_locked ) + ); + //! @end + +endmodule diff --git a/target/pocket/mf_pllbase.ppf b/target/pocket/mf_pllbase.ppf new file mode 100644 index 0000000..22e69f8 --- /dev/null +++ b/target/pocket/mf_pllbase.ppf @@ -0,0 +1,15 @@ + + + + + + + + + + + diff --git a/target/pocket/mf_pllbase.qip b/target/pocket/mf_pllbase.qip new file mode 100644 index 0000000..ff96c62 --- /dev/null +++ b/target/pocket/mf_pllbase.qip @@ -0,0 +1,337 @@ +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_TOOL_VERSION "18.0" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_TOOL_ENV "mwpim" +set_global_assignment -library "mf_pllbase" -name MISC_FILE [file join $::quartus(qip_path) "mf_pllbase.cmp"] +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_QSYS_MODE "UNKNOWN" +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_NAME "bWZfcGxsYmFzZQ==" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA=" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_VERSION "MTguMA==" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_NAME "bWZfcGxsYmFzZV8wMDAy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_VERSION "MTguMA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NzQuMjU=::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NzQuMjUgTUh6::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::bm9ybWFs::T3BlcmF0aW9uIE1vZGU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::bm9ybWFs::b3BlcmF0aW9uX21vZGU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mw==::TnVtYmVyIE9mIENsb2Nrcw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mw==::bnVtYmVyX29mX2Nsb2Nrcw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::NDguMA==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::NjQ=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::OTk=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::Ni4w::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::NjQ=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::Nzky::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::Mjc2Ljc0MDY0MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MjAzNDU=::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::Ni4w::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::NjQ=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::Nzky::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::OTAuMA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTMzLjExOTk4OQ==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::NTgxMQ==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::LTQ1LjA=::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MjI1LjAgZGVn::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTMzLjExOTk4OQ==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::NTY0Mg==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MjcwLjA=::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::NDguMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::Ni4wMDAwMDAgTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::Ni4wMDAwMDAgTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::NDE2NjcgcHM=::cGhhc2Vfc2hpZnQy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T2Zm::UExMIEF1dG8gUmVzZXQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::MzIsMzIsNiw1LGZhbHNlLGZhbHNlLGZhbHNlLHRydWUsNSw0LDEsMCxwaF9tdXhfY2xrLGZhbHNlLHRydWUsMzYsMzYsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMzYsMzYsMTksMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDIsMjAsMTIwMDAsNDMyLjAgTUh6LDEsZ2NsayxnbGIsZmJfMSxwaF9tdXhfY2xrLGZhbHNl::UGFyYW1ldGVyIFZhbHVlcw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw=" + +set_global_assignment -library "mf_pllbase" -name VERILOG_FILE [file join $::quartus(qip_path) "mf_pllbase.v"] +set_global_assignment -library "mf_pllbase" -name VERILOG_FILE [file join $::quartus(qip_path) "mf_pllbase/mf_pllbase_0002.v"] +set_global_assignment -library "mf_pllbase" -name QIP_FILE [file join $::quartus(qip_path) "mf_pllbase/mf_pllbase_0002.qip"] + +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_TOOL_VERSION "18.0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_TOOL_ENV "mwpim" diff --git a/target/pocket/mf_pllbase.v b/target/pocket/mf_pllbase.v new file mode 100644 index 0000000..dae679f --- /dev/null +++ b/target/pocket/mf_pllbase.v @@ -0,0 +1,257 @@ +// megafunction wizard: %PLL Intel FPGA IP v18.0% +// GENERATION: XML +// mf_pllbase.v + +// Generated using ACDS version 18.0 614 + +`timescale 1 ps / 1 ps +module mf_pllbase ( + input wire refclk, // refclk.clk + input wire rst, // reset.reset + output wire outclk_0, // outclk0.clk + output wire outclk_1, // outclk1.clk + output wire outclk_2, // outclk2.clk + output wire locked // locked.export + ); + + mf_pllbase_0002 mf_pllbase_inst ( + .refclk (refclk), // refclk.clk + .rst (rst), // reset.reset + .outclk_0 (outclk_0), // outclk0.clk + .outclk_1 (outclk_1), // outclk1.clk + .outclk_2 (outclk_2), // outclk2.clk + .locked (locked) // locked.export + ); + +endmodule +// Retrieval info: +// +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// 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PLL_AUTO_RESET OFF -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" diff --git a/target/pocket/mf_pllbase/mf_pllbase_0002.v b/target/pocket/mf_pllbase/mf_pllbase_0002.v new file mode 100644 index 0000000..67b6ad0 --- /dev/null +++ b/target/pocket/mf_pllbase/mf_pllbase_0002.v @@ -0,0 +1,93 @@ +`timescale 1ns/10ps +module mf_pllbase_0002( + + // interface 'refclk' + input wire refclk, + + // interface 'reset' + input wire rst, + + // interface 'outclk0' + output wire outclk_0, + + // interface 'outclk1' + output wire outclk_1, + + // interface 'outclk2' + output wire outclk_2, + + // interface 'locked' + output wire locked +); + + altera_pll #( + .fractional_vco_multiplier("false"), + .reference_clock_frequency("74.25 MHz"), + .operation_mode("normal"), + .number_of_clocks(3), + .output_clock_frequency0("48.000000 MHz"), + .phase_shift0("0 ps"), + .duty_cycle0(50), + .output_clock_frequency1("6.000000 MHz"), + .phase_shift1("0 ps"), + .duty_cycle1(50), + .output_clock_frequency2("6.000000 MHz"), + .phase_shift2("41667 ps"), + .duty_cycle2(50), + .output_clock_frequency3("0 MHz"), + .phase_shift3("0 ps"), + .duty_cycle3(50), + .output_clock_frequency4("0 MHz"), + .phase_shift4("0 ps"), + .duty_cycle4(50), + .output_clock_frequency5("0 MHz"), + .phase_shift5("0 ps"), + .duty_cycle5(50), + .output_clock_frequency6("0 MHz"), + .phase_shift6("0 ps"), + .duty_cycle6(50), + .output_clock_frequency7("0 MHz"), + .phase_shift7("0 ps"), + .duty_cycle7(50), + .output_clock_frequency8("0 MHz"), + .phase_shift8("0 ps"), + .duty_cycle8(50), + .output_clock_frequency9("0 MHz"), + .phase_shift9("0 ps"), + .duty_cycle9(50), + .output_clock_frequency10("0 MHz"), + .phase_shift10("0 ps"), + .duty_cycle10(50), + .output_clock_frequency11("0 MHz"), + .phase_shift11("0 ps"), + .duty_cycle11(50), + .output_clock_frequency12("0 MHz"), + .phase_shift12("0 ps"), + .duty_cycle12(50), + .output_clock_frequency13("0 MHz"), + .phase_shift13("0 ps"), + .duty_cycle13(50), + .output_clock_frequency14("0 MHz"), + .phase_shift14("0 ps"), + .duty_cycle14(50), + .output_clock_frequency15("0 MHz"), + .phase_shift15("0 ps"), + .duty_cycle15(50), + .output_clock_frequency16("0 MHz"), + .phase_shift16("0 ps"), + .duty_cycle16(50), + .output_clock_frequency17("0 MHz"), + .phase_shift17("0 ps"), + .duty_cycle17(50), + .pll_type("General"), + .pll_subtype("General") + ) altera_pll_i ( + .rst (rst), + .outclk ({outclk_2, outclk_1, outclk_0}), + .locked (locked), + .fboutclk ( ), + .fbclk (1'b0), + .refclk (refclk) + ); +endmodule + diff --git a/target/pocket/pin_ddio_clk.ppf b/target/pocket/pin_ddio_clk.ppf new file mode 100644 index 0000000..7f6c108 --- /dev/null +++ b/target/pocket/pin_ddio_clk.ppf @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/target/pocket/pin_ddio_clk.qip b/target/pocket/pin_ddio_clk.qip new file mode 100644 index 0000000..a79964f --- /dev/null +++ b/target/pocket/pin_ddio_clk.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" +set_global_assignment -name IP_TOOL_VERSION "18.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pin_ddio_clk.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pin_ddio_clk_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pin_ddio_clk.ppf"] diff --git a/target/pocket/pin_ddio_clk.v b/target/pocket/pin_ddio_clk.v new file mode 100644 index 0000000..5885794 --- /dev/null +++ b/target/pocket/pin_ddio_clk.v @@ -0,0 +1,108 @@ +// megafunction wizard: %ALTDDIO_OUT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_OUT + +// ============================================================ +// File Name: pin_ddio_clk.v +// Megafunction Name(s): +// ALTDDIO_OUT +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.1.1 Build 646 04/11/2019 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2019 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details, at +//https://fpgasoftware.intel.com/eula. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pin_ddio_clk ( + datain_h, + datain_l, + outclock, + dataout); + + input [0:0] datain_h; + input [0:0] datain_l; + input outclock; + output [0:0] dataout; + + wire [0:0] sub_wire0; + wire [0:0] dataout = sub_wire0[0:0]; + + altddio_out ALTDDIO_OUT_component ( + .datain_h (datain_h), + .datain_l (datain_l), + .outclock (outclock), + .dataout (sub_wire0), + .aclr (1'b0), + .aset (1'b0), + .oe (1'b1), + .oe_out (), + .outclocken (1'b1), + .sclr (1'b0), + .sset (1'b0)); + defparam + ALTDDIO_OUT_component.extend_oe_disable = "OFF", + ALTDDIO_OUT_component.intended_device_family = "Cyclone V", + ALTDDIO_OUT_component.invert_output = "OFF", + ALTDDIO_OUT_component.lpm_hint = "UNUSED", + ALTDDIO_OUT_component.lpm_type = "altddio_out", + ALTDDIO_OUT_component.oe_reg = "UNREGISTERED", + ALTDDIO_OUT_component.power_up_high = "OFF", + ALTDDIO_OUT_component.width = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" +// Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +// Retrieval info: CONSTANT: WIDTH NUMERIC "1" +// Retrieval info: USED_PORT: datain_h 0 0 1 0 INPUT NODEFVAL "datain_h[0..0]" +// Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 1 0 +// Retrieval info: USED_PORT: datain_l 0 0 1 0 INPUT NODEFVAL "datain_l[0..0]" +// Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 1 0 +// Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]" +// Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0 +// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" +// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk.bsf FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk_inst.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk_bb.v FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk.inc FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk.cmp FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk.ppf TRUE FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/target/pocket/stp1.stp b/target/pocket/stp1.stp new file mode 100644 index 0000000..bc21612 --- /dev/null +++ b/target/pocket/stp1.stp @@ -0,0 +1,1135 @@ + + + + + + + + + + + + + + +
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