diff --git a/kernels/relu/16x16xf64/snitch_stream.xdsl.mlir b/kernels/relu/16x16xf64/snitch_stream.xdsl.mlir
index 1b088f5c..0aff2ef2 100644
--- a/kernels/relu/16x16xf64/snitch_stream.xdsl.mlir
+++ b/kernels/relu/16x16xf64/snitch_stream.xdsl.mlir
@@ -6,7 +6,7 @@ riscv.assembly_section ".text" {
     %Y_moved = riscv.mv %Y : (!riscv.reg<a1>) -> !riscv.reg<>
 
     %zero_int = riscv.get_register : () -> !riscv.reg<zero>
-    %zero_float = riscv.fcvt.d.w %zero_int : (!riscv.reg<zero>) -> !riscv.freg<ft2>
+    %zero_float = riscv.fcvt.d.w %zero_int : (!riscv.reg<zero>) -> !riscv.freg<ft3>
 
     %stride_pattern = "snitch_stream.stride_pattern"() {"ub" = [#int<16>, #int<16>], "strides" = [#int<128>, #int<8>], "dm" = #int<31>} : () -> !snitch_stream.stride_pattern_type
     %X_stream = "snitch_stream.strided_read"(%X_moved, %stride_pattern) {"dm" = #int<0>, "rank" = #int<2>} : (!riscv.reg<>, !snitch_stream.stride_pattern_type) -> !stream.readable<!riscv.freg<ft0>>
@@ -14,7 +14,7 @@ riscv.assembly_section ".text" {
     %count = riscv.li 256 : () -> !riscv.reg<>
     "snitch_stream.generic"(%count, %X_stream, %Y_stream) <{"operandSegmentSizes" = array<i32: 1, 1, 1>}> ({
     ^0(%x : !riscv.freg<ft0>):
-        %res = riscv.fmax.d %x, %zero_float : (!riscv.freg<ft0>, !riscv.freg<ft2>) -> !riscv.freg<ft1>
+        %res = riscv.fmax.d %x, %zero_float : (!riscv.freg<ft0>, !riscv.freg<ft3>) -> !riscv.freg<ft1>
         snitch_stream.yield %res : !riscv.freg<ft1>
     }) : (!riscv.reg<>, !stream.readable<!riscv.freg<ft0>>, !stream.writable<!riscv.freg<ft1>>) -> ()
     riscv_func.return