23 Feb 03:43

0739687

v5.9-rc3 Pre-release

Pre-release

skiboot-5.9-rc3

skiboot v5.9-rc3 was released on Wednesday October 18th 2017. It is the
third release candidate of skiboot 5.9, which will become the new stable
release of skiboot following the 5.8 release, first released August 31st
2017.

skiboot v5.9-rc3 contains all bug fixes as of skiboot-5.4.8 and
skiboot-5.1.21 (the currently maintained stable releases). We do not
currently expect to do any 5.8.x stable releases.

For how the skiboot stable releases work, see stable-rules for details.

The current plan is to cut the final 5.9 by October 20th, with skiboot
5.9 being for all POWER8 and POWER9 platforms in op-build v1.20 (Due
October 18th). This release will be targetted to early POWER9 systems.

Over skiboot-5.9-rc2, we have the following changes:

Improvements to vpd device tree entries

Previously we would miss some properties
Revert "npu2: Add vendor cap for IRQ testing"

This reverts commit 9817c9e which
seems to break setting the PCI dev flag and the link number in the
PCIe vendor specific config space. This leads to the device driver
attempting to re-init the DL when it shouldn't which can cause
HMI's.
hw/imc: Fix IMC Catalog load for DD2.X processors
cpu: Add OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED

Add a new CPU reinit flag, "TM Suspend Disabled", which requests
that CPUs be configured so that TM (Transactional Memory) suspend
mode is disabled.

Currently this always fails, because skiboot has no way to query the
state. A future hostboot change will add a mechanism for skiboot to
determine the status and return an appropriate error code.

Assets 2

23 Feb 03:43

v5.9-rc2

073cbf6

v5.9-rc2 Pre-release

Pre-release

skiboot-5.9-rc2

skiboot v5.9-rc2 was released on Monday October 16th 2017. It is the
second release candidate of skiboot 5.9, which will become the new
stable release of skiboot following the 5.8 release, first released
August 31st 2017.

skiboot v5.9-rc2 contains all bug fixes as of skiboot-5.4.8 and
skiboot-5.1.21 (the currently maintained stable releases). We do not
currently expect to do any 5.8.x stable releases.

For how the skiboot stable releases work, see stable-rules for details.

The current plan is to cut the final 5.9 by October 17th, with skiboot
5.9 being for all POWER8 and POWER9 platforms in op-build v1.20 (Due
October 18th). This release will be targetted to early POWER9 systems.

Over skiboot-5.9-rc1, we have the following changes:

opal-prd: Fix memory leak
hdata/i2c: update the list of known i2c devs

This updates the list of known i2c devices - as of HDAT spec
v10.5e - so that they can be properly identified during the hdat
parsing.
hdata/i2c: log unknown i2c devices

An i2c device is unknown if either the i2c device list is outdated
or the device is marked as unknown (0xFF) in the hdat.

opal/cpu: Mark the core as bad while disabling threads of the core.

If any of the core fails to sync its TB during chipTOD
initialization, all the threads of that core are disabled. But this
does not make linux kernel to ignore the core/cpus. It crashes while
bringing them up with below backtrace: :

[   38.883898] kexec_core: Starting new kernel
cpu 0x0: Vector: 300 (Data Access) at [c0000003f277b730]
    pc: c0000000001b9890: internal_create_group+0x30/0x304
    lr: c0000000001b9880: internal_create_group+0x20/0x304
    sp: c0000003f277b9b0
   msr: 900000000280b033
   dar: 40
 dsisr: 40000000
  current = 0xc0000003f9f41000
  paca    = 0xc00000000fe00000   softe: 0        irq_happened: 0x01
    pid   = 2572, comm = kexec
Linux version 4.13.2-openpower1 (jenkins@p89) (gcc version 6.4.0 (Buildroot 2017.08-00006-g319c6e1)) #1 SMP Wed Sep 20 05:42:11 UTC 2017
enter ? for help
[c0000003f277b9b0] c0000000008a8780 (unreliable)
[c0000003f277ba50] c00000000041c3ac topology_add_dev+0x2c/0x40
[c0000003f277ba70] c00000000006b078 cpuhp_invoke_callback+0x88/0x170
[c0000003f277bac0] c00000000006b22c cpuhp_up_callbacks+0x54/0xb8
[c0000003f277bb10] c00000000006bc68 cpu_up+0x11c/0x168
[c0000003f277bbc0] c00000000002f0e0 default_machine_kexec+0x1fc/0x274
[c0000003f277bc50] c00000000002e2d8 machine_kexec+0x50/0x58
[c0000003f277bc70] c0000000000de4e8 kernel_kexec+0x98/0xb4
[c0000003f277bce0] c00000000008b0f0 SyS_reboot+0x1c8/0x1f4
[c0000003f277be30] c00000000000b118 system_call+0x58/0x6c

hw/imc: pause microcode at boot

IMC nest counters has both in-band (ucode access) and out of band
access to it. Since not all nest counter configurations are
supported by ucode, out of band tools are used to characterize other
configuration.

So it is prefer to pause the nest microcode at boot to aid the nest
out of band tools. If the ucode not paused and OS does not have IMC
driver support, then out to band tools will race with ucode and end
up getting undesirable values. Patch to check and pause the ucode at
boot.

OPAL provides APIs to control IMC counters.
OPAL_IMC_COUNTERS_INIT is used to initialize these counters at
boot. OPAL_IMC_COUNTERS_START and OPAL_IMC_COUNTERS_STOP API
calls should be used to start and pause these IMC engines.
doc/opal-api/opal-imc-counters.rst details the OPAL APIs and their
usage.
xive: Fix VP free block group mode false-positive parameter check

The check to ensure the buddy allocation idx is aligned to its
allocation order was not taking into account the allocation split.
This would result in opal_xive_free_vp_block failures despite
giving the same value as returned by opal_xive_alloc_vp_block.

E.g., starting then stopping 4 KVM guests gives the following
pattern in the host: :
```
opal_xive_alloc_vp_block(5)=0x45000020
opal_xive_alloc_vp_block(5)=0x45000040
opal_xive_alloc_vp_block(5)=0x45000060
opal_xive_alloc_vp_block(5)=0x45000080
opal_xive_free_vp_block(0x45000020)=-1
opal_xive_free_vp_block(0x45000040)=0
opal_xive_free_vp_block(0x45000060)=-1
opal_xive_free_vp_block(0x45000080)=0
```
hw/p8-i2c: Fix deadlock in p9_i2c_bus_owner_change

When debugging a system where Linux was taking soft lockup errors
with two CPUs stuck in OPAL:

CPU0 CPU1

lock
p8_i2c_recover
opal_handle_interrupt
sync_timer
cancel_timer
p9_i2c_bus_o wner_change
occ_p9_inter rupt
xive_source interrupt
opal_handle interrupt

p8_i2c_recover() is a timer, and is stuck trying to take
master->lock. p9_i2c_bus_owner_change() has taken
master->lock, but then is stuck waiting for all timers to
complete. We deadlock.

Fix this by using cancel_timer_async().
FSP/CONSOLE: Limit number of error logging

Commit c8a7535 (FSP/CONSOLE: Workaround for unresponsive ipmi
daemon) added error logging when buffer is full. In some corner
cases kernel may call this function multiple time and we may endup
logging error again and again.

This patch fixes it by generating error log only once.
FSP/CONSOLE: Fix fsp_console_write_buffer_space() call

Kernel calls fsp_console_write_buffer_space() to check console
buffer space availability. If there is enough buffer space to write
data, then kernel will call fsp_console_write() to write actual
data.

In some extreme corner cases (like one explained in commit c8a7535)
console becomes full and this function returns 0 to kernel (or space
available in console buffer < next incoming data size). Kernel
will continue retrying until it gets enough space. So we will start
seeing RCU stalls.

This patch keeps track of previous available space. If previous
space is same as current means not enough space in console buffer to
write incoming data. It may be due to very high console write
operation and slow response from FSP -OR- FSP has stopped processing
data (ex: because of ipmi daemon died). At this point we will start
timer with timeout of SER_BUFFER_OUT_TIMEOUT (10 secs). If
situation is not improved within 10 seconds means something went
bad. Lets return OPAL_RESOURCE so that kernel can drop console
write and continue.

FSP/CONSOLE: Close SOL session during R/R

Presently we are not closing SOL and FW console sessions during R/R.
Host will continue to write to SOL buffer during FSP R/R. If there
is heavy console write operation happening during FSP R/R (like
running top command inside console), then at some point console
buffer becomes full. fsp_console_write_buffer_space() returns 0
(or less than required space to write data) to host. While one
thread is busy writing to console, if some other threads tries to
write data to console we may see RCU stalls (like below) in kernel.
:

[ 2082.828363] INFO: rcu_sched detected stalls on CPUs/tasks: { 32} (detected by 16, t=6002 jiffies, g=23154, c=23153, q=254769)
[ 2082.828365] Task dump for CPU 32:
[ 2082.828368] kworker/32:3    R  running task        0  4637      2 0x00000884
[ 2082.828375] Workqueue: events dump_work_fn
[ 2082.828376] Call Trace:
[ 2082.828382] [c000000f1633fa00] [c00000000013b6b0] console_unlock+0x570/0x600 (unreliable)
[ 2082.828384] [c000000f1633fae0] [c00000000013ba34] vprintk_emit+0x2f4/0x5c0
[ 2082.828389] [c000000f1633fb60] [c00000000099e644] printk+0x84/0x98
[ 2082.828391] [c000000f1633fb90] [c0000000000851a8] dump_work_fn+0x238/0x250
[ 2082.828394] [c000000f1633fc60] [c0000000000ecb98] process_one_work+0x198/0x4b0
[ 2082.828396] [c000000f1633fcf0] [c0000000000ed3dc] worker_thread+0x18c/0x5a0
[ 2082.828399] [c000000f1633fd80] [c0000000000f4650] kthread+0x110/0x130
[ 2082.828403] [c000000f1633fe30] [c000000000009674] ret_from_kernel_thread+0x5c/0x68

Hence lets close SOL (and FW console) during FSP R/R.

FSP/CONSOLE: Do not associate unavailable console

Presently OPAL sends associate/unassociate MBOX command for all FSP
serial console (like below OPAL message). We have to check console
is available or not before sending this message. :
```
[ 5013.227994012,7] FSP: Reassociating HVSI console 1
[ 5013.227997540,7] FSP: Reassociating HVSI console 2
```
FSP: Disable PSI link whenever FSP tells OPAL about impending R/R

Commit 42d5d04 fixed scenario where DPO has been initiated, but FSP
went into reset before the CEC power down came in. But this is
generic issue that can happen in normal shutdown path as well.

Hence disable PSI link as soon as we detect FSP impending R/R.
fsp: return OPAL_BUSY_EVENT on failure sending
FSP_CMD_POWERDOWN_NORM Also, return OPAL_BUSY_EVENT on failure
sending FSP_CMD_REBOOT / DEEP_REBOOT.

We had a race condition between FSP Reset/Reload and powering down
the system from the host:

Roughly:

# FSP Host
---- -------...

Assets 2

23 Feb 03:43

v5.9-rc1

e363cd6

v5.9-rc1 Pre-release

Pre-release

skiboot-5.9-rc1

skiboot v5.9-rc1 was released on Wednesday October 11th 2017. It is the
first release candidate of skiboot 5.9, which will become the new stable
release of skiboot following the 5.8 release, first released August 31st
2017.

skiboot v5.9-rc1 contains all bug fixes as of skiboot-5.4.7 and
skiboot-5.1.21 (the currently maintained stable releases). We do not
currently expect to do any 5.8.x stable releases.

For how the skiboot stable releases work, see stable-rules for details.

Over skiboot-5.8, we have the following changes:

New Features

POWER8

fast-reset by default (if possible)

Currently, this is limited to POWER8 systems.

A normal reboot will, rather than doing a full IPL, go through a
fast reboot procedure. This reduces the "reboot to petitboot" time
from minutes to a handful of seconds.

POWER9

POWER9 power management during boot

Less power should be consumed during boot.
OPAL_SIGNAL_SYSTEM_RESET for POWER9

This implements OPAL_SIGNAL_SYSTEM_RESET, using scom registers to
quiesce the target thread and raise a system reset exception on it.
It has been tested on DD2 with stop0 ESL=0 and ESL=1 shallow power
saving modes.

DD1 is not implemented because it is sufficiently different as to
make support difficult.
Enable deep idle states for POWER9
- SLW: Add support for p9_stop_api
  
  p9_stop_api's are used to set SPR state on a core wakeup form
  a deeper low power state. p9_stop_api uses low level platform
  formware and self-restore microcode to restore the sprs to
  requested values.
  
  Code is taken from :
  https://github.com/open-power/hostboot/tree/master/src/import/chips/p9/procedures/utils/stopreg
- SLW: Removing timebase related flags for stop4
  
  When a core enters stop4, it does not loose decrementer and time
  base. Hence removing flags OPAL_PM_DEC_STOP and
  OPAL_PM_TIMEBASE_STOP.
- SLW: Allow deep states if homer address is known
  
  Use a common variable has_wakeup_engine instead of has_slw to
  tell if the:
  - SLW image is populated in case of power8
  - CME image is populated in case of power9
  Currently we expect CME to be loaded if homer address is known (
  except for simulators)
- SLW: Configure self-restore for HRMOR
  
  Make a stop api call using libpore to restore HRMOR register.
  HRMOR needs to be cleared so that when thread exits stop, they
  arrives at linux system_reset vector (0x100).
- SLW: Add opal_slw_set_reg support for power9
This OPAL call is made from Linux to OPAL to configure values in
various SPRs after wakeup from a deep idle state.
PHB4: CAPP recovery

CAPP recovery is initiated when a CAPP Machine Check is detected.
The capp recovery procedure is initiated via a Hypervisor
Maintenance interrupt (HMI).

CAPP Machine Check may arise from either an error that results in a
PHB freeze or from an internal CAPP error with CAPP checkstop FIR
action. An error that causes a PHB freeze will result in the link
down signal being asserted. The system continues running and the
CAPP and PSL will be re-initialized.

This implements CAPP recovery for POWER9 systems
Add wafer-location property for POWER9

Extract wafer-location from ECID and add property under xscom node.
- bits 64:71 are the chip x location (7:0)
- bits 72:79 are the chip y location (7:0)
Sample output: :
```
[root@wsp xscom@623fc00000000]# lsprop ecid
ecid             019a00d4 03100718 852c0000 00fd7911
[root@wsp xscom@623fc00000000]# lsprop wafer-location
wafer-location   00000085 0000002c
```

Add wafer-id property for POWER9

Wafer id is derived from ECID data.

bits 4:63 are the wafer id ( ten 6 bit fields each containing a
code)

Sample output: :

[root@wsp xscom@623fc00000000]# lsprop ecid
ecid             019a00d4 03100718 852c0000 00fd7911
[root@wsp xscom@623fc00000000]# lsprop wafer-id
wafer-id         "6Q0DG340SO"

Add ecid property under xscom node for POWER9. Sample output: :

[root@wsp xscom@623fc00000000]# lsprop ecid
ecid             019a00d4 03100718 852c0000 00fd7911

Add ibm,firmware-versions device tree node

In P8, hostboot provides mini device tree. It contains
/ibm,firmware-versions node which has various firmware component
version details.

In P9, OPAL is building device tree. This patch adds support to
parse VERSION section of PNOR and create /ibm,firmware-versions
device tree node.

Sample output: :
```
/sys/firmware/devicetree/base/ibm,firmware-versions # lsprop .
occ              "6a00709"
skiboot          "v5.7-rc1-p344fb62"
buildroot        "2017.02.2-7-g23118ce"
capp-ucode       "9c73e9f"
petitboot        "v1.4.3-p98b6d83"
sbe              "02021c6"
open-power       "witherspoon-v1.17-128-gf1b53c7-dirty"
....
....
```

POWER9

Disable Transactional Memory on Power9 DD 2.1

Update pa_features_p9[] to disable TM (Transactional Memory). On
DD 2.1 TM is not usable by Linux without other workarounds, so
skiboot must disable it.
xscom: Do not print error message for 'chiplet offline' return
values

xscom_read/write operations returns CHIPLET_OFFLINE when chiplet
is offline. Some multicast xscom_read/write requests from HBRT
results in xscom operation on offline chiplet(s) and printing below
warnings in OPAL console: :
```
[ 135.036327572,3] XSCOM: Read failed, ret = -14
[ 135.092689829,3] XSCOM: Read failed, ret = -14
```
Some SCOM users can deal correctly with this error code (notably
opal-prd), so the error message is (in practice) erroneous.
IMC: Fix the core_imc_event_mask

CORE_IMC_EVENT_MASK is a scom that contains bits to control event
sampling for different machine state for core imc. The current
event-mask setting sample events only on host kernel (hypervisor)
and host userspace.

Patch to enable the sampling of events in other machine states (like
guest kernel and guest userspace).
IMC: Update the nest_pmus array with occ/gpe microcode uav updates

OOC/gpe nest microcode maintains the list of individual nest units
supported. Sync the recent updates to the UAV with nest_pmus array.

For reference occ/gpr microcode link for the UAV:
https://github.com/open-power/occ/blob/master/src/occ_gpe1/gpe1_24x7.h
Parse IOSLOT information from HDAT

Add structure definitions that describe the physical PCIe topology
of a system and parse them into the device-tree based PCIe slot
description.
idle: user context state loss flags fix for stop states

The "lite" stop variants with PSSCR[ESL]=PSSCR[EC]=1 do not lose
user context, while the non-lite variants do (ESL: enable state
loss).

Some of the POWER9 idle states had these wrong.

CAPI

POWER9 DD2 update

The CAPI initialization sequence has been updated in DD2. This patch
adapts to the changes, retaining compatibility with DD1. The patch
includes some changes to DD1 fix-ups as well.
Load CAPP microcode for POWER9 DD2.0 and DD2.1
capi: Mask Psl Credit timeout error for POWER9

Mask the PSL credit timeout error in CAPP FIR Mask register bit(46).
As per the h/w team this error is now deprecated and shouldn't cause
any fir-action for P9.

NVLINK2

A notabale change is that we now generate the device tree description of
NVLINK based on the HDAT we get from hostboot. Since Hostboot will
generate HDAT based on VPD, you now MUST have correct VPD programmed
or we will default to a Sequoia layout, which will lead to random
problems if you are not booting a Sequoia Witherspoon planar. In the
case of booting with old VPD and/or Hostboot, we print a giant scary
warning in order to scare you.

npu2: Read slot label from the HDAT link node

Binding GPU to emulated NPU PCI devices is done using the slot
labels since the NPU devices do not have a patching slot node we
need to copy the label in here.
npu2: Copy link speed from the npu HDAT node

This needs to be in the PCI device node so the speed of the NVLink
can be passed to the GPU driver.
npu2: hw-procedures: Add settings to PHY_RESET

Set a few new values in the PHY_RESET procedure, as specified by
our updated programming guide documentation.
Parse NVLink information from HDAT

Add the per-chip structures that descibe how the
A-Bus/NVLink/OpenCAPI phy is configured. This generates the
npu@xyz nodes for each chip on systems that support it.
npu2: Add vendor cap for IRQ testing

Provide a way to test recoverable data link interrupts via a new
vendor capability byte.
npu2: Enable recoverable data link (no-stall) interrupts

Allow the NPU2 to trigger "recoverable data link" interrupts.
npu2: Implement basic FLR (Function Level Reset)
npu2: hw-procedures: Update PHY DC calibration procedure
npu2: hw-procedures: Change rx_pr_phase_step value

XIVE

xive: Fix opal_xive_dump_tm() to access W2 properly. The HW only
supported limited access sizes....

Assets 2

23 Feb 03:44

skiboot-5.4.8

43290f9

skiboot-5.4.8

skiboot-5.4.8 was released on Wednesday October 11th, 2017. It replaces
skiboot-5.4.7 as the current stable release in the 5.4.x series.

Over skiboot-5.4.7, we have a few bug fixes for FSP platforms:

libflash/file: Handle short read()s and write()s correctly

Currently we don't move the buffer along for a short read() or
write() and nor do we request only the remaining amount.
FSP/NVRAM: Handle "get vNVRAM statistics" command

FSP sends MBOX command (cmd : 0xEB, subcmd : 0x05, mod : 0x00) to
get vNVRAM statistics. OPAL doesn't maintain any such statistics.
Hence return FSP_STATUS_INVALID_SUBCMD.
Sample OPAL log: :
```
[16944.384670488,3] FSP: Unhandled message eb0500
[16944.474110465,3] FSP: Unhandled message eb0500
[16945.111280784,3] FSP: Unhandled message eb0500
[16945.293393485,3] FSP: Unhandled message eb0500
```
FSP/CONSOLE: Limit number of error logging

Commit c8a7535 (FSP/CONSOLE: Workaround for unresponsive ipmi
daemon, added in skiboot 5.4.6 and 5.7-rc1) added error logging when
buffer is full. In some corner cases kernel may call this function
multiple time and we may endup logging error again and again.

This patch fixes it by generating error log only once.
FSP/CONSOLE: Fix fsp_console_write_buffer_space() call

Kernel calls fsp_console_write_buffer_space() to check console
buffer space availability. If there is enough buffer space to write
data, then kernel will call fsp_console_write() to write actual
data.

In some extreme corner cases (like one explained in commit c8a7535)
console becomes full and this function returns 0 to kernel (or space
available in console buffer < next incoming data size). Kernel
will continue retrying until it gets enough space. So we will start
seeing RCU stalls.

This patch keeps track of previous available space. If previous
space is same as current means not enough space in console buffer to
write incoming data. It may be due to very high console write
operation and slow response from FSP -OR- FSP has stopped processing
data (ex: because of ipmi daemon died). At this point we will start
timer with timeout of SER_BUFFER_OUT_TIMEOUT (10 secs). If
situation is not improved within 10 seconds means something went
bad. Lets return OPAL_RESOURCE so that kernel can drop console
write and continue.

FSP/CONSOLE: Close SOL session during R/R

kernel call trace: :

[ 2082.828363] INFO: rcu_sched detected stalls on CPUs/tasks: { 32} (detected by 16, t=6002 jiffies, g=23154, c=23153, q=254769)
[ 2082.828365] Task dump for CPU 32:
[ 2082.828368] kworker/32:3    R  running task        0  4637      2 0x00000884
[ 2082.828375] Workqueue: events dump_work_fn
[ 2082.828376] Call Trace:
[ 2082.828382] [c000000f1633fa00] [c00000000013b6b0] console_unlock+0x570/0x600 (unreliable)
[ 2082.828384] [c000000f1633fae0] [c00000000013ba34] vprintk_emit+0x2f4/0x5c0
[ 2082.828389] [c000000f1633fb60] [c00000000099e644] printk+0x84/0x98
[ 2082.828391] [c000000f1633fb90] [c0000000000851a8] dump_work_fn+0x238/0x250
[ 2082.828394] [c000000f1633fc60] [c0000000000ecb98] process_one_work+0x198/0x4b0
[ 2082.828396] [c000000f1633fcf0] [c0000000000ed3dc] worker_thread+0x18c/0x5a0
[ 2082.828399] [c000000f1633fd80] [c0000000000f4650] kthread+0x110/0x130
[ 2082.828403] [c000000f1633fe30] [c000000000009674] ret_from_kernel_thread+0x5c/0x68

Hence lets close SOL (and FW console) during FSP R/R.

FSP/CONSOLE: Do not associate unavailable console

Presently OPAL sends associate/unassociate MBOX command for all FSP
serial console (like below OPAL message). We have to check console
is available or not before sending this message.

OPAL log: :
```
[ 5013.227994012,7] FSP: Reassociating HVSI console 1
[ 5013.227997540,7] FSP: Reassociating HVSI console 2
```
FSP: Disable PSI link whenever FSP tells OPAL about impending
Reset/Reload

Commit 42d5d04 fixed scenario where DPO has been initiated, but FSP
went into reset before the CEC power down came in. But this is
generic issue that can happen in normal shutdown path as well.

Hence disable PSI link as soon as we detect FSP impending R/R.
fsp: return OPAL_BUSY_EVENT on failure sending
FSP_CMD_POWERDOWN_NORM Also, return OPAL_BUSY_EVENT on failure
sending FSP_CMD_REBOOT / DEEP_REBOOT.

We had a race condition between FSP Reset/Reload and powering down
the system from the host:

Roughly:

# FSP Host

1 Power on
2 Power on
3 (inject EPOW)
4 (trigger FSP R/R)
5 Processes EPOW event, starts shutting down
6 calls OPAL_CEC_POWER_DOWN
7 (is still in R/R)
8 gets OPAL_INTERNAL_ERROR, spins in opal_poll_events
9 (FSP comes back)
10 spinning in opal_poll_events
11 (thinks host is running)

The call to OPAL_CEC_POWER_DOWN is only made once as the
reset/reload error path for fsp_sync_msg() is to return -1, which
means we give the OS OPAL_INTERNAL_ERROR, which is fine, except
that our own API docs give us the opportunity to return OPAL_BUSY
when trying again later may be successful, and we're ambiguous as to
if you should retry on OPAL_INTERNAL_ERROR.

For reference, the linux code looks like this: :
```
static void __noreturn pnv_power_off(void)
{
        long rc = OPAL_BUSY;

        pnv_prepare_going_down();

        while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
                rc = opal_cec_power_down(0);
                if (rc == OPAL_BUSY_EVENT)
                        opal_poll_events(NULL);
                else
                        mdelay(10);
        }
        for (;;)
                opal_poll_events(NULL);
}
```
Which means that practically our only option is to return
OPAL_BUSY or OPAL_BUSY_EVENT.

We choose OPAL_BUSY_EVENT for FSP systems as we do want to ensure
we're running pollers to communicate with the FSP and do the final
bits of Reset/Reload handling before we power off the system.

Assets 2

19 Sep 06:49

skiboot-5.4.7

17661be

skiboot-5.4.7

skiboot-5.4.7 was released on Tuesday September 19th, 2017. It
replaces skiboot-5.4.6 as the current stable release in the 5.4.x
series.

Over skiboot-5.4.6, we have two backported bug fixes for FSP
platforms:

FSP: Add check to detect FSP Reset/Reload inside fsp_sync_msg()

During FSP Reset/Reload we move outstanding MBOX messages from msgq
to rr_queue including inflight message (fsp_reset_cmdclass()). But
we are not resetting inflight message state.

In extreme corner case where we sent message to FSP via
fsp_sync_msg() path and FSP Reset/Reload happens before getting
respose from FSP, then we will endup waiting in fsp_sync_msg() until
everything becomes normal.

This patch adds fsp_in_rr() check to fsp_sync_msg() and return error
to caller if FSP is in R/R.
platforms/ibm-fsp/firenze: Fix PCI slot power-off pattern

When powering off the PCI slot, the corresponding bits should be set
to 0bxx00xx00 instead of 0bxx11xx11. Otherwise, the specified PCI
slot can’t be put into power-off state. Fortunately, it didn’t
introduce any side-effects so far.

Assets 2

19 Sep 06:49

skiboot-5.1.21

7d64a8b

skiboot 5.1.21

skiboot-5.1.21 was released on Tuesday 19th September 2017.

skiboot-5.1.21 is the 22nd stable release of 5.1, it follows skiboot-5.1.20
(which was released 18th August 2017).

This release contains one backported bug fix to the 5.1.x series.

Changes are:

FSP: Add check to detect FSP Reset/Reload inside fsp_sync_msg()

During FSP Reset/Reload we move outstanding MBOX messages from msgq to
rr_queue including inflight message (fsp_reset_cmdclass()). But we are not
resetting inflight message state.

In extreme corner case where we sent message to FSP via fsp_sync_msg() path
and FSP Reset/Reload happens before getting respose from FSP, then we will
endup waiting in fsp_sync_msg() until everything becomes normal.

This patch adds fsp_in_rr() check to fsp_sync_msg() and return error to
caller
if FSP is in R/R.

Assets 2

31 Aug 04:18

v5.8

2047010

v5.8

skiboot-5.8

skiboot v5.8 was released on Tuesday August 31st 2017. It is the first
release of skiboot 5.8, which becomes the new stable release. It follows
the 5.7 release, first released 25th July 2017.

skiboot v5.8 contains all bug fixes as of skiboot-5.4.6 and
skiboot-5.1.20 (the currently maintained stable releases). We do not
currently expect to do any 5.7.x stable releases.

For how the skiboot stable releases work, see stable-rules for details.

Over skiboot-5.7, we have the following changes:

New Features

sensors: occ: Add support to clear sensor groups

Adds a generic API to clear sensor groups. OCC inband sensor groups
such as CSM, Profiler and Job Scheduler can be cleared using this
API. It will clear the min/max of all sensors belonging to OCC
sensor groups.
sensors: occ: Add CSM{min/max} sensors

HWMON's lowest/highest attribute is used by CSM agent, so map
min/max device-tree properties "sensor-data-min" and
"sensor-data-max" to the min/max of CSM.
sensors: occ: Add support for OCC inband sensors

Add support to parse and export OCC inband sensors which are copied
by OCC to main memory in P9. Each OCC writes three buffers which
includes one names buffer for sensor meta data and two buffers for
sensor readings. While OCC writes to one buffer the sensor values
can be read from the other buffer. The sensors are updated every
100ms.

This patch adds power, temperature, current and voltage sensors to
/ibm,opal/sensors device-tree node which can be exported by the
ibmpowernv-hwmon driver in Linux.
psr: occ: Add support to change power-shifting-ratio

Add support to set the CPU-GPU power shifting ratio which is used by
the OCC power capping algorithm. PSR value of 100 takes all power
away from CPU first and a PSR value of 0 caps GPU first.
powercap: occ: Add a generic powercap framework

This patch adds a generic powercap framework and exports OCC
powercap sensors using which system powercap can be set inband
through OPAL-OCC command-response interface.
phb4: Enable PCI peer-to-peer

P9 supports PCI peer-to-peer: a PCI device can write directly to the
mmio space of another PCI device. It completely by-passes the CPU.

It requires some configuration on the PHBs involved:
1. on the initiating side, the address for the read/write operation
  is in the mmio space of the target, i.e. well outside the range
  normally allowed. So we disable range-checking on the TVT entry
  in bypass mode.
2. on the target side, we need to explicitly enable p2p by setting
  a bit in a configuration register. It has the side-effect of
  reserving an outbound (as seen from the CPU) store queue for
  p2p. Therefore we only enable p2p on the PHBs using it, as we
  don't want to waste the resource if we don't have to.
P9 supports p2p mmio writes. Reads are currently only supported if
the two devices are under the same PHB but that is expected to
change in the future, and it raises questions about intermediate
switches configuration, so we report an error for the time being.

The patch adds a new OPAL call to allow the OS to declare a p2p
(initiator, target) pair.
NX 842 and GZIP support on POWER9

POWER9 DD2

Further support for POWER9 DD2 revision chips. Notable changes include:

xscom: Grab P9 DD2 revision level
vas: Set mmio enable bits in DD2

POWER9 DD2 added some new "enable" bits that must be set for VAS to
work. These bits were unused in DD1.
hdat: Add POWER9 DD2.0 specific pa_features

Same as the default but with TM off.

POWER9

Since skiboot-5.8-rc1:

hw/npu2.c: Add ibm,nvlink-speed device-tree property

NVLink2 links can support multiple different speeds. However the
device driver has no way of determining which speed was programmed
so pass it down as a device tree property.
hw/npu2-hw-procedures.c: Update PHY_RESET procedure

Newer versions of Hostboot will have various clocks powered down by
default to save power. Therefore we need to power them up before
accessing the OBUS PHY.
p8-i2c: Fix random data corruption (POWER9 specific) While waiting
for the OCC to signal that it has finished using the I2C master we
put the master into the, poorly named, occache_dis state. While in
this state the transaction hasn't been started, but
p8_i2c_check_status() will only skip it's checks when the master
is in the idle state. Any action that checks that cranks the I2C
state machine (interrupt, poll, etc) will call
p8_i2c_check_status() and since the master is not idle, it will
check the status register, see the transaction complete flag set and
complete the i2c request without actually doing anything.

If the transaction was a I2C read, the resulting output will be a
zeroed data buffer.
hw/p8-i2c: Fix OCC locking (POWER9 specific)

There's a few issues with the Host<->OCC I2C bus handshaking.
First up, skiboot is currently examining the wrong bit when checking
if the OCC is currently using the bus. Secondly, when we need to
wait for the OCC to release the bus we are scheduling a recovery
timer to run zero timebase ticks after the current moment so the
recovery timeout handler will run immediately after the bus was
requested, which will in turn re-schedule itself, etc, etc. There's
also a race between the OCC interrupt and the recovery handler which
can result in an assertion failure in the recovery thread. All of
this is bad.

This patch addresses all these issues and sets the recovery timeout
to 10ms.
vas: export chip-id to vas platform device This is needed so VAS in
the kernel can perform cpu to vas id mapping.
slw: Modify the power9 stop0_lite latency & residency

Currently skiboot exposes the exit-latency for stop0_lite as 200ns
and the target-residency to be 2us.

However, the kernel cpu-idle infrastructure rounds up the latency to
microseconds and lists the stop0_lite latency as 0us, putting it on
par with snooze state. As a result, when the predicted latency is
small (< 1us), cpuidle will select stop0_lite instead of snooze.
The difference between these states is that snooze doesn't require
an interrupt to exit from the state, but stop0_lite does. And the
value 200ns doesn't include the interrupt latency.

This shows up in the context_switch2 benchmark
(http://ozlabs.org/~anton/junkcode/context_switch2.c) where the
number of context switches per second with the stop0_lite disabled
is found to be roughly 30% more than with stop0_lite enabled. This
can be correlated with the number of times cpuidle enters
stop0_lite compared to snooze.

Hence, bump up the exit latency of stop0_lite to 1us. Since the
target residency is chosen to be 10 times the exit latency, set the
target residency to 10us.

With these values, we see a 50% improvement in the number of context
switches.

Since skiboot-5.7:

Base NPU2 support on POWER9 DD2
hdata/i2c: Work around broken I2C array version

Work around a bug in the I2C devices array that shows the array
version as being v2 when only the v1 data is populated.
Recognize the 2s2u zz platform

OPAL currently doesn't know about the 2s2u zz. It recognizes such a
box as a generic BMC machine and fails to boot. Add the 2s2u as a
supported platform.

There will subsequently be a 2s2u-L system which may have a
different compatible property, which will need to be handled later.
hdata/spira: POWER9 NX isn't software compatible with P7/P8 NX,
don't claim so
NX: Add P9 NX support for gzip compression engine

Power 9 introduces NX gzip compression engine. This patch adds gzip
compression support in NX. Virtual Accelerator Switch (VAS) is used
to access NX gzip engine and the channel configuration will be done
with the receive FIFO. So RxFIFO address, logical partition ID
(lpid), process ID (pid) and thread ID (tid) are used to configure
RxFIFO. P9 NX supports high and normal priority FIFOS. Skiboot
configures User Mode Access Control (UMAC) noitify match register
with these values and also enables other registers to enable /
disable the engine.

Creates the following device-tree entries to provide RxFIFO address,
RxFIFO size, Fifo priority, lpid, pid and tid values so that kernel
can drive P9 NX gzip engine.

The following nodes are located under an xscom node: ::

: /xscom@<xscom_addr>/nx@<nx_addr>
```
/ibm,gzip-high-fifo : High priority gzip RxFIFO
/ibm,gzip-normal-fifo : Normal priority gzip RxFIFO
```
Each RxFIFO node contain:s

compatible

: ibm,p9-nx-gzip

priority

: High or Normal

rx-fifo-address

: RxFIFO address

rx-fifo-size

: RxFIFO size

lpid

: 0xfff (1's for 12 bits in UMAC notify match register)

pid

: gzip coprocessor type

tid

: counter for gzip
NX: Add P9 NX support for 842 compression engine

This patch adds changes needed for 842 compression engine on power
9. Virtual Accelerator Switch (VAS) is used to access NX 842 engine
on P9 and the channel setup will be done with receive FIFO. So
RxFIFO address, logical partition ID (lpid), process ID (pid) and
thread ID ...

Assets 2

24 Aug 02:49

v5.8-rc1

d9715bb

v5.8-rc1 Pre-release

Pre-release

skiboot-5.8-rc1

skiboot v5.8-rc1 was released on Tuesday August 22nd 2017. It is the
first release candidate of skiboot 5.8, which will become the new stable
release of skiboot following the 5.7 release, first released 25th July
2017.

skiboot v5.8-rc1 contains all bug fixes as of skiboot-5.4.6 and
skiboot-5.1.20 (the currently maintained stable releases). We do not
currently expect to do any 5.7.x stable releases.

For how the skiboot stable releases work, see stable-rules for details.

The current plan is to cut the final 5.8 by August 25th, with skiboot
5.8 being for all POWER8 and POWER9 platforms in op-build v1.19 (Due
August 25th). This is a short cycle as this release is mainly targetted
towards POWER9 bringup efforts.

Over skiboot-5.7, we have the following changes:

New Features

sensors: occ: Add support to clear sensor groups

Adds a generic API to clear sensor groups. OCC inband sensor groups
such as CSM, Profiler and Job Scheduler can be cleared using this
API. It will clear the min/max of all sensors belonging to OCC
sensor groups.
sensors: occ: Add CSM{min/max} sensors

HWMON's lowest/highest attribute is used by CSM agent, so map
min/max device-tree properties "sensor-data-min" and
"sensor-data-max" to the min/max of CSM.
sensors: occ: Add support for OCC inband sensors

Add support to parse and export OCC inband sensors which are copied
by OCC to main memory in P9. Each OCC writes three buffers which
includes one names buffer for sensor meta data and two buffers for
sensor readings. While OCC writes to one buffer the sensor values
can be read from the other buffer. The sensors are updated every
100ms.

This patch adds power, temperature, current and voltage sensors to
/ibm,opal/sensors device-tree node which can be exported by the
ibmpowernv-hwmon driver in Linux.
psr: occ: Add support to change power-shifting-ratio

Add support to set the CPU-GPU power shifting ratio which is used by
the OCC power capping algorithm. PSR value of 100 takes all power
away from CPU first and a PSR value of 0 caps GPU first.
powercap: occ: Add a generic powercap framework

This patch adds a generic powercap framework and exports OCC
powercap sensors using which system powercap can be set inband
through OPAL-OCC command-response interface.
phb4: Enable PCI peer-to-peer

P9 supports PCI peer-to-peer: a PCI device can write directly to the
mmio space of another PCI device. It completely by-passes the CPU.

It requires some configuration on the PHBs involved:
1. on the initiating side, the address for the read/write operation
  is in the mmio space of the target, i.e. well outside the range
  normally allowed. So we disable range-checking on the TVT entry
  in bypass mode.
2. on the target side, we need to explicitly enable p2p by setting
  a bit in a configuration register. It has the side-effect of
  reserving an outbound (as seen from the CPU) store queue for
  p2p. Therefore we only enable p2p on the PHBs using it, as we
  don't want to waste the resource if we don't have to.
P9 supports p2p mmio writes. Reads are currently only supported if
the two devices are under the same PHB but that is expected to
change in the future, and it raises questions about intermediate
switches configuration, so we report an error for the time being.

The patch adds a new OPAL call to allow the OS to declare a p2p
(initiator, target) pair.
NX 842 and GZIP support on POWER9

POWER9 DD2

Further support for POWER9 DD2 revision chips. Notable changes include:

xscom: Grab P9 DD2 revision level
vas: Set mmio enable bits in DD2

POWER9 DD2 added some new "enable" bits that must be set for VAS to
work. These bits were unused in DD1.
hdat: Add POWER9 DD2.0 specific pa_features

Same as the default but with TM off.

POWER9

Base NPU2 support on POWER9 DD2
hdata/i2c: Work around broken I2C array version

Work around a bug in the I2C devices array that shows the array
version as being v2 when only the v1 data is populated.
Recognize the 2s2u zz platform

OPAL currently doesn't know about the 2s2u zz. It recognizes such a
box as a generic BMC machine and fails to boot. Add the 2s2u as a
supported platform.

There will subsequently be a 2s2u-L system which may have a
different compatible property, which will need to be handled later.
hdata/spira: POWER9 NX isn't software compatible with P7/P8 NX,
don't claim so
NX: Add P9 NX support for gzip compression engine

Power 9 introduces NX gzip compression engine. This patch adds gzip
compression support in NX. Virtual Accelerator Switch (VAS) is used
to access NX gzip engine and the channel configuration will be done
with the receive FIFO. So RxFIFO address, logical partition ID
(lpid), process ID (pid) and thread ID (tid) are used to configure
RxFIFO. P9 NX supports high and normal priority FIFOS. Skiboot
configures User Mode Access Control (UMAC) noitify match register
with these values and also enables other registers to enable /
disable the engine.

Creates the following device-tree entries to provide RxFIFO address,
RxFIFO size, Fifo priority, lpid, pid and tid values so that kernel
can drive P9 NX gzip engine.

The following nodes are located under an xscom node: ::

: /xscom@<xscom_addr>/nx@<nx_addr>
```
/ibm,gzip-high-fifo : High priority gzip RxFIFO
/ibm,gzip-normal-fifo : Normal priority gzip RxFIFO
```
Each RxFIFO node contain:s

compatible

: ibm,p9-nx-gzip

priority

: High or Normal

rx-fifo-address

: RxFIFO address

rx-fifo-size

: RxFIFO size

lpid

: 0xfff (1's for 12 bits in UMAC notify match register)

pid

: gzip coprocessor type

tid

: counter for gzip
NX: Add P9 NX support for 842 compression engine

This patch adds changes needed for 842 compression engine on power
9. Virtual Accelerator Switch (VAS) is used to access NX 842 engine
on P9 and the channel setup will be done with receive FIFO. So
RxFIFO address, logical partition ID (lpid), process ID (pid) and
thread ID (tid) are used for this setup. p9 NX supports high and
normal priority FIFOs. skiboot is not involved to process data with
842 engine, but configures User Mode Access Control (UMAC) noitify
match register with these values and export them to kernel with
device-tree entries.

Also configure registers to setup and enable / disable the engine
with the appropriate registers. Creates the following device-tree
entries to provide RxFIFO address, RxFIFO size, Fifo priority, lpid,
pid and tid values so that kernel can drive P9 NX 842 engine.

The following nodes are located under an xscom node:
/xscom@<xscom_addr>/nx@<nx_addr>

/ibm,842-high-fifo

: High priority 842 RxFIFO

/ibm,842-normal-fifo

: Normal priority 842 RxFIFO

Each RxFIFO node contains:

compatible

: ibm,p9-nx-842

priority

: High or Normal

rx-fifo-address

: RxFIFO address

rx-fifo-size

: RXFIFO size

lpid

: 0xfff (1's for 12 bits set in UMAC notify match register)

pid

: 842 coprocessor type

tid

: Counter for 842
vas: Create MMIO device tree node

Create a device tree node for VAS and add properties that Linux will
need to configure/use VAS.
opal: Extract sw checkstop fir address from HDAT.

Extract sw checkstop fir address info from HDAT and populate device
tree node ibm,sw-checkstop-fir.

This patch is required for OPAL_CEC_REBOOT2 OPAL call to work as
expected on p9.

With this patch a device property 'ibm,sw-checkstop-fir' is now
properly populated: :
```
# lsprop ibm,sw-checkstop-fir
ibm,sw-checkstop-fir
                 05012000 0000001f
```

PHB4

hdat: Fix PCIe GEN4 lane-eq setting for DD2

For PCIe GEN4, DD2 uses only 1 byte per PCIe lane for the lane-eq
settings (DD1 uses 2 bytes)
pci: Wait for CRS and switch link when restoring bus numbers

When a complete reset occurs, after the PHB recovers it propagates a
reset down the wire to every device. At the same time, skiboot talks
to every device in order to restore the state of devices to what
they were before the reset.

In some situations, such as devices that recovered slowly and/or
were behind a switch, skiboot attempted to access config space of
the device before the link was up and the device could respond.

Fix this by retrying CRS until the device responds correctly, and
for devices behind a switch, making sure the switch has its link up
first.
pci: Track whether a PCI device is a virtual function

This can be checked from config space, but we will need to know this
when restoring the PCI topology, and it is not always safe to access
config space during this period.
phb4: Enhanced PCIe training tracing

This add more details to the PCI training tracing (aka Rick Mata
mode). It enables the PCIe Link Training and Status State Machine
...

Assets 2

24 Aug 02:49

skiboot-5.1.20

8a9c042

skiboot 5.1.20

skiboot-5.1.20

skiboot-5.1.20 was released on Friday 18th August 2017.

skiboot-5.1.20 is the 21st stable release of 5.1, it follows
skiboot-5.1.19 (which was released 16th January 2017).

This release contains a few minor bug fixes backported to the 5.1.x
series. All of the fixes have previously appeared in the 5.4.x stable
series.

Changes are:

FSP/CONSOLE: Workaround for unresponsive ipmi daemon

In some corner cases, where FSP is active but not responding to
console MBOX message (due to buggy IPMI) and we have heavy console
write happening from kernel, then eventually our console buffer
becomes full. At this point OPAL starts sending OPAL_BUSY_EVENT to
kernel. Kernel will keep on retrying. This is creating kernel soft
lockups. In some extreme case when every CPU is trying to write to
console, user will not be able to ssh and thinks system is hang.

If we reset FSP or restart IPMI daemon on FSP, system recovers and
everything becomes normal.

This patch adds workaround to above issue by returning
OPAL_HARDWARE when cosole is full. Side effect of this patch is, we
may endup dropping latest console data. But better to drop console
data than system hang.

Alternative approach is to drop old data from console buffer, make
space for new data. But in normal condition only FSP can update
'next_out' pointer and if we touch that pointer, it may introduce
some other race conditions. Hence we decided to just new console
write request.
FSP: Set status field in response message for timed out message

For timed out FSP messages, we set message status as
"fsp_msg_timeout". But most FSP driver users (like surviellance)
are ignoring this field. They always look for FSP returned status
value in callback function (second byte in word1). So we endup
treating timed out message as success response from FSP.

Sample output: :
```
[69902.432509048,7] SURV: Sending the heartbeat command to FSP
[70023.226860117,4] FSP: Response from FSP timed out, word0 = d66a00d7, word1 = 0 state: 3
....
[70023.226901445,7] SURV: Received heartbeat acknowledge from FSP
[70023.226903251,3] FSP: fsp_trigger_reset() entry
```
Here SURV code thought it got valid response from FSP. But actually
we didn't receive response from FSP.
FSP: Improve timeout message

Presently we print word0 and word1 in error log. word0 contains
sequence number and command class. One has to understand word0
format to identify command class.

Lets explicitly print command class, sub command etc.
FSP/RTC: Remove local fsp_in_reset variable

Now that we are using fsp_in_rr() to detect FSP reset/reload,
fsp_in_reset become redundant. Lets remove this local variable.
FSP/RTC: Fix possible FSP R/R issue in rtc write path

fsp_opal_rtc_write() checks FSP status before queueing message to
FSP. But if FSP R/R starts before getting response to queued message
then we will continue to return OPAL_BUSY_EVENT to host. In some
extreme condition host may experience hang. Once FSP is back we will
repost message, get response from FSP and return OPAL_SUCCESS to
host.

This patch caches new values and returns OPAL_SUCCESS if FSP R/R is
happening. And once FSP is back we will send cached value to FSP.

hw/fsp/rtc: read/write cached rtc tod on fsp hir.

Currently fsp-rtc reads/writes the cached RTC TOD on an fsp reset.
Use latest fsp_in_rr() function to properly read the cached rtc
value when fsp reset initiated by the hir.

Below is the kernel trace when we set hw clock, when hir process
starts. :

[ 1727.775824] NMI watchdog: BUG: soft lockup - CPU#57 stuck for 23s! [hwclock:7688]
[ 1727.775856] Modules linked in: vmx_crypto ibmpowernv ipmi_powernv uio_pdrv_genirq ipmi_devintf powernv_op_panel uio ipmi_msghandler powernv_rng leds_powernv ip_tables x_tables autofs4 ses enclosure scsi_transport_sas crc32c_vpmsum lpfc ipr tg3 scsi_transport_fc
[ 1727.775883] CPU: 57 PID: 7688 Comm: hwclock Not tainted 4.10.0-14-generic #16-Ubuntu
[ 1727.775883] task: c000000fdfdc8400 task.stack: c000000fdfef4000
[ 1727.775884] NIP: c00000000090540c LR: c0000000000846f4 CTR: 000000003006dd70
[ 1727.775885] REGS: c000000fdfef79a0 TRAP: 0901   Not tainted  (4.10.0-14-generic)
[ 1727.775886] MSR: 9000000000009033 <SF,HV,EE,ME,IR,DR,RI,LE>
[ 1727.775889]   CR: 28024442  XER: 20000000
[ 1727.775890] CFAR: c00000000008472c SOFTE: 1
               GPR00: 0000000030005128 c000000fdfef7c20 c00000000144c900 fffffffffffffff4
               GPR04: 0000000028024442 c00000000090540c 9000000000009033 0000000000000000
               GPR08: 0000000000000000 0000000031fc4000 c000000000084710 9000000000001003
               GPR12: c0000000000846e8 c00000000fba0100
[ 1727.775897] NIP [c00000000090540c] opal_set_rtc_time+0x4c/0xb0
[ 1727.775899] LR [c0000000000846f4] opal_return+0xc/0x48
[ 1727.775899] Call Trace:
[ 1727.775900] [c000000fdfef7c20] [c00000000090540c] opal_set_rtc_time+0x4c/0xb0 (unreliable)
[ 1727.775901] [c000000fdfef7c60] [c000000000900828] rtc_set_time+0xb8/0x1b0
[ 1727.775903] [c000000fdfef7ca0] [c000000000902364] rtc_dev_ioctl+0x454/0x630
[ 1727.775904] [c000000fdfef7d40] [c00000000035b1f4] do_vfs_ioctl+0xd4/0x8c0
[ 1727.775906] [c000000fdfef7de0] [c00000000035bab4] SyS_ioctl+0xd4/0xf0
[ 1727.775907] [c000000fdfef7e30] [c00000000000b184] system_call+0x38/0xe0
[ 1727.775908] Instruction dump:
[ 1727.775909] f821ffc1 39200000 7c832378 91210028 38a10020 39200000 38810028 f9210020
[ 1727.775911] 4bfffe6d e8810020 80610028 4b77f61d <60000000> 7c7f1b78 3860000a 2fbffff4

This is found when executing the op-test-framework fspresetReload
testcase

With this fix ran fsp hir torture testcase in the above test which
is working fine.

FSP/CHIPTOD: Return false in error path
On FSP platforms: notify FSP of Platform Log ID after Host Initiated
Reset Reload Trigging a Host Initiated Reset (when the host detects
the FSP has gone out to lunch and should be rebooted), would cause
"Unknown Command" messages to appear in the OPAL log.

This patch implements those messages.

Log showing unknown command: :
```
/ # cat /sys/firmware/opal/msglog | grep -i ,3
[  110.232114723,3] FSP: fsp_trigger_reset() entry
[  188.431793837,3] FSP #0: Link down, starting R&R
[  464.109239162,3] FSP #0: Got XUP with no pending message !
[  466.340598554,3] FSP-DPO: Unknown command 0xce0900
[  466.340600126,3] FSP: Unhandled message ce0900
```
hw/i2c: Fix early lock drop

When interacting with an I2C master the p8-i2c driver (common to p9)
aquires a per-master lock which it holds for the duration of it's
interaction with the master. Unfortunately, when
p8_i2c_check_initial_status() detects that the master is busy
with another transaction it drops the lock and returns OPAL_BUSY.
This is contrary to the driver's locking strategy which requires
that the caller aquire and drop the lock. This leads to a crash due
to the double unlock(), which skiboot treats as fatal.
head.S: store all of LR and CTR

When saving the CTR and LR registers the skiboot exception handlers
use the 'stw' instruction which only saves the lower 32 bits of the
register. Given these are both 64 bit registers this leads to some
strange register dumps, for example: :
```
***********************************************
Unexpected exception 200 !
SRR0 : 0000000030016968 SRR1 : 9000000000201000
HSRR0: 0000000000000180 HSRR1: 9000000000001000
LR   : 3003438830823f50 CTR  : 3003438800000018
CFAR : 00000000300168fc
CR   : 40004208  XER: 00000000
```
In this dump the upper 32 bits of LR and CTR are actually stack gunk
which obscures the underlying issue.
hw/fsp: Do not queue SP and SPCN class messages during reset/reload
In certain cases of communicating with the FSP (e.g. sensors), the
OPAL FSP driver returns a default code (async completion) even
though there is no known bound from the time of this error return to
the actual data being available. The kernel driver keeps waiting
leading to soft-lockup on the host side.

Mitigate both these (known) cases by returning OPAL_BUSY so the
host driver knows to retry later.

Assets 2

27 Jul 02:30

v5.7

fb64fdb

v5.7

skiboot-5.7

skiboot v5.7 was released on Tuesday July 25th 2017. It follows two
release candidates of skiboot 5.7, and is now the new stable release of
skiboot following the 5.6 release, first released 24th May 2017.

skiboot v5.7 contains all bug fixes as of skiboot-5.4.6 and
skiboot-5.1.19 (the currently maintained stable releases). We do not
currently expect to do any 5.6.x stable releases.

For how the skiboot stable releases work, see stable-rules for details.

POWER9 is still in development, and thus all POWER9 users must upgrade
to skiboot v5.7.

This is the second release using the new regular six week release cycle,
similar to op-build, but slightly offset to allow for a short
stabilisation period. Expected release dates and contents are tracked
using GitHub milestone and issues:
https://github.com/open-power/skiboot/milestones

New Features

Since skiboot-5.6.0, we have a few new features:

New features in this release for POWER9 systems:

In Memory Counters (IMC) (See imc for details)
phb4: Activate shared PCI slot on witherspoon (see
Shared Slot <shared-slot-rn>)
phb4 capi (i.e. CAPI2): Enable capi mode for PHB4 (see
CAPI on PHB4 <capi2-rn>)

New feature for IBM FSP based systems:

fsp/tpo: Provide support for disabling TPO alarm

This patch adds support for disabling a preconfigured
Timed-Power-On(TPO) alarm on FSP based systems. Presently once a TPO
alarm is configured from the kernel it will be triggered even if its
subsequently disabled.

With this patch a TPO alarm can be disabled by passing
y_m_d==hr_min==0 to fsp_opal_tpo_write(). A branch is added to
the function to handle this case by sending FSP_CMD_TPO_DISABLE
message to the FSP instead of usual FSP_CMD_TPO_WRITE message.
The kernel is expected to call opal_tpo_write() with
y_m_d==hr_min==0 to request opal to disable TPO alarm.

POWER9

There are many important changes for POWER9 DD1 and DD2 systems. POWER9
support should be considered in development and skiboot 5.7 is certainly
NOT suitable for POWER9 production environments.

Since skiboot-5.7-rc2:

platform/witherspoon: Enable eSEL logging

OpenBMC stack added IPMI OEM extension to log eSEL events. Lets
enable eSEL logging from OPAL side.

See:
https://github.com/openbmc/openpower-host-ipmi-oem/blob/d9296050bcece5c2eca5ede0932d944b0ced66c9/oemhandler.cpp#L142
(yes, that is the documentation)
hdat/i2c: Fix array version check
mem_region: Check for no-map in reserved nodes

Regions with the no-map property should be handled seperately to
"normal" firmware reservations. When creating mem_region regions
from a reserved-memory DT node use the no-map property to select the
right reservation type.
hdata/memory: Add memory reservations to the DT

Currently we just add these to a list of pre-boot reserved regions
which is then converted into a the contents of the /reserved-memory/
node just before Skiboot jumps into the firmware kernel.

This approach is insufficent because we need to add the
ibm,prd-instance labels to the various hostboot reserved regions. To
do this we want to create these resevation nodes inside the HDAT
parser rather than having the mem_region flattening code handle it.
On P8 systems Hostboot placed its memory reservations under the
/ibm,hostboot/ node and this patch makes the HDAT parser do the
same.

Since Since skiboot-5.7-rc1:

HDAT: Add IPMI sensor data under /bmc node
numa/associativity: Add a new level of NUMA for GPU's

Today we have an issue where the NUMA nodes corresponding to GPU's
have the same affinity/distance as normal memory nodes. Our
reference-points today supports two levels [0x4, 0x4] for normal
systems and [0x4, 0x3] for Power8E systems. This patch adds a new
level [0x4, X, 0x2] and uses node-id as at all levels for the GPU.
xive: Enable memory backing of queues

This dedicates 6x64k pages of memory permanently for the XIVE to use
for internal queue overflow. This allows the XIVE to deal with some
corner cases where the internal queues might prove insufficient.
xive: Properly get rid of donated indirect pages during reset

Otherwise they keep being used accross kexec causing memory
corruption in subsequent kernels once KVM has been used.
cpu: Better handle unknown flags in opal_reinit_cpus()

At the moment, if we get passed flags we don't know about, we return
OPAL_UNSUPPORTED but we still perform whatever actions was requied
by the flags we do support. Additionally, on P8, we attempt a SLW
re-init which hasn't been supported since Murano DD2.0 and will
crash your system.

It's too late to fix on existing systems so Linux will have to be
careful at least on P8, but to avoid future issues let's clean that
up, make sure we only use slw_reinit() when HILE isn't supported.
cpu: Unconditionally cleanup TLBs on P9 in opal_reinit_cpus()

This can work around problems where Linux fails to properly cleanup
part or all of the TLB on kexec.
Fix scom addresses for power9 nx checkstop hmi handling.

Scom addresses for NX status, DMA & ENGINE FIR and PBI FIR has
changed for Power9. Fixup thoes while handling nx checkstop for
Power9.
Fix scom addresses for power9 core checkstop hmi handling.

Scom addresses for CORE FIR (Fault Isolation Register) and
Malfunction Alert Register has changed for Power9. Fixup those while
handling core checkstop for Power9.

Without this change HMI handler fails to check for correct reason
for core checkstop on Power9.
core/mem_region: check return value of add_region

The only sensible thing to do if this fails is to abort() as we've
likely just failed reserving reserved memory regions, and nothing
good comes from that.

Since Since skiboot-5.6.0:

hdata: Reserve Trace Areas

When hostboot is configured to setup in memory tracing it will
reserve some memory for use by the hardware tracing facility. We
need to mark these areas as off limits to the operating system and
firmware.
hdata: Make out-of-range idata print at PR_DEBUG

Some fields just aren't populated on some systems.
hdata: Ignore unnamed memory reservations.

Hostboot should name any and all memory reservations that it
provides. Currently some hostboots export a broken reservation
covering the first 256MB of memory and this causes the system to
crash at boot due to an invalid free because this overlaps with the
static "ibm,os-reserve" region (which covers the first 768MB of
memory).

According to the hostboot team unnamed reservations are invalid and
can be ignored.
hdata: Check the Host I2C devices array version

Currently this is not populated on FSP machines which causes some
obnoxious errors to appear in the boot log. We also only want to
parse version 1 of this structure since future versions will
completely change the array item format.
Ensure P9 DD1 workarounds apply only to Nimbus

The workarounds for P9 DD1 are only needed for Nimbus. P9 Cumulus
will be DD1 but don't need these same workarounds.

This patch ensures the P9 DD1 workarounds only apply to Nimbus. It
also renames some things to make clear what's what.
cpu: Cleanup AMR and IAMR when re-initializing CPUs

There's a bug in current Linux kernels leaving crap in those
registers accross kexec and not sanitizing them on boot. This breaks
kexec under some circumstances (such as booting a hash kernel from a
radix one on P9 DD2.0).

The long term fix is in Linux, but this workaround is a reasonable
way of "sanitizing" those SPRs when Linux calls opal_reinit_cpus()
and shouldn't have adverse effects.

We could also use that same mechanism to cleanup other things as
well such as restoring some other SPRs to their default value in the
future.
Set POWER9 RPR SPR to 0x00000103070F1F3F. Same value as P8.

Without this, thread priorities inside a core don't work.
cpu: Support setting HID[RADIX] and set it by default on P9

This adds new opal_reinit_cpus() flags to setup radix or hash mode
in HID[8] on POWER9.

By default HID[8] will be set. On P9 DD1.0, Linux will change it
as needed. On P9 DD2.0 hash works in radix mode (radix is really
"dual" mode) so KVM won't break and existing kernels will work.

Newer kernels built for hash will call this to clear the HID bit and
thus get the full size of the TLB as an optimization.
Add "cleanup_global_tlb" for P9 and later

Uses broadcast TLBIE's to cleanup the TLB on all cores and on the
nest MMU
xive: DD2.0 updates

Add support for StoreEOI, fix StoreEOI MMIO offset in ESB page, and
other cleanups
Update default TSCR value for P9 as recommended by HW folk.
xive: Fix initialisation of xive_cpu_state struct

When using XIVE emulation with DEBUG=1, we run into crashes in
log_add() due to the xive_cpu_state->log_pos being
uninitialised (and thus, with DEBUG enabled, initialised to the
poison value of 0x99999999).

PHB4

Since skiboot-5.7-rc2:

phb4: Add link training trace mode

Add a mode to PHB4 to trace training process closely. This activates
as soon as PERST is deasserted and produces human readable output of
the process.

This may increase training times since it duplicates some of the
training code. This code has it's own simple checks for fe...

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