npu2: hw-procedures: Change phy_rx_clock_sel values

The clock selection bits we set here are inputs to a state machine.

  DL clock select (bits 30-31)
    0b00: lane 0 clock
    0b01: lane 7 clock
    0b10: grid clock
    0b11: invalid/noop

To recover from a potential glitch, we need to ensure that the value we
set forces a state change. Our current sequence is to set 0x3 followed
by 0x1. With the above now known, that is actually a noop followed by
selection of lane 7. Depending on lane reversal, that selection is not a
state change for some bricks.

The way to force a state change in all cases is to switch to the grid
clock, and then back to a lane.

Signed-off-by: Reza Arbab <[email protected]>
Acked-by: Alistair Popple <[email protected]>
Signed-off-by: Stewart Smith <[email protected]>
(cherry picked from commit 878c718)
Signed-off-by: Stewart Smith <[email protected]>

hw/npu2-hw-procedures.c

@@ -633,11 +633,11 @@ static uint32_t phy_rx_clock_sel(struct npu2_dev *ndev)
 	 *
 	 * Work around a known DL bug by doing these writes twice.
 	 */
-	npu2_write_mask_4b(ndev->npu, NPU2_NTL_DL_CLK_CTRL(ndev), 0x80000003, 0x80000003);
-	npu2_write_mask_4b(ndev->npu, NPU2_NTL_DL_CLK_CTRL(ndev), 0x80000003, 0x80000003);
+	npu2_write_mask_4b(ndev->npu, NPU2_NTL_DL_CLK_CTRL(ndev), 0x80000002, 0x80000003);
+	npu2_write_mask_4b(ndev->npu, NPU2_NTL_DL_CLK_CTRL(ndev), 0x80000002, 0x80000003);
 
-	npu2_write_mask_4b(ndev->npu, NPU2_NTL_DL_CLK_CTRL(ndev), 0x80000001, 0x80000003);
-	npu2_write_mask_4b(ndev->npu, NPU2_NTL_DL_CLK_CTRL(ndev), 0x80000001, 0x80000003);
+	npu2_write_mask_4b(ndev->npu, NPU2_NTL_DL_CLK_CTRL(ndev), 0x80000000, 0x80000003);
+	npu2_write_mask_4b(ndev->npu, NPU2_NTL_DL_CLK_CTRL(ndev), 0x80000000, 0x80000003);
 
 	return PROCEDURE_NEXT;
 }