diff --git a/core.json b/core.json index bfb59c8..ba7fb9c 100644 --- a/core.json +++ b/core.json @@ -7,8 +7,8 @@ "description": "APF core template. Displays gray test screen.", "author": "Developer", "url": "https://github.com/open-fpga/core-template", - "version": "1.1.0", - "date_release": "2022-08-23" + "version": "1.2.0", + "date_release": "2022-11-05" }, "framework": { "target_product": "Analogue Pocket", diff --git a/output/bitstream.rbf_r b/output/bitstream.rbf_r index 93e6ddd..f46d60a 100644 Binary files a/output/bitstream.rbf_r and b/output/bitstream.rbf_r differ diff --git a/src/fpga/ap_core.qsf b/src/fpga/ap_core.qsf index 02c707b..422084a 100644 --- a/src/fpga/ap_core.qsf +++ b/src/fpga/ap_core.qsf @@ -744,5 +744,9 @@ set_global_assignment -name SDC_FILE core/core_constraints.sdc set_global_assignment -name SIGNALTAP_FILE core/stp1.stp set_global_assignment -name QIP_FILE core/mf_pllbase.qip set_global_assignment -name SIP_FILE core/mf_pllbase.sip -set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to bridge_1wire +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to bridge_spiclk +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to bridge_spimiso +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to bridge_spimosi +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp \ No newline at end of file diff --git a/src/fpga/apf/apf_top.v b/src/fpga/apf/apf_top.v index e82f37b..f0deb04 100644 --- a/src/fpga/apf/apf_top.v +++ b/src/fpga/apf/apf_top.v @@ -280,10 +280,10 @@ mf_ddio_bidir_12 isclk( // controller data (pad) controller. - wire [15:0] cont1_key; - wire [15:0] cont2_key; - wire [15:0] cont3_key; - wire [15:0] cont4_key; + wire [31:0] cont1_key; + wire [31:0] cont2_key; + wire [31:0] cont3_key; + wire [31:0] cont4_key; wire [31:0] cont1_joy; wire [31:0] cont2_joy; wire [31:0] cont3_joy; diff --git a/src/fpga/apf/build_id.mif b/src/fpga/apf/build_id.mif index 4184716..2fca0aa 100644 --- a/src/fpga/apf/build_id.mif +++ b/src/fpga/apf/build_id.mif @@ -9,8 +9,8 @@ DATA_RADIX = HEX; CONTENT BEGIN - 0E0 : 20220823; - 0E1 : 00024957; - 0E2 : b7d9142a; + 0E0 : 20221025; + 0E1 : 00195120; + 0E2 : 3c157f76; END; diff --git a/src/fpga/apf/io_pad_controller.v b/src/fpga/apf/io_pad_controller.v index c3886ac..d14b33c 100644 --- a/src/fpga/apf/io_pad_controller.v +++ b/src/fpga/apf/io_pad_controller.v @@ -45,10 +45,10 @@ input wire reset_n, inout reg pad_1wire, -output reg [15:0] cont1_key, -output reg [15:0] cont2_key, -output reg [15:0] cont3_key, -output reg [15:0] cont4_key, +output reg [31:0] cont1_key, +output reg [31:0] cont2_key, +output reg [31:0] cont3_key, +output reg [31:0] cont4_key, output reg [31:0] cont1_joy, output reg [31:0] cont2_joy, output reg [31:0] cont3_joy, @@ -140,19 +140,19 @@ always @(posedge clk) begin if(rx_word_done) begin cnt <= cnt + 1'b1; case(cnt) - 0: cont1_key <= rx_word[15:0]; + 0: cont1_key <= rx_word; 1: cont1_joy <= rx_word; 2: cont1_trig <= rx_word[15:0]; - 3: cont2_key <= rx_word[15:0]; + 3: cont2_key <= rx_word; 4: cont2_joy <= rx_word; 5: cont2_trig <= rx_word[15:0]; - 6: cont3_key <= rx_word[15:0]; + 6: cont3_key <= rx_word; 7: cont3_joy <= rx_word; 8: cont3_trig <= rx_word[15:0]; - 9: cont4_key <= rx_word[15:0]; + 9: cont4_key <= rx_word; 10: cont4_joy <= rx_word; 11: begin cont4_trig <= rx_word[15:0]; diff --git a/src/fpga/core/core_bridge_cmd.v b/src/fpga/core/core_bridge_cmd.v index 1039089..8729a0a 100644 --- a/src/fpga/core/core_bridge_cmd.v +++ b/src/fpga/core/core_bridge_cmd.v @@ -40,11 +40,21 @@ input wire dataslot_requestread_ok, output reg dataslot_requestwrite, output reg [15:0] dataslot_requestwrite_id, +output reg [31:0] dataslot_requestwrite_size, input wire dataslot_requestwrite_ack, input wire dataslot_requestwrite_ok, +output reg dataslot_update, +output reg [15:0] dataslot_update_id, +output reg [31:0] dataslot_update_size, + output reg dataslot_allcomplete, +output reg [31:0] rtc_epoch_seconds, +output reg [31:0] rtc_date_bcd, +output reg [31:0] rtc_time_bcd, +output reg rtc_valid, + input wire savestate_supported, input wire [31:0] savestate_addr, input wire [31:0] savestate_size, @@ -64,6 +74,18 @@ input wire savestate_load_busy, input wire savestate_load_ok, input wire savestate_load_err, +input wire target_dataslot_read, // rising edge triggered +input wire target_dataslot_write, + +output reg target_dataslot_ack, // asserted upon command start until completion +output reg target_dataslot_done, // asserted upon command finish until next command is issued +output reg [2:0] target_dataslot_err, // contains result of command execution. zero is OK + +input wire [15:0] target_dataslot_id, // parameters for each of the read/reload/write commands +input wire [31:0] target_dataslot_slotoffset, +input wire [31:0] target_dataslot_bridgeaddr, +input wire [31:0] target_dataslot_length, + input wire [9:0] datatable_addr, input wire datatable_wren, input wire [31:0] datatable_data, @@ -146,27 +168,33 @@ localparam [3:0] ST_DONE_ERR = 'd15; localparam [3:0] TARG_ST_IDLE = 'd0; localparam [3:0] TARG_ST_READYTORUN = 'd1; -localparam [3:0] TARG_ST_DISPMSG = 'd2; -localparam [3:0] TARG_ST_SLOTREAD = 'd3; -localparam [3:0] TARG_ST_SLOTRELOAD = 'd4; -localparam [3:0] TARG_ST_SLOTWRITE = 'd5; -localparam [3:0] TARG_ST_SLOTFLUSH = 'd6; -localparam [3:0] TARG_ST_WAITRESULT = 'd15; +localparam [3:0] TARG_ST_DATASLOTOP = 'd2; +localparam [3:0] TARG_ST_WAITRESULT_RTR = 'd14; +localparam [3:0] TARG_ST_WAITRESULT_DSO = 'd15; reg [3:0] tstate; - reg status_setup_done_1; - reg status_setup_done_queue; + reg status_setup_done_1, status_setup_done_queue; + reg target_dataslot_read_1, target_dataslot_read_queue; + reg target_dataslot_write_1, target_dataslot_write_queue; initial begin reset_n <= 0; dataslot_requestread <= 0; dataslot_requestwrite <= 0; + dataslot_update <= 0; dataslot_allcomplete <= 0; + rtc_valid <= 0; savestate_start <= 0; savestate_load <= 0; osnotify_inmenu <= 0; + status_setup_done_queue <= 0; + target_dataslot_read_queue <= 0; + target_dataslot_write_queue <= 0; + target_dataslot_ack <= 0; + target_dataslot_done <= 0; + target_dataslot_err <= 0; end always @(posedge clk) begin @@ -174,9 +202,19 @@ always @(posedge clk) begin // detect a rising edge on the input signal // and flag a queue that will be cleared later status_setup_done_1 <= status_setup_done; + target_dataslot_read_1 <= target_dataslot_read; + target_dataslot_write_1 <= target_dataslot_write; + if(status_setup_done & ~status_setup_done_1) begin status_setup_done_queue <= 1; end + if(target_dataslot_read & ~target_dataslot_read_1) begin + target_dataslot_read_queue <= 1; + end + if(target_dataslot_write & ~target_dataslot_write_1) begin + target_dataslot_write_queue <= 1; + end + b_datatable_wren <= 0; b_datatable_addr <= bridge_addr >> 2; @@ -257,6 +295,7 @@ always @(posedge clk) begin dataslot_requestread <= 0; dataslot_requestwrite <= 0; + dataslot_update <= 0; savestate_start <= 0; savestate_load <= 0; @@ -314,17 +353,34 @@ always @(posedge clk) begin dataslot_allcomplete <= 0; dataslot_requestwrite <= 1; dataslot_requestwrite_id <= host_20[15:0]; + dataslot_requestwrite_size <= host_24; if(dataslot_requestwrite_ack) begin host_resultcode <= 0; if(!dataslot_requestwrite_ok) host_resultcode <= 2; hstate <= ST_DONE_CODE; end end + 16'h008A: begin + // Data slot update (sent on deferload marked slots only) + dataslot_update <= 1; + dataslot_update_id <= host_20[15:0]; + dataslot_update_size <= host_24; + hstate <= ST_DONE_OK; + end 16'h008F: begin // Data slot access all complete dataslot_allcomplete <= 1; hstate <= ST_DONE_OK; end + 16'h0090: begin + // Real-time Clock Data + // user logic should detect rising edge, it is not continuously updated + rtc_valid <= 1; + rtc_epoch_seconds <= host_20; + rtc_date_bcd <= host_24; + rtc_time_bcd <= host_28; + hstate <= ST_DONE_OK; + end 16'h00A0: begin // Savestate: Start/Query host_40 <= savestate_supported; @@ -397,22 +453,63 @@ always @(posedge clk) begin endcase - - // target > host command executer case(tstate) TARG_ST_IDLE: begin + + target_dataslot_ack <= 0; + if(status_setup_done_queue) begin status_setup_done_queue <= 0; tstate <= TARG_ST_READYTORUN; - end - + + end else if(target_dataslot_read_queue) begin + target_dataslot_read_queue <= 0; + target_0[15:0] <= 16'h0180; + + target_20 <= target_dataslot_id; + target_24 <= target_dataslot_slotoffset; + target_28 <= target_dataslot_bridgeaddr; + target_2C <= target_dataslot_length; + + tstate <= TARG_ST_DATASLOTOP; + + end else if(target_dataslot_write_queue) begin + target_dataslot_write_queue <= 0; + target_0[15:0] <= 16'h0184; + + target_20 <= target_dataslot_id; + target_24 <= target_dataslot_slotoffset; + target_28 <= target_dataslot_bridgeaddr; + target_2C <= target_dataslot_length; + + tstate <= TARG_ST_DATASLOTOP; + end end TARG_ST_READYTORUN: begin target_0 <= 32'h636D_0140; - tstate <= TARG_ST_WAITRESULT; + tstate <= TARG_ST_WAITRESULT_RTR; + end + TARG_ST_DATASLOTOP: begin + target_0[31:16] <= 16'h636D; + + target_dataslot_done <= 0; + tstate <= TARG_ST_WAITRESULT_DSO; + end + TARG_ST_WAITRESULT_DSO: begin + if(target_0[31:16] == 16'h6275) begin + target_dataslot_ack <= 1; + end + if(target_0[31:16] == 16'h6F6B) begin + // done + // save result code + target_dataslot_err <= target_0[2:0]; + // assert done + target_dataslot_done <= 1; + tstate <= TARG_ST_IDLE; + end end - TARG_ST_WAITRESULT: begin + TARG_ST_WAITRESULT_RTR: begin if(target_0[31:16] == 16'h6F6B) begin // done tstate <= TARG_ST_IDLE; diff --git a/src/fpga/core/core_top.v b/src/fpga/core/core_top.v index 58ade65..03f3cc2 100644 --- a/src/fpga/core/core_top.v +++ b/src/fpga/core/core_top.v @@ -200,6 +200,7 @@ input wire [31:0] bridge_wr_data, // [13] trig_r3 // [14] face_select // [15] face_start +// [31:28] type // joy values - unsigned // [ 7: 0] lstick_x // [15: 8] lstick_y @@ -209,10 +210,10 @@ input wire [31:0] bridge_wr_data, // [ 7: 0] ltrig // [15: 8] rtrig // -input wire [15:0] cont1_key, -input wire [15:0] cont2_key, -input wire [15:0] cont3_key, -input wire [15:0] cont4_key, +input wire [31:0] cont1_key, +input wire [31:0] cont2_key, +input wire [31:0] cont3_key, +input wire [31:0] cont4_key, input wire [31:0] cont1_joy, input wire [31:0] cont2_joy, input wire [31:0] cont3_joy, @@ -248,7 +249,8 @@ assign cart_pin30_pwroff_reset = 1'b0; // hardware can control this assign cart_tran_pin31 = 1'bz; // input assign cart_tran_pin31_dir = 1'b0; // input -// link port is input only +// link port is unused, set to input only to be safe +// each bit may be bidirectional in some applications assign port_tran_so = 1'bz; assign port_tran_so_dir = 1'b0; // SO is output only assign port_tran_si = 1'bz; @@ -345,11 +347,21 @@ end wire dataslot_requestwrite; wire [15:0] dataslot_requestwrite_id; + wire [31:0] dataslot_requestwrite_size; wire dataslot_requestwrite_ack = 1; wire dataslot_requestwrite_ok = 1; + wire dataslot_update; + wire [15:0] dataslot_update_id; + wire [31:0] dataslot_update_size; + wire dataslot_allcomplete; + wire [31:0] rtc_epoch_seconds; + wire [31:0] rtc_date_bcd; + wire [31:0] rtc_time_bcd; + wire rtc_valid; + wire savestate_supported; wire [31:0] savestate_addr; wire [31:0] savestate_size; @@ -372,8 +384,20 @@ end // bridge target commands // synchronous to clk_74a + reg target_dataslot_read; + reg target_dataslot_write; + + wire target_dataslot_ack; + wire target_dataslot_done; + wire [2:0] target_dataslot_err; + reg [15:0] target_dataslot_id; + reg [31:0] target_dataslot_slotoffset; + reg [31:0] target_dataslot_bridgeaddr; + reg [31:0] target_dataslot_length; + // bridge data slot access +// synchronous to clk_74a wire [9:0] datatable_addr; wire datatable_wren; @@ -403,11 +427,21 @@ core_bridge_cmd icb ( .dataslot_requestwrite ( dataslot_requestwrite ), .dataslot_requestwrite_id ( dataslot_requestwrite_id ), + .dataslot_requestwrite_size ( dataslot_requestwrite_size ), .dataslot_requestwrite_ack ( dataslot_requestwrite_ack ), .dataslot_requestwrite_ok ( dataslot_requestwrite_ok ), + .dataslot_update ( dataslot_update ), + .dataslot_update_id ( dataslot_update_id ), + .dataslot_update_size ( dataslot_update_size ), + .dataslot_allcomplete ( dataslot_allcomplete ), + .rtc_epoch_seconds ( rtc_epoch_seconds ), + .rtc_date_bcd ( rtc_date_bcd ), + .rtc_time_bcd ( rtc_time_bcd ), + .rtc_valid ( rtc_valid ), + .savestate_supported ( savestate_supported ), .savestate_addr ( savestate_addr ), .savestate_size ( savestate_size ), @@ -427,10 +461,22 @@ core_bridge_cmd icb ( .osnotify_inmenu ( osnotify_inmenu ), + .target_dataslot_read ( target_dataslot_read ), + .target_dataslot_write ( target_dataslot_write ), + + .target_dataslot_ack ( target_dataslot_ack ), + .target_dataslot_done ( target_dataslot_done ), + .target_dataslot_err ( target_dataslot_err ), + + .target_dataslot_id ( target_dataslot_id ), + .target_dataslot_slotoffset ( target_dataslot_slotoffset ), + .target_dataslot_bridgeaddr ( target_dataslot_bridgeaddr ), + .target_dataslot_length ( target_dataslot_length ), + .datatable_addr ( datatable_addr ), .datatable_wren ( datatable_wren ), .datatable_data ( datatable_data ), - .datatable_q ( datatable_q ), + .datatable_q ( datatable_q ) ); diff --git a/src/fpga/output_files/ap_core.rbf b/src/fpga/output_files/ap_core.rbf index e66f9c8..afbb77a 100644 Binary files a/src/fpga/output_files/ap_core.rbf and b/src/fpga/output_files/ap_core.rbf differ diff --git a/src/fpga/output_files/ap_core.sof b/src/fpga/output_files/ap_core.sof index ac75654..e29c175 100644 Binary files a/src/fpga/output_files/ap_core.sof and b/src/fpga/output_files/ap_core.sof differ