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blackfin.cfg
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; The format of the input file:
; each device definition begins with a line like this:
;
; .devicename
;
; after it go the port definitions in this format:
;
; portname address
;
; the bit definitions (optional) are represented like this:
;
; portname.bitname bitnumber
;
; lines beginning with a space are ignored.
; comment lines should be started with ';' character.
;
; the default device is specified at the start of the file
;
; .default device_name
;
; all lines non conforming to the format are passed to the callback function
;
.default ADSP-BF524
; http://www.analog.com/media/en/dsp-documentation/processor-manuals/ADSP-BF52x_hwr_rev1.2.pdf
.ADSP-BF524
; MEMORY MAP
area DATA CMMR 0xFFE00000:0xFFFFFFFE Core MMR address range
area DATA SMMR 0xFFC00000:0xFFDFFFFE System MMR address range
; INPUT/OUTPUT
DMEM_CONTROL 0xffe00004
DCPLB_STATUS 0xffe00008
DCPLB_FAULT_ADDR 0xffe0000c
DCPLB_ADDR0 0xffe00100
DCPLB_ADDR1 0xffe00104
DCPLB_ADDR2 0xffe00108
DCPLB_ADDR3 0xffe0010c
DCPLB_ADDR4 0xffe00110
DCPLB_ADDR5 0xffe00114
DCPLB_ADDR6 0xffe00118
DCPLB_ADDR7 0xffe0011c
DCPLB_ADDR8 0xffe00120
DCPLB_ADDR9 0xffe00124
DCPLB_ADDR10 0xffe00128
DCPLB_ADDR11 0xffe0012c
DCPLB_ADDR12 0xffe00130
DCPLB_ADDR13 0xffe00134
DCPLB_ADDR14 0xffe00138
DCPLB_ADDR15 0xffe0013c
DCPLB_DATA0 0xffe00200
DCPLB_DATA1 0xffe00204
DCPLB_DATA2 0xffe00208
DCPLB_DATA3 0xffe0020c
DCPLB_DATA4 0xffe00210
DCPLB_DATA5 0xffe00214
DCPLB_DATA6 0xffe00218
DCPLB_DATA7 0xffe0021c
DCPLB_DATA8 0xffe00220
DCPLB_DATA9 0xffe00224
DCPLB_DATA10 0xffe00228
DCPLB_DATA11 0xffe0022c
DCPLB_DATA12 0xffe00230
DCPLB_DATA13 0xffe00234
DCPLB_DATA14 0xffe00238
DCPLB_DATA15 0xffe0023c
DTEST_COMMAND 0xffe00300
DTEST_DATA0 0xffe00400
DTEST_DATA1 0xffe00404
IMEM_CONTROL 0xffe01004
ICPLB_STATUS 0xffe01008
ICPLB_FAULT_ADDR 0xffe0100c
ICPLB_ADDR0 0xffe01100
ICPLB_ADDR1 0xffe01104
ICPLB_ADDR2 0xffe01108
ICPLB_ADDR3 0xffe0110c
ICPLB_ADDR4 0xffe01110
ICPLB_ADDR5 0xffe01114
ICPLB_ADDR6 0xffe01118
ICPLB_ADDR7 0xffe0111c
ICPLB_ADDR8 0xffe01120
ICPLB_ADDR9 0xffe01124
ICPLB_ADDR10 0xffe01128
ICPLB_ADDR11 0xffe0112c
ICPLB_ADDR12 0xffe01130
ICPLB_ADDR13 0xffe01134
ICPLB_ADDR14 0xffe01138
ICPLB_ADDR15 0xffe0113c
ICPLB_DATA0 0xffe01200
ICPLB_DATA1 0xffe01204
ICPLB_DATA2 0xffe01208
ICPLB_DATA3 0xffe0120c
ICPLB_DATA4 0xffe01210
ICPLB_DATA5 0xffe01214
ICPLB_DATA6 0xffe01218
ICPLB_DATA7 0xffe0121c
ICPLB_DATA8 0xffe01220
ICPLB_DATA9 0xffe01224
ICPLB_DATA10 0xffe01228
ICPLB_DATA11 0xffe0122c
ICPLB_DATA12 0xffe01230
ICPLB_DATA13 0xffe01234
ICPLB_DATA14 0xffe01238
ICPLB_DATA15 0xffe0123c
ITEST_COMMAND 0xffe01300
ITEST_DATA0 0xffe01400
ITEST_DATA1 0xffe01404
;Interrupt Controller Registers
EVT0_EMU 0xffe02000
EVT1_RST 0xffe02004
EVT2_NMI 0xffe02008
EVT3_EVX 0xffe0200c
EVT4 0xffe02010
EVT5_IVHW 0xffe02014
EVT6_TMR 0xffe02018
EVT7_IVG7 0xffe0201c
EVT8_IVG8 0xffe02020
EVT9_IVG9 0xffe02024
EVT10_IVG10 0xffe02028
EVT11_IVG11 0xffe0202c
EVT12_IVG12 0xffe02030
EVT13_IVG13 0xffe02034
EVT14_IVG14 0xffe02038
EVT15_IVG15 0xffe0203c
IMASK 0xffe02104
IPEND 0xffe02108
ILAT 0xffe0210c
IPRIO 0xffe02110
;Core Timer Registers
TCNTL 0xffe03000
TPERIOD 0xffe03004
TSCALE 0xffe03008
TCOUNT 0xffe0300c
;Debug, MP and Emulation Unit registers
DSPID 0xffe05000
TBUFCTL 0xffe06000
TBUFSTAT 0xffe06004
TBUF 0xffe06100
;Watchpoint and Patch Registers
WPIACTL 0xffe07000
WPIA0 0xffe07040
WPIA1 0xffe07044
WPIA2 0xffe07048
WPIA3 0xffe0704c
WPIA4 0xffe07050
WPIA5 0xffe07054
WPIACNT0 0xffe07080
WPIACNT1 0xffe07084
WPIACNT2 0xffe07088
WPIACNT3 0xffe0708c
WPIACNT4 0xffe07090
WPIACNT5 0xffe07094
WPDACTL 0xffe07100
WPDA0 0xffe07140
WPDA1 0xffe07144
WPDACNT0 0xffe07180
WPDACNT1 0xffe07184
WPSTAT 0xffe07200
;Performance Monitor Registers
PFCTL 0xffe08000
PFCNTR0 0xffe08100
PFCNTR1 0xffe08104
;Dynamic Power Management Registers
PLL_CTL 0xffc00000
PLL_DIV 0xffc00004
VR_CTL 0xffc00008
PLL_STAT 0xffc0000c
PLL_LOCKCNT 0xffc00010
;System Reset and Interrupt Control Registers
SIC_SWRST 0xffc00100
SIC_SYSCR 0xffc00104
SIC_IMASK0 0xffc0010c
SIC_IMASK1 0xffc0014c
SIC_IAR0 0xffc00110
SIC_IAR1 0xffc00114
SIC_IAR2 0xffc00118
SIC_IAR3 0xffc0011c
SIC_IAR4 0xffc00150
SIC_IAR5 0xffc00154
SIC_IAR6 0xffc00158
SIC_IAR7 0xffc0015c
SIC_ISR0 0xffc00120
SIC_ISR1 0xffc00160
SIC_IWR0 0xffc00124
SIC_IWR1 0xffc00164
;Watchdog Timer Registers
WDOG_CTL 0xffc00200
WDOG_CNT 0xffc00204
WDOG_STAT 0xffc00208
;Real-Time Clock Registers
RTC_STAT 0xffc00300
RTC_ICTL 0xffc00304
RTC_ISTAT 0xffc00308
RTC_SWCNT 0xffc0030c
RTC_ALARM 0xffc00310
RTC_PREN 0xffc00314
;Parallel Peripheral Interface Registers
PPI_CONTROL 0xffc01000
PPI_STATUS 0xffc01004
PPI_COUNT 0xffc01008
PPI_DELAY 0xffc0100c
PPI_FRAME 0xffc01010
;UART Control Registers
UART0_THR_RBR_DLL 0xffc00400
UART0_DLH_IER 0xffc00404
UART0_IIR 0xffc00408
UART0_LCR 0xffc0040c
UART0_MCR 0xffc00410
UART0_LSR 0xffc00414
UART0_SCR 0xffc0041c
UART0_GCTL 0xffc00424
;SPI Controller Registers
SPI_CTL 0xffc00500
SPI_FLG 0xffc00504
SPI_STAT 0xffc00508
SPI_TDBR 0xffc0050c
SPI_RDBR 0xffc00510
SPI_BAUD 0xffc00514
SPI_SHADOW 0xffc00518
;Timer Registers
TIMER0_CONFIG 0xffc00600
TIMER0_COUNTER 0xffc00604
TIMER0_PERIOD 0xffc00608
TIMER0_WIDTH 0xffc0060c
TIMER1_CONFIG 0xffc00610
TIMER1_COUNTER 0xffc00614
TIMER1_PERIOD 0xffc00618
TIMER1_WIDTH 0xffc0061c
TIMER2_CONFIG 0xffc00620
TIMER2_COUNTER 0xffc00624
TIMER2_PERIOD 0xffc00628
TIMER2_WIDTH 0xffc0062c
TIMER3_CONFIG 0xffc00630
TIMER3_COUNTER 0xffc00634
TIMER3_PERIOD 0xffc00638
TIMER3_WIDTH 0xffc0063c
TIMER4_CONFIG 0xffc00640
TIMER4_COUNTER 0xffc00644
TIMER4_PERIOD 0xffc00648
TIMER4_WIDTH 0xffc0064c
TIMER5_CONFIG 0xffc00650
TIMER5_COUNTER 0xffc00654
TIMER5_PERIOD 0xffc00658
TIMER5_WIDTH 0xffc0065c
TIMER6_CONFIG 0xffc00660
TIMER6_COUNTER 0xffc00664
TIMER6_PERIOD 0xffc00668
TIMER6_WIDTH 0xffc0066c
TIMER7_CONFIG 0xffc00670
TIMER7_COUNTER 0xffc00674
TIMER7_PERIOD 0xffc00678
TIMER7_WIDTH 0xffc0067c
TIMER_ENABLE 0xffc00680
TIMER_DISABLE 0xffc00684
TIMER_STATUS 0xffc00688
;Programmable Flag Registers
PORTFIO 0xffc00700
PORTFIO_CLEAR 0xffc00704
PORTFIO_SET 0xffc00708
PORTFIO_TOGGLE 0xffc0070c
PORTFIO_MASKA 0xffc00710
PORTFIO_MASKA_CLEAR 0xffc00714
PORTFIO_MASKA_SET 0xffc00718
PORTFIO_MASKA_TOGGLE 0xffc0071c
PORTFIO_MASKB 0xffc00720
PORTFIO_MASKB_CLEAR 0xffc00724
PORTFIO_MASKB_SET 0xffc00728
PORTFIO_MASKB_TOGGLE 0xffc0072c
PORTFIO_DIR 0xffc00730
PORTFIO_POLAR 0xffc00734
PORTFIO_EDGE 0xffc00738
PORTFIO_BOTH 0xffc0073c
PORTFIO_INEN 0xffc00740
PORTGIO 0xffc01500
PORTGIO_CLEAR 0xffc01504
PORTGIO_SET 0xffc01508
PORTGIO_TOGGLE 0xffc0150c
PORTGIO_MASKA 0xffc01510
PORTGIO_MASKA_CLEAR 0xffc01514
PORTGIO_MASKA_SET 0xffc01518
PORTGIO_MASKA_TOGGLE 0xffc0151c
PORTGIO_MASKB 0xffc01520
PORTGIO_MASKB_CLEAR 0xffc01524
PORTGIO_MASKB_SET 0xffc01528
PORTGIO_MASKB_TOGGLE 0xffc0152c
PORTGIO_DIR 0xffc01530
PORTGIO_POLAR 0xffc01534
PORTGIO_EDGE 0xffc01538
PORTGIO_BOTH 0xffc0153c
PORTGIO_INEN 0xffc01540
PORTHIO 0xffc01700
PORTHIO_CLEAR 0xffc01704
PORTHIO_SET 0xffc01708
PORTHIO_TOGGLE 0xffc0170c
PORTHIO_MASKA 0xffc01710
PORTHIO_MASKA_CLEAR 0xffc01714
PORTHIO_MASKA_SET 0xffc01718
PORTHIO_MASKA_TOGGLE 0xffc0171c
PORTHIO_MASKB 0xffc01720
PORTHIO_MASKB_CLEAR 0xffc01724
PORTHIO_MASKB_SET 0xffc01728
PORTHIO_MASKB_TOGGLE 0xffc0172c
PORTHIO_DIR 0xffc01730
PORTHIO_POLAR 0xffc01734
PORTHIO_EDGE 0xffc01738
PORTHIO_BOTH 0xffc0173c
PORTHIO_INEN 0xffc01740
PORTF_FER 0xffc03200
PORTG_FER 0xffc03204
PORTH_FER 0xffc03208
PORTF_MUX 0xffc03210
PORTG_MUX 0xffc03214
PORTH_MUX 0xffc03218
PORTF_HYSTERESIS 0xffc03240
PORTG_HYSTERESIS 0xffc03244
PORTH_HYSTERESIS 0xffc03248
NONGPIO_HYSTERESIS 0xffc03288
;SPORT0 Controller Registers
SPORT0_TCR1 0xffc00800
SPORT0_TCR2 0xffc00804
sPORT0_TCLKDIV 0xffc00808
SPORT0_TFSDIV 0xffc0080c
SPORT0_TX 0xffc00810
SPORT0_RX 0xffc00818
SPORT0_RCR1 0xffc00820
SPORT0_RCR2 0xffc00824
SPORT0_RCLKDIV 0xffc00828
SPORT0_RFSDIV 0xffc0082c
SPORT0_STAT 0xffc00830
SPORT0_CHNL 0xffc00834
SPORT0_MCMC1 0xffc00838
SPORT0_MCMC2 0xffc0083c
SPORT0_MTCS0 0xffc00840
SPORT0_MTCS1 0xffc00844
SPORT0_MTCS2 0xffc00848
SPORT0_MTCS3 0xffc0084c
SPORT0_MRCS0 0xffc00850
SPORT0_MRCS1 0xffc00854
SPORT0_MRCS2 0xffc00858
SPORT0_MRCS3 0xffc0085c
;SPORT1 Controller Registers
SPORT1_TCR1 0xffc00900
SPORT1_TCR2 0xffc00904
sPORT1_TCLKDIV 0xffc00908
SPORT1_TFSDIV 0xffc0090c
SPORT1_TX 0xffc00910
SPORT1_RX 0xffc00918
SPORT1_RCR1 0xffc00920
SPORT1_RCR2 0xffc00924
SPORT1_RCLKDIV 0xffc00928
SPORT1_RFSDIV 0xffc0092c
SPORT1_STAT 0xffc00930
SPORT1_CHNL 0xffc00934
SPORT1_MCMC1 0xffc00938
SPORT1_MCMC2 0xffc0093c
SPORT1_MTCS0 0xffc00940
SPORT1_MTCS1 0xffc00944
SPORT1_MTCS2 0xffc00948
SPORT1_MTCS3 0xffc0094c
SPORT1_MRCS0 0xffc00950
SPORT1_MRCS1 0xffc00954
SPORT1_MRCS2 0xffc00958
SPORT1_MRCS3 0xffc0095c
;DMA Traffic Control Registers
DMA_TC_PER 0xffc01b0c
DMA_TC_CNT 0xffc01b10
;DMA Channel Register
DMA0_NEXT_DESC_PTR 0xffc00c00
DMA0_START_ADDR 0xffc00c04
DMA0_CONFIG 0xffc00c08
DMA0_X_COUNT 0xffc00c10
DMA0_X_MODIFY 0xffc00c14
DMA0_Y_COUNT 0xffc00c18
DMA0_Y_MODIFY 0xffc00c1c
DMA0_CURR_DESC_PTR 0xffc00c20
DMA0_CURR_ADDR 0xffc00c24
DMA0_IRQ_STATUS 0xffc00c28
DMA0_PERIPHERAL_MAP 0xffc00c2c
DMA0_CURR_X_COUNT 0xffc00c30
DMA0_CURR_Y_COUNT 0xffc00c38
DMA1_NEXT_DESC_PTR 0xffc00c40
DMA1_START_ADDR 0xffc00c44
DMA1_CONFIG 0xffc00c48
DMA1_X_COUNT 0xffc00c50
DMA1_X_MODIFY 0xffc00c54
DMA1_Y_COUNT 0xffc00c58
DMA1_Y_MODIFY 0xffc00c5c
DMA1_CURR_DESC_PTR 0xffc00c60
DMA1_CURR_ADDR 0xffc00c64
DMA1_IRQ_STATUS 0xffc00c68
DMA1_PERIPHERAL_MAP 0xffc00c6c
DMA1_CURR_X_COUNT 0xffc00c70
DMA1_CURR_Y_COUNT 0xffc00c78
DMA2_NEXT_DESC_PTR 0xffc00c80
DMA2_START_ADDR 0xffc00c84
DMA2_CONFIG 0xffc00c88
DMA2_X_COUNT 0xffc00c90
DMA2_X_MODIFY 0xffc00c94
DMA2_Y_COUNT 0xffc00c98
DMA2_Y_MODIFY 0xffc00c9c
DMA2_CURR_DESC_PTR 0xffc00ca0
DMA2_CURR_ADDR 0xffc00ca4
DMA2_IRQ_STATUS 0xffc00ca8
DMA2_PERIPHERAL_MAP 0xffc00cac
DMA2_CURR_X_COUNT 0xffc00cb0
DMA2_CURR_Y_COUNT 0xffc00cb8
DMA3_NEXT_DESC_PTR 0xffc00cc0
DMA3_START_ADDR 0xffc00cc4
DMA3_CONFIG 0xffc00cc8
DMA3_X_COUNT 0xffc00cd0
DMA3_X_MODIFY 0xffc00cd4
DMA3_Y_COUNT 0xffc00cd8
DMA3_Y_MODIFY 0xffc00cdc
DMA3_CURR_DESC_PTR 0xffc00ce0
DMA3_CURR_ADDR 0xffc00ce4
DMA3_IRQ_STATUS 0xffc00ce8
DMA3_PERIPHERAL_MAP 0xffc00cec
DMA3_CURR_X_COUNT 0xffc00cf0
DMA3_CURR_Y_COUNT 0xffc00cf8
DMA4_NEXT_DESC_PTR 0xffc00d00
DMA4_START_ADDR 0xffc00d04
DMA4_CONFIG 0xffc00d08
DMA4_X_COUNT 0xffc00d10
DMA4_X_MODIFY 0xffc00d14
DMA4_Y_COUNT 0xffc00d18
DMA4_Y_MODIFY 0xffc00d1c
DMA4_CURR_DESC_PTR 0xffc00d20
DMA4_CURR_ADDR 0xffc00d24
DMA4_IRQ_STATUS 0xffc00d28
DMA4_PERIPHERAL_MAP 0xffc00d2c
DMA4_CURR_X_COUNT 0xffc00d30
DMA4_CURR_Y_COUNT 0xffc00d38
DMA5_NEXT_DESC_PTR 0xffc00d40
DMA5_START_ADDR 0xffc00d44
DMA5_CONFIG 0xffc00d48
DMA5_X_COUNT 0xffc00d50
DMA5_X_MODIFY 0xffc00d54
DMA5_Y_COUNT 0xffc00d58
DMA5_Y_MODIFY 0xffc00d5c
DMA5_CURR_DESC_PTR 0xffc00d60
DMA5_CURR_ADDR 0xffc00d64
DMA5_IRQ_STATUS 0xffc00d68
DMA5_PERIPHERAL_MAP 0xffc00d6c
DMA5_CURR_X_COUNT 0xffc00d70
DMA5_CURR_Y_COUNT 0xffc00d78
DMA6_NEXT_DESC_PTR 0xffc00d80
DMA6_START_ADDR 0xffc00d84
DMA6_CONFIG 0xffc00d88
DMA6_X_COUNT 0xffc00d90
DMA6_X_MODIFY 0xffc00d94
DMA6_Y_COUNT 0xffc00d98
DMA6_Y_MODIFY 0xffc00d9c
DMA6_CURR_DESC_PTR 0xffc00da0
DMA6_CURR_ADDR 0xffc00da4
DMA6_IRQ_STATUS 0xffc00da8
DMA6_PERIPHERAL_MAP 0xffc00dac
DMA6_CURR_X_COUNT 0xffc00db0
DMA6_CURR_Y_COUNT 0xffc00db8
DMA7_NEXT_DESC_PTR 0xffc00dc0
DMA7_START_ADDR 0xffc00dc4
DMA7_CONFIG 0xffc00dc8
DMA7_X_COUNT 0xffc00dd0
DMA7_X_MODIFY 0xffc00dd4
DMA7_Y_COUNT 0xffc00dd8
DMA7_Y_MODIFY 0xffc00ddc
DMA7_CURR_DESC_PTR 0xffc00de0
DMA7_CURR_ADDR 0xffc00de4
DMA7_IRQ_STATUS 0xffc00de8
DMA7_PERIPHERAL_MAP 0xffc00dec
DMA7_CURR_X_COUNT 0xffc00df0
DMA7_CURR_Y_COUNT 0xffc00df8
DMA8_NEXT_DESC_PTR 0xffc00e00
DMA8_START_ADDR 0xffc00e04
DMA8_CONFIG 0xffc00e08
DMA8_X_COUNT 0xffc00e10
DMA8_X_MODIFY 0xffc00e14
DMA8_Y_COUNT 0xffc00e18
DMA8_Y_MODIFY 0xffc00e1c
DMA8_CURR_DESC_PTR 0xffc00e20
DMA8_CURR_ADDR 0xffc00e24
DMA8_IRQ_STATUS 0xffc00e28
DMA8_PERIPHERAL_MAP 0xffc00e2c
DMA8_CURR_X_COUNT 0xffc00e30
DMA8_CURR_Y_COUNT 0xffc00e38
DMA9_NEXT_DESC_PTR 0xffc00e40
DMA9_START_ADDR 0xffc00e44
DMA9_CONFIG 0xffc00e48
DMA9_X_COUNT 0xffc00e50
DMA9_X_MODIFY 0xffc00e54
DMA9_Y_COUNT 0xffc00e58
DMA9_Y_MODIFY 0xffc00e5c
DMA9_CURR_DESC_PTR 0xffc00e60
DMA9_CURR_ADDR 0xffc00e64
DMA9_IRQ_STATUS 0xffc00e68
DMA9_PERIPHERAL_MAP 0xffc00e6c
DMA9_CURR_X_COUNT 0xffc00e70
DMA9_CURR_Y_COUNT 0xffc00e78
DMA10_NEXT_DESC_PTR 0xffc00e80
DMA10_START_ADDR 0xffc00e84
DMA10_CONFIG 0xffc00e88
DMA10_X_COUNT 0xffc00e90
DMA10_X_MODIFY 0xffc00e94
DMA10_Y_COUNT 0xffc00e98
DMA10_Y_MODIFY 0xffc00e9c
DMA10_CURR_DESC_PTR 0xffc00ea0
DMA10_CURR_ADDR 0xffc00ea4
DMA10_IRQ_STATUS 0xffc00ea8
DMA10_PERIPHERAL_MAP 0xffc00eac
DMA10_CURR_X_COUNT 0xffc00eb0
DMA10_CURR_Y_COUNT 0xffc00eb8
DMA11_NEXT_DESC_PTR 0xffc00ec0
DMA11_START_ADDR 0xffc00ec4
DMA11_CONFIG 0xffc00ec8
DMA11_X_COUNT 0xffc00ed0
DMA11_X_MODIFY 0xffc00ed4
DMA11_Y_COUNT 0xffc00ed8
DMA11_Y_MODIFY 0xffc00edc
DMA11_CURR_DESC_PTR 0xffc00ee0
DMA11_CURR_ADDR 0xffc00ee4
DMA11_IRQ_STATUS 0xffc00ee8
DMA11_PERIPHERAL_MAP 0xffc00eec
DMA11_CURR_X_COUNT 0xffc00ef0
DMA11_CURR_Y_COUNT 0xffc00ef8
MDMA_D0_NEXT_DESC_PTR 0xffc00f00
MDMA_D0_START_ADDR 0xffc00f04
MDMA_D0_CONFIG 0xffc00f08
MDMA_D0_X_COUNT 0xffc00f10
MDMA_D0_X_MODIFY 0xffc00f14
MDMA_D0_Y_COUNT 0xffc00f18
MDMA_D0_Y_MODIFY 0xffc00f1c
MDMA_D0_CURR_DESC_PTR 0xffc00f20
MDMA_D0_CURR_ADDR 0xffc00f24
MDMA_D0_IRQ_STATUS 0xffc00f28
MDMA_D0_PERIPHERAL_MAP 0xffc00f2c
MDMA_D0_CURR_X_COUNT 0xffc00f30
MDMA_D0_CURR_Y_COUNT 0xffc00f38
MDMA_S0_NEXT_DESC_PTR 0xffc00f40
MDMA_S0_START_ADDR 0xffc00f44
MDMA_S0_CONFIG 0xffc00f48
MDMA_S0_X_COUNT 0xffc00f50
MDMA_S0_X_MODIFY 0xffc00f54
MDMA_S0_Y_COUNT 0xffc00f58
MDMA_S0_Y_MODIFY 0xffc00f5c
MDMA_S0_CURR_DESC_PTR 0xffc00f60
MDMA_S0_CURR_ADDR 0xffc00f64
MDMA_S0_IRQ_STATUS 0xffc00f68
MDMA_S0_PERIPHERAL_MAP 0xffc00f6c
MDMA_S0_CURR_X_COUNT 0xffc00f70
MDMA_S0_CURR_Y_COUNT 0xffc00f78
MDMA_D1_NEXT_DESC_PTR 0xffc00f80
MDMA_D1_START_ADDR 0xffc00f84
MDMA_D1_CONFIG 0xffc00f88
MDMA_D1_X_COUNT 0xffc00f90
MDMA_D1_X_MODIFY 0xffc00f94
MDMA_D1_Y_COUNT 0xffc00f98
MDMA_D1_Y_MODIFY 0xffc00f9c
MDMA_D1_CURR_DESC_PTR 0xffc00fa0
MDMA_D1_CURR_ADDR 0xffc00fa4
MDMA_D1_IRQ_STATUS 0xffc00fa8
MDMA_D1_PERIPHERAL_MAP 0xffc00fac
MDMA_D1_CURR_X_COUNT 0xffc00fb0
MDMA_D1_CURR_Y_COUNT 0xffc00fb8
MDMA_S1_NEXT_DESC_PTR 0xffc00fc0
MDMA_S1_START_ADDR 0xffc00fc4
MDMA_S1_CONFIG 0xffc00fc8
MDMA_S1_X_COUNT 0xffc00fd0
MDMA_S1_X_MODIFY 0xffc00fd4
MDMA_S1_Y_COUNT 0xffc00fd8
MDMA_S1_Y_MODIFY 0xffc00fdc
MDMA_S1_CURR_DESC_PTR 0xffc00fe0
MDMA_S1_CURR_ADDR 0xffc00fe4
MDMA_S1_IRQ_STATUS 0xffc00fe8
MDMA_S1_PERIPHERAL_MAP 0xffc00fec
MDMA_S1_CURR_X_COUNT 0xffc00ff0
MDMA_S1_CURR_Y_COUNT 0xffc00ff8
;External Bus Interface Unit Registers
EBIU_AMGCTL 0xffc00a00
EBIU_AMBCTL0 0xffc00a04
EBIU_AMBCTL1 0xffc00a08
EBIU_SDGCTL 0xffc00a10
EBIU_SDBCTL 0xffc00a14
EBIU_SDRRC 0xffc00a18
EBIU_SDSTAT 0xffc00a1c