From a5eb6c564131f73015ad6746f374955e99ad0e73 Mon Sep 17 00:00:00 2001 From: Neeraj Dantu Date: Thu, 2 Feb 2023 14:03:15 -0600 Subject: [PATCH] Add support for OSD32MP1-RED-V1_2 --- Makefile | 78 +- files/fsbl/Makefile.sdk | 12 +- .../fstab_emmc_stm32mp157c-osd32mp1-red-v1_2 | 7 + ...fstab_sdcard_stm32mp157c-osd32mp1-red-v1_2 | 7 + files/ssbl/Makefile.sdk | 2 +- ...for-800MHz-speedgrade-MP1-to-work-wi.patch | 25 + ...SD32MP1-RED-V1_2-Device-tree-support.patch | 604 ++++++ ...for-800MHz-speedgrade-MP1-to-work-wi.patch | 24 + ...SD32MP1-RED-V1_2-Device-tree-support.patch | 1466 ++++++++++++++ ...for-800MHz-speedgrade-MP1-to-work-wi.patch | 24 + ...SD32MP1-RED-V1_2-Device-tree-support.patch | 1710 +++++++++++++++++ stm32mp157c-osd32mp1-red-v1_2-extlinux.sh | 57 + 12 files changed, 4002 insertions(+), 14 deletions(-) create mode 100644 files/rootfs/fstab_emmc_stm32mp157c-osd32mp1-red-v1_2 create mode 100644 files/rootfs/fstab_sdcard_stm32mp157c-osd32mp1-red-v1_2 create mode 100644 patches/arm-trusted-firmware-2.4/0003-Fix-device-tree-for-800MHz-speedgrade-MP1-to-work-wi.patch create mode 100644 patches/arm-trusted-firmware-2.4/0004-Add-OSD32MP1-RED-V1_2-Device-tree-support.patch create mode 100644 patches/linux-5.10/0025-Fix-device-tree-for-800MHz-speedgrade-MP1-to-work-wi.patch create mode 100644 patches/linux-5.10/0026-Add-OSD32MP1-RED-V1_2-Device-tree-support.patch create mode 100644 patches/u-boot-2020.10/0009-Fix-device-tree-for-800MHz-speedgrade-MP1-to-work-wi.patch create mode 100644 patches/u-boot-2020.10/0010-Add-OSD32MP1-RED-V1_2-Device-tree-support.patch create mode 100755 stm32mp157c-osd32mp1-red-v1_2-extlinux.sh diff --git a/Makefile b/Makefile index c9b926c..25f53bc 100644 --- a/Makefile +++ b/Makefile @@ -2,12 +2,21 @@ # SPDX-License-Identifier: GPL-2.0+ ROOT_DIR = $(PWD) + +# version of TF-A to determine path ATF_VERSION=arm-trusted-firmware-2.4 + +# version of u-boot to determine path UBOOT_VERSION = u-boot-2020.10 + +# version of kernel to determine path KERNEL_VERSION=linux-5.10 + +# version of gcnano to determine path GCNANO_VERSION=6.4.3 GCNANO_SUBVERSION=20200902 +# Setting up directories FSBL_DIR ?= $(realpath bootloader/$(ATF_VERSION)) SSBL_DIR ?= $(realpath bootloader/$(UBOOT_VERSION)) KERNEL_DIR ?= $(realpath kernel/$(KERNEL_VERSION)) @@ -22,25 +31,45 @@ M4PROJECTS_DIR ?= $(realpath STM32CubeMP1) DEPLOY_DIR ?= $(PWD)/deploy BUILDTOOLS_DIR ?= $(realpath build-tools) +# FSBL = First stage boot loader SSBL = Second stage boot loader +# trusted mode is default (FSBL = TF-A, SSBL = U-Boot) MODE ?= trusted -BOARD_NAME := stm32mp157c-osd32mp1-red + +# machine name(name of the device tree file) +BOARD_NAME := stm32mp157c-osd32mp1-red-v1_2 + +# defconfig for kernel +# costum configuration can be added in build-tools/patches/linux-[version] KDEFCONFIG ?= multi_v7_defconfig + +# boot mode enable. Only enable boot modes you know you have in hardware +# RED supports EMMC and SD +# BRK only supports SD BOOT_EMMC = 1 BOOT_SD = 1 + +# Boards supported BOARD_RED = stm32mp157c-osd32mp1-red BOARD_BRK = stm32mp157c-osd32mp1-brk +BOARD_RED_V12 = stm32mp157c-osd32mp1-red-v1_2 +# Cross compiler setup ARCH ?= arm CROSS_COMPILE ?= arm-linux-gnueabihf- +# use as many threads as you can for build NPROCS=$(shell nproc) FLAGS=-j $(NPROCS) +# default SD card size = 8GB SDCARD_SIZE_GB=8192 + +# Add 1GB to rootfilesystem ROOTFS_EXTRA_SPACE=1024 .PHONY: setup patch_fsbl patch_ssbl patch_kernel fsbl ssbl kernel bootfs gcnano rootfs vendorfs m4_demo all clean +# Apply patches to FSBL patch_fsbl: for file in $(BUILDTOOLS_DIR)/patches/$(ATF_VERSION)/*.patch; do \ git apply --check --directory=bootloader/$(ATF_VERSION) $$file > /dev/null 2>&1; \ @@ -51,6 +80,7 @@ patch_fsbl: done touch $(KERNEL_DIR)/.scmversion +# Apply patches to SSBL patch_ssbl: for file in $(BUILDTOOLS_DIR)/patches/$(UBOOT_VERSION)/*.patch; do \ git apply --check --directory=bootloader/$(UBOOT_VERSION) $$file > /dev/null 2>&1; \ @@ -61,6 +91,7 @@ patch_ssbl: done touch $(KERNEL_DIR)/.scmversion +# Apply patches to kernel patch_kernel: for file in $(BUILDTOOLS_DIR)/patches/$(KERNEL_VERSION)/*.patch; do \ git apply --check --directory=kernel/$(KERNEL_VERSION) $$file > /dev/null 2>&1; \ @@ -72,6 +103,8 @@ patch_kernel: cp $(BUILDTOOLS_DIR)/patches/$(KERNEL_VERSION)/fragment-* kernel/$(KERNEL_VERSION)/arch/arm/configs touch $(KERNEL_DIR)/.scmversion +# setup fiptool to generate fip binary that packages u-boot for TF-A +# create bootfs deploy directory to store FSBL/SSBL and boot related files setup: PWD=$(FSBL_DIR)/tools/fiptool $(MAKE) -C $(FSBL_DIR)/tools/fiptool cp $(FSBL_DIR)/tools/fiptool/fiptool /bin/ @@ -81,8 +114,11 @@ setup: cp $(BUILDTOOLS_DIR)/files/flash-tools/create_sdcard_from_flashlayout.sh $(DEPLOY_DIR)/ patch --ignore-whitespace $(DEPLOY_DIR)/create_sdcard_from_flashlayout.sh $(BUILDTOOLS_DIR)/files/flash-tools/sdcard-script.patch -# First stage bootloader +# Build First stage bootloader # Add to if statement for custom board +# currently generating the binary is handled by Makefile.sdk in build-tools/files/fsbl/Makefile.sdk +# To add a custom board, update Makefile.sdk to add new machine name +# FSBL binary is copied to /deploy directory fsbl: setup patch_fsbl cp $(BUILDTOOLS_DIR)/files/fsbl/Makefile.sdk $(FSBL_DIR) PWD=$(FSBL_DIR) $(MAKE) $(FLAGS) -C $(FSBL_DIR) -f Makefile.sdk stm32 @@ -95,13 +131,17 @@ fsbl: setup patch_fsbl fi -# Second stage bootloader +# Build Second stage bootloader +# For custom boards, need to add machine name to build-tools/files/ssbl/Makefile.sdk +# SSBL binary is generated in /deploy directory ssbl: setup fsbl patch_ssbl cp $(BUILDTOOLS_DIR)/files/ssbl/boot.scr.cmd $(SSBL_DIR) cp $(BUILDTOOLS_DIR)/files/ssbl/Makefile.sdk $(SSBL_DIR) PWD=$(SSBL_DIR) FIP_DEPLOYDIR_FIP=$(DEPLOY_DIR) FIP_DEPLOYDIR_TFA=$(FIP_TFA_DIR) FIP_DEPLOYDIR_FWCONF=$(FIP_FWCONF_DIR) $(MAKE) $(FLAGS) -C $(SSBL_DIR) -f Makefile.sdk all UBOOT_CONFIG=trusted UBOOT_DEFCONFIG=stm32mp15_trusted_defconfig UBOOT_BINARY=u-boot.dtb FIP_CONFIG="trusted" FIP_BL32_CONF="tfa," DEVICETREE=$(BOARD_NAME) - +# Apply fragment configs +# Generate kernel binary and store in /deply/bootfs/ +# also copy the machine device tree to /deploy/bootfs/ kernel: setup patch_kernel $(MAKE) $(FLAGS) -C $(KERNEL_DIR) $(KDEFCONFIG) fragment*.config yes '' | $(MAKE) -C $(KERNEL_DIR) oldconfig @@ -110,6 +150,13 @@ kernel: setup patch_kernel mkimage -A arm -O linux -T kernel -C none -a 0xC2000040 -e 0xC2000040 -n "Linux kernel" -d $(KERNEL_DIR)/arch/arm/boot/zImage $(DEPLOY_DIR)/bootfs/uImage cp $(KERNEL_DIR)/arch/arm/boot/dts/$(BOARD_NAME).dtb $(DEPLOY_DIR)/bootfs + +# Create boot file system +# Contains: +# 1. Kernel Binary(uImage) +# 2. Machine device tree +# 3. board extlinux file for boot time configuration(Need to create for custom board) +# 4. boot script for u-boot and splash image bootfs: kernel # Generate extlinux files $(BUILDTOOLS_DIR)/$(BOARD_NAME)-extlinux.sh -d $(DEPLOY_DIR)/bootfs @@ -123,6 +170,7 @@ bootfs: kernel sync mkfs.ext4 -b 1024 -d $(DEPLOY_DIR)/bootfs -L bootfs $(DEPLOY_DIR)/octavo-bootfs-debian-lxqt-$(BOARD_NAME).ext4 +# Compile gcnano binaries for gpu gcnano: kernel if [ ! -d $(GCNANO_DRV_DIR)/ ]; then \ tar xvf $(GCNANO_DIR)/gcnano-driver-*.tar.xz -C $(GCNANO_DIR); \ @@ -138,6 +186,8 @@ gcnano: kernel # Signing out of tree galcore module $(KERNEL_DIR)/scripts/sign-file sha256 $(KERNEL_DIR)/certs/signing_key.pem $(KERNEL_DIR)/certs/signing_key.x509 $(GCNANO_DRV_DIR)/galcore.ko + +# Make rootfilesystem rootfs: kernel gcnano m4_demo $(MAKE) $(FLAGS) -C $(MULTISTRAP_DIR) all @@ -174,6 +224,13 @@ ifeq ($(BOARD_NAME), $(BOARD_RED)) cp $(BUILDTOOLS_DIR)/files/demo_red/OSD32MP1_RED_intro_360p.mp4 $(ROOTFS_DIR)/home/debian; endif + # Install demo files for OSD32MP1-RED-V12 +ifeq ($(BOARD_NAME), $(BOARD_RED_V12)) + cp $(BUILDTOOLS_DIR)/files/demo_red/demo_camera.sh $(ROOTFS_DIR)/home/debian; \ + cp $(BUILDTOOLS_DIR)/files/demo_red/demo_video.sh $(ROOTFS_DIR)/home/debian; \ + cp $(BUILDTOOLS_DIR)/files/demo_red/OSD32MP1_RED_intro_360p.mp4 $(ROOTFS_DIR)/home/debian; +endif + # Instll demo files for OSD32MP1-BRK ifeq ($(BOARD_NAME), $(BOARD_BRK)) mkdir -p $(ROOTFS_DIR)/usr/local/demo/; \ @@ -196,9 +253,8 @@ endif fi - - - +# Build vendor file system +# Contains GCNANO binaries vendorfs: setup gcnano dd if=/dev/zero of=$(DEPLOY_DIR)/octavo-vendorfs-debian-lxqt-$(BOARD_NAME).ext4 bs=1M count=16 sync @@ -210,12 +266,15 @@ vendorfs: setup gcnano mkfs.ext4 -b 1024 -d $(GCNANO_USR_DIR)/usr/ -L vendorfs $(DEPLOY_DIR)/octavo-vendorfs-debian-lxqt-$(BOARD_NAME).ext4 +# Build M4 projects from STM32MP1CUBE package m4_demo: setup if [ ! -d $(M4PROJECTS_DIR)/deploy ]; then \ cp $(BUILDTOOLS_DIR)/files/m4projects/* $(M4PROJECTS_DIR); \ cd $(M4PROJECTS_DIR) ; ./build_m4projects.sh; \ fi +# Build image +# Generate TSV handles eMMC and SD as per RED board interface definition image: fsbl ssbl bootfs rootfs vendorfs if [ $(BOOT_SD) -eq 1 ]; then \ $(DEPLOY_DIR)/generate_tsv.sh -b $(BOARD_NAME) -m $(MODE) -d 0; \ @@ -225,26 +284,31 @@ image: fsbl ssbl bootfs rootfs vendorfs $(DEPLOY_DIR)/generate_tsv.sh -b $(BOARD_NAME) -m $(MODE) -d 1; \ fi +# Build all all: ssbl fsbl bootfs rootfs vendorfs image +# Clean FSBL directory fsbl_clean: $(MAKE) $(FLAGS) -C $(FSBL_DIR) clean $(MAKE) $(FLAGS) -C $(FSBL_DIR) distclean git --git-dir=$(FSBL_DIR)/.git --work-tree=$(FSBL_DIR) reset --hard HEAD git --git-dir=$(FSBL_DIR)/.git --work-tree=$(FSBL_DIR) clean -f -d +# Clean SSBL directory ssbl_clean: $(MAKE) $(FLAGS) -C $(SSBL_DIR) clean $(MAKE) $(FLAGS) -C $(SSBL_DIR) distclean git --git-dir=$(SSBL_DIR)/.git --work-tree=$(SSBL_DIR) reset --hard HEAD git --git-dir=$(SSBL_DIR)/.git --work-tree=$(SSBL_DIR) clean -f -d +# Clean Kernel directory kernel_clean: $(MAKE) $(FLAGS) -C $(KERNEL_DIR) clean $(MAKE) $(FLAGS) -C $(KERNEL_DIR) distclean git --git-dir=$(KERNEL_DIR)/.git --work-tree=$(KERNEL_DIR) reset --hard HEAD git --git-dir=$(KERNEL_DIR)/.git --work-tree=$(KERNEL_DIR) clean -f -d +# Clean all clean: ssbl_clean fsbl_clean kernel_clean $(MAKE) $(FLAGS) -C $(MULTISTRAP_DIR) clean @rm -rf $(GCNANO_DRV_DIR) diff --git a/files/fsbl/Makefile.sdk b/files/fsbl/Makefile.sdk index aa9dbbd..755bd8f 100644 --- a/files/fsbl/Makefile.sdk +++ b/files/fsbl/Makefile.sdk @@ -28,13 +28,13 @@ TF_A_BINARY_optee ?= tf-a TF_A_MAKE_TARGET_optee ?= dtbs # Init default config settings -TF_A_DEVICETREE_trusted ?= stm32mp157a-dk1 stm32mp157d-dk1 stm32mp157c-dk2 stm32mp157f-dk2 stm32mp157c-ed1 stm32mp157f-ed1 stm32mp157a-ev1 stm32mp157c-ev1 stm32mp157d-ev1 stm32mp157f-ev1 stm32mp157c-osd32mp1-red stm32mp157c-osd32mp1-brk +TF_A_DEVICETREE_trusted ?= stm32mp157a-dk1 stm32mp157d-dk1 stm32mp157c-dk2 stm32mp157f-dk2 stm32mp157c-ed1 stm32mp157f-ed1 stm32mp157a-ev1 stm32mp157c-ev1 stm32mp157d-ev1 stm32mp157f-ev1 stm32mp157c-osd32mp1-red stm32mp157c-osd32mp1-brk stm32mp157c-osd32mp1-red-v1_2 TF_A_EXTRA_OPTFLAGS_trusted ?= AARCH32_SP=sp_min TF_A_BINARY_trusted ?= tf-a TF_A_MAKE_TARGET_trusted ?= bl32 dtbs # Init default config settings -TF_A_DEVICETREE_emmc ?= stm32mp157c-ed1 stm32mp157f-ed1 stm32mp157a-ev1 stm32mp157c-ev1 stm32mp157d-ev1 stm32mp157f-ev1 stm32mp157c-osd32mp1-red +TF_A_DEVICETREE_emmc ?= stm32mp157c-ed1 stm32mp157f-ed1 stm32mp157a-ev1 stm32mp157c-ev1 stm32mp157d-ev1 stm32mp157f-ev1 stm32mp157c-osd32mp1-red stm32mp157c-osd32mp1-red stm32mp157c-osd32mp1-red-v1_2 TF_A_EXTRA_OPTFLAGS_emmc ?= STM32MP_EMMC=1 TF_A_BINARY_emmc ?= tf-a TF_A_MAKE_TARGET_emmc ?= all @@ -52,19 +52,19 @@ TF_A_BINARY_nor ?= tf-a TF_A_MAKE_TARGET_nor ?= all # Init default config settings -TF_A_DEVICETREE_sdcard ?= stm32mp157a-dk1 stm32mp157d-dk1 stm32mp157c-dk2 stm32mp157f-dk2 stm32mp157c-ed1 stm32mp157f-ed1 stm32mp157a-ev1 stm32mp157c-ev1 stm32mp157d-ev1 stm32mp157f-ev1 stm32mp157c-osd32mp1-red stm32mp157c-osd32mp1-brk +TF_A_DEVICETREE_sdcard ?= stm32mp157a-dk1 stm32mp157d-dk1 stm32mp157c-dk2 stm32mp157f-dk2 stm32mp157c-ed1 stm32mp157f-ed1 stm32mp157a-ev1 stm32mp157c-ev1 stm32mp157d-ev1 stm32mp157f-ev1 stm32mp157c-osd32mp1-red stm32mp157c-osd32mp1-brk stm32mp157c-osd32mp1-red-v1_2 TF_A_EXTRA_OPTFLAGS_sdcard ?= STM32MP_SDMMC=1 TF_A_BINARY_sdcard ?= tf-a TF_A_MAKE_TARGET_sdcard ?= all # Init default config settings -TF_A_DEVICETREE_uart ?= stm32mp157a-dk1 stm32mp157d-dk1 stm32mp157c-dk2 stm32mp157f-dk2 stm32mp157c-ed1 stm32mp157f-ed1 stm32mp157a-ev1 stm32mp157c-ev1 stm32mp157d-ev1 stm32mp157f-ev1 stm32mp157c-osd32mp1-red stm32mp157c-osd32mp1-brk +TF_A_DEVICETREE_uart ?= stm32mp157a-dk1 stm32mp157d-dk1 stm32mp157c-dk2 stm32mp157f-dk2 stm32mp157c-ed1 stm32mp157f-ed1 stm32mp157a-ev1 stm32mp157c-ev1 stm32mp157d-ev1 stm32mp157f-ev1 stm32mp157c-osd32mp1-red stm32mp157c-osd32mp1-brk stm32mp157c-osd32mp1-red-v1_2 TF_A_EXTRA_OPTFLAGS_uart ?= STM32MP_UART_PROGRAMMER=1 TF_A_BINARY_uart ?= tf-a TF_A_MAKE_TARGET_uart ?= all # Init default config settings -TF_A_DEVICETREE_usb ?= stm32mp157a-dk1 stm32mp157d-dk1 stm32mp157c-dk2 stm32mp157f-dk2 stm32mp157c-ed1 stm32mp157f-ed1 stm32mp157a-ev1 stm32mp157c-ev1 stm32mp157d-ev1 stm32mp157f-ev1 stm32mp157c-osd32mp1-red stm32mp157c-osd32mp1-brk +TF_A_DEVICETREE_usb ?= stm32mp157a-dk1 stm32mp157d-dk1 stm32mp157c-dk2 stm32mp157f-dk2 stm32mp157c-ed1 stm32mp157f-ed1 stm32mp157a-ev1 stm32mp157c-ev1 stm32mp157d-ev1 stm32mp157f-ev1 stm32mp157c-osd32mp1-red stm32mp157c-osd32mp1-brk stm32mp157c-osd32mp1-red-v1_2 TF_A_EXTRA_OPTFLAGS_usb ?= STM32MP_USB_PROGRAMMER=1 TF_A_BINARY_usb ?= tf-a TF_A_MAKE_TARGET_usb ?= all @@ -83,7 +83,7 @@ NM = EXTRA_OEMAKE ?= CROSS_COMPILE=arm-linux-gnueabihf- DEBUG=1 LOG_LEVEL=40 PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 # Configure overall devicetree list for FIP -TF_A_DEVICETREE_ALL = stm32mp157a-dk1 stm32mp157a-ev1 stm32mp157c-dk2 stm32mp157c-ed1 stm32mp157c-ev1 stm32mp157d-dk1 stm32mp157d-ev1 stm32mp157f-dk2 stm32mp157f-ed1 stm32mp157f-ev1 stm32mp157c-osd32mp1-red stm32mp157c-osd32mp1-brk +TF_A_DEVICETREE_ALL = stm32mp157a-dk1 stm32mp157a-ev1 stm32mp157c-dk2 stm32mp157c-ed1 stm32mp157c-ev1 stm32mp157d-dk1 stm32mp157d-ev1 stm32mp157f-dk2 stm32mp157f-ed1 stm32mp157f-ev1 stm32mp157c-osd32mp1-red stm32mp157c-osd32mp1-brk stm32mp157c-osd32mp1-red-v1_2 # Display TF-A config details define tf-configs diff --git a/files/rootfs/fstab_emmc_stm32mp157c-osd32mp1-red-v1_2 b/files/rootfs/fstab_emmc_stm32mp157c-osd32mp1-red-v1_2 new file mode 100644 index 0000000..9caa556 --- /dev/null +++ b/files/rootfs/fstab_emmc_stm32mp157c-osd32mp1-red-v1_2 @@ -0,0 +1,7 @@ +/dev/root / auto defaults 1 1 +proc /proc proc defaults 0 0 +devpts /dev/pts devpts mode=0620,gid=5 0 0 +tmpfs /run tmpfs mode=0755,nodev,nosuid,strictatime 0 0 +tmpfs /var/volatile tmpfs defaults 0 0 +/dev/mmcblk2p2 /boot ext4 defaults,sync 0 1 +/dev/mmcblk2p3 /vendor ext4 defaults,sync 0 1 diff --git a/files/rootfs/fstab_sdcard_stm32mp157c-osd32mp1-red-v1_2 b/files/rootfs/fstab_sdcard_stm32mp157c-osd32mp1-red-v1_2 new file mode 100644 index 0000000..26f3ded --- /dev/null +++ b/files/rootfs/fstab_sdcard_stm32mp157c-osd32mp1-red-v1_2 @@ -0,0 +1,7 @@ +/dev/root / auto defaults 1 1 +proc /proc proc defaults 0 0 +devpts /dev/pts devpts mode=0620,gid=5 0 0 +tmpfs /run tmpfs mode=0755,nodev,nosuid,strictatime 0 0 +tmpfs /var/volatile tmpfs defaults 0 0 +/dev/mmcblk1p4 /boot ext4 defaults,sync 0 1 +/dev/mmcblk1p5 /vendor ext4 defaults,sync 0 1 diff --git a/files/ssbl/Makefile.sdk b/files/ssbl/Makefile.sdk index b5bdf4f..6e7bae2 100644 --- a/files/ssbl/Makefile.sdk +++ b/files/ssbl/Makefile.sdk @@ -12,7 +12,7 @@ UBOOT_LOCALVERSION = # Configure default U-Boot configs UBOOT_CONFIGS ?= stm32mp15_trusted_defconfig,trusted,u-boot.dtb stm32mp15_basic_defconfig,basic,u-boot.img -DEVICE_TREE ?= stm32mp157a-dk1 stm32mp157d-dk1 stm32mp157c-dk2 stm32mp157f-dk2 stm32mp157c-ed1 stm32mp157f-ed1 stm32mp157a-ev1 stm32mp157c-ev1 stm32mp157d-ev1 stm32mp157f-ev1 stm32mp157c-osd32mp1-red stm32mp157c-osd32mp1-brk +DEVICE_TREE ?= stm32mp157a-dk1 stm32mp157d-dk1 stm32mp157c-dk2 stm32mp157f-dk2 stm32mp157c-ed1 stm32mp157f-ed1 stm32mp157a-ev1 stm32mp157c-ev1 stm32mp157d-ev1 stm32mp157f-ev1 stm32mp157c-osd32mp1-red stm32mp157c-osd32mp1-brk stm32mp157c-osd32mp1-red-v1_2 # Configure default fip feature ENABLE_FIP ?= "1" diff --git a/patches/arm-trusted-firmware-2.4/0003-Fix-device-tree-for-800MHz-speedgrade-MP1-to-work-wi.patch b/patches/arm-trusted-firmware-2.4/0003-Fix-device-tree-for-800MHz-speedgrade-MP1-to-work-wi.patch new file mode 100644 index 0000000..1c9027d --- /dev/null +++ b/patches/arm-trusted-firmware-2.4/0003-Fix-device-tree-for-800MHz-speedgrade-MP1-to-work-wi.patch @@ -0,0 +1,25 @@ +From 9a7e86d095a1bcd15cace673bac2536a036a59d0 Mon Sep 17 00:00:00 2001 +From: Neeraj Dantu +Date: Tue, 22 Nov 2022 17:05:56 -0600 +Subject: [PATCH] Fix device tree for 800MHz speedgrade MP1 to work with 650MHz + config + +--- + fdts/stm32mp15xa.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/fdts/stm32mp15xa.dtsi b/fdts/stm32mp15xa.dtsi +index 5ed7e594f..59da3e5dc 100644 +--- a/fdts/stm32mp15xa.dtsi ++++ b/fdts/stm32mp15xa.dtsi +@@ -8,6 +8,6 @@ + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + opp-microvolt = <1200000>; +- opp-supported-hw = <0x1>; ++ opp-supported-hw = <0x1 0x2>; + }; + }; +-- +2.25.1 + diff --git a/patches/arm-trusted-firmware-2.4/0004-Add-OSD32MP1-RED-V1_2-Device-tree-support.patch b/patches/arm-trusted-firmware-2.4/0004-Add-OSD32MP1-RED-V1_2-Device-tree-support.patch new file mode 100644 index 0000000..4dda5a0 --- /dev/null +++ b/patches/arm-trusted-firmware-2.4/0004-Add-OSD32MP1-RED-V1_2-Device-tree-support.patch @@ -0,0 +1,604 @@ +From 761541466cdb52b914904e332b196a0e5ffb6567 Mon Sep 17 00:00:00 2001 +From: Neeraj Dantu +Date: Tue, 24 Jan 2023 15:14:00 -0600 +Subject: [PATCH] Add OSD32MP1-RED V1_2 Device tree support + +--- + ...tm32mp157c-osd32mp1-red-v1_2-fw-config.dts | 6 + + fdts/stm32mp157c-osd32mp1-red-v1_2.dts | 571 ++++++++++++++++++ + 2 files changed, 577 insertions(+) + create mode 100644 fdts/stm32mp157c-osd32mp1-red-v1_2-fw-config.dts + create mode 100644 fdts/stm32mp157c-osd32mp1-red-v1_2.dts + +diff --git a/fdts/stm32mp157c-osd32mp1-red-v1_2-fw-config.dts b/fdts/stm32mp157c-osd32mp1-red-v1_2-fw-config.dts +new file mode 100644 +index 000000000..256d0db93 +--- /dev/null ++++ b/fdts/stm32mp157c-osd32mp1-red-v1_2-fw-config.dts +@@ -0,0 +1,6 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * Copyright (c) 2020, STMicroelectronics - All Rights Reserved ++ */ ++ ++#include "stm32mp15-ddr-512m-fw-config.dts" +diff --git a/fdts/stm32mp157c-osd32mp1-red-v1_2.dts b/fdts/stm32mp157c-osd32mp1-red-v1_2.dts +new file mode 100644 +index 000000000..b2e00e1af +--- /dev/null ++++ b/fdts/stm32mp157c-osd32mp1-red-v1_2.dts +@@ -0,0 +1,571 @@ ++/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ ++/* ++ * Copyright (C) STMicroelectronics 2020 - All Rights Reserved ++ * Author: STM32CubeMX code generation for STMicroelectronics. ++ */ ++ ++/dts-v1/; ++#include ++#include ++#include ++#include ++ ++#include "stm32mp157.dtsi" ++#include "stm32mp15xc.dtsi" ++#include "stm32mp15xxac-pinctrl.dtsi" ++#include "osd32mp1_ddr_1x4Gb.dtsi" ++ ++/ { ++ model = "Octavo OSD32MP1 RED board"; ++ compatible = "octavo,stm32mp157c-osd32mp1-red-v1_2", "st,stm32mp157"; ++ ++ aliases { ++ serial0 = &uart4; ++ }; ++ ++ memory@c0000000 { ++ device_type = "memory"; ++ reg = <0xc0000000 0x20000000>; ++ }; ++ ++ vin: vin { ++ compatible = "regulator-fixed"; ++ regulator-name = "vin"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++}; ++ ++&bsec { ++ board_id: board_id@ec { ++ reg = <0xec 0x4>; ++ st,non-secure-otp; ++ }; ++}; ++ ++&clk_hse { ++ st,digbypass; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vddcore>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vddcore>; ++}; ++ ++&hash1 { ++ status = "okay"; ++}; ++ ++&cryp1 { ++ status = "okay"; ++}; ++ ++&etzpc { ++ st,decprot = < ++ DECPROT(STM32MP1_ETZPC_DCMI_ID, DECPROT_NS_RW, DECPROT_UNLOCK) ++ DECPROT(STM32MP1_ETZPC_ETH_ID, DECPROT_NS_RW, DECPROT_UNLOCK) ++ DECPROT(STM32MP1_ETZPC_USART1_ID, DECPROT_NS_RW, DECPROT_UNLOCK) ++ DECPROT(STM32MP1_ETZPC_SPI6_ID, DECPROT_NS_RW, DECPROT_UNLOCK) ++ DECPROT(STM32MP1_ETZPC_I2C4_ID, DECPROT_NS_RW, DECPROT_UNLOCK) ++ DECPROT(STM32MP1_ETZPC_SPI2_ID, DECPROT_NS_RW, DECPROT_UNLOCK) ++ DECPROT(STM32MP1_ETZPC_I2C6_ID, DECPROT_NS_RW, DECPROT_UNLOCK) ++ DECPROT(STM32MP1_ETZPC_RNG1_ID, DECPROT_NS_RW, DECPROT_UNLOCK) ++ DECPROT(STM32MP1_ETZPC_HASH1_ID, DECPROT_NS_RW, DECPROT_UNLOCK) ++ DECPROT(STM32MP1_ETZPC_CRYP1_ID, DECPROT_NS_RW, DECPROT_UNLOCK) ++ DECPROT(STM32MP1_ETZPC_DDRCTRL_ID, DECPROT_NS_R_S_W, DECPROT_LOCK) ++ DECPROT(STM32MP1_ETZPC_DDRPHYC_ID, DECPROT_NS_R_S_W, DECPROT_LOCK) ++ DECPROT(STM32MP1_ETZPC_STGENC_ID, DECPROT_S_RW, DECPROT_LOCK) ++ DECPROT(STM32MP1_ETZPC_BKPSRAM_ID, DECPROT_S_RW, DECPROT_LOCK) ++ DECPROT(STM32MP1_ETZPC_IWDG1_ID, DECPROT_S_RW, DECPROT_LOCK) ++ >; ++}; ++ ++ ++ ++&i2c4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c4_pins_z_mx>; ++ i2c-scl-rising-time-ns = <185>; ++ i2c-scl-falling-time-ns = <20>; ++ clock-frequency = <400000>; ++ status = "okay"; ++ secure-status = "okay"; ++ ++ pmic: stpmic@33 { ++ compatible = "st,stpmic1"; ++ reg = <0x33>; ++ interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ status = "okay"; ++ secure-status = "okay"; ++ ++ regulators { ++ compatible = "st,stpmic1-regulators"; ++ buck1-supply = <&vin>; ++ buck2-supply = <&vin>; ++ buck3-supply = <&vin>; ++ buck4-supply = <&vin>; ++ ldo1-supply = <&v3v3>; ++ ldo2-supply = <&vin>; ++ ldo3-supply = <&vdd_ddr>; ++ ldo4-supply = <&vin>; ++ ldo5-supply = <&vin>; ++ ldo6-supply = <&v3v3>; ++ vref_ddr-supply = <&vin>; ++ boost-supply = <&vin>; ++ pwr_sw1-supply = <&bst_out>; ++ pwr_sw2-supply = <&bst_out>; ++ ++ vddcore: buck1 { ++ regulator-name = "vddcore"; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-always-on; ++ regulator-initial-mode = <0>; ++ regulator-over-current-protection; ++ lp-stop{ ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1200000>; ++ }; ++ standby-ddr-sr{ ++ regulator-off-in-suspend; ++ }; ++ standby-ddr-off{ ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_ddr: buck2 { ++ regulator-name = "vdd_ddr"; ++ regulator-min-microvolt = <1350000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-always-on; ++ regulator-initial-mode = <0>; ++ regulator-over-current-protection; ++ lp-stop{ ++ regulator-suspend-microvolt = <1350000>; ++ regulator-on-in-suspend; ++ }; ++ standby-ddr-sr{ ++ regulator-suspend-microvolt = <1350000>; ++ regulator-on-in-suspend; ++ }; ++ standby-ddr-off{ ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd: buck3 { ++ regulator-name = "vdd"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ st,mask-reset; ++ regulator-initial-mode = <0>; ++ regulator-over-current-protection; ++ lp-stop{ ++ regulator-suspend-microvolt = <3300000>; ++ regulator-on-in-suspend; ++ }; ++ standby-ddr-sr{ ++ regulator-suspend-microvolt = <3300000>; ++ regulator-on-in-suspend; ++ }; ++ standby-ddr-off{ ++ regulator-suspend-microvolt = <3300000>; ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ v3v3: buck4 { ++ regulator-name = "v3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-over-current-protection; ++ regulator-initial-mode = <0>; ++ lp-stop{ ++ regulator-suspend-microvolt = <3300000>; ++ regulator-on-in-suspend; ++ }; ++ standby-ddr-sr{ ++ regulator-off-in-suspend; ++ }; ++ standby-ddr-off{ ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ v1v8_ldo1: ldo1 { ++ regulator-name = "v1v8_audio"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ standby-ddr-sr{ ++ regulator-off-in-suspend; ++ }; ++ standby-ddr-off{ ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ v3v3_ldo2: ldo2 { ++ regulator-name = "v3v3_hdmi"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ standby-ddr-sr{ ++ regulator-off-in-suspend; ++ }; ++ standby-ddr-off{ ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vtt_ddr: ldo3 { ++ regulator-name = "vtt_ddr"; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <750000>; ++ regulator-always-on; ++ regulator-over-current-protection; ++ lp-stop{ ++ regulator-off-in-suspend; ++ }; ++ standby-ddr-sr{ ++ regulator-off-in-suspend; ++ }; ++ standby-ddr-off{ ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_usb: ldo4 { ++ regulator-name = "vdd_usb"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ standby-ddr-sr{ ++ regulator-on-in-suspend; ++ }; ++ standby-ddr-off{ ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda: ldo5 { ++ regulator-name = "vdda"; ++ regulator-min-microvolt = <2900000>; ++ regulator-max-microvolt = <2900000>; ++ regulator-boot-on; ++ standby-ddr-sr{ ++ regulator-off-in-suspend; ++ }; ++ standby-ddr-off{ ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ v1v2_ldo6: ldo6 { ++ regulator-name = "v1v2_ldo6"; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-always-on; ++ standby-ddr-sr{ ++ regulator-off-in-suspend; ++ }; ++ standby-ddr-off{ ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vref_ddr: vref_ddr { ++ regulator-name = "vref_ddr"; ++ regulator-always-on; ++ regulator-over-current-protection; ++ lp-stop{ ++ regulator-on-in-suspend; ++ }; ++ standby-ddr-sr{ ++ regulator-on-in-suspend; ++ }; ++ standby-ddr-off{ ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ bst_out: boost { ++ regulator-name = "bst_out"; ++ }; ++ ++ vbus_otg: pwr_sw1 { ++ regulator-name = "vbus_otg"; ++ }; ++ ++ vbus_sw: pwr_sw2 { ++ regulator-name = "vbus_sw"; ++ regulator-active-discharge = <1>; ++ }; ++ }; ++ }; ++}; ++ ++&iwdg2 { ++ timeout-sec = <32>; ++ secure-timeout-sec = <5>; ++ status = "okay"; ++ secure-status = "okay"; ++}; ++ ++&nvmem_layout { ++ nvmem-cells = <&cfg0_otp>, ++ <&part_number_otp>, ++ <&monotonic_otp>, ++ <&nand_otp>, ++ <&uid_otp>, ++ <&package_otp>, ++ <&hw2_otp>, ++ <&pkh_otp>, ++ <&board_id>; ++ ++ nvmem-cell-names = "cfg0_otp", ++ "part_number_otp", ++ "monotonic_otp", ++ "nand_otp", ++ "uid_otp", ++ "package_otp", ++ "hw2_otp", ++ "pkh_otp", ++ "board_id"; ++}; ++ ++&pwr_regulators { ++ system_suspend_supported_soc_modes = < ++ STM32_PM_CSLEEP_RUN ++ STM32_PM_CSTOP_ALLOW_LP_STOP ++ STM32_PM_CSTOP_ALLOW_STANDBY_DDR_SR ++ >; ++ system_off_soc_mode = ; ++ vdd-supply = <&vdd>; ++ vdd_3v3_usbfs-supply = <&vdd_usb>; ++}; ++ ++&rcc { ++ st,hsi-cal; ++ st,csi-cal; ++ st,cal-sec = <60>; ++ st,clksrc = < ++ CLK_MPU_PLL1P ++ CLK_AXI_PLL2P ++ CLK_MCU_PLL3P ++ CLK_PLL12_HSE ++ CLK_PLL3_HSE ++ CLK_PLL4_HSE ++ CLK_RTC_LSE ++ CLK_MCO1_DISABLED ++ CLK_MCO2_DISABLED ++ >; ++ ++ st,clkdiv = < ++ 1 /*MPU*/ ++ 0 /*AXI*/ ++ 0 /*MCU*/ ++ 1 /*APB1*/ ++ 1 /*APB2*/ ++ 1 /*APB3*/ ++ 1 /*APB4*/ ++ 2 /*APB5*/ ++ 23 /*RTC*/ ++ 0 /*MCO1*/ ++ 0 /*MCO2*/ ++ >; ++ ++ st,pkcs = < ++ CLK_CKPER_HSE ++ CLK_ETH_DISABLED ++ CLK_SDMMC12_PLL4P ++ CLK_DSI_DSIPLL ++ CLK_STGEN_HSE ++ CLK_USBPHY_HSE ++ CLK_SPI2S1_PLL3Q ++ CLK_SPI2S23_CKPER ++ CLK_SPI45_PCLK2 ++ CLK_SPI6_DISABLED ++ CLK_I2C46_HSI ++ CLK_SDMMC3_PLL4P ++ CLK_USBO_USBPHY ++ CLK_ADC_CKPER ++ CLK_CEC_LSE ++ CLK_I2C12_HSI ++ CLK_I2C35_HSI ++ CLK_UART1_DISABLED ++ CLK_UART24_HSI ++ CLK_UART35_HSI ++ CLK_UART6_DISABLED ++ CLK_UART78_DISABLED ++ CLK_SPDIF_DISABLED ++ CLK_SAI1_DISABLED ++ CLK_SAI2_DISABLED ++ CLK_SAI3_DISABLED ++ CLK_SAI4_DISABLED ++ CLK_RNG1_LSI ++ CLK_LPTIM1_DISABLED ++ CLK_LPTIM23_DISABLED ++ CLK_LPTIM45_DISABLED ++ >; ++ ++ pll1:st,pll@0 { ++ cfg = < 2 80 0 1 1 PQR(1,0,0) >; ++ frac = < 0x800>; ++ }; ++ ++ pll2:st,pll@1 { ++ cfg = < 2 65 1 0 0 PQR(1,1,1) >; ++ frac = < 0x1400>; ++ }; ++ ++ pll3:st,pll@2 { ++ cfg = < 1 61 3 5 36 PQR(1,1,0) >; ++ frac = < 0x1000 >; ++ }; ++ ++ pll4: st,pll@3 { ++ cfg = < 3 98 5 7 7 PQR(1,1,1) >; ++ }; ++}; ++ ++&rng1 { ++ status = "okay"; ++ secure-status = "okay"; ++}; ++ ++&rtc { ++ status = "okay"; ++ secure-status = "okay"; ++}; ++ ++&sdmmc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc1_pins_mx>; ++ disable-wp; ++ st,neg-edge; ++ bus-width = <4>; ++ vmmc-supply = <&v3v3>; ++ status = "okay"; ++}; ++ ++&sdmmc2{ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc2_pins_mx>; ++ status = "okay"; ++}; ++ ++&timers15 { ++ secure-status = "okay"; ++ st,hsi-cal-input = <7>; ++ st,csi-cal-input = <8>; ++}; ++&uart4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart4_pins_mx>; ++ status = "okay"; ++}; ++ ++&usbotg_hs { ++ phys = <&usbphyc_port1 0>; ++ phy-names = "usb2-phy"; ++ usb-role-switch; ++ status = "okay"; ++}; ++ ++&usbphyc { ++ status = "okay"; ++}; ++ ++&usbphyc_port0 { ++ phy-supply = <&vdd_usb>; ++}; ++ ++&usbphyc_port1 { ++ phy-supply = <&vdd_usb>; ++}; ++ ++ ++ ++ ++&pinctrl { ++ sdmmc1_pins_mx: sdmmc1-b4-0 { ++ pins1 { ++ pinmux = , /* SDMMC1_D0 */ ++ , /* SDMMC1_D1 */ ++ , /* SDMMC1_D2 */ ++ , /* SDMMC1_D3 */ ++ ; /* SDMMC1_CMD */ ++ slew-rate = <1>; ++ drive-push-pull; ++ bias-disable; ++ }; ++ pins2 { ++ pinmux = ; /* SDMMC1_CK */ ++ slew-rate = <2>; ++ drive-push-pull; ++ bias-disable; ++ }; ++ }; ++ ++ sdmmc2_pins_mx: sdmmc2_mx-0 { ++ pins1 { ++ pinmux = , /* SDMMC2_D4 */ ++ , /* SDMMC2_D5 */ ++ , /* SDMMC2_D2 */ ++ , /* SDMMC2_D3 */ ++ , /* SDMMC2_D0 */ ++ , /* SDMMC2_D1 */ ++ , /* SDMMC2_D7 */ ++ , /* SDMMC2_D6 */ ++ ; /* SDMMC2_CMD */ ++ bias-pull-up; ++ drive-push-pull; ++ slew-rate = <1>; ++ }; ++ pins2 { ++ pinmux = ; /* SDMMC2_CK */ ++ bias-pull-up; ++ drive-push-pull; ++ slew-rate = <2>; ++ }; ++ }; ++ ++ uart4_pins_mx: uart4-0 { ++ pins1 { ++ pinmux = ; /* UART4_TX */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <0>; ++ }; ++ pins2 { ++ pinmux = ; /* UART4_RX */ ++ bias-disable; ++ }; ++ }; ++}; ++ ++&pinctrl_z { ++ i2c4_pins_z_mx: i2c4-0 { ++ pins { ++ pinmux = , /* I2C4_SCL */ ++ ; /* I2C4_SDA */ ++ bias-disable; ++ drive-open-drain; ++ slew-rate = <0>; ++ }; ++ }; ++}; +-- +2.25.1 + diff --git a/patches/linux-5.10/0025-Fix-device-tree-for-800MHz-speedgrade-MP1-to-work-wi.patch b/patches/linux-5.10/0025-Fix-device-tree-for-800MHz-speedgrade-MP1-to-work-wi.patch new file mode 100644 index 0000000..57b8667 --- /dev/null +++ b/patches/linux-5.10/0025-Fix-device-tree-for-800MHz-speedgrade-MP1-to-work-wi.patch @@ -0,0 +1,24 @@ +From 600078f67600a30c5f2a23a268540aea10b40d19 Mon Sep 17 00:00:00 2001 +From: Neeraj Dantu +Date: Tue, 22 Nov 2022 17:15:26 -0600 +Subject: [PATCH] Fix device tree for 800MHz speedgrade MP1 to work with 650MHz + +--- + arch/arm/boot/dts/stm32mp15xa.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/stm32mp15xa.dtsi b/arch/arm/boot/dts/stm32mp15xa.dtsi +index 5ed7e594f4cd..59da3e5dc824 100644 +--- a/arch/arm/boot/dts/stm32mp15xa.dtsi ++++ b/arch/arm/boot/dts/stm32mp15xa.dtsi +@@ -8,6 +8,6 @@ &cpu0_opp_table { + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + opp-microvolt = <1200000>; +- opp-supported-hw = <0x1>; ++ opp-supported-hw = <0x1 0x2>; + }; + }; +-- +2.25.1 + diff --git a/patches/linux-5.10/0026-Add-OSD32MP1-RED-V1_2-Device-tree-support.patch b/patches/linux-5.10/0026-Add-OSD32MP1-RED-V1_2-Device-tree-support.patch new file mode 100644 index 0000000..3daee02 --- /dev/null +++ b/patches/linux-5.10/0026-Add-OSD32MP1-RED-V1_2-Device-tree-support.patch @@ -0,0 +1,1466 @@ +From 7dc74585c077d4b4b8fbde34f0d09af744677a94 Mon Sep 17 00:00:00 2001 +From: Neeraj Dantu +Date: Tue, 24 Jan 2023 16:03:02 -0600 +Subject: [PATCH] Add OSD32MP1-RED V1_2 Device tree support + +--- + arch/arm/boot/dts/Makefile | 3 +- + .../dts/stm32mp157c-osd32mp1-red-v1_2.dts | 1432 +++++++++++++++++ + 2 files changed, 1434 insertions(+), 1 deletion(-) + create mode 100644 arch/arm/boot/dts/stm32mp157c-osd32mp1-red-v1_2.dts + +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index 901ef5f30..c53d6746b 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -1120,7 +1120,8 @@ dtb-$(CONFIG_ARCH_STM32) += \ + stm32mp157c-lxa-mc1.dtb \ + stm32mp157c-odyssey.dtb \ + stm32mp157c-osd32mp1-brk.dtb \ +- stm32mp157c-osd32mp1-red.dtb ++ stm32mp157c-osd32mp1-red.dtb \ ++ stm32mp157c-osd32mp1-red-v1_2.dtb + dtb-$(CONFIG_MACH_SUN4I) += \ + sun4i-a10-a1000.dtb \ + sun4i-a10-ba10-tvbox.dtb \ +diff --git a/arch/arm/boot/dts/stm32mp157c-osd32mp1-red-v1_2.dts b/arch/arm/boot/dts/stm32mp157c-osd32mp1-red-v1_2.dts +new file mode 100644 +index 000000000..a930ca6a3 +--- /dev/null ++++ b/arch/arm/boot/dts/stm32mp157c-osd32mp1-red-v1_2.dts +@@ -0,0 +1,1432 @@ ++/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ ++/* ++ * Copyright (C) Octavo Systems 2021 - All Rights Reserved ++ * Author: Neeraj Dantu for Octavo Systems ++ */ ++ ++/dts-v1/; ++ ++#include ++#include "stm32mp157.dtsi" ++#include "stm32mp15xc.dtsi" ++#include "stm32mp15xxac-pinctrl.dtsi" ++#include "stm32mp15-m4-srm.dtsi" ++#include ++#include ++#include ++ ++/ { ++ model = "Octavo OSD32MP1 RED board"; ++ compatible = "octavo,stm32mp157c-osd32mp1-red-v1_2", "st,stm32mp157"; ++ ++ memory@c0000000 { ++ device_type = "memory"; ++ reg = <0xc0000000 0x20000000>; ++ }; ++ ++ wifi_pwrseq: wifi-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&gpiog 5 GPIO_ACTIVE_LOW>; ++ }; ++ ++ clocks { ++ clk_ext_camera: clk-ext-camera { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++ }; ++ }; ++ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ mcuram2:mcuram2@10000000{ ++ compatible = "shared-dma-pool"; ++ reg = <0x10000000 0x40000>; ++ no-map; ++ }; ++ ++ vdev0vring0:vdev0vring0@10040000{ ++ compatible = "shared-dma-pool"; ++ reg = <0x10040000 0x1000>; ++ no-map; ++ }; ++ ++ vdev0vring1:vdev0vring1@10041000{ ++ compatible = "shared-dma-pool"; ++ reg = <0x10041000 0x1000>; ++ no-map; ++ }; ++ ++ vdev0buffer:vdev0buffer@10042000{ ++ compatible = "shared-dma-pool"; ++ reg = <0x10042000 0x4000>; ++ no-map; ++ }; ++ ++ mcuram:mcuram@30000000{ ++ compatible = "shared-dma-pool"; ++ reg = <0x30000000 0x40000>; ++ no-map; ++ }; ++ ++ retram:retram@38000000{ ++ compatible = "shared-dma-pool"; ++ reg = <0x38000000 0x10000>; ++ no-map; ++ }; ++ ++ gpu_reserved:gpu@d4000000{ ++ reg = <0xd4000000 0x4000000>; ++ no-map; ++ }; ++ }; ++ ++ ++ aliases { ++ ethernet0 = ðernet0; ++ serial0 = &uart4; ++ serial1 = &usart3; ++ serial2 = &uart7; ++ serial3 = &usart2; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ led { ++ compatible = "gpio-leds"; ++ blue { ++ label = "heartbeat"; ++ gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ default-state = "off"; ++ }; ++ }; ++ ++ usb_phy_tuning:usb-phy-tuning{ ++ st,hs-dc-level = <2>; ++ st,fs-rftime-tuning; ++ st,hs-rftime-reduction; ++ st,hs-current-trim = <15>; ++ st,hs-impedance-trim = <1>; ++ st,squelch-level = <3>; ++ st,hs-rx-offset = <2>; ++ st,no-lsfs-sc; ++ }; ++ ++ vin:vin{ ++ compatible = "regulator-fixed"; ++ regulator-name = "vin"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ sound { ++ compatible = "audio-graph-card"; ++ label = "STM32MP15-DK"; ++ routing = ++ "Playback" , "MCLK", ++ "Capture" , "MCLK", ++ "MICL" , "Mic Bias"; ++ dais = <&i2s2_port>; ++ status = "okay"; ++ }; ++}; ++ ++&pinctrl { ++ u-boot,dm-pre-reloc; ++ dcmi_pins_mx: dcmi_mx-0 { ++ pins { ++ pinmux = , /* DCMI_HSYNC */ ++ , /* DCMI_PIXCLK */ ++ , /* DCMI_D1 */ ++ , /* DCMI_D7 */ ++ , /* DCMI_D0 */ ++ , /* DCMI_D2 */ ++ , /* DCMI_D3 */ ++ , /* DCMI_D4 */ ++ , /* DCMI_D6 */ ++ , /* DCMI_VSYNC */ ++ , /* DCMI_D8 */ ++ , /* DCMI_D9 */ ++ , /* DCMI_D11 */ ++ , /* DCMI_D10 */ ++ ; /* DCMI_D5 */ ++ bias-disable; ++ }; ++ }; ++ ++ dcmi_sleep_pins_mx: dcmi_sleep_mx-0 { ++ pins { ++ pinmux = , /* DCMI_HSYNC */ ++ , /* DCMI_PIXCLK */ ++ , /* DCMI_D1 */ ++ , /* DCMI_D7 */ ++ , /* DCMI_D0 */ ++ , /* DCMI_D2 */ ++ , /* DCMI_D3 */ ++ , /* DCMI_D4 */ ++ , /* DCMI_D6 */ ++ , /* DCMI_VSYNC */ ++ , /* DCMI_D8 */ ++ , /* DCMI_D9 */ ++ , /* DCMI_D11 */ ++ , /* DCMI_D10 */ ++ ; /* DCMI_D5 */ ++ }; ++ }; ++ ++ eth1_pins_mx: eth1_mx-0 { ++ pins1 { ++ pinmux = , /* ETH1_REF_CLK */ ++ , /* ETH1_CRS_DV */ ++ , /* ETH1_RXD0 */ ++ ; /* ETH1_RXD1 */ ++ bias-disable; ++ }; ++ pins2 { ++ pinmux = ; /* ETH1_MDIO */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <0>; ++ }; ++ pins3 { ++ pinmux = , /* ETH1_TX_EN */ ++ , /* ETH1_MDC */ ++ , /* ETH1_TXD0 */ ++ ; /* ETH1_TXD1 */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <2>; ++ }; ++ }; ++ ++ eth1_sleep_pins_mx: eth1_sleep_mx-0 { ++ pins { ++ pinmux = , /* ETH1_REF_CLK */ ++ , /* ETH1_MDIO */ ++ , /* ETH1_CRS_DV */ ++ , /* ETH1_TX_EN */ ++ , /* ETH1_MDC */ ++ , /* ETH1_RXD0 */ ++ , /* ETH1_RXD1 */ ++ , /* ETH1_TXD0 */ ++ ; /* ETH1_TXD1 */ ++ }; ++ }; ++ ++ i2c1_pins_mx: i2c1_mx-0 { ++ pins { ++ pinmux = , /* I2C1_SCL */ ++ ; /* I2C1_SDA */ ++ bias-disable; ++ drive-open-drain; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ i2c1_sleep_pins_mx: i2c1_sleep_mx-0 { ++ pins { ++ pinmux = , /* I2C1_SCL */ ++ ; /* I2C1_SDA */ ++ }; ++ }; ++ ++ i2c2_pins_mx: i2c2_mx-0 { ++ pins { ++ pinmux = ; /* I2C2_SDA */ ++ bias-disable; ++ drive-open-drain; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ i2c2_sleep_pins_mx: i2c2_sleep_mx-0 { ++ pins { ++ pinmux = ; /* I2C2_SDA */ ++ }; ++ }; ++ ++ i2c5_pins_mx: i2c5_mx-0 { ++ pins { ++ pinmux = , /* I2C5_SCL */ ++ ; /* I2C5_SDA */ ++ bias-disable; ++ drive-open-drain; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ i2c5_sleep_pins_mx: i2c5_sleep_mx-0 { ++ pins { ++ pinmux = , /* I2C5_SCL */ ++ ; /* I2C5_SDA */ ++ }; ++ }; ++ ++ i2s2_pins_mx: i2s2_mx-0 { ++ pins { ++ pinmux = , /* I2S2_WS */ ++ , /* I2S2_CK */ ++ ; /* I2S2_SDO */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <1>; ++ }; ++ }; ++ ++ i2s2_sleep_pins_mx: i2s2_sleep_mx-0 { ++ pins { ++ pinmux = , /* I2S2_WS */ ++ , /* I2S2_CK */ ++ ; /* I2S2_SDO */ ++ }; ++ }; ++ ++ ltdc_pins_mx: ltdc_mx-0 { ++ pins1 { ++ pinmux = , /* LTDC_B5 */ ++ , /* LTDC_B6 */ ++ , /* LTDC_R5 */ ++ , /* LTDC_B7 */ ++ , /* LTDC_B0 */ ++ , /* LTDC_B3 */ ++ , /* LTDC_G1 */ ++ , /* LTDC_B4 */ ++ , /* LTDC_G0 */ ++ , /* LTDC_R7 */ ++ , /* LTDC_DE */ ++ , /* LTDC_B2 */ ++ , /* LTDC_B1 */ ++ , /* LTDC_R0 */ ++ , /* LTDC_R1 */ ++ , /* LTDC_G4 */ ++ , /* LTDC_R2 */ ++ , /* LTDC_R3 */ ++ , /* LTDC_R4 */ ++ , /* LTDC_R6 */ ++ , /* LTDC_G2 */ ++ , /* LTDC_G3 */ ++ , /* LTDC_G5 */ ++ , /* LTDC_G6 */ ++ , /* LTDC_G7 */ ++ , /* LTDC_VSYNC */ ++ ; /* LTDC_HSYNC */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <0>; ++ }; ++ pins2 { ++ pinmux = ; /* LTDC_CLK */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <1>; ++ }; ++ }; ++ ++ ltdc_sleep_pins_mx: ltdc_sleep_mx-0 { ++ pins { ++ pinmux = , /* LTDC_B5 */ ++ , /* LTDC_B6 */ ++ , /* LTDC_R5 */ ++ , /* LTDC_B7 */ ++ , /* LTDC_B0 */ ++ , /* LTDC_B3 */ ++ , /* LTDC_G1 */ ++ , /* LTDC_B4 */ ++ , /* LTDC_G0 */ ++ , /* LTDC_R7 */ ++ , /* LTDC_DE */ ++ , /* LTDC_CLK */ ++ , /* LTDC_B2 */ ++ , /* LTDC_B1 */ ++ , /* LTDC_R0 */ ++ , /* LTDC_R1 */ ++ , /* LTDC_G4 */ ++ , /* LTDC_R2 */ ++ , /* LTDC_R3 */ ++ , /* LTDC_R4 */ ++ , /* LTDC_R6 */ ++ , /* LTDC_G2 */ ++ , /* LTDC_G3 */ ++ , /* LTDC_G5 */ ++ , /* LTDC_G6 */ ++ , /* LTDC_G7 */ ++ , /* LTDC_VSYNC */ ++ ; /* LTDC_HSYNC */ ++ }; ++ }; ++ ++ sdmmc1_pins_mx: sdmmc1_mx-0 { ++ u-boot,dm-pre-reloc; ++ pins1 { ++ u-boot,dm-pre-reloc; ++ pinmux = , /* SDMMC1_D0 */ ++ , /* SDMMC1_D1 */ ++ , /* SDMMC1_D2 */ ++ , /* SDMMC1_D3 */ ++ ; /* SDMMC1_CMD */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <1>; ++ }; ++ pins2 { ++ u-boot,dm-pre-reloc; ++ pinmux = ; /* SDMMC1_CK */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <2>; ++ }; ++ }; ++ ++ sdmmc1_opendrain_pins_mx: sdmmc1_opendrain_mx-0 { ++ u-boot,dm-pre-reloc; ++ pins1 { ++ u-boot,dm-pre-reloc; ++ pinmux = , /* SDMMC1_D0 */ ++ , /* SDMMC1_D1 */ ++ , /* SDMMC1_D2 */ ++ ; /* SDMMC1_D3 */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <1>; ++ }; ++ pins2 { ++ u-boot,dm-pre-reloc; ++ pinmux = ; /* SDMMC1_CK */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <2>; ++ }; ++ pins3 { ++ u-boot,dm-pre-reloc; ++ pinmux = ; /* SDMMC1_CMD */ ++ bias-disable; ++ drive-open-drain; ++ slew-rate = <1>; ++ }; ++ }; ++ ++ sdmmc1_sleep_pins_mx: sdmmc1_sleep_mx-0 { ++ u-boot,dm-pre-reloc; ++ pins { ++ u-boot,dm-pre-reloc; ++ pinmux = , /* SDMMC1_D0 */ ++ , /* SDMMC1_D1 */ ++ , /* SDMMC1_D2 */ ++ , /* SDMMC1_D3 */ ++ , /* SDMMC1_CK */ ++ ; /* SDMMC1_CMD */ ++ }; ++ }; ++ ++ sdmmc2_pins_mx: sdmmc2_mx-0 { ++ u-boot,dm-pre-reloc; ++ pins1 { ++ u-boot,dm-pre-reloc; ++ pinmux = , /* SDMMC2_D4 */ ++ , /* SDMMC2_D5 */ ++ , /* SDMMC2_D2 */ ++ , /* SDMMC2_D3 */ ++ , /* SDMMC2_D0 */ ++ , /* SDMMC2_D1 */ ++ , /* SDMMC2_D7 */ ++ , /* SDMMC2_D6 */ ++ ; /* SDMMC2_CMD */ ++ bias-pull-up; ++ drive-push-pull; ++ slew-rate = <1>; ++ }; ++ pins2 { ++ u-boot,dm-pre-reloc; ++ pinmux = ; /* SDMMC2_CK */ ++ bias-pull-up; ++ drive-push-pull; ++ slew-rate = <2>; ++ }; ++ }; ++ ++ sdmmc2_opendrain_pins_mx: sdmmc2_opendrain_mx-0 { ++ u-boot,dm-pre-reloc; ++ pins1 { ++ u-boot,dm-pre-reloc; ++ pinmux = , /* SDMMC2_D4 */ ++ , /* SDMMC2_D5 */ ++ , /* SDMMC2_D2 */ ++ , /* SDMMC2_D3 */ ++ , /* SDMMC2_D0 */ ++ , /* SDMMC2_D1 */ ++ , /* SDMMC2_D7 */ ++ ; /* SDMMC2_D6 */ ++ bias-pull-up; ++ drive-push-pull; ++ slew-rate = <1>; ++ }; ++ pins2 { ++ u-boot,dm-pre-reloc; ++ pinmux = ; /* SDMMC2_CK */ ++ bias-pull-up; ++ drive-push-pull; ++ slew-rate = <2>; ++ }; ++ pins3 { ++ u-boot,dm-pre-reloc; ++ pinmux = ; /* SDMMC2_CMD */ ++ bias-pull-up; ++ drive-open-drain; ++ slew-rate = <1>; ++ }; ++ }; ++ ++ sdmmc2_sleep_pins_mx: sdmmc2_sleep_mx-0 { ++ u-boot,dm-pre-reloc; ++ pins { ++ u-boot,dm-pre-reloc; ++ pinmux = , /* SDMMC2_D4 */ ++ , /* SDMMC2_D5 */ ++ , /* SDMMC2_D2 */ ++ , /* SDMMC2_D3 */ ++ , /* SDMMC2_D0 */ ++ , /* SDMMC2_D1 */ ++ , /* SDMMC2_D7 */ ++ , /* SDMMC2_CK */ ++ , /* SDMMC2_D6 */ ++ ; /* SDMMC2_CMD */ ++ }; ++ }; ++ ++ sdmmc3_pins_mx: sdmmc3_mx-0 { ++ u-boot,dm-pre-reloc; ++ pins1 { ++ u-boot,dm-pre-reloc; ++ pinmux = , /* SDMMC3_D3 */ ++ , /* SDMMC3_D0 */ ++ , /* SDMMC3_CMD */ ++ , /* SDMMC3_D1 */ ++ ; /* SDMMC3_D2 */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <1>; ++ }; ++ pins2 { ++ u-boot,dm-pre-reloc; ++ pinmux = ; /* SDMMC3_CK */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <2>; ++ }; ++ }; ++ ++ sdmmc3_opendrain_pins_mx: sdmmc3_opendrain_mx-0 { ++ u-boot,dm-pre-reloc; ++ pins1 { ++ u-boot,dm-pre-reloc; ++ pinmux = , /* SDMMC3_D3 */ ++ , /* SDMMC3_D0 */ ++ , /* SDMMC3_D1 */ ++ ; /* SDMMC3_D2 */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <1>; ++ }; ++ pins2 { ++ u-boot,dm-pre-reloc; ++ pinmux = ; /* SDMMC3_CMD */ ++ bias-disable; ++ drive-open-drain; ++ slew-rate = <1>; ++ }; ++ pins3 { ++ u-boot,dm-pre-reloc; ++ pinmux = ; /* SDMMC3_CK */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <2>; ++ }; ++ }; ++ ++ sdmmc3_sleep_pins_mx: sdmmc3_sleep_mx-0 { ++ u-boot,dm-pre-reloc; ++ pins { ++ u-boot,dm-pre-reloc; ++ pinmux = , /* SDMMC3_D3 */ ++ , /* SDMMC3_D0 */ ++ , /* SDMMC3_CMD */ ++ , /* SDMMC3_D1 */ ++ , /* SDMMC3_D2 */ ++ ; /* SDMMC3_CK */ ++ }; ++ }; ++ ++ spi5_pins_mx: spi5_mx-0 { ++ pins { ++ pinmux = , /* SPI5_SCK */ ++ , /* SPI5_MISO */ ++ ; /* SPI5_MOSI */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <1>; ++ }; ++ }; ++ ++ spi5_sleep_pins_mx: spi5_sleep_mx-0 { ++ pins { ++ pinmux = , /* SPI5_SCK */ ++ , /* SPI5_MISO */ ++ ; /* SPI5_MOSI */ ++ }; ++ }; ++ ++ tim5_pwm_pins_mx: tim5_pwm_mx-0 { ++ pins { ++ pinmux = ; /* TIM5_CH2 */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ tim5_pwm_sleep_pins_mx: tim5_pwm_sleep_mx-0 { ++ pins { ++ pinmux = ; /* TIM5_CH2 */ ++ }; ++ }; ++ ++ uart4_pins_mx: uart4_mx-0 { ++ u-boot,dm-pre-reloc; ++ pins1 { ++ u-boot,dm-pre-reloc; ++ pinmux = ; /* UART4_RX */ ++ bias-disable; ++ }; ++ pins2 { ++ u-boot,dm-pre-reloc; ++ pinmux = ; /* UART4_TX */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ uart4_sleep_pins_mx: uart4_sleep_mx-0 { ++ u-boot,dm-pre-reloc; ++ pins { ++ u-boot,dm-pre-reloc; ++ pinmux = , /* UART4_RX */ ++ ; /* UART4_TX */ ++ }; ++ }; ++ ++ usart2_pins_mx: usart2_mx-0 { ++ pins1 { ++ pinmux = , /* USART2_CTS */ ++ ; /* USART2_RX */ ++ bias-disable; ++ }; ++ pins2 { ++ pinmux = , /* USART2_RTS */ ++ ; /* USART2_TX */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ usart2_sleep_pins_mx: usart2_sleep_mx-0 { ++ pins { ++ pinmux = , /* USART2_CTS */ ++ , /* USART2_RTS */ ++ , /* USART2_TX */ ++ ; /* USART2_RX */ ++ }; ++ }; ++ ++ cec_pins_mx: cec-1 { ++ pins { ++ pinmux = ; ++ bias-disable; ++ drive-open-drain; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ cec_sleep_pins_mx: cec-sleep-1 { ++ pins { ++ pinmux = ; /* HDMI_CEC */ ++ }; ++ }; ++ ++ stusb1600_pins_mx: stusb1600-0 { ++ pins { ++ pinmux = ; ++ bias-pull-up; ++ }; ++ }; ++ ++ m_can1_pins_mx: m_can1_sleep_mx-0 { ++ pins1 { ++ pinmux = ; /* CAN1_TX */ ++ slew-rate = <0>; ++ drive-push-pull; ++ bias-disable; ++ }; ++ pins2 { ++ pinmux = ; /* CAN1_RX */ ++ bias-disable; ++ }; ++ }; ++ ++ m_can1_sleep_pins_mx: m_can1_sleep-0 { ++ pins { ++ pinmux = , /* CAN1_TX */ ++ ; /* CAN1_RX */ ++ }; ++ }; ++ ++}; ++ ++&pinctrl_z { ++ u-boot,dm-pre-reloc; ++ ++ i2c2_pins_z_mx: i2c2_mx-0 { ++ pins { ++ pinmux = ; /* I2C2_SCL */ ++ bias-disable; ++ drive-open-drain; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ i2c2_sleep_pins_z_mx: i2c2_sleep_mx-0 { ++ pins { ++ pinmux = ; /* I2C2_SCL */ ++ }; ++ }; ++ ++ i2c4_pins_z_mx: i2c4_mx-0 { ++ u-boot,dm-pre-reloc; ++ pins { ++ u-boot,dm-pre-reloc; ++ pinmux = , /* I2C4_SCL */ ++ ; /* I2C4_SDA */ ++ bias-disable; ++ drive-open-drain; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ i2c4_sleep_pins_z_mx: i2c4_sleep_mx-0 { ++ u-boot,dm-pre-reloc; ++ pins { ++ u-boot,dm-pre-reloc; ++ pinmux = , /* I2C4_SCL */ ++ ; /* I2C4_SDA */ ++ }; ++ }; ++}; ++ ++&m4_rproc{ ++ memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, ++ <&vdev0vring1>, <&vdev0buffer>; ++ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; ++ mbox-names = "vq0", "vq1", "shutdown"; ++ interrupt-parent = <&exti>; ++ interrupts = <68 1>; ++ wakeup-source; ++ status = "okay"; ++}; ++ ++&dcmi{ ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&dcmi_pins_mx>; ++ pinctrl-1 = <&dcmi_sleep_pins_mx>; ++ status = "okay"; ++ ++ port { ++ dcmi_0: endpoint { ++ remote-endpoint = <&ov5640_0>; ++ bus-width = <8>; ++ hsync-active = <0>; ++ vsync-active = <0>; ++ pclk-sample = <1>; ++ pclk-max-frequency = <77000000>; ++ }; ++ }; ++}; ++ ++&dsi{ ++ status = "okay"; ++ ++ ports { ++ port@0 { ++ reg = <0>; ++ dsi_in: endpoint { ++ remote-endpoint = <<dc_ep1_out>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ dsi_out: endpoint { ++ remote-endpoint = <&panel_in>; ++ }; ++ }; ++ }; ++ ++ panel_otm8009a: panel-otm8009a@0 { ++ compatible = "orisetech,otm8009a"; ++ reg = <0>; ++ reset-gpios = <&gpioe 9 GPIO_ACTIVE_LOW>; ++ power-supply = <&v3v3>; ++ status = "okay"; ++ ++ port { ++ panel_in: endpoint { ++ remote-endpoint = <&dsi_out>; ++ }; ++ }; ++ }; ++}; ++ ++ðernet0{ ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <ð1_pins_mx>; ++ pinctrl-1 = <ð1_sleep_pins_mx>; ++ status = "okay"; ++ ++ phy-mode = "rmii"; ++ max-speed = <100>; ++ phy-handle = <&phy0>; ++ nvmem-cells = <ðernet_mac_address>; ++ nvmem-cell-names = "mac-address"; ++ ++ mdio0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "snps,dwmac-mdio"; ++ phy0: ethernet-phy@0 { ++ reg = <7>; ++ }; ++ }; ++}; ++ ++&gpu{ ++ status = "okay"; ++ contiguous-area = <&gpu_reserved>; ++}; ++ ++&hash1 { ++ status = "okay"; ++}; ++ ++&hsem{ ++ status = "okay"; ++}; ++ ++&cryp1{ ++ u-boot,dm-pre-reloc; ++ status = "okay"; ++}; ++ ++&i2c1{ ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&i2c1_pins_mx>; ++ pinctrl-1 = <&i2c1_sleep_pins_mx>; ++ status = "okay"; ++ i2c-scl-rising-time-ns = <100>; ++ i2c-scl-falling-time-ns = <7>; ++ /delete-property/dmas; ++ /delete-property/dma-names; ++ ++ touchscreen@2a { ++ compatible = "focaltech,ft6236"; ++ reg = <0x2a>; ++ interrupts = <2 2>; ++ interrupt-parent = <&gpiof>; ++ interrupt-controller; ++ touchscreen-size-x = <480>; ++ touchscreen-size-y = <800>; ++ panel = <&panel_otm8009a>; ++ vcc-supply = <&v3v3>; ++ status = "okay"; ++ }; ++ touchscreen@38 { ++ compatible = "focaltech,ft6236"; ++ reg = <0x38>; ++ interrupts = <2 2>; ++ interrupt-parent = <&gpiof>; ++ interrupt-controller; ++ touchscreen-size-x = <480>; ++ touchscreen-size-y = <800>; ++ panel = <&panel_otm8009a>; ++ vcc-supply = <&v3v3>; ++ status = "okay"; ++ }; ++ ++ hdmi-transmitter@39 { ++ compatible = "sil,sii9022"; ++ reg = <0x39>; ++ reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; ++ interrupts = <1 IRQ_TYPE_EDGE_FALLING>; ++ interrupt-parent = <&gpiog>; ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <<dc_pins_mx>; ++ pinctrl-1 = <<dc_sleep_pins_mx>; ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ sii9022_in: endpoint { ++ remote-endpoint = <<dc_ep0_out>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ sii9022_tx_endpoint: endpoint { ++ remote-endpoint = <&i2s2_endpoint>; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&i2c2{ ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&i2c2_pins_mx &i2c2_pins_z_mx>; ++ pinctrl-1 = <&i2c2_sleep_pins_mx &i2c2_sleep_pins_z_mx>; ++ status = "okay"; ++ i2c-scl-rising-time-ns = <185>; ++ i2c-scl-falling-time-ns = <20>; ++ /delete-property/dmas; ++ /delete-property/dma-names; ++ ++ ov5640: camera@3c { ++ compatible = "ovti,ov5640"; ++ reg = <0x3c>; ++ clocks = <&clk_ext_camera>; ++ clock-names = "xclk"; ++ DOVDD-supply = <&v3v3>; ++ //powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>; ++ //reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; ++ //powerdown-gpios = <&gpioc 3 GPIO_ACTIVE_HIGH>; //custom ++ //reset-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; //custom ++ rotation = <180>; ++ status = "okay"; ++ ++ port { ++ ov5640_0: endpoint { ++ remote-endpoint = <&dcmi_0>; ++ bus-width = <8>; ++ data-shift = <2>; /* lines 9:2 are used */ ++ hsync-active = <0>; ++ vsync-active = <0>; ++ pclk-sample = <1>; ++ pclk-max-frequency = <77000000>; ++ }; ++ }; ++ }; ++}; ++ ++&i2c4{ ++ u-boot,dm-pre-reloc; ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&i2c4_pins_z_mx>; ++ pinctrl-1 = <&i2c4_sleep_pins_z_mx>; ++ status = "okay"; ++ i2c-scl-rising-time-ns = <185>; ++ i2c-scl-falling-time-ns = <20>; ++ clock-frequency = <400000>; ++ /delete-property/ dmas; ++ /delete-property/ dma-names; ++ ++ typec: stusb1600@28 { ++ compatible = "st,stusb1600"; ++ reg = <0x28>; ++ interrupt-parent = <&gpioe>; ++ interrupts = <8 IRQ_TYPE_EDGE_FALLING>; ++ pinctrl-0 = <&stusb1600_pins_mx>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ vdd-supply = <&vin>; ++ ++ typec_con: connector { ++ compatible = "usb-c-connector"; ++ label = "USB-C"; ++ power-role = "dual"; ++ power-opmode = "default"; ++ ++ port { ++ con_usbotg_hs_ep: endpoint { ++ remote-endpoint = <&usbotg_hs_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ pmic:stpmic@33{ ++ compatible = "st,stpmic1"; ++ reg = <0x33>; ++ interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ status = "okay"; ++ ++ st,main-control-register = <0x04>; ++ st,vin-control-register = <0xc0>; ++ st,usb-control-register = <0x20>; ++ ++ regulators{ ++ compatible = "st,stpmic1-regulators"; ++ buck1-supply = <&vin>; ++ buck2-supply = <&vin>; ++ buck3-supply = <&vin>; ++ buck4-supply = <&vin>; ++ ldo1-supply = <&v3v3>; ++ ldo2-supply = <&vin>; ++ ldo3-supply = <&vdd_ddr>; ++ ldo4-supply = <&vin>; ++ ldo5-supply = <&vin>; ++ ldo6-supply = <&v3v3>; ++ vref_ddr-supply = <&vin>; ++ boost-supply = <&vin>; ++ pwr_sw1-supply = <&bst_out>; ++ pwr_sw2-supply = <&bst_out>; ++ ++ ++ vddcore:buck1{ ++ regulator-name = "vddcore"; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-always-on; ++ regulator-initial-mode = <0>; ++ regulator-over-current-protection; ++ }; ++ ++ vdd_ddr:buck2{ ++ regulator-name = "vdd_ddr"; ++ regulator-min-microvolt = <1350000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-always-on; ++ regulator-initial-mode = <0>; ++ regulator-over-current-protection; ++ }; ++ ++ vdd:buck3{ ++ regulator-name = "vdd"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ st,mask-reset; ++ regulator-initial-mode = <0>; ++ regulator-over-current-protection; ++ }; ++ ++ v3v3:buck4{ ++ regulator-name = "v3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-over-current-protection; ++ regulator-initial-mode = <0>; ++ }; ++ ++ v1v8_audio:ldo1{ ++ regulator-name = "v1v8_audio"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ interrupts = ; ++ }; ++ ++ v3v3_hdmi:ldo2{ ++ regulator-name = "v3v3_hdmi"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ interrupts = ; ++ }; ++ ++ vtt_ddr:ldo3{ ++ regulator-name = "vtt_ddr"; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <750000>; ++ regulator-always-on; ++ regulator-over-current-protection; ++ }; ++ ++ vdd_usb:ldo4{ ++ regulator-name = "vdd_usb"; ++ interrupts = ; ++ }; ++ ++ v3v3_eth:ldo5{ ++ regulator-name = "v3v3_eth"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ interrupts = ; ++ regulator-boot-on; ++ }; ++ ++ v3v3_dsi:ldo6{ ++ regulator-name = "v3v3_dsi"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ interrupts = ; ++ }; ++ ++ vref_ddr:vref_ddr{ ++ regulator-name = "vref_ddr"; ++ regulator-always-on; ++ regulator-over-current-protection; ++ }; ++ ++ bst_out:boost{ ++ regulator-name = "bst_out"; ++ interrupts = ; ++ regulator-always-on; ++ }; ++ ++ vbus_otg:pwr_sw1{ ++ regulator-name = "vbus_otg"; ++ interrupts = ; ++ regulator-active-discharge; ++ regulator-always-on; ++ }; ++ ++ vbus_sw:pwr_sw2{ ++ regulator-name = "vbus_sw"; ++ interrupts = ; ++ regulator-active-discharge = <1>; ++ regulator-always-on; ++ }; ++ }; ++ ++ onkey{ ++ compatible = "st,stpmic1-onkey"; ++ interrupts = , ; ++ interrupt-names = "onkey-falling", "onkey-rising"; ++ power-off-time-sec = <10>; ++ status = "okay"; ++ }; ++ ++ watchdog { ++ compatible = "st,stpmic1-wdt"; ++ status = "disabled"; ++ }; ++ }; ++ eeprom@50 { ++ compatible = "atmel,24c02"; ++ reg = <0x50>; ++ pagesize = <16>; ++ }; ++}; ++ ++&i2c5{ ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&i2c5_pins_mx>; ++ pinctrl-1 = <&i2c5_sleep_pins_mx>; ++ status = "okay"; ++ ++ /delete-property/dmas; ++ /delete-property/dma-names; ++ ++}; ++ ++&spi5 { ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&spi5_pins_mx>; ++ pinctrl-1 = <&spi5_sleep_pins_mx>; ++ cs-gpios = <&gpiof 6 0>; ++ status = "okay"; ++ ++ spidev: spidev@0 { ++ compatible = "rohm,dh2228fv"; ++ spi-max-frequency = <30000000>; ++ reg = <0>; ++ }; ++}; ++ ++&i2s2{ ++ clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc CK_PER>, <&rcc PLL3_R>; ++ clock-names = "pclk", "i2sclk", "x8k", "x11k"; ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&i2s2_pins_mx>; ++ pinctrl-1 = <&i2s2_sleep_pins_mx>; ++ status = "okay"; ++ ++ i2s2_port: port { ++ i2s2_endpoint: endpoint { ++ remote-endpoint = <&sii9022_tx_endpoint>; ++ format = "i2s"; ++ mclk-fs = <256>; ++ }; ++ }; ++}; ++ ++&ipcc{ ++ status = "okay"; ++}; ++ ++&iwdg2{ ++ status = "okay"; ++ timeout-sec = <32>; ++}; ++ ++<dc{ ++ status = "okay"; ++ port { ++ ltdc_ep0_out: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&sii9022_in>; ++ }; ++ ++ ltdc_ep1_out: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&dsi_in>; ++ }; ++ }; ++}; ++ ++&pwr_regulators { ++ vdd-supply = <&vdd>; ++ vdd_3v3_usbfs-supply = <&vdd_usb>; ++}; ++ ++&rcc{ ++ u-boot,dm-pre-reloc; ++ status = "okay"; ++}; ++ ++&rng1{ ++ status = "okay"; ++}; ++ ++&rtc{ ++ status = "okay"; ++}; ++ ++&cec { ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&cec_pins_mx>; ++ pinctrl-1 = <&cec_sleep_pins_mx>; ++ status = "okay"; ++}; ++ ++&cpu0{ ++ cpu-supply = <&vddcore>; ++}; ++ ++&cpu1{ ++ cpu-supply = <&vddcore>; ++}; ++ ++&crc1 { ++ status = "okay"; ++}; ++ ++&dts { ++ status = "okay"; ++}; ++ ++&sdmmc1{ ++ u-boot,dm-pre-reloc; ++ pinctrl-names = "default", "opendrain", "sleep"; ++ pinctrl-0 = <&sdmmc1_pins_mx>; ++ pinctrl-1 = <&sdmmc1_opendrain_pins_mx>; ++ pinctrl-2 = <&sdmmc1_sleep_pins_mx>; ++ status = "okay"; ++ ++ cd-gpios = <&gpioe 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; ++ disable-wp; ++ st,neg-edge; ++ bus-width = <4>; ++ vmmc-supply = <&v3v3>; ++}; ++ ++&sdmmc2{ ++ u-boot,dm-pre-reloc; ++ pinctrl-names = "default", "opendrain", "sleep"; ++ pinctrl-0 = <&sdmmc2_pins_mx>; ++ pinctrl-1 = <&sdmmc2_opendrain_pins_mx>; ++ pinctrl-2 = <&sdmmc2_sleep_pins_mx>; ++ status = "okay"; ++ non-removable; ++ no-sd; ++ no-sdio; ++ st,neg-edge; ++ bus-width = <8>; ++ vmmc-supply = <&v3v3>; ++ vqmmc-supply = <&v3v3>; ++ mmc-ddr-3_3v; ++}; ++ ++&sdmmc3{ ++ pinctrl-names = "default", "opendrain", "sleep"; ++ pinctrl-0 = <&sdmmc3_pins_mx>; ++ pinctrl-1 = <&sdmmc3_opendrain_pins_mx>; ++ pinctrl-2 = <&sdmmc3_sleep_pins_mx>; ++ arm,primecell-periphid = <0x10153180>; ++ non-removable; ++ st,neg-edge; ++ bus-width = <4>; ++ vmmc-supply = <&v3v3>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ keep-power-in-suspend; ++ status = "okay"; ++ ++ brcmf: bcrmf@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ }; ++}; ++ ++&tamp{ ++ status = "okay"; ++}; ++ ++&timers5 { ++ /delete-property/dmas; ++ /delete-property/dma-names; ++ status = "okay"; ++ pwm { ++ pinctrl-0 = <&tim5_pwm_pins_mx>; ++ pinctrl-1 = <&tim5_pwm_sleep_pins_mx>; ++ pinctrl-names = "default", "sleep"; ++ status = "okay"; ++ }; ++ timer@4 { ++ status = "okay"; ++ }; ++}; ++ ++&uart4{ ++ u-boot,dm-pre-reloc; ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&uart4_pins_mx>; ++ pinctrl-1 = <&uart4_sleep_pins_mx>; ++ /delete-property/dmas; ++ /delete-property/dma-names; ++ status = "okay"; ++}; ++ ++&usart2{ ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&usart2_pins_mx>; ++ pinctrl-1 = <&usart2_sleep_pins_mx>; ++ uart-has-rtscts; ++ status = "okay"; ++ ++ bluetooth { ++ shutdown-gpios = <&gpioe 10 GPIO_ACTIVE_HIGH>; ++ compatible = "brcm,bcm43438-bt"; ++ max-speed = <3000000>; ++ vbat-supply = <&v3v3>; ++ vddio-supply = <&v3v3>; ++ }; ++}; ++ ++&sram { ++ dma_pool: dma_pool@0 { ++ reg = <0x50000 0x10000>; ++ pool; ++ }; ++}; ++ ++&dma1 { ++ sram = <&dma_pool>; ++}; ++ ++&dma2 { ++ sram = <&dma_pool>; ++}; ++ ++&adc { ++ vdd-supply = <&vdd>; ++ vdda-supply = <&v3v3_eth>; ++ vref-supply = <&v3v3_eth>; ++ status = "okay"; ++ adc1: adc@0 { ++ st,min-sample-time-nsecs = <5000>; ++ st,adc-channels = <0 1>; ++ status = "okay"; ++ }; ++ ++ adc_temp: temp { ++ status = "okay"; ++ }; ++}; ++ ++ ++// WARNING: Do not try to enable DAC1 and DCMI ++// This devices share the same pin PA4 ++/* &dac { ++ pinctrl-names = "default"; ++ status = "okay"; ++ dac1: dac@1 { ++ pinctrl-0 = <&dac_ch1_pins_a>; ++ status = "disabled"; ++ }; ++ dac2: dac@2 { ++ pinctrl-0 = <&dac_ch2_pins_a>; ++ status = "okay"; ++ }; ++};*/ ++ ++&usbh_ehci { ++ phys = <&usbphyc_port0>; ++ phy-names = "usb"; ++ status = "okay"; ++}; ++ ++&usbh_ohci{ ++ phys = <&usbphyc_port0>; ++ phy-names = "usb"; ++ status = "okay"; ++}; ++ ++&usbotg_hs { ++ phys = <&usbphyc_port1 0>; ++ phy-names = "usb2-phy"; ++ usb-role-switch; ++ status = "okay"; ++ ++ port { ++ usbotg_hs_ep: endpoint { ++ remote-endpoint = <&con_usbotg_hs_ep>; ++ }; ++ }; ++}; ++ ++&usbphyc { ++ status = "okay"; ++}; ++ ++&usbphyc_port0 { ++ phy-supply = <&vdd_usb>; ++ st,phy-tuning = <&usb_phy_tuning>; ++}; ++ ++&usbphyc_port1 { ++ phy-supply = <&vdd_usb>; ++ st,phy-tuning = <&usb_phy_tuning>; ++}; ++ ++&m_can1 { ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&m_can1_pins_mx>; ++ pinctrl-1 = <&m_can1_sleep_pins_mx>; ++ status = "okay"; ++}; +-- +2.25.1 + diff --git a/patches/u-boot-2020.10/0009-Fix-device-tree-for-800MHz-speedgrade-MP1-to-work-wi.patch b/patches/u-boot-2020.10/0009-Fix-device-tree-for-800MHz-speedgrade-MP1-to-work-wi.patch new file mode 100644 index 0000000..9b91272 --- /dev/null +++ b/patches/u-boot-2020.10/0009-Fix-device-tree-for-800MHz-speedgrade-MP1-to-work-wi.patch @@ -0,0 +1,24 @@ +From f1346392029d64af36135efc95c6dc46c06edd7d Mon Sep 17 00:00:00 2001 +From: Neeraj Dantu +Date: Tue, 22 Nov 2022 17:12:46 -0600 +Subject: [PATCH] Fix device tree for 800MHz speedgrade MP1 to work with 650MHz + +--- + arch/arm/dts/stm32mp15xa.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/dts/stm32mp15xa.dtsi b/arch/arm/dts/stm32mp15xa.dtsi +index 5ed7e594f4..59da3e5dc8 100644 +--- a/arch/arm/dts/stm32mp15xa.dtsi ++++ b/arch/arm/dts/stm32mp15xa.dtsi +@@ -8,6 +8,6 @@ + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + opp-microvolt = <1200000>; +- opp-supported-hw = <0x1>; ++ opp-supported-hw = <0x1 0x2>; + }; + }; +-- +2.25.1 + diff --git a/patches/u-boot-2020.10/0010-Add-OSD32MP1-RED-V1_2-Device-tree-support.patch b/patches/u-boot-2020.10/0010-Add-OSD32MP1-RED-V1_2-Device-tree-support.patch new file mode 100644 index 0000000..313589d --- /dev/null +++ b/patches/u-boot-2020.10/0010-Add-OSD32MP1-RED-V1_2-Device-tree-support.patch @@ -0,0 +1,1710 @@ +From 29a2fa33cbeadd65292ca76d14ba89bc4ffc21d3 Mon Sep 17 00:00:00 2001 +From: Neeraj Dantu +Date: Tue, 24 Jan 2023 15:40:42 -0600 +Subject: [PATCH] Add OSD32MP1-RED V1_2 Device tree support + +--- + arch/arm/dts/Makefile | 3 +- + .../stm32mp157c-osd32mp1-red-v1_2-u-boot.dtsi | 233 +++ + .../arm/dts/stm32mp157c-osd32mp1-red-v1_2.dts | 1435 +++++++++++++++++ + 3 files changed, 1670 insertions(+), 1 deletion(-) + create mode 100644 arch/arm/dts/stm32mp157c-osd32mp1-red-v1_2-u-boot.dtsi + create mode 100644 arch/arm/dts/stm32mp157c-osd32mp1-red-v1_2.dts + +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 7f4d9efe11..8d25f38a5f 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -967,7 +967,8 @@ dtb-$(CONFIG_STM32MP15x) += \ + stm32mp15xx-dhcom-pdk2.dtb \ + stm32mp15xx-dhcor-avenger96.dtb \ + stm32mp157c-osd32mp1-brk.dtb \ +- stm32mp157c-osd32mp1-red.dtb ++ stm32mp157c-osd32mp1-red.dtb \ ++ stm32mp157c-osd32mp1-red-v1_2.dtb + + dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb + dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \ +diff --git a/arch/arm/dts/stm32mp157c-osd32mp1-red-v1_2-u-boot.dtsi b/arch/arm/dts/stm32mp157c-osd32mp1-red-v1_2-u-boot.dtsi +new file mode 100644 +index 0000000000..6da91e0bb8 +--- /dev/null ++++ b/arch/arm/dts/stm32mp157c-osd32mp1-red-v1_2-u-boot.dtsi +@@ -0,0 +1,233 @@ ++/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause*/ ++/* ++ * Copyright (C) 2020, Octavo Systems LLC - All Rights Reserved ++ */ ++ ++/* For more information on Device Tree configuration, please refer to ++ * https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration ++ */ ++ ++#include ++#include "stm32mp15-osd32mp1-ddr3-1x4Gb.dtsi" ++#include "stm32mp15-u-boot.dtsi" ++#include "stm32mp15-ddr.dtsi" ++ ++ ++/ { ++ ++ aliases{ ++ i2c0 = &i2c4; ++ mmc0 = &sdmmc1; ++ usb0 = &usbotg_hs; ++ }; ++ ++ config{ ++ u-boot,boot-led = "heartbeat"; ++ u-boot,error-led = "error"; ++ u-boot,mmc-env-partition = "fip"; ++ }; ++ ++#ifdef CONFIG_STM32MP15x_STM32IMAGE ++ config { ++ u-boot,mmc-env-partition = "ssbl"; ++ }; ++ ++ /* only needed for boot with TF-A, witout FIP support */ ++ firmware { ++ optee { ++ compatible = "linaro,optee-tz"; ++ method = "smc"; ++ }; ++ }; ++ ++ reserved-memory { ++ optee@de000000 { ++ reg = <0xde000000 0x02000000>; ++ no-map; ++ }; ++ }; ++#endif ++ ++ led { ++ red { ++ label = "error"; ++ gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ status = "okay"; ++ }; ++ ++ blue { ++ default-state = "on"; ++ }; ++ }; ++}; /*root*/ ++ ++#ifndef CONFIG_TFABOOT ++ ++&i2s2{ ++ clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>; ++}; ++ ++ ++ ++&sai2{ ++ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; ++}; ++ ++ ++&clk_hse { ++ st,digbypass; ++}; ++ ++&rcc { ++ u-boot,dm-pre-reloc; ++ st,clksrc = < ++ CLK_MPU_PLL1P ++ CLK_AXI_PLL2P ++ CLK_MCU_PLL3P ++ CLK_PLL12_HSE ++ CLK_PLL3_HSE ++ CLK_PLL4_HSE ++ CLK_RTC_LSE ++ CLK_MCO1_DISABLED ++ CLK_MCO2_DISABLED ++ >; ++ st,clkdiv = < ++ 1 /*MPU*/ ++ 0 /*AXI*/ ++ 0 /*MCU*/ ++ 1 /*APB1*/ ++ 1 /*APB2*/ ++ 1 /*APB3*/ ++ 1 /*APB4*/ ++ 2 /*APB5*/ ++ 23 /*RTC*/ ++ 0 /*MCO1*/ ++ 0 /*MCO2*/ ++ >; ++ st,pkcs = < ++ CLK_CKPER_HSE ++ CLK_ETH_PLL3Q ++ CLK_SDMMC12_PLL4P ++ CLK_DSI_DSIPLL ++ CLK_STGEN_HSE ++ CLK_USBPHY_HSE ++ CLK_SPI2S1_PLL3Q ++ CLK_SPI2S23_CKPER ++ CLK_SPI45_PCLK2 ++ CLK_SPI6_DISABLED ++ CLK_I2C46_HSI ++ CLK_SDMMC3_PLL4P ++ CLK_USBO_USBPHY ++ CLK_ADC_CKPER ++ CLK_CEC_LSE ++ CLK_I2C12_HSI ++ CLK_I2C35_HSI ++ CLK_UART1_DISABLED ++ CLK_UART24_HSI ++ CLK_UART35_HSI ++ CLK_UART6_DISABLED ++ CLK_UART78_DISABLED ++ CLK_SPDIF_DISABLED ++ CLK_SAI1_DISABLED ++ CLK_SAI2_DISABLED ++ CLK_SAI3_DISABLED ++ CLK_SAI4_DISABLED ++ CLK_RNG1_LSI ++ CLK_LPTIM1_DISABLED ++ CLK_LPTIM23_DISABLED ++ CLK_LPTIM45_DISABLED ++ >; ++ pll1:st,pll@0 { ++ cfg = < 2 80 0 1 1 PQR(1,0,0) >; ++ frac = < 0x800>; ++ u-boot,dm-pre-reloc; ++ }; ++ pll2:st,pll@1 { ++ cfg = < 2 65 1 0 0 PQR(1,1,1) >; ++ frac = < 0x1400>; ++ u-boot,dm-pre-reloc; ++ }; ++ pll3:st,pll@2 { ++ cfg = < 1 61 3 5 36 PQR(1,1,0) >; ++ frac = < 0x1000 >; ++ u-boot,dm-pre-reloc; ++ }; ++ pll4:st,pll@3 { ++ cfg = < 3 98 5 7 7 PQR(1,1,1) >; ++ u-boot,dm-pre-reloc; ++ }; ++}; ++ ++&i2c4{ ++ u-boot,dm-pre-reloc; ++}; ++ ++&i2c4_pins_z_mx { ++ u-boot,dm-pre-reloc; ++ pins { ++ u-boot,dm-pre-reloc; ++ }; ++}; ++ ++&sdmmc1{ ++ u-boot,dm-pre-reloc; ++}; ++ ++&sdmmc2{ ++ u-boot,dm-pre-reloc; ++}; ++ ++&sdmmc1_pins_mx { ++ u-boot,dm-spl; ++ pins1 { ++ u-boot,dm-spl; ++ }; ++ pins2 { ++ u-boot,dm-spl; ++ }; ++}; ++ ++&sdmmc2_pins_mx { ++ u-boot,dm-spl; ++ pins1 { ++ u-boot,dm-spl; ++ }; ++ pins2 { ++ u-boot,dm-spl; ++ }; ++}; ++ ++#endif /*CONFIG_TFABOOT*/ ++ ++&cryp1{ ++ u-boot,dm-pre-reloc; ++}; ++ ++&hash1{ ++ u-boot,dm-pre-reloc; ++}; ++ ++&uart4{ ++ u-boot,dm-pre-reloc; ++}; ++ ++&usbotg_hs{ ++ u-boot,dm-pre-reloc; ++ u-boot,force-b-session-valid; ++ hnp-srp-disable; ++ dr_mode = "peripheral"; ++}; ++ ++&usbphyc{ ++ u-boot,dm-pre-reloc; ++}; ++ ++&usbphyc_port0{ ++ u-boot,dm-pre-reloc; ++}; ++ ++&usbphyc_port1{ ++ u-boot,dm-pre-reloc; ++}; ++ +diff --git a/arch/arm/dts/stm32mp157c-osd32mp1-red-v1_2.dts b/arch/arm/dts/stm32mp157c-osd32mp1-red-v1_2.dts +new file mode 100644 +index 0000000000..1bf82471f7 +--- /dev/null ++++ b/arch/arm/dts/stm32mp157c-osd32mp1-red-v1_2.dts +@@ -0,0 +1,1435 @@ ++/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ ++/* ++ * Copyright (C) Octavo Systems 2021 - All Rights Reserved ++ * Author: Neeraj Dantu for Octavo Systems ++ */ ++ ++/dts-v1/; ++ ++#include ++#include "stm32mp157.dtsi" ++#include "stm32mp15xc.dtsi" ++#include "stm32mp15xxac-pinctrl.dtsi" ++#include "stm32mp15-m4-srm.dtsi" ++#include ++#include ++#include ++ ++/ { ++ model = "Octavo OSD32MP1 RED board"; ++ compatible = "st,stm32mp157c-osd32mp1-red-v1_2", "st,stm32mp157"; ++ ++ memory@c0000000 { ++ device_type = "memory"; ++ reg = <0xc0000000 0x20000000>; ++ }; ++ ++ wifi_pwrseq: wifi-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&gpiog 5 GPIO_ACTIVE_LOW>; ++ }; ++ ++ clocks { ++ clk_ext_camera: clk-ext-camera { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++ }; ++ }; ++ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ mcuram2:mcuram2@10000000{ ++ compatible = "shared-dma-pool"; ++ reg = <0x10000000 0x40000>; ++ no-map; ++ }; ++ ++ vdev0vring0:vdev0vring0@10040000{ ++ compatible = "shared-dma-pool"; ++ reg = <0x10040000 0x1000>; ++ no-map; ++ }; ++ ++ vdev0vring1:vdev0vring1@10041000{ ++ compatible = "shared-dma-pool"; ++ reg = <0x10041000 0x1000>; ++ no-map; ++ }; ++ ++ vdev0buffer:vdev0buffer@10042000{ ++ compatible = "shared-dma-pool"; ++ reg = <0x10042000 0x4000>; ++ no-map; ++ }; ++ ++ mcuram:mcuram@30000000{ ++ compatible = "shared-dma-pool"; ++ reg = <0x30000000 0x40000>; ++ no-map; ++ }; ++ ++ retram:retram@38000000{ ++ compatible = "shared-dma-pool"; ++ reg = <0x38000000 0x10000>; ++ no-map; ++ }; ++ ++ gpu_reserved:gpu@d4000000{ ++ reg = <0xd4000000 0x4000000>; ++ no-map; ++ }; ++ }; ++ ++ ++ aliases { ++ ethernet0 = ðernet0; ++ serial0 = &uart4; ++ serial1 = &usart3; ++ serial2 = &uart7; ++ serial3 = &usart2; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ led { ++ compatible = "gpio-leds"; ++ blue { ++ label = "heartbeat"; ++ gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ default-state = "off"; ++ }; ++ }; ++ ++ usb_phy_tuning:usb-phy-tuning{ ++ st,hs-dc-level = <2>; ++ st,fs-rftime-tuning; ++ st,hs-rftime-reduction; ++ st,hs-current-trim = <15>; ++ st,hs-impedance-trim = <1>; ++ st,squelch-level = <3>; ++ st,hs-rx-offset = <2>; ++ st,no-lsfs-sc; ++ }; ++ ++ vin:vin{ ++ compatible = "regulator-fixed"; ++ regulator-name = "vin"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ sound { ++ compatible = "audio-graph-card"; ++ label = "STM32MP15-DK"; ++ routing = ++ "Playback" , "MCLK", ++ "Capture" , "MCLK", ++ "MICL" , "Mic Bias"; ++ dais = <&i2s2_port>; ++ status = "okay"; ++ }; ++}; ++ ++&pinctrl { ++ u-boot,dm-pre-reloc; ++ dcmi_pins_mx: dcmi_mx-0 { ++ pins { ++ pinmux = , /* DCMI_HSYNC */ ++ , /* DCMI_PIXCLK */ ++ , /* DCMI_D1 */ ++ , /* DCMI_D7 */ ++ , /* DCMI_D0 */ ++ , /* DCMI_D2 */ ++ , /* DCMI_D3 */ ++ , /* DCMI_D4 */ ++ , /* DCMI_D6 */ ++ , /* DCMI_VSYNC */ ++ , /* DCMI_D8 */ ++ , /* DCMI_D9 */ ++ , /* DCMI_D11 */ ++ , /* DCMI_D10 */ ++ ; /* DCMI_D5 */ ++ bias-disable; ++ }; ++ }; ++ ++ dcmi_sleep_pins_mx: dcmi_sleep_mx-0 { ++ pins { ++ pinmux = , /* DCMI_HSYNC */ ++ , /* DCMI_PIXCLK */ ++ , /* DCMI_D1 */ ++ , /* DCMI_D7 */ ++ , /* DCMI_D0 */ ++ , /* DCMI_D2 */ ++ , /* DCMI_D3 */ ++ , /* DCMI_D4 */ ++ , /* DCMI_D6 */ ++ , /* DCMI_VSYNC */ ++ , /* DCMI_D8 */ ++ , /* DCMI_D9 */ ++ , /* DCMI_D11 */ ++ , /* DCMI_D10 */ ++ ; /* DCMI_D5 */ ++ }; ++ }; ++ ++ eth1_pins_mx: eth1_mx-0 { ++ pins1 { ++ pinmux = , /* ETH1_REF_CLK */ ++ , /* ETH1_CRS_DV */ ++ , /* ETH1_RXD0 */ ++ ; /* ETH1_RXD1 */ ++ bias-disable; ++ }; ++ pins2 { ++ pinmux = ; /* ETH1_MDIO */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <0>; ++ }; ++ pins3 { ++ pinmux = , /* ETH1_TX_EN */ ++ , /* ETH1_MDC */ ++ , /* ETH1_TXD0 */ ++ ; /* ETH1_TXD1 */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <2>; ++ }; ++ }; ++ ++ eth1_sleep_pins_mx: eth1_sleep_mx-0 { ++ pins { ++ pinmux = , /* ETH1_REF_CLK */ ++ , /* ETH1_MDIO */ ++ , /* ETH1_CRS_DV */ ++ , /* ETH1_TX_EN */ ++ , /* ETH1_MDC */ ++ , /* ETH1_RXD0 */ ++ , /* ETH1_RXD1 */ ++ , /* ETH1_TXD0 */ ++ ; /* ETH1_TXD1 */ ++ }; ++ }; ++ ++ i2c1_pins_mx: i2c1_mx-0 { ++ pins { ++ pinmux = , /* I2C1_SCL */ ++ ; /* I2C1_SDA */ ++ bias-disable; ++ drive-open-drain; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ i2c1_sleep_pins_mx: i2c1_sleep_mx-0 { ++ pins { ++ pinmux = , /* I2C1_SCL */ ++ ; /* I2C1_SDA */ ++ }; ++ }; ++ ++ i2c2_pins_mx: i2c2_mx-0 { ++ pins { ++ pinmux = ; /* I2C2_SDA */ ++ bias-disable; ++ drive-open-drain; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ i2c2_sleep_pins_mx: i2c2_sleep_mx-0 { ++ pins { ++ pinmux = ; /* I2C2_SDA */ ++ }; ++ }; ++ ++ i2c5_pins_mx: i2c5_mx-0 { ++ pins { ++ pinmux = , /* I2C5_SCL */ ++ ; /* I2C5_SDA */ ++ bias-disable; ++ drive-open-drain; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ i2c5_sleep_pins_mx: i2c5_sleep_mx-0 { ++ pins { ++ pinmux = , /* I2C5_SCL */ ++ ; /* I2C5_SDA */ ++ }; ++ }; ++ ++ i2s2_pins_mx: i2s2_mx-0 { ++ pins { ++ pinmux = , /* I2S2_WS */ ++ , /* I2S2_CK */ ++ ; /* I2S2_SDO */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <1>; ++ }; ++ }; ++ ++ i2s2_sleep_pins_mx: i2s2_sleep_mx-0 { ++ pins { ++ pinmux = , /* I2S2_WS */ ++ , /* I2S2_CK */ ++ ; /* I2S2_SDO */ ++ }; ++ }; ++ ++ ltdc_pins_mx: ltdc_mx-0 { ++ pins1 { ++ pinmux = , /* LTDC_B5 */ ++ , /* LTDC_B6 */ ++ , /* LTDC_R5 */ ++ , /* LTDC_B7 */ ++ , /* LTDC_B0 */ ++ , /* LTDC_B3 */ ++ , /* LTDC_G1 */ ++ , /* LTDC_B4 */ ++ , /* LTDC_G0 */ ++ , /* LTDC_R7 */ ++ , /* LTDC_DE */ ++ , /* LTDC_B2 */ ++ , /* LTDC_B1 */ ++ , /* LTDC_R0 */ ++ , /* LTDC_R1 */ ++ , /* LTDC_G4 */ ++ , /* LTDC_R2 */ ++ , /* LTDC_R3 */ ++ , /* LTDC_R4 */ ++ , /* LTDC_R6 */ ++ , /* LTDC_G2 */ ++ , /* LTDC_G3 */ ++ , /* LTDC_G5 */ ++ , /* LTDC_G6 */ ++ , /* LTDC_G7 */ ++ , /* LTDC_VSYNC */ ++ ; /* LTDC_HSYNC */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <0>; ++ }; ++ pins2 { ++ pinmux = ; /* LTDC_CLK */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <1>; ++ }; ++ }; ++ ++ ltdc_sleep_pins_mx: ltdc_sleep_mx-0 { ++ pins { ++ pinmux = , /* LTDC_B5 */ ++ , /* LTDC_B6 */ ++ , /* LTDC_R5 */ ++ , /* LTDC_B7 */ ++ , /* LTDC_B0 */ ++ , /* LTDC_B3 */ ++ , /* LTDC_G1 */ ++ , /* LTDC_B4 */ ++ , /* LTDC_G0 */ ++ , /* LTDC_R7 */ ++ , /* LTDC_DE */ ++ , /* LTDC_CLK */ ++ , /* LTDC_B2 */ ++ , /* LTDC_B1 */ ++ , /* LTDC_R0 */ ++ , /* LTDC_R1 */ ++ , /* LTDC_G4 */ ++ , /* LTDC_R2 */ ++ , /* LTDC_R3 */ ++ , /* LTDC_R4 */ ++ , /* LTDC_R6 */ ++ , /* LTDC_G2 */ ++ , /* LTDC_G3 */ ++ , /* LTDC_G5 */ ++ , /* LTDC_G6 */ ++ , /* LTDC_G7 */ ++ , /* LTDC_VSYNC */ ++ ; /* LTDC_HSYNC */ ++ }; ++ }; ++ ++ sdmmc1_pins_mx: sdmmc1_mx-0 { ++ u-boot,dm-pre-reloc; ++ pins1 { ++ u-boot,dm-pre-reloc; ++ pinmux = , /* SDMMC1_D0 */ ++ , /* SDMMC1_D1 */ ++ , /* SDMMC1_D2 */ ++ , /* SDMMC1_D3 */ ++ ; /* SDMMC1_CMD */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <1>; ++ }; ++ pins2 { ++ u-boot,dm-pre-reloc; ++ pinmux = ; /* SDMMC1_CK */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <2>; ++ }; ++ }; ++ ++ sdmmc1_opendrain_pins_mx: sdmmc1_opendrain_mx-0 { ++ u-boot,dm-pre-reloc; ++ pins1 { ++ u-boot,dm-pre-reloc; ++ pinmux = , /* SDMMC1_D0 */ ++ , /* SDMMC1_D1 */ ++ , /* SDMMC1_D2 */ ++ ; /* SDMMC1_D3 */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <1>; ++ }; ++ pins2 { ++ u-boot,dm-pre-reloc; ++ pinmux = ; /* SDMMC1_CK */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <2>; ++ }; ++ pins3 { ++ u-boot,dm-pre-reloc; ++ pinmux = ; /* SDMMC1_CMD */ ++ bias-disable; ++ drive-open-drain; ++ slew-rate = <1>; ++ }; ++ }; ++ ++ sdmmc1_sleep_pins_mx: sdmmc1_sleep_mx-0 { ++ u-boot,dm-pre-reloc; ++ pins { ++ u-boot,dm-pre-reloc; ++ pinmux = , /* SDMMC1_D0 */ ++ , /* SDMMC1_D1 */ ++ , /* SDMMC1_D2 */ ++ , /* SDMMC1_D3 */ ++ , /* SDMMC1_CK */ ++ ; /* SDMMC1_CMD */ ++ }; ++ }; ++ ++ sdmmc2_pins_mx: sdmmc2_mx-0 { ++ u-boot,dm-pre-reloc; ++ pins1 { ++ u-boot,dm-pre-reloc; ++ pinmux = , /* SDMMC2_D4 */ ++ , /* SDMMC2_D5 */ ++ , /* SDMMC2_D2 */ ++ , /* SDMMC2_D3 */ ++ , /* SDMMC2_D0 */ ++ , /* SDMMC2_D1 */ ++ , /* SDMMC2_D7 */ ++ , /* SDMMC2_D6 */ ++ ; /* SDMMC2_CMD */ ++ bias-pull-up; ++ drive-push-pull; ++ slew-rate = <1>; ++ }; ++ pins2 { ++ u-boot,dm-pre-reloc; ++ pinmux = ; /* SDMMC2_CK */ ++ bias-pull-up; ++ drive-push-pull; ++ slew-rate = <2>; ++ }; ++ }; ++ ++ sdmmc2_opendrain_pins_mx: sdmmc2_opendrain_mx-0 { ++ u-boot,dm-pre-reloc; ++ pins1 { ++ u-boot,dm-pre-reloc; ++ pinmux = , /* SDMMC2_D4 */ ++ , /* SDMMC2_D5 */ ++ , /* SDMMC2_D2 */ ++ , /* SDMMC2_D3 */ ++ , /* SDMMC2_D0 */ ++ , /* SDMMC2_D1 */ ++ , /* SDMMC2_D7 */ ++ ; /* SDMMC2_D6 */ ++ bias-pull-up; ++ drive-push-pull; ++ slew-rate = <1>; ++ }; ++ pins2 { ++ u-boot,dm-pre-reloc; ++ pinmux = ; /* SDMMC2_CK */ ++ bias-pull-up; ++ drive-push-pull; ++ slew-rate = <2>; ++ }; ++ pins3 { ++ u-boot,dm-pre-reloc; ++ pinmux = ; /* SDMMC2_CMD */ ++ bias-pull-up; ++ drive-open-drain; ++ slew-rate = <1>; ++ }; ++ }; ++ ++ sdmmc2_sleep_pins_mx: sdmmc2_sleep_mx-0 { ++ u-boot,dm-pre-reloc; ++ pins { ++ u-boot,dm-pre-reloc; ++ pinmux = , /* SDMMC2_D4 */ ++ , /* SDMMC2_D5 */ ++ , /* SDMMC2_D2 */ ++ , /* SDMMC2_D3 */ ++ , /* SDMMC2_D0 */ ++ , /* SDMMC2_D1 */ ++ , /* SDMMC2_D7 */ ++ , /* SDMMC2_CK */ ++ , /* SDMMC2_D6 */ ++ ; /* SDMMC2_CMD */ ++ }; ++ }; ++ ++ sdmmc3_pins_mx: sdmmc3_mx-0 { ++ u-boot,dm-pre-reloc; ++ pins1 { ++ u-boot,dm-pre-reloc; ++ pinmux = , /* SDMMC3_D3 */ ++ , /* SDMMC3_D0 */ ++ , /* SDMMC3_CMD */ ++ , /* SDMMC3_D1 */ ++ ; /* SDMMC3_D2 */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <1>; ++ }; ++ pins2 { ++ u-boot,dm-pre-reloc; ++ pinmux = ; /* SDMMC3_CK */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <2>; ++ }; ++ }; ++ ++ sdmmc3_opendrain_pins_mx: sdmmc3_opendrain_mx-0 { ++ u-boot,dm-pre-reloc; ++ pins1 { ++ u-boot,dm-pre-reloc; ++ pinmux = , /* SDMMC3_D3 */ ++ , /* SDMMC3_D0 */ ++ , /* SDMMC3_D1 */ ++ ; /* SDMMC3_D2 */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <1>; ++ }; ++ pins2 { ++ u-boot,dm-pre-reloc; ++ pinmux = ; /* SDMMC3_CMD */ ++ bias-disable; ++ drive-open-drain; ++ slew-rate = <1>; ++ }; ++ pins3 { ++ u-boot,dm-pre-reloc; ++ pinmux = ; /* SDMMC3_CK */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <2>; ++ }; ++ }; ++ ++ sdmmc3_sleep_pins_mx: sdmmc3_sleep_mx-0 { ++ u-boot,dm-pre-reloc; ++ pins { ++ u-boot,dm-pre-reloc; ++ pinmux = , /* SDMMC3_D3 */ ++ , /* SDMMC3_D0 */ ++ , /* SDMMC3_CMD */ ++ , /* SDMMC3_D1 */ ++ , /* SDMMC3_D2 */ ++ ; /* SDMMC3_CK */ ++ }; ++ }; ++ ++ spi5_pins_mx: spi5_mx-0 { ++ pins { ++ pinmux = , /* SPI5_SCK */ ++ , /* SPI5_MISO */ ++ ; /* SPI5_MOSI */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <1>; ++ }; ++ }; ++ ++ spi5_sleep_pins_mx: spi5_sleep_mx-0 { ++ pins { ++ pinmux = , /* SPI5_SCK */ ++ , /* SPI5_MISO */ ++ ; /* SPI5_MOSI */ ++ }; ++ }; ++ ++ tim5_pwm_pins_mx: tim5_pwm_mx-0 { ++ pins { ++ pinmux = ; /* TIM5_CH2 */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ tim5_pwm_sleep_pins_mx: tim5_pwm_sleep_mx-0 { ++ pins { ++ pinmux = ; /* TIM5_CH2 */ ++ }; ++ }; ++ ++ uart4_pins_mx: uart4_mx-0 { ++ u-boot,dm-pre-reloc; ++ pins1 { ++ u-boot,dm-pre-reloc; ++ pinmux = ; /* UART4_RX */ ++ bias-disable; ++ }; ++ pins2 { ++ u-boot,dm-pre-reloc; ++ pinmux = ; /* UART4_TX */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ uart4_sleep_pins_mx: uart4_sleep_mx-0 { ++ u-boot,dm-pre-reloc; ++ pins { ++ u-boot,dm-pre-reloc; ++ pinmux = , /* UART4_RX */ ++ ; /* UART4_TX */ ++ }; ++ }; ++ ++ usart2_pins_mx: usart2_mx-0 { ++ pins1 { ++ pinmux = , /* USART2_CTS */ ++ ; /* USART2_RX */ ++ bias-disable; ++ }; ++ pins2 { ++ pinmux = , /* USART2_RTS */ ++ ; /* USART2_TX */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ usart2_sleep_pins_mx: usart2_sleep_mx-0 { ++ pins { ++ pinmux = , /* USART2_CTS */ ++ , /* USART2_RTS */ ++ , /* USART2_TX */ ++ ; /* USART2_RX */ ++ }; ++ }; ++ ++ cec_pins_mx: cec-1 { ++ pins { ++ pinmux = ; ++ bias-disable; ++ drive-open-drain; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ cec_sleep_pins_mx: cec-sleep-1 { ++ pins { ++ pinmux = ; /* HDMI_CEC */ ++ }; ++ }; ++ ++ stusb1600_pins_mx: stusb1600-0 { ++ pins { ++ pinmux = ; ++ bias-pull-up; ++ }; ++ }; ++ ++ m_can1_pins_mx: m_can1_sleep_mx-0 { ++ pins1 { ++ pinmux = ; /* CAN1_TX */ ++ slew-rate = <0>; ++ drive-push-pull; ++ bias-disable; ++ }; ++ pins2 { ++ pinmux = ; /* CAN1_RX */ ++ bias-disable; ++ }; ++ }; ++ ++ m_can1_sleep_pins_mx: m_can1_sleep-0 { ++ pins { ++ pinmux = , /* CAN1_TX */ ++ ; /* CAN1_RX */ ++ }; ++ }; ++ ++}; ++ ++&pinctrl_z { ++ u-boot,dm-pre-reloc; ++ ++ i2c2_pins_z_mx: i2c2_mx-0 { ++ pins { ++ pinmux = ; /* I2C2_SCL */ ++ bias-disable; ++ drive-open-drain; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ i2c2_sleep_pins_z_mx: i2c2_sleep_mx-0 { ++ pins { ++ pinmux = ; /* I2C2_SCL */ ++ }; ++ }; ++ ++ i2c4_pins_z_mx: i2c4_mx-0 { ++ u-boot,dm-pre-reloc; ++ pins { ++ u-boot,dm-pre-reloc; ++ pinmux = , /* I2C4_SCL */ ++ ; /* I2C4_SDA */ ++ bias-disable; ++ drive-open-drain; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ i2c4_sleep_pins_z_mx: i2c4_sleep_mx-0 { ++ u-boot,dm-pre-reloc; ++ pins { ++ u-boot,dm-pre-reloc; ++ pinmux = , /* I2C4_SCL */ ++ ; /* I2C4_SDA */ ++ }; ++ }; ++}; ++ ++&m4_rproc{ ++ memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, ++ <&vdev0vring1>, <&vdev0buffer>; ++ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; ++ mbox-names = "vq0", "vq1", "shutdown"; ++ interrupt-parent = <&exti>; ++ interrupts = <68 1>; ++ wakeup-source; ++ status = "okay"; ++}; ++ ++&dcmi{ ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&dcmi_pins_mx>; ++ pinctrl-1 = <&dcmi_sleep_pins_mx>; ++ status = "okay"; ++ ++ port { ++ dcmi_0: endpoint { ++ remote-endpoint = <&ov5640_0>; ++ bus-width = <8>; ++ hsync-active = <0>; ++ vsync-active = <0>; ++ pclk-sample = <1>; ++ pclk-max-frequency = <77000000>; ++ }; ++ }; ++}; ++ ++&dsi{ ++ status = "okay"; ++ ++ ports { ++ port@0 { ++ reg = <0>; ++ dsi_in: endpoint { ++ remote-endpoint = <<dc_ep1_out>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ dsi_out: endpoint { ++ remote-endpoint = <&panel_in>; ++ }; ++ }; ++ }; ++ ++ panel_otm8009a: panel-otm8009a@0 { ++ compatible = "orisetech,otm8009a"; ++ reg = <0>; ++ reset-gpios = <&gpioe 9 GPIO_ACTIVE_LOW>; ++ power-supply = <&v3v3>; ++ status = "okay"; ++ ++ port { ++ panel_in: endpoint { ++ remote-endpoint = <&dsi_out>; ++ }; ++ }; ++ }; ++}; ++ ++ðernet0{ ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <ð1_pins_mx>; ++ pinctrl-1 = <ð1_sleep_pins_mx>; ++ status = "okay"; ++ ++ ++ //st,eth-clk-sel; //custom ++ phy-mode = "rmii"; ++ max-speed = <100>; ++ phy-handle = <&phy0>; ++ nvmem-cells = <ðernet_mac_address>; ++ nvmem-cell-names = "mac-address"; ++ ++ mdio0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "snps,dwmac-mdio"; ++ phy0: ethernet-phy@0 { ++ reg = <7>; ++ }; ++ }; ++}; ++ ++&gpu{ ++ status = "okay"; ++ contiguous-area = <&gpu_reserved>; ++}; ++ ++&hash1 { ++ status = "okay"; ++}; ++ ++&hsem{ ++ status = "okay"; ++}; ++ ++&cryp1{ ++ u-boot,dm-pre-reloc; ++ status = "okay"; ++}; ++ ++&i2c1{ ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&i2c1_pins_mx>; ++ pinctrl-1 = <&i2c1_sleep_pins_mx>; ++ status = "okay"; ++ i2c-scl-rising-time-ns = <100>; ++ i2c-scl-falling-time-ns = <7>; ++ /delete-property/dmas; ++ /delete-property/dma-names; ++ ++ touchscreen@2a { ++ compatible = "focaltech,ft6236"; ++ reg = <0x2a>; ++ interrupts = <2 2>; ++ interrupt-parent = <&gpiof>; ++ interrupt-controller; ++ touchscreen-size-x = <480>; ++ touchscreen-size-y = <800>; ++ panel = <&panel_otm8009a>; ++ vcc-supply = <&v3v3>; ++ status = "okay"; ++ }; ++ touchscreen@38 { ++ compatible = "focaltech,ft6236"; ++ reg = <0x38>; ++ interrupts = <2 2>; ++ interrupt-parent = <&gpiof>; ++ interrupt-controller; ++ touchscreen-size-x = <480>; ++ touchscreen-size-y = <800>; ++ panel = <&panel_otm8009a>; ++ vcc-supply = <&v3v3>; ++ status = "okay"; ++ }; ++ ++ hdmi-transmitter@39 { ++ compatible = "sil,sii9022"; ++ reg = <0x39>; ++ reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; ++ interrupts = <1 IRQ_TYPE_EDGE_FALLING>; ++ interrupt-parent = <&gpiog>; ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <<dc_pins_mx>; ++ pinctrl-1 = <<dc_sleep_pins_mx>; ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ sii9022_in: endpoint { ++ remote-endpoint = <<dc_ep0_out>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ sii9022_tx_endpoint: endpoint { ++ remote-endpoint = <&i2s2_endpoint>; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&i2c2{ ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&i2c2_pins_mx &i2c2_pins_z_mx>; ++ pinctrl-1 = <&i2c2_sleep_pins_mx &i2c2_sleep_pins_z_mx>; ++ status = "okay"; ++ i2c-scl-rising-time-ns = <185>; ++ i2c-scl-falling-time-ns = <20>; ++ /delete-property/dmas; ++ /delete-property/dma-names; ++ ++ ov5640: camera@3c { ++ compatible = "ovti,ov5640"; ++ reg = <0x3c>; ++ clocks = <&clk_ext_camera>; ++ clock-names = "xclk"; ++ DOVDD-supply = <&v3v3>; ++ //powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>; ++ //reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; ++ //powerdown-gpios = <&gpioc 3 GPIO_ACTIVE_HIGH>; //custom ++ //reset-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; //custom ++ rotation = <180>; ++ status = "okay"; ++ ++ port { ++ ov5640_0: endpoint { ++ remote-endpoint = <&dcmi_0>; ++ bus-width = <8>; ++ data-shift = <2>; /* lines 9:2 are used */ ++ hsync-active = <0>; ++ vsync-active = <0>; ++ pclk-sample = <1>; ++ pclk-max-frequency = <77000000>; ++ }; ++ }; ++ }; ++}; ++ ++&i2c4{ ++ u-boot,dm-pre-reloc; ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&i2c4_pins_z_mx>; ++ pinctrl-1 = <&i2c4_sleep_pins_z_mx>; ++ status = "okay"; ++ i2c-scl-rising-time-ns = <185>; ++ i2c-scl-falling-time-ns = <20>; ++ clock-frequency = <400000>; ++ /delete-property/ dmas; ++ /delete-property/ dma-names; ++ ++ typec: stusb1600@28 { ++ compatible = "st,stusb1600"; ++ reg = <0x28>; ++ interrupt-parent = <&gpioe>; ++ interrupts = <8 IRQ_TYPE_EDGE_FALLING>; ++ pinctrl-0 = <&stusb1600_pins_mx>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ vdd-supply = <&vin>; ++ ++ typec_con: connector { ++ compatible = "usb-c-connector"; ++ label = "USB-C"; ++ power-role = "dual"; ++ power-opmode = "default"; ++ ++ port { ++ con_usbotg_hs_ep: endpoint { ++ remote-endpoint = <&usbotg_hs_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ pmic:stpmic@33{ ++ compatible = "st,stpmic1"; ++ reg = <0x33>; ++ interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ status = "okay"; ++ ++ st,main-control-register = <0x04>; ++ st,vin-control-register = <0xc0>; ++ st,usb-control-register = <0x20>; ++ ++ regulators{ ++ compatible = "st,stpmic1-regulators"; ++ buck1-supply = <&vin>; ++ buck2-supply = <&vin>; ++ buck3-supply = <&vin>; ++ buck4-supply = <&vin>; ++ ldo1-supply = <&v3v3>; ++ ldo2-supply = <&vin>; ++ ldo3-supply = <&vdd_ddr>; ++ ldo4-supply = <&vin>; ++ ldo5-supply = <&vin>; ++ ldo6-supply = <&v3v3>; ++ vref_ddr-supply = <&vin>; ++ boost-supply = <&vin>; ++ pwr_sw1-supply = <&bst_out>; ++ pwr_sw2-supply = <&bst_out>; ++ ++ ++ vddcore:buck1{ ++ regulator-name = "vddcore"; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-always-on; ++ regulator-initial-mode = <0>; ++ regulator-over-current-protection; ++ }; ++ ++ vdd_ddr:buck2{ ++ regulator-name = "vdd_ddr"; ++ regulator-min-microvolt = <1350000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-always-on; ++ regulator-initial-mode = <0>; ++ regulator-over-current-protection; ++ }; ++ ++ vdd:buck3{ ++ regulator-name = "vdd"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ st,mask-reset; ++ regulator-initial-mode = <0>; ++ regulator-over-current-protection; ++ }; ++ ++ v3v3:buck4{ ++ regulator-name = "v3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-over-current-protection; ++ regulator-initial-mode = <0>; ++ }; ++ ++ v1v8_audio:ldo1{ ++ regulator-name = "v1v8_audio"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ interrupts = ; ++ }; ++ ++ v3v3_hdmi:ldo2{ ++ regulator-name = "v3v3_hdmi"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ interrupts = ; ++ }; ++ ++ vtt_ddr:ldo3{ ++ regulator-name = "vtt_ddr"; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <750000>; ++ regulator-always-on; ++ regulator-over-current-protection; ++ }; ++ ++ vdd_usb:ldo4{ ++ regulator-name = "vdd_usb"; ++ interrupts = ; ++ }; ++ ++ v3v3_eth:ldo5{ ++ regulator-name = "v3v3_eth"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ interrupts = ; ++ regulator-boot-on; ++ }; ++ ++ v3v3_dsi:ldo6{ ++ regulator-name = "v3v3_dsi"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ interrupts = ; ++ }; ++ ++ vref_ddr:vref_ddr{ ++ regulator-name = "vref_ddr"; ++ regulator-always-on; ++ regulator-over-current-protection; ++ }; ++ ++ bst_out:boost{ ++ regulator-name = "bst_out"; ++ interrupts = ; ++ regulator-always-on; ++ }; ++ ++ vbus_otg:pwr_sw1{ ++ regulator-name = "vbus_otg"; ++ interrupts = ; ++ regulator-active-discharge; ++ regulator-always-on; ++ }; ++ ++ vbus_sw:pwr_sw2{ ++ regulator-name = "vbus_sw"; ++ interrupts = ; ++ regulator-active-discharge = <1>; ++ regulator-always-on; ++ }; ++ }; ++ ++ onkey{ ++ compatible = "st,stpmic1-onkey"; ++ interrupts = , ; ++ interrupt-names = "onkey-falling", "onkey-rising"; ++ power-off-time-sec = <10>; ++ status = "okay"; ++ }; ++ ++ watchdog { ++ compatible = "st,stpmic1-wdt"; ++ status = "disabled"; ++ }; ++ }; ++ eeprom@50 { ++ compatible = "atmel,24c02"; ++ reg = <0x50>; ++ pagesize = <16>; ++ }; ++}; ++ ++&i2c5{ ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&i2c5_pins_mx>; ++ pinctrl-1 = <&i2c5_sleep_pins_mx>; ++ status = "okay"; ++ ++ /delete-property/dmas; ++ /delete-property/dma-names; ++ ++}; ++ ++&spi5 { ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&spi5_pins_mx>; ++ pinctrl-1 = <&spi5_sleep_pins_mx>; ++ cs-gpios = <&gpiof 6 0>; ++ status = "okay"; ++ ++ spidev: spidev@0 { ++ compatible = "rohm,dh2228fv"; ++ spi-max-frequency = <30000000>; ++ reg = <0>; ++ }; ++}; ++ ++&i2s2{ ++ clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>; ++ clock-names = "pclk", "i2sclk", "x8k", "x11k"; ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&i2s2_pins_mx>; ++ pinctrl-1 = <&i2s2_sleep_pins_mx>; ++ status = "okay"; ++ ++ i2s2_port: port { ++ i2s2_endpoint: endpoint { ++ remote-endpoint = <&sii9022_tx_endpoint>; ++ format = "i2s"; ++ mclk-fs = <256>; ++ }; ++ }; ++}; ++ ++&ipcc{ ++ status = "okay"; ++}; ++ ++&iwdg2{ ++ status = "okay"; ++ timeout-sec = <32>; ++}; ++ ++<dc{ ++ status = "okay"; ++ port { ++ ltdc_ep0_out: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&sii9022_in>; ++ }; ++ ++ ltdc_ep1_out: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&dsi_in>; ++ }; ++ }; ++}; ++ ++&pwr_regulators { ++ vdd-supply = <&vdd>; ++ vdd_3v3_usbfs-supply = <&vdd_usb>; ++}; ++ ++&rcc{ ++ u-boot,dm-pre-reloc; ++ status = "okay"; ++}; ++ ++&rng1{ ++ status = "okay"; ++}; ++ ++&rtc{ ++ status = "okay"; ++}; ++ ++&cec { ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&cec_pins_mx>; ++ pinctrl-1 = <&cec_sleep_pins_mx>; ++ status = "okay"; ++}; ++ ++&cpu0{ ++ cpu-supply = <&vddcore>; ++}; ++ ++&cpu1{ ++ cpu-supply = <&vddcore>; ++}; ++ ++&crc1 { ++ status = "okay"; ++}; ++ ++&dts { ++ status = "okay"; ++}; ++ ++&sdmmc1{ ++ u-boot,dm-pre-reloc; ++ pinctrl-names = "default", "opendrain", "sleep"; ++ pinctrl-0 = <&sdmmc1_pins_mx>; ++ pinctrl-1 = <&sdmmc1_opendrain_pins_mx>; ++ pinctrl-2 = <&sdmmc1_sleep_pins_mx>; ++ status = "okay"; ++ ++ cd-gpios = <&gpioe 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; ++ disable-wp; ++ st,neg-edge; ++ bus-width = <4>; ++ vmmc-supply = <&v3v3>; ++}; ++ ++&sdmmc2{ ++ u-boot,dm-pre-reloc; ++ pinctrl-names = "default", "opendrain", "sleep"; ++ pinctrl-0 = <&sdmmc2_pins_mx>; ++ pinctrl-1 = <&sdmmc2_opendrain_pins_mx>; ++ pinctrl-2 = <&sdmmc2_sleep_pins_mx>; ++ status = "okay"; ++ non-removable; ++ no-sd; ++ no-sdio; ++ st,neg-edge; ++ bus-width = <8>; ++ vmmc-supply = <&v3v3>; ++ vqmmc-supply = <&v3v3>; ++ mmc-ddr-3_3v; ++}; ++ ++&sdmmc3{ ++ pinctrl-names = "default", "opendrain", "sleep"; ++ pinctrl-0 = <&sdmmc3_pins_mx>; ++ pinctrl-1 = <&sdmmc3_opendrain_pins_mx>; ++ pinctrl-2 = <&sdmmc3_sleep_pins_mx>; ++ arm,primecell-periphid = <0x10153180>; ++ non-removable; ++ st,neg-edge; ++ bus-width = <4>; ++ vmmc-supply = <&v3v3>; ++ //mmc-pwrseq = <&wifi_pwrseq>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ keep-power-in-suspend; ++ status = "disabled"; ++ //status = "okay"; ++ ++ brcmf: bcrmf@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ }; ++}; ++ ++&tamp{ ++ status = "okay"; ++}; ++ ++&timers5 { ++ /delete-property/dmas; ++ /delete-property/dma-names; ++ status = "okay"; ++ pwm { ++ pinctrl-0 = <&tim5_pwm_pins_mx>; ++ pinctrl-1 = <&tim5_pwm_sleep_pins_mx>; ++ pinctrl-names = "default", "sleep"; ++ status = "okay"; ++ }; ++ timer@4 { ++ status = "okay"; ++ }; ++}; ++ ++&uart4{ ++ u-boot,dm-pre-reloc; ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&uart4_pins_mx>; ++ pinctrl-1 = <&uart4_sleep_pins_mx>; ++ /delete-property/dmas; ++ /delete-property/dma-names; ++ status = "okay"; ++}; ++ ++&usart2{ ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&usart2_pins_mx>; ++ pinctrl-1 = <&usart2_sleep_pins_mx>; ++ uart-has-rtscts; ++ status = "okay"; ++ ++ bluetooth { ++ shutdown-gpios = <&gpioe 10 GPIO_ACTIVE_HIGH>; ++ compatible = "brcm,bcm43438-bt"; ++ max-speed = <3000000>; ++ vbat-supply = <&v3v3>; ++ vddio-supply = <&v3v3>; ++ }; ++}; ++ ++&sram { ++ dma_pool: dma_pool@0 { ++ reg = <0x50000 0x10000>; ++ pool; ++ }; ++}; ++ ++&dma1 { ++ sram = <&dma_pool>; ++}; ++ ++&dma2 { ++ sram = <&dma_pool>; ++}; ++ ++&adc { ++ vdd-supply = <&vdd>; ++ vdda-supply = <&v3v3_eth>; ++ vref-supply = <&v3v3_eth>; ++ status = "okay"; ++ adc1: adc@0 { ++ st,min-sample-time-nsecs = <5000>; ++ st,adc-channels = <0 1>; ++ status = "okay"; ++ }; ++ ++ adc_temp: temp { ++ status = "okay"; ++ }; ++}; ++ ++ ++// WARNING: Do not try to enable DAC1 and DCMI ++// This devices share the same pin PA4 ++/* &dac { ++ pinctrl-names = "default"; ++ status = "okay"; ++ dac1: dac@1 { ++ pinctrl-0 = <&dac_ch1_pins_a>; ++ status = "disabled"; ++ }; ++ dac2: dac@2 { ++ pinctrl-0 = <&dac_ch2_pins_a>; ++ status = "okay"; ++ }; ++};*/ ++ ++&usbh_ehci { ++ phys = <&usbphyc_port0>; ++ phy-names = "usb"; ++ status = "okay"; ++}; ++ ++&usbh_ohci{ ++ phys = <&usbphyc_port0>; ++ phy-names = "usb"; ++ status = "okay"; ++}; ++ ++&usbotg_hs { ++ phys = <&usbphyc_port1 0>; ++ phy-names = "usb2-phy"; ++ usb-role-switch; ++ status = "okay"; ++ ++ port { ++ usbotg_hs_ep: endpoint { ++ remote-endpoint = <&con_usbotg_hs_ep>; ++ }; ++ }; ++}; ++ ++&usbphyc { ++ status = "okay"; ++}; ++ ++&usbphyc_port0 { ++ phy-supply = <&vdd_usb>; ++ st,phy-tuning = <&usb_phy_tuning>; ++}; ++ ++&usbphyc_port1 { ++ phy-supply = <&vdd_usb>; ++ st,phy-tuning = <&usb_phy_tuning>; ++}; ++ ++&m_can1 { ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&m_can1_pins_mx>; ++ pinctrl-1 = <&m_can1_sleep_pins_mx>; ++ status = "okay"; ++}; +-- +2.25.1 + diff --git a/stm32mp157c-osd32mp1-red-v1_2-extlinux.sh b/stm32mp157c-osd32mp1-red-v1_2-extlinux.sh new file mode 100755 index 0000000..4aee883 --- /dev/null +++ b/stm32mp157c-osd32mp1-red-v1_2-extlinux.sh @@ -0,0 +1,57 @@ +#!/bin/bash -e + +DEPLOY_DIR=./ + +while getopts d: option +do +case "${option}" +in +d) DEPLOY_DIR=${OPTARG};; +esac +done + +BOARD_NAME=stm32mp157c-osd32mp1-red-v1_2 + +export BOOT_DEVICES_LIST=" \ + mmc0 \ + mmc1 \ +" + +UBOOT_SPLASH_IMAGE_mmc0="/splash.bmp" +UBOOT_EXTLINUX_TIMEOUT_mmc0=20 +UBOOT_EXTLINUX_DEFAULT_LABEL_mmc0=osd32mp1-red-v1_2-sdcard +UBOOT_EXTLINUX_LABEL_mmc0=osd32mp1-red-v1_2-sdcard +UBOOT_EXTLINUX_KERNEL_IMAGE_mmc0="/uImage" +UBOOT_EXTLINUX_FDTDIR_mmc0="/stm32mp157c-osd32mp1-red-v1_2.dtb" +UBOOT_EXTLINUX_ARGS_mmc0="root=/dev/mmcblk1p6 rootwait rw console=ttySTM0,115200 init=/sbin/init firmware_class.path=/lib/firmware/" + +UBOOT_SPLASH_IMAGE_mmc1="/splash.bmp" +UBOOT_EXTLINUX_TIMEOUT_mmc1=20 +UBOOT_EXTLINUX_DEFAULT_LABEL_mmc1=osd32mp1-red-v1_2-emmc +UBOOT_EXTLINUX_LABEL_mmc1=osd32mp1-red-v1_2-emmc +UBOOT_EXTLINUX_KERNEL_IMAGE_mmc1="/uImage" +UBOOT_EXTLINUX_FDTDIR_mmc1="/stm32mp157c-osd32mp1-red-v1_2.dtb" +UBOOT_EXTLINUX_ARGS_mmc1="root=/dev/mmcblk2p4 rootwait rw console=ttySTM0,115200 init=/sbin/init firmware_class.path=/lib/firmware/" + + +for boot_device in ${BOOT_DEVICES_LIST} ; do + mkdir -p ${DEPLOY_DIR}/${boot_device}_extlinux + UBOOT_SPLASH_IMAGE=UBOOT_SPLASH_IMAGE_$boot_device + UBOOT_EXTLINUX_TIMEOUT=UBOOT_EXTLINUX_TIMEOUT_$boot_device + UBOOT_EXTLINUX_DEFAULT_LABEL=UBOOT_EXTLINUX_DEFAULT_LABEL_$boot_device + UBOOT_EXTLINUX_LABEL=UBOOT_EXTLINUX_LABEL_$boot_device + UBOOT_EXTLINUX_KERNEL_IMAGE=UBOOT_EXTLINUX_KERNEL_IMAGE_$boot_device + UBOOT_EXTLINUX_FDTDIR=UBOOT_EXTLINUX_FDTDIR_$boot_device + UBOOT_EXTLINUX_ARGS=UBOOT_EXTLINUX_ARGS_$boot_device +cat <${DEPLOY_DIR}/${boot_device}_extlinux/extlinux.conf +# Generic Distro Configuration file generated by Octavo Build System +menu title Select the boot mode +MENU BACKGROUND ${!UBOOT_SPLASH_IMAGE} +TIMEOUT ${!UBOOT_EXTLINUX_TIMEOUT} +DEFAULT ${!UBOOT_EXTLINUX_DEFAULT_LABEL} +LABEL ${!UBOOT_EXTLINUX_LABEL} + KERNEL ${!UBOOT_EXTLINUX_KERNEL_IMAGE} + FDT ${!UBOOT_EXTLINUX_FDTDIR} + APPEND ${!UBOOT_EXTLINUX_ARGS} +EOF +done