stm32mp157c-osd32mp1-red-u-boot.dtsi

/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause*/
/*
 * Copyright (C) 2020, Octavo Systems LLC - All Rights Reserved
 */

/* For more information on Device Tree configuration, please refer to
 * https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
 */

#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include "stm32mp15-osd32mp1-ddr3-1x4Gb.dtsi"
#include "stm32mp15-u-boot.dtsi"
#include "stm32mp15-ddr.dtsi"


/ {

	aliases{
		i2c0 = &i2c4;
		mmc0 = &sdmmc1;
		usb0 = &usbotg_hs;
	};

	config{
		u-boot,boot-led = "heartbeat";
		u-boot,error-led = "error";
		u-boot,mmc-env-partition = "fip";
	};

#ifdef CONFIG_STM32MP15x_STM32IMAGE
	config {
		u-boot,mmc-env-partition = "ssbl";
	};

	/* only needed for boot with TF-A, witout FIP support */
	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};

	reserved-memory {
		optee@de000000 {
			reg = <0xde000000 0x02000000>;
			no-map;
		};
	};
#endif

	led {
		red {
			label = "error";
			gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
			default-state = "off";
			status = "okay";
		};

		blue {
			default-state = "on";
		};
	};
}; /*root*/

#ifndef CONFIG_TFABOOT

&i2s2{
	clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
};



&sai2{
	clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
};


&clk_hse {
	st,digbypass;
};

&rcc {
	u-boot,dm-pre-reloc;
	st,clksrc = <
		CLK_MPU_PLL1P
		CLK_AXI_PLL2P
		CLK_MCU_PLL3P
		CLK_PLL12_HSE
		CLK_PLL3_HSE
		CLK_PLL4_HSE
		CLK_RTC_LSE
		CLK_MCO1_DISABLED
		CLK_MCO2_DISABLED
	>;
	st,clkdiv = <
		1 		/*MPU*/
		0 		/*AXI*/
		0 		/*MCU*/
		1 		/*APB1*/
		1 		/*APB2*/
		1 		/*APB3*/
		1 		/*APB4*/
		2 		/*APB5*/
		23 		/*RTC*/
		0 		/*MCO1*/
		0 		/*MCO2*/
	>;
	st,pkcs = <
		CLK_CKPER_HSE
		CLK_ETH_PLL3Q
		CLK_SDMMC12_PLL4P
		CLK_DSI_DSIPLL
		CLK_STGEN_HSE
		CLK_USBPHY_HSE
		CLK_SPI2S1_PLL3Q
		CLK_SPI2S23_CKPER
		CLK_SPI45_PCLK2
		CLK_SPI6_DISABLED
		CLK_I2C46_HSI
		CLK_SDMMC3_PLL4P
                CLK_USBO_USBPHY
		CLK_ADC_CKPER
		CLK_CEC_LSE
		CLK_I2C12_HSI
		CLK_I2C35_HSI
		CLK_UART1_DISABLED
		CLK_UART24_HSI
		CLK_UART35_HSI
		CLK_UART6_DISABLED
		CLK_UART78_DISABLED
		CLK_SPDIF_DISABLED
		CLK_SAI1_DISABLED
		CLK_SAI2_DISABLED
		CLK_SAI3_DISABLED
		CLK_SAI4_DISABLED
		CLK_RNG1_LSI
		CLK_LPTIM1_DISABLED
		CLK_LPTIM23_DISABLED
		CLK_LPTIM45_DISABLED
	>;
	pll1:st,pll@0 {
		cfg = < 2 80 0 1 1 PQR(1,0,0) >;
		frac = < 0x800>;
		u-boot,dm-pre-reloc;
	};
	pll2:st,pll@1 {
		cfg = < 2 65 1 0 0 PQR(1,1,1) >;
		frac = < 0x1400>;
		u-boot,dm-pre-reloc;
	};
	pll3:st,pll@2 {
		cfg = < 1 61 3 5 36 PQR(1,1,0) >;
		frac = < 0x1000 >;
		u-boot,dm-pre-reloc;
	};
	pll4:st,pll@3 {
		cfg = < 3 98 5 7 7 PQR(1,1,1) >;
		u-boot,dm-pre-reloc;
	};
};

&i2c4{
	u-boot,dm-pre-reloc;
};

&i2c4_pins_z_mx {
	u-boot,dm-pre-reloc;
	pins {
		u-boot,dm-pre-reloc;
	};
};

&sdmmc1{
	u-boot,dm-pre-reloc;
};

&sdmmc2{
	u-boot,dm-pre-reloc;
};

&sdmmc1_pins_mx {
	u-boot,dm-spl;
	pins1 {
		u-boot,dm-spl;
	};
	pins2 {
		u-boot,dm-spl;
	};
};

&sdmmc2_pins_mx {
	u-boot,dm-spl;
	pins1 {
		u-boot,dm-spl;
	};
	pins2 {
		u-boot,dm-spl;
	};
};

#endif	/*CONFIG_TFABOOT*/

&cryp1{
	u-boot,dm-pre-reloc;
};

&hash1{
	u-boot,dm-pre-reloc;
};

&uart4{
	u-boot,dm-pre-reloc;
};

&usbotg_hs{
	u-boot,dm-pre-reloc;
	u-boot,force-b-session-valid;
	hnp-srp-disable;
	dr_mode = "peripheral";
};

&usbphyc{
	u-boot,dm-pre-reloc;
};

&usbphyc_port0{
	u-boot,dm-pre-reloc;
};

&usbphyc_port1{
	u-boot,dm-pre-reloc;
};