From 2c2d3d13c8991535673af2c56159949eb8ef890a Mon Sep 17 00:00:00 2001 From: Aaron Luft Date: Sun, 2 Oct 2022 21:53:40 -0700 Subject: [PATCH 1/3] adding language verilog #490 --- languages.yaml | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/languages.yaml b/languages.yaml index fb161f83f..930b6b4ef 100644 --- a/languages.yaml +++ b/languages.yaml @@ -2331,6 +2331,34 @@ Vala: - magenta - white chip: '#A56DE2' +Verilog: + type: programming + ascii: | + {0} _.._ _.._ _.._ + {0} _.._ _.._ _.._ + {0} _.._ _.._ _.._ + {0} _......................_ + {0} _.{1} ----- ----- {0}._ + {0} _..._.{1} --- --- {0}._..._ + {0} _..._.{1} --- --- {0}._..._ + {0} _.{1} --- --- {0}._ + {0} _.{1} --- --- {0}._ + {0} _..._.{1} --- --- {0}._..._ + {0} _..._.{1} --- --- {0}._..._ + {0} _.{1} --- --- {0}._ + {0} _.{1} -- -- {0}._ + {0} _..._.{1} ----- {0}._..._ + {0} _..._.{1} --- {0}._..._ + {0} _.{1} - {0}.._ + {0} _......................_ + {0} _.._ _.._ _.._ + {0} _.._ _.._ _.._ + {0} _.._ _.._ _.._ + colors: + ansi: + - white + - magenta + chip: '#C5C2FA' Vhdl: type: programming ascii: | From 6295069f085bc2a7c59ec5278a5fd892570e3704 Mon Sep 17 00:00:00 2001 From: Aaron Luft Date: Mon, 3 Oct 2022 14:54:47 -0700 Subject: [PATCH 2/3] Update languages.yaml straighter lines look better Co-authored-by: Ossama Hjaji --- languages.yaml | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/languages.yaml b/languages.yaml index 930b6b4ef..27f8918a1 100644 --- a/languages.yaml +++ b/languages.yaml @@ -2334,26 +2334,26 @@ Vala: Verilog: type: programming ascii: | - {0} _.._ _.._ _.._ - {0} _.._ _.._ _.._ - {0} _.._ _.._ _.._ - {0} _......................_ - {0} _.{1} ----- ----- {0}._ - {0} _..._.{1} --- --- {0}._..._ - {0} _..._.{1} --- --- {0}._..._ - {0} _.{1} --- --- {0}._ - {0} _.{1} --- --- {0}._ - {0} _..._.{1} --- --- {0}._..._ - {0} _..._.{1} --- --- {0}._..._ - {0} _.{1} --- --- {0}._ - {0} _.{1} -- -- {0}._ - {0} _..._.{1} ----- {0}._..._ - {0} _..._.{1} --- {0}._..._ - {0} _.{1} - {0}.._ - {0} _......................_ - {0} _.._ _.._ _.._ - {0} _.._ _.._ _.._ - {0} _.._ _.._ _.._ + {0} _.._ _.._ _.._ + {0} _.._ _.._ _.._ + {0} _.._ _.._ _.._ + {0} _........................_ + {0} _.{1}----- -----{0}._ + {0}_..._.{1} --- --- {0}._..._ + {0}_..._.{1} --- --- {0}._..._ + {0} _.{1} --- --- {0}._ + {0} _.{1} --- --- {0}._ + {0}_..._.{1} --- --- {0}._..._ + {0}_..._.{1} --- --- {0}._..._ + {0} _.{1} --- --- {0}._ + {0} _.{1} --- --- {0}._ + {0}_..._.{1} ----- {0}._..._ + {0}_..._.{1} --- {0}._..._ + {0} _.{1} - {0}._ + {0} _........................_ + {0} _.._ _.._ _.._ + {0} _.._ _.._ _.._ + {0} _.._ _.._ _.._ colors: ansi: - white From 45c579a8628000c3281d011e6905663c7d9f480f Mon Sep 17 00:00:00 2001 From: Aaron Luft Date: Mon, 3 Oct 2022 15:01:14 -0700 Subject: [PATCH 3/3] more v straightening and updated chip value --- languages.yaml | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/languages.yaml b/languages.yaml index 27f8918a1..0b4627b85 100644 --- a/languages.yaml +++ b/languages.yaml @@ -2337,20 +2337,20 @@ Verilog: {0} _.._ _.._ _.._ {0} _.._ _.._ _.._ {0} _.._ _.._ _.._ - {0} _........................_ - {0} _.{1}----- -----{0}._ - {0}_..._.{1} --- --- {0}._..._ - {0}_..._.{1} --- --- {0}._..._ - {0} _.{1} --- --- {0}._ - {0} _.{1} --- --- {0}._ - {0}_..._.{1} --- --- {0}._..._ - {0}_..._.{1} --- --- {0}._..._ - {0} _.{1} --- --- {0}._ - {0} _.{1} --- --- {0}._ - {0}_..._.{1} ----- {0}._..._ - {0}_..._.{1} --- {0}._..._ - {0} _.{1} - {0}._ - {0} _........................_ + {0} _......................._ + {0} _.{1}----- -----{0}._ + {0}_..._.{1} --- --- {0}._..._ + {0}_..._.{1} --- --- {0}._..._ + {0} _.{1} --- --- {0}._ + {0} _.{1} --- --- {0}._ + {0}_..._.{1} --- --- {0}._..._ + {0}_..._.{1} --- --- {0}._..._ + {0} _.{1} --- --- {0}._ + {0} _.{1} --- --- {0}._ + {0}_..._.{1} ----- {0}._..._ + {0}_..._.{1} --- {0}._..._ + {0} _.{1} - {0}._ + {0} _......................._ {0} _.._ _.._ _.._ {0} _.._ _.._ _.._ {0} _.._ _.._ _.._ @@ -2358,7 +2358,7 @@ Verilog: ansi: - white - magenta - chip: '#C5C2FA' + chip: '#b2b7f8' Vhdl: type: programming ascii: |