From c124063e09eae525fdb56007f723370dede0fde7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Mon, 17 Feb 2025 13:06:21 +0100 Subject: [PATCH 01/10] Revert "[nrf noup] samples: bluetooth: update autoconf.h header path" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit 40520509dae1ce09e277f68eadca8ee23621dd96. Signed-off-by: Krzysztof Chruściński --- samples/bluetooth/bap_unicast_client/src/stream_tx.c | 2 +- samples/bluetooth/cap_acceptor/src/cap_acceptor_unicast.c | 2 +- samples/bluetooth/cap_acceptor/src/main.c | 2 +- samples/bluetooth/cap_initiator/src/cap_initiator_unicast.c | 2 +- samples/bluetooth/cap_initiator/src/main.c | 2 +- soc/nordic/nrf54l/soc.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/samples/bluetooth/bap_unicast_client/src/stream_tx.c b/samples/bluetooth/bap_unicast_client/src/stream_tx.c index 44c81f08749..ebdc01ab87f 100644 --- a/samples/bluetooth/bap_unicast_client/src/stream_tx.c +++ b/samples/bluetooth/bap_unicast_client/src/stream_tx.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include #include #include #include diff --git a/samples/bluetooth/cap_acceptor/src/cap_acceptor_unicast.c b/samples/bluetooth/cap_acceptor/src/cap_acceptor_unicast.c index b7f685d1d08..132ee499c87 100644 --- a/samples/bluetooth/cap_acceptor/src/cap_acceptor_unicast.c +++ b/samples/bluetooth/cap_acceptor/src/cap_acceptor_unicast.c @@ -7,7 +7,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include #include #include #include diff --git a/samples/bluetooth/cap_acceptor/src/main.c b/samples/bluetooth/cap_acceptor/src/main.c index c84ab70e94a..37ba41d32ec 100644 --- a/samples/bluetooth/cap_acceptor/src/main.c +++ b/samples/bluetooth/cap_acceptor/src/main.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include #include #include #include diff --git a/samples/bluetooth/cap_initiator/src/cap_initiator_unicast.c b/samples/bluetooth/cap_initiator/src/cap_initiator_unicast.c index b30f34c6f99..25dba8cc16d 100644 --- a/samples/bluetooth/cap_initiator/src/cap_initiator_unicast.c +++ b/samples/bluetooth/cap_initiator/src/cap_initiator_unicast.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include #include #include #include diff --git a/samples/bluetooth/cap_initiator/src/main.c b/samples/bluetooth/cap_initiator/src/main.c index 8eab76938bc..1b35ea7981f 100644 --- a/samples/bluetooth/cap_initiator/src/main.c +++ b/samples/bluetooth/cap_initiator/src/main.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include #include #include diff --git a/soc/nordic/nrf54l/soc.c b/soc/nordic/nrf54l/soc.c index eab3bf18a14..d7f3005d1f4 100644 --- a/soc/nordic/nrf54l/soc.c +++ b/soc/nordic/nrf54l/soc.c @@ -13,7 +13,7 @@ */ #ifdef __NRF_TFM__ -#include +#include #endif #include From b21d303abd760581ed46f1d51b1de3de644d7405 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Mon, 17 Feb 2025 13:06:31 +0100 Subject: [PATCH 02/10] Revert "[nrf noup] soc: nordic: nrf54l Fix for wait lasting half expected time" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit 482ff99a72787460dfd0d595aaf809ff3e820043. Signed-off-by: Krzysztof Chruściński --- soc/nordic/nrf54l/soc.c | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/soc/nordic/nrf54l/soc.c b/soc/nordic/nrf54l/soc.c index d7f3005d1f4..26248018f6b 100644 --- a/soc/nordic/nrf54l/soc.c +++ b/soc/nordic/nrf54l/soc.c @@ -48,13 +48,6 @@ LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); #define HFXO_NODE DT_NODELABEL(hfxo) #endif -/* Building for cpuflpr with ns uses cpu_1 instead of cpu_0 */ -#if DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) -#define DEVICE_DT_CLOCK_FREQ DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) -#elif DT_PROP(DT_PATH(cpus, cpu_1), clock_frequency) -#define DEVICE_DT_CLOCK_FREQ DT_PROP(DT_PATH(cpus, cpu_1), clock_frequency) -#endif - #if defined(NRF_APPLICATION) static inline void power_and_clock_configuration(void) { @@ -179,18 +172,16 @@ int nordicsemi_nrf54l_init(void) /* Update the SystemCoreClock global variable with current core clock * retrieved from hardware state. */ +#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) || defined(__NRF_TFM__) + /* Currently not supported for non-secure */ + SystemCoreClockUpdate(); +#endif #ifdef __NRF_TFM__ /* TF-M enables the instruction cache from target_cfg.c, so we * don't need to enable it here. */ #else - - /* Update SystemCoreClock in Zephyr based on device tree to avoid SystemCoreClock - * being overwritten with default value when initializing with TF-M - */ - SystemCoreClock = DEVICE_DT_CLOCK_FREQ; - /* Enable ICACHE */ sys_cache_instr_enable(); #endif From 8626a26bd7f0331574686d6ca9dc28a405f10eba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Mon, 17 Feb 2025 13:06:40 +0100 Subject: [PATCH 03/10] Revert "[nrf noup] soc: nordic: nrf54l: Port Soc.c to be compatible with TFM" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit 840fc4597d7b06e9291b74b352daf1bf6ecd0f6d. Signed-off-by: Krzysztof Chruściński --- soc/nordic/nrf54l/soc.c | 66 +++++++++++------------------------------ 1 file changed, 17 insertions(+), 49 deletions(-) diff --git a/soc/nordic/nrf54l/soc.c b/soc/nordic/nrf54l/soc.c index 26248018f6b..abb0f778ac3 100644 --- a/soc/nordic/nrf54l/soc.c +++ b/soc/nordic/nrf54l/soc.c @@ -12,21 +12,13 @@ * for the Nordic Semiconductor nRF54L family processor. */ -#ifdef __NRF_TFM__ -#include -#endif - #include #include #include #include #include #include - -#ifndef __NRF_TFM__ #include -#endif - #include #if defined(NRF_APPLICATION) @@ -48,9 +40,17 @@ LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); #define HFXO_NODE DT_NODELABEL(hfxo) #endif -#if defined(NRF_APPLICATION) -static inline void power_and_clock_configuration(void) +static int nordicsemi_nrf54l_init(void) { + /* Update the SystemCoreClock global variable with current core clock + * retrieved from hardware state. + */ + SystemCoreClockUpdate(); + +#if defined(NRF_APPLICATION) + /* Enable ICACHE */ + sys_cache_instr_enable(); + #if DT_ENUM_HAS_VALUE(LFXO_NODE, load_capacitors, internal) uint32_t xosc32ktrim = NRF_FICR->XOSC32KTRIM; @@ -77,16 +77,16 @@ static inline void power_and_clock_configuration(void) * NOTE: The desired capacitance value is used in encoded from in INTCAP calculation formula * That is different than in case of HFXO. */ - uint32_t cap_val_encoded = - (((DT_PROP(LFXO_NODE, load_capacitance_femtofarad) - 4000UL) * 2UL) / 1000UL); + uint32_t cap_val_encoded = (((DT_PROP(LFXO_NODE, load_capacitance_femtofarad) - 4000UL) + * 2UL) / 1000UL); /* Calculation of INTCAP code before rounding. Min that calculations here are done on * values multiplied by 2^9, e.g. 0.765625 * 2^9 = 392. * offset_k should be divided by 2^6, but to add it to value shifted by 2^9 we have to * multiply it be 2^3. */ - uint32_t mid_val = - (cap_val_encoded - 4UL) * (uint32_t)(slope_k + 392UL) + (offset_k << 3UL); + uint32_t mid_val = (cap_val_encoded - 4UL) * (uint32_t)(slope_k + 392UL) + + (offset_k << 3UL); /* Get integer part of the INTCAP code */ uint32_t lfxo_intcap = mid_val >> 9UL; @@ -132,9 +132,8 @@ static inline void power_and_clock_configuration(void) */ uint32_t cap_val_femto_f = DT_PROP(HFXO_NODE, load_capacitance_femtofarad); - uint32_t mid_val_intcap = (((cap_val_femto_f - 5500UL) * (uint32_t)(slope_m + 791UL)) + - (offset_m << 2UL) * 1000UL) >> - 8UL; + uint32_t mid_val_intcap = (((cap_val_femto_f - 5500UL) * (uint32_t)(slope_m + 791UL)) + + (offset_m << 2UL) * 1000UL) >> 8UL; /* Convert the calculated value to piko Farads */ uint32_t hfxo_intcap = mid_val_intcap / 1000; @@ -164,39 +163,8 @@ static inline void power_and_clock_configuration(void) #endif nrf_regulators_vreg_enable_set(NRF_REGULATORS, NRF_REGULATORS_VREG_MAIN, true); #endif -} -#endif /* NRF_APPLICATION */ -int nordicsemi_nrf54l_init(void) -{ - /* Update the SystemCoreClock global variable with current core clock - * retrieved from hardware state. - */ -#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) || defined(__NRF_TFM__) - /* Currently not supported for non-secure */ - SystemCoreClockUpdate(); -#endif - -#ifdef __NRF_TFM__ - /* TF-M enables the instruction cache from target_cfg.c, so we - * don't need to enable it here. - */ -#else - /* Enable ICACHE */ - sys_cache_instr_enable(); -#endif - - /* NRF_REGULATORS and NRF_OSCILLATORS are configured to be secure - * as NRF_REGULATORS.POFCON is needed by the secure domain to - * prevent glitches when the power supply is attacked. - * - * NRF_OSCILLATORS is also configured as secure because of a HW limitation - * that requires them to be configured with the same security property. - */ -#if (defined(NRF_APPLICATION) && !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)) || \ - defined(__NRF_TFM__) - power_and_clock_configuration(); -#endif +#endif /* NRF_APPLICATION */ return 0; } From baa976fd7fa5661694cf2ded3b6189f959865d2f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Tue, 14 Jan 2025 10:58:58 +0100 Subject: [PATCH 04/10] [nrf fromtree] tests: kernel: timer: timer_api: Tweak test_timer_remaining MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Test test_timer_remaining is comparing time captured by k_busy_wait and k_timer_remaining_ticks. Test was accepting 1 tick difference between those two. If system clock frequency is low (e.g. 100 Hz) 1 tick is a long time but if system clock is high then 1 tick may not cover for processing latency. Instead of using fixed 1 tick test is now converting 100 us to ticks (ceiling) to cover for cases where system clock is high. 100 us processing latency time is an arbitrary value. Signed-off-by: Krzysztof Chruściński (cherry picked from commit 04e8d08e04deecccbf20557c56eff68b5d225cbc) --- tests/kernel/timer/timer_api/src/main.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/tests/kernel/timer/timer_api/src/main.c b/tests/kernel/timer/timer_api/src/main.c index b996baa72e3..899d2c92583 100644 --- a/tests/kernel/timer/timer_api/src/main.c +++ b/tests/kernel/timer/timer_api/src/main.c @@ -680,10 +680,20 @@ ZTEST_USER(timer_api, test_timer_remaining) uint32_t dur_ticks = k_ms_to_ticks_ceil32(DURATION); uint32_t target_rem_ticks = k_ms_to_ticks_ceil32(DURATION / 2); uint32_t rem_ms, rem_ticks, exp_ticks; + uint32_t latency_ticks; int32_t delta_ticks; uint32_t slew_ticks; uint64_t now; + /* Test is running in a user space thread so there is an additional latency + * involved in executing k_busy_wait and k_timer_remaining_ticks. Due + * to that latency, returned ticks won't be exact as expected even if + * k_busy_wait is running using the same clock source as the system clock. + * If system clock frequency is low (e.g. 100Hz) 1 tick will be enough but + * for cases where clock frequency is much higher we need to accept higher + * deviation (in ticks). Arbitrary value of 100 us processing overhead is used. + */ + latency_ticks = k_us_to_ticks_ceil32(100); init_timer_data(); k_timer_start(&remain_timer, K_MSEC(DURATION), K_NO_WAIT); @@ -713,7 +723,7 @@ ZTEST_USER(timer_api, test_timer_remaining) */ delta_ticks = (int32_t)(rem_ticks - target_rem_ticks); slew_ticks = BUSY_SLEW_THRESHOLD_TICKS(DURATION * USEC_PER_MSEC / 2U); - zassert_true(abs(delta_ticks) <= MAX(slew_ticks, 1U), + zassert_true(abs(delta_ticks) <= MAX(slew_ticks, latency_ticks), "tick/busy slew %d larger than test threshold %u", delta_ticks, slew_ticks); From aed31af96336868aa9b7452dea186e0810f0e4dd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Fri, 17 Jan 2025 06:01:28 +0100 Subject: [PATCH 05/10] [nrf fromtree] soc: nordic: nrf54l: Set SystemCoreClock using frequency from DT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use cpu clock source frequency as system core clock. Signed-off-by: Krzysztof Chruściński (cherry picked from commit df32919a526e20fc9928a8431dc03c9443c3230a) --- soc/nordic/nrf54l/soc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/soc/nordic/nrf54l/soc.c b/soc/nordic/nrf54l/soc.c index abb0f778ac3..5c24df49d54 100644 --- a/soc/nordic/nrf54l/soc.c +++ b/soc/nordic/nrf54l/soc.c @@ -32,6 +32,7 @@ #include #include +#include LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); @@ -43,9 +44,9 @@ LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); static int nordicsemi_nrf54l_init(void) { /* Update the SystemCoreClock global variable with current core clock - * retrieved from hardware state. + * retrieved from the DT. */ - SystemCoreClockUpdate(); + SystemCoreClock = NRF_PERIPH_GET_FREQUENCY(DT_NODELABEL(cpu)); #if defined(NRF_APPLICATION) /* Enable ICACHE */ From d9eadaa9b07ab2f80058b02c71aba9657ccc5610 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Fri, 3 Jan 2025 11:51:50 +0100 Subject: [PATCH 06/10] [nrf fromtree] dts: common: nordic: nrf54l: Add clocks to cpu MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add clocks property to CPUs. nRF54Lx series is using hfpll as clock source for CPU (and fast peripherals). CPU clock frequency can be derived from frequency of the source clock so clock-frequency property is removed from cpu as it is redundant. nrfx/MDK expects that NRF_CONFIG_CPU_FREQ_MHZ define is set to correct CPU frequency. Modified nrfx CMakeLists.txt to use clock frequency of hfpll instead of CPU clock-frequency property. Signed-off-by: Krzysztof Chruściński (cherry picked from commit 43f442be462e95b68bebc7e56489200b01f97c81) --- dts/common/nordic/nrf54l09.dtsi | 2 +- dts/common/nordic/nrf54l20.dtsi | 2 +- dts/common/nordic/nrf54l_05_10_15.dtsi | 4 ++-- modules/hal_nordic/nrfx/CMakeLists.txt | 5 ++++- 4 files changed, 8 insertions(+), 5 deletions(-) diff --git a/dts/common/nordic/nrf54l09.dtsi b/dts/common/nordic/nrf54l09.dtsi index e73a609a813..b86e4c9607e 100644 --- a/dts/common/nordic/nrf54l09.dtsi +++ b/dts/common/nordic/nrf54l09.dtsi @@ -27,7 +27,7 @@ compatible = "arm,cortex-m33f"; reg = <0>; device_type = "cpu"; - clock-frequency = ; + clocks = <&hfpll>; #address-cells = <1>; #size-cells = <1>; itm: itm@e0000000 { diff --git a/dts/common/nordic/nrf54l20.dtsi b/dts/common/nordic/nrf54l20.dtsi index a7f72bf5a30..7784342d121 100644 --- a/dts/common/nordic/nrf54l20.dtsi +++ b/dts/common/nordic/nrf54l20.dtsi @@ -23,7 +23,7 @@ compatible = "arm,cortex-m33f"; reg = <0>; device_type = "cpu"; - clock-frequency = ; + clocks = <&hfpll>; #address-cells = <1>; #size-cells = <1>; itm: itm@e0000000 { diff --git a/dts/common/nordic/nrf54l_05_10_15.dtsi b/dts/common/nordic/nrf54l_05_10_15.dtsi index d4e0ee6df00..660b2b4769f 100644 --- a/dts/common/nordic/nrf54l_05_10_15.dtsi +++ b/dts/common/nordic/nrf54l_05_10_15.dtsi @@ -27,7 +27,7 @@ compatible = "arm,cortex-m33f"; reg = <0>; device_type = "cpu"; - clock-frequency = ; + clocks = <&hfpll>; #address-cells = <1>; #size-cells = <1>; itm: itm@e0000000 { @@ -41,7 +41,7 @@ compatible = "nordic,vpr"; reg = <1>; device_type = "cpu"; - clock-frequency = ; + clocks = <&hfpll>; riscv,isa = "rv32emc"; nordic,bus-width = <32>; }; diff --git a/modules/hal_nordic/nrfx/CMakeLists.txt b/modules/hal_nordic/nrfx/CMakeLists.txt index 0954f111618..62262d31e87 100644 --- a/modules/hal_nordic/nrfx/CMakeLists.txt +++ b/modules/hal_nordic/nrfx/CMakeLists.txt @@ -183,7 +183,10 @@ if(DEFINED uicr_path) endif() if(CONFIG_SOC_NRF54L_CPUAPP_COMMON) - dt_prop(clock_frequency PATH "/cpus/cpu@0" PROPERTY "clock-frequency") + # Ideally, hfpll should taken as a phandle from clocks property from cpu but it + # seems that there is no such option in DT cmake functions. Assuming that nrf54l + # is using hfpll as CPU clock source (true for all existing devices). + dt_prop(clock_frequency PATH "/clocks/hfpll" PROPERTY "clock-frequency") math(EXPR clock_frequency_mhz "${clock_frequency} / 1000000") zephyr_compile_definitions("NRF_CONFIG_CPU_FREQ_MHZ=${clock_frequency_mhz}") endif() From 80f14ca3d72b21f9063f54598fc20d69edea0638 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Fri, 3 Jan 2025 11:56:54 +0100 Subject: [PATCH 07/10] [nrf fromtree] boards: nordic: Set 64M CPU frequency for nrf54l20pdk and nrf54l09pdk MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit nrf54l20pdk and nrf54l09pdk must use 64 MHz for now. So far it was done by using SOC_NRF54LX_SKIP_CLOCK_CONFIG Kconfig option which was skipping oscillator configuration so that it was running the default frequency (which is 64 MHz). This approach was a bit cryptic because DT was indicating that CPU was running 128 MHz when actual frequency was different (and it was relying on assumption that default frequency is 64 MHz). After adding hfpll as clock source for CPU Kconfig option can be replaced with DT setting where actual frequency is correctly indicated. Since hfpll is a clock source for fast peripherals (e.g. TIMER00) it is possible to have single source of information regarding frequency. Signed-off-by: Krzysztof Chruściński (cherry picked from commit d619fd607cbb3551b08dd6f3fa8796cd799f06ae) --- boards/nordic/nrf54l09pdk/Kconfig.defconfig | 3 --- boards/nordic/nrf54l09pdk/nrf54l09_cpuapp_common.dtsi | 5 +++++ boards/nordic/nrf54l20pdk/Kconfig.defconfig | 3 --- boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi | 5 +++++ 4 files changed, 10 insertions(+), 6 deletions(-) diff --git a/boards/nordic/nrf54l09pdk/Kconfig.defconfig b/boards/nordic/nrf54l09pdk/Kconfig.defconfig index e495d3e67ce..44589c9b35b 100644 --- a/boards/nordic/nrf54l09pdk/Kconfig.defconfig +++ b/boards/nordic/nrf54l09pdk/Kconfig.defconfig @@ -9,9 +9,6 @@ config BT_CTLR config ROM_START_OFFSET default 0x800 if BOOTLOADER_MCUBOOT -config SOC_NRF54LX_SKIP_CLOCK_CONFIG - default y - config SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE default y diff --git a/boards/nordic/nrf54l09pdk/nrf54l09_cpuapp_common.dtsi b/boards/nordic/nrf54l09pdk/nrf54l09_cpuapp_common.dtsi index 454996a405c..d3b0156e838 100644 --- a/boards/nordic/nrf54l09pdk/nrf54l09_cpuapp_common.dtsi +++ b/boards/nordic/nrf54l09pdk/nrf54l09_cpuapp_common.dtsi @@ -27,6 +27,11 @@ status = "okay"; }; +&hfpll { + /* For now use 64 MHz clock for CPU and fast peripherals. */ + clock-frequency = ; +}; + &lfxo { load-capacitors = "internal"; load-capacitance-femtofarad = <15500>; diff --git a/boards/nordic/nrf54l20pdk/Kconfig.defconfig b/boards/nordic/nrf54l20pdk/Kconfig.defconfig index f6987b80087..406a65c8826 100644 --- a/boards/nordic/nrf54l20pdk/Kconfig.defconfig +++ b/boards/nordic/nrf54l20pdk/Kconfig.defconfig @@ -6,9 +6,6 @@ if BOARD_NRF54L20PDK_NRF54L20_CPUAPP config ROM_START_OFFSET default 0x800 if BOOTLOADER_MCUBOOT -config SOC_NRF54LX_SKIP_CLOCK_CONFIG - default y - config SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE default y diff --git a/boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi b/boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi index ed9d76a6b19..ec6f2740648 100644 --- a/boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi +++ b/boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi @@ -27,6 +27,11 @@ status = "okay"; }; +&hfpll { + /* For now use 64 MHz clock for CPU and fast peripherals. */ + clock-frequency = ; +}; + &lfxo { load-capacitors = "internal"; load-capacitance-femtofarad = <15500>; From 526188f9e22c1e32a34454b4c1402376ed709398 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Mon, 17 Feb 2025 13:31:24 +0100 Subject: [PATCH 08/10] [nrf fromlist] soc: nordic: nrf54l: Setup power and clock only on secure build MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Setup regulators and oscillators only on cpuapp secure target. Upstream PR #: 85870 Signed-off-by: Krzysztof Chruściński --- soc/nordic/nrf54l/soc.c | 58 +++++++++++++++++++++++------------------ 1 file changed, 33 insertions(+), 25 deletions(-) diff --git a/soc/nordic/nrf54l/soc.c b/soc/nordic/nrf54l/soc.c index 5c24df49d54..b0f601448be 100644 --- a/soc/nordic/nrf54l/soc.c +++ b/soc/nordic/nrf54l/soc.c @@ -13,45 +13,38 @@ */ #include -#include #include #include #include #include #include -#include +#include +#include +#include +LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); -#if defined(NRF_APPLICATION) -#include +#if (defined(NRF_APPLICATION) && !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)) || \ + !defined(__ZEPHYR__) + +#include #include #include #include #include -#endif -#include - -#include -#include -#include - -LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); +#include -#if defined(NRF_APPLICATION) #define LFXO_NODE DT_NODELABEL(lfxo) #define HFXO_NODE DT_NODELABEL(hfxo) -#endif -static int nordicsemi_nrf54l_init(void) +static inline void power_and_clock_configuration(void) { - /* Update the SystemCoreClock global variable with current core clock - * retrieved from the DT. - */ - SystemCoreClock = NRF_PERIPH_GET_FREQUENCY(DT_NODELABEL(cpu)); - -#if defined(NRF_APPLICATION) - /* Enable ICACHE */ - sys_cache_instr_enable(); - +/* NRF_REGULATORS and NRF_OSCILLATORS are configured to be secure + * as NRF_REGULATORS.POFCON is needed by the secure image to + * prevent glitches when the power supply is attacked. + * + * NRF_OSCILLATORS is also configured as secure because of a HW limitation + * that requires them to be configured with the same security property. + */ #if DT_ENUM_HAS_VALUE(LFXO_NODE, load_capacitors, internal) uint32_t xosc32ktrim = NRF_FICR->XOSC32KTRIM; @@ -165,7 +158,22 @@ static int nordicsemi_nrf54l_init(void) nrf_regulators_vreg_enable_set(NRF_REGULATORS, NRF_REGULATORS_VREG_MAIN, true); #endif -#endif /* NRF_APPLICATION */ +} +#endif /* NRF_APPLICATION && !CONFIG_TRUSTED_EXECUTION_NONSECURE */ + +int nordicsemi_nrf54l_init(void) +{ + /* Update the SystemCoreClock global variable with current core clock + * retrieved from the DT. + */ + SystemCoreClock = NRF_PERIPH_GET_FREQUENCY(DT_NODELABEL(cpu)); + + sys_cache_instr_enable(); + +#if (defined(NRF_APPLICATION) && !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)) || \ + !defined(__ZEPHYR__) + power_and_clock_configuration(); +#endif return 0; } From 04a165798aedf7184b4b9594f17d653fb09250b5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Mon, 17 Feb 2025 13:39:23 +0100 Subject: [PATCH 09/10] [nrf fromlist] soc: nordic: nrf54l: Explicitly include autoconf.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Include configuration file for cases when this file is complied in special builds (e.g. TFM). Upstream PR #: 85870 Signed-off-by: Krzysztof Chruściński --- soc/nordic/nrf54l/soc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/soc/nordic/nrf54l/soc.c b/soc/nordic/nrf54l/soc.c index b0f601448be..475615271cf 100644 --- a/soc/nordic/nrf54l/soc.c +++ b/soc/nordic/nrf54l/soc.c @@ -12,6 +12,9 @@ * for the Nordic Semiconductor nRF54L family processor. */ +/* Include autoconf for cases when this file is used in special build (e.g. TFM) */ +#include + #include #include #include From 9a2ca2e880b582e74c91ef1e58cf8d567257eadf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Tue, 18 Feb 2025 14:58:13 +0100 Subject: [PATCH 10/10] [nrf fromlist] drivers: clock_control: nrf: Move NRF_PERIPH_GET_FREQUENCY MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move macro from nrf_clock_control.h to soc_nrf_common.h. Clock control header fetches many dependencies (e.g. onoff.h) so move macro to more low level header. Upstream PR #: 85870 Signed-off-by: Krzysztof Chruściński --- drivers/counter/counter_nrfx_timer.c | 1 + .../drivers/clock_control/nrf_clock_control.h | 19 ------------------- soc/nordic/common/soc_nrf_common.h | 19 +++++++++++++++++++ 3 files changed, 20 insertions(+), 19 deletions(-) diff --git a/drivers/counter/counter_nrfx_timer.c b/drivers/counter/counter_nrfx_timer.c index afbdb4ed1ad..6af5a31ad15 100644 --- a/drivers/counter/counter_nrfx_timer.c +++ b/drivers/counter/counter_nrfx_timer.c @@ -3,6 +3,7 @@ * * SPDX-License-Identifier: Apache-2.0 */ +#include #include #include #include diff --git a/include/zephyr/drivers/clock_control/nrf_clock_control.h b/include/zephyr/drivers/clock_control/nrf_clock_control.h index 866b4fe2ee1..acc74a85357 100644 --- a/include/zephyr/drivers/clock_control/nrf_clock_control.h +++ b/include/zephyr/drivers/clock_control/nrf_clock_control.h @@ -343,25 +343,6 @@ void nrf_clock_control_hfxo_release(void); #endif /* defined(CONFIG_CLOCK_CONTROL_NRF2) */ -/** @brief Get clock frequency that is used for the given node. - * - * Macro checks if node has clock property and if yes then if clock has clock_frequency property - * then it is returned. If it has supported_clock_frequency property with the list of supported - * frequencies then the last one is returned with assumption that they are ordered and the last - * one is the highest. If node does not have clock then 16 MHz is returned which is the default - * frequency. - * - * @param node Devicetree node. - * - * @return Frequency of the clock that is used for the node. - */ -#define NRF_PERIPH_GET_FREQUENCY(node) \ - COND_CODE_1(DT_CLOCKS_HAS_IDX(node, 0), \ - (COND_CODE_1(DT_NODE_HAS_PROP(DT_CLOCKS_CTLR(node), clock_frequency), \ - (DT_PROP(DT_CLOCKS_CTLR(node), clock_frequency)), \ - (DT_PROP_LAST(DT_CLOCKS_CTLR(node), supported_clock_frequency)))), \ - (NRFX_MHZ_TO_HZ(16))) - #ifdef __cplusplus } #endif diff --git a/soc/nordic/common/soc_nrf_common.h b/soc/nordic/common/soc_nrf_common.h index 1e5e603967b..dd6fb8866bf 100644 --- a/soc/nordic/common/soc_nrf_common.h +++ b/soc/nordic/common/soc_nrf_common.h @@ -236,6 +236,25 @@ DT_PINCTRL_HAS_NAME(node_id, sleep), \ DT_NODE_PATH(node_id) " defined without sleep state") +/** @brief Get clock frequency that is used for the given node. + * + * Macro checks if node has clock property and if yes then if clock has clock_frequency property + * then it is returned. If it has supported_clock_frequency property with the list of supported + * frequencies then the last one is returned with assumption that they are ordered and the last + * one is the highest. If node does not have clock then 16 MHz is returned which is the default + * frequency. + * + * @param node Devicetree node. + * + * @return Frequency of the clock that is used for the node. + */ +#define NRF_PERIPH_GET_FREQUENCY(node) \ + COND_CODE_1(DT_CLOCKS_HAS_IDX(node, 0), \ + (COND_CODE_1(DT_NODE_HAS_PROP(DT_CLOCKS_CTLR(node), clock_frequency), \ + (DT_PROP(DT_CLOCKS_CTLR(node), clock_frequency)), \ + (DT_PROP_LAST(DT_CLOCKS_CTLR(node), supported_clock_frequency)))), \ + (NRFX_MHZ_TO_HZ(16))) + #endif /* !_ASMLANGUAGE */ #endif