From 55236576bd75c78905896654a14024aeb28da48e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Mon, 13 Jan 2025 14:13:09 +0100 Subject: [PATCH 1/2] [nrf fromtree] tests: kernel: gen_isr_table: Fix test for nRF VPR targets MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Test was using interrupt lines which does not exist on nRF VPR targets. nRF54Lx FLPR has interrupts >= 16 and nRF54Hx PPR does not have interrupt 17. Added configuration which works for nrf54h20_cpuppr and nrf54lx_flpr. Signed-off-by: Krzysztof Chruściński (cherry picked from commit 0359f37263c920c71bca32bdd354da5abe08269f) --- tests/kernel/gen_isr_table/src/main.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/tests/kernel/gen_isr_table/src/main.c b/tests/kernel/gen_isr_table/src/main.c index 82683f68363..475c2c903f6 100644 --- a/tests/kernel/gen_isr_table/src/main.c +++ b/tests/kernel/gen_isr_table/src/main.c @@ -20,10 +20,21 @@ extern uint32_t _irq_vector_table[]; #if defined(CONFIG_RISCV) #if defined(CONFIG_NRFX_CLIC) -#define ISR1_OFFSET 15 -#define ISR3_OFFSET 16 -#define ISR5_OFFSET 17 -#define TRIG_CHECK_SIZE 18 + +#if defined(CONFIG_SOC_SERIES_NRF54LX) && defined(CONFIG_RISCV_CORE_NORDIC_VPR) +#define ISR1_OFFSET 16 +#define ISR3_OFFSET 17 +#define ISR5_OFFSET 18 +#define TRIG_CHECK_SIZE 19 +#elif defined(CONFIG_SOC_NRF54H20_CPUPPR) +#define ISR1_OFFSET 14 +#define ISR3_OFFSET 15 +#define ISR5_OFFSET 16 +#define TRIG_CHECK_SIZE 17 +#else +#error "Target not supported" +#endif + #elif defined(CONFIG_RISCV_HAS_CLIC) #define ISR1_OFFSET 3 #define ISR3_OFFSET 17 From c605ec4291eea7dc0ac7eda6695b8ec2c2bfaf78 Mon Sep 17 00:00:00 2001 From: Adam Kondraciuk Date: Thu, 6 Feb 2025 15:28:10 +0100 Subject: [PATCH 2/2] [nrf fromtree] tests: kernel: gen_isr_table: Fix kernel test for nRF FLPR target Fix kernel `gen_isr_table` test for nRF FLPR target similairly to PPR target. Signed-off-by: Adam Kondraciuk (cherry picked from commit 85282d604c0ec0988625ed2f3fe7c76473bdbe0b) --- tests/kernel/gen_isr_table/src/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/kernel/gen_isr_table/src/main.c b/tests/kernel/gen_isr_table/src/main.c index 475c2c903f6..f789c612370 100644 --- a/tests/kernel/gen_isr_table/src/main.c +++ b/tests/kernel/gen_isr_table/src/main.c @@ -26,7 +26,7 @@ extern uint32_t _irq_vector_table[]; #define ISR3_OFFSET 17 #define ISR5_OFFSET 18 #define TRIG_CHECK_SIZE 19 -#elif defined(CONFIG_SOC_NRF54H20_CPUPPR) +#elif defined(CONFIG_SOC_NRF54H20_CPUPPR) || defined(CONFIG_SOC_NRF54H20_CPUFLPR) #define ISR1_OFFSET 14 #define ISR3_OFFSET 15 #define ISR5_OFFSET 16