diff --git a/CMakeLists.txt b/CMakeLists.txt index 401060f989c..f87a7d8553d 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1579,11 +1579,14 @@ endif() if(CONFIG_BUILD_OUTPUT_ADJUST_LMA) math(EXPR adjustment "${CONFIG_BUILD_OUTPUT_ADJUST_LMA}" OUTPUT_FORMAT DECIMAL) + set(args_adjustment ${CONFIG_BUILD_OUTPUT_ADJUST_LMA_SECTIONS}) + list(TRANSFORM args_adjustment PREPEND $) + list(TRANSFORM args_adjustment APPEND +${adjustment}) list(APPEND post_build_commands COMMAND $ $ - $${adjustment} + ${args_adjustment} $${KERNEL_ELF_NAME} $${KERNEL_ELF_NAME} ) diff --git a/Kconfig.zephyr b/Kconfig.zephyr index adb72a219f9..904999f9f66 100644 --- a/Kconfig.zephyr +++ b/Kconfig.zephyr @@ -813,6 +813,23 @@ config BUILD_OUTPUT_ADJUST_LMA default "$(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_M4))-\ $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))" +config BUILD_OUTPUT_ADJUST_LMA_SECTIONS + def_string "*" + depends on BUILD_OUTPUT_ADJUST_LMA!="" + help + This determines the output sections to which the above LMA adjustment + will be applied. + The value can be the name of a section in the final ELF, like "text". + It can also be a pattern with wildcards, such as "*bss", which could + match more than one section name. Multiple such patterns can be given + as a ";"-separated list. It's possible to supply a 'negative' pattern + starting with "!", to exclude sections matched by a preceding pattern. + + By default, all sections will have their LMA adjusted. The following + example excludes one section produced by the code relocation feature: + config BUILD_OUTPUT_ADJUST_LMA_SECTIONS + default "*;!.extflash_text_reloc" + config BUILD_OUTPUT_INFO_HEADER bool "Create a image information header" help diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi index 0d79ea5b556..b94430e56ba 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi @@ -127,7 +127,7 @@ status = "disabled"; #memory-region-cells = <0>; zephyr,memory-region = "DMA_RAM21"; - zephyr,memory-attr = <( DT_MEM_CACHEABLE )>; + zephyr,memory-attr = <( DT_MEM_DMA | DT_MEM_CACHEABLE )>; }; }; @@ -171,6 +171,7 @@ status = "disabled"; #memory-region-cells = <0>; zephyr,memory-region = "DMA_RAM3x_APP"; + zephyr,memory-attr = <( DT_MEM_DMA )>; }; cpurad_dma_region: memory@1e80 { @@ -179,6 +180,7 @@ status = "disabled"; #memory-region-cells = <0>; zephyr,memory-region = "DMA_RAM3x_RAD"; + zephyr,memory-attr = <( DT_MEM_DMA )>; }; }; }; diff --git a/boards/nordic/nrf9280pdk/Kconfig.defconfig b/boards/nordic/nrf9280pdk/Kconfig.defconfig new file mode 100644 index 00000000000..c5c3576b4c2 --- /dev/null +++ b/boards/nordic/nrf9280pdk/Kconfig.defconfig @@ -0,0 +1,24 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF9280PDK_NRF9280_CPUAPP + +config BT_HCI_IPC + default y if BT + +endif # BOARD_NRF9280PDK_NRF9280_CPUAPP + +if BOARD_NRF9280PDK_NRF9280_CPURAD + +config BT_CTLR + default y if BT + +endif # BOARD_NRF9280PDK_NRF9280_CPURAD + +if BOARD_NRF9280PDK_NRF9280_CPUPPR + +# As PPR has limited memory most of tests does not fit with asserts enabled. +config ASSERT + default n if ZTEST + +endif # BOARD_NRF9280PDK_NRF9280_CPUPPR diff --git a/boards/nordic/nrf9280pdk/Kconfig.nrf9280pdk b/boards/nordic/nrf9280pdk/Kconfig.nrf9280pdk new file mode 100644 index 00000000000..54865a1b235 --- /dev/null +++ b/boards/nordic/nrf9280pdk/Kconfig.nrf9280pdk @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF9280PDK + select SOC_NRF9280_CPUAPP if BOARD_NRF9280PDK_NRF9280_CPUAPP + select SOC_NRF9280_CPURAD if BOARD_NRF9280PDK_NRF9280_CPURAD + select SOC_NRF9280_CPUPPR if BOARD_NRF9280PDK_NRF9280_CPUPPR || \ + BOARD_NRF9280PDK_NRF9280_CPUPPR_XIP diff --git a/boards/nordic/nrf9280pdk/board.cmake b/boards/nordic/nrf9280pdk/board.cmake new file mode 100644 index 00000000000..0690bf366bf --- /dev/null +++ b/boards/nordic/nrf9280pdk/board.cmake @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) + +if(CONFIG_BOARD_NRF9280PDK_NRF9280_CPUAPP OR CONFIG_BOARD_NRF9280PDK_NRF9280_CPURAD) + if(CONFIG_BOARD_NRF9280PDK_NRF9280_CPUAPP) + set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf9280_cpuapp.JLinkScript) + else() + set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf9280_cpurad.JLinkScript) + endif() + + board_runner_args(jlink "--device=CORTEX-M33" "--speed=4000" "--tool-opt=-jlinkscriptfile ${JLINKSCRIPTFILE}") + include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +endif() diff --git a/boards/nordic/nrf9280pdk/board.yml b/boards/nordic/nrf9280pdk/board.yml new file mode 100644 index 00000000000..450ef9db901 --- /dev/null +++ b/boards/nordic/nrf9280pdk/board.yml @@ -0,0 +1,8 @@ +board: + name: nrf9280pdk + vendor: nordic + socs: + - name: nrf9280 + variants: + - name: xip + cpucluster: cpuppr diff --git a/boards/nordic/nrf9280pdk/doc/index.rst b/boards/nordic/nrf9280pdk/doc/index.rst new file mode 100644 index 00000000000..ef230148d5e --- /dev/null +++ b/boards/nordic/nrf9280pdk/doc/index.rst @@ -0,0 +1,175 @@ +.. _nrf9280pdk_nrf9280: + +nRF9280 PDK +########### + +Overview +******** + +.. note:: + + All software for the nRF9280 SiP is experimental and hardware availability + is restricted to the participants in the limited sampling program. + +The nRF9280 DK is a single-board development kit for evaluation and development +on the Nordic nRF9280 System-in-Package (SiP). + +The nRF9280 is a multicore SiP with: + +* an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security + Extensions, running at up to 320 MHz, referred to as the **application core** +* an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security + Extensions, running at up to 256 MHz, referred to as the **radio core**. + +The ``nrf9280pdk/nrf9280/cpuapp`` board target provides support for +the application core on the nRF9280 SiP. +The ``nrf9280pdk/nrf9280/cpurad`` board target provides support for +the radio core on the nRF9280 SiP. +The ``nrf9280pdk/nrf9280/cpuppr`` board target provides support for +the PPR core on the nRF9280 SiP. + +nRF9280 SiP provides support for the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`GRTC (Global real-time counter)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* MRAM +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +Hardware +******** + +nRF9280 DK has two crystal oscillators: + +* High-frequency 32 MHz crystal oscillator (HFXO) +* Low-frequency 32.768 kHz crystal oscillator (LFXO) + +Supported Features +================== + +The ``nrf9280pdk/nrf9280/cpuapp`` board target supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| GRTC | on-chip | system clock | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +The ``nrf9280pdk/nrf9280/cpurad`` board target supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| GRTC | on-chip | system clock | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +The ``nrf9280pdk/nrf9280/cpuppr`` board target supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| GRTC | on-chip | system clock | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +LEDs +---- + +* LED1 (green) = P9.02 +* LED2 (green) = P9.03 +* LED3 (green) = P9.04 +* LED4 (green) = P9.05 + +Push buttons +------------ + +* BUTTON1 = P0.8 +* BUTTON2 = P0.9 +* BUTTON3 = P0.10 +* BUTTON4 = P0.11 +* RESET (SW1) + +Programming and Debugging +************************* + +Applications for both the ``nrf9280pdk/nrf9280/cpuapp`` and +``nrf9280pdk/nrf9280/cpurad`` board targets can be built, flashed, +and debugged in the usual way. See :ref:`build_an_application` +and :ref:`application_run` for more details on building and running. + +Flashing +======== + +As an example, this section shows how to build and flash the :ref:`hello_world` +application. + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. + +To build and program the sample to the nRF9280 DK, complete the following steps: + +1. Connect the nRF9280 DK to your computer using the IMCU USB port on the DK. +#. Build the sample by running the following command: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf9280pdk/nrf9280/cpuapp + :goals: build flash + +Testing the LEDs and buttons in the nRF9280 DK +*********************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs +on the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` +* :zephyr:code-sample:`button` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts`. diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-ipc_conf.dtsi b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-ipc_conf.dtsi new file mode 100644 index 00000000000..944dd7fb6ab --- /dev/null +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-ipc_conf.dtsi @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + ipc { + cpusec_cpuapp_ipc: ipc-1-2 { + compatible = "zephyr,ipc-icmsg"; + status = "disabled"; + mboxes = <&cpusec_bellboard 12>, + <&cpuapp_bellboard 0>; + }; + + cpusec_cpurad_ipc: ipc-1-3 { + compatible = "zephyr,ipc-icmsg"; + status = "disabled"; + mboxes = <&cpusec_bellboard 18>, + <&cpurad_bellboard 0>; + }; + + cpuapp_cpurad_ipc: ipc-2-3 { + compatible = "zephyr,ipc-icbmsg"; + status = "disabled"; + mboxes = <&cpuapp_bellboard 18>, + <&cpurad_bellboard 12>; + }; + + cpuapp_cpusys_ipc: ipc-2-12 { + compatible = "zephyr,ipc-icmsg"; + status = "disabled"; + mboxes = <&cpuapp_bellboard 6>, + <&cpusys_vevif 12>; + }; + + cpuapp_cpuppr_ipc: ipc-2-13 { + compatible = "zephyr,ipc-icmsg"; + status = "disabled"; + mboxes = <&cpuapp_bellboard 13>, + <&cpuppr_vevif 12>; + }; + + cpurad_cpusys_ipc: ipc-3-12 { + compatible = "zephyr,ipc-icmsg"; + status = "disabled"; + mboxes = <&cpurad_bellboard 6>, + <&cpusys_vevif 18>; + }; + }; +}; diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-memory_map.dtsi b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-memory_map.dtsi new file mode 100644 index 00000000000..78e3be8825f --- /dev/null +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-memory_map.dtsi @@ -0,0 +1,276 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include + +/ { + reserved-memory { + /* The first 64kb are reserved for SecDom. + * The next 4kb are reserved for IPC between SecDom and Cellcore. + */ + + cpurad_ram0x_region: memory@2f011000 { + compatible = "nordic,owned-memory"; + reg = <0x2f011000 DT_SIZE_K(4)>; + status = "disabled"; + perm-read; + perm-write; + perm-secure; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2f011000 0x1000>; + + cpusec_cpurad_ipc_shm: memory@0 { + reg = <0x0 DT_SIZE_K(2)>; + }; + + cpurad_cpusec_ipc_shm: memory@800 { + reg = <0x800 DT_SIZE_K(2)>; + }; + }; + + cpuapp_ram0x_region: memory@2f012000 { + compatible = "nordic,owned-memory"; + reg = <0x2f012000 DT_SIZE_K(516)>; + status = "disabled"; + perm-read; + perm-write; + perm-secure; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2f012000 0x81000>; + + cpusec_cpuapp_ipc_shm: memory@0 { + reg = <0x0 DT_SIZE_K(2)>; + }; + + cpuapp_cpusec_ipc_shm: memory@800 { + reg = <0x800 DT_SIZE_K(2)>; + }; + + cpuapp_data: memory@1000 { + reg = <0x1000 DT_SIZE_K(512)>; + }; + }; + + cpuapp_cpurad_ram0x_region: memory@2f0cf000 { + compatible = "nordic,owned-memory"; + reg = <0x2f0cf000 DT_SIZE_K(4)>; + status = "disabled"; + perm-read; + perm-write; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2f0cf000 0x1000>; + + cpuapp_cpurad_ipc_shm: memory@0 { + reg = <0x0 DT_SIZE_K(2)>; + }; + + cpurad_cpuapp_ipc_shm: memory@800 { + reg = <0x800 DT_SIZE_K(2)>; + }; + }; + + cpuapp_cpucell_ram0x_region: memory@2f0d0000 { + reg = <0x2f0d0000 DT_SIZE_K(36)>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2f0d0000 0x9000>; + + /* Control region, with ICmsg buffers. + * Size is fixed. + */ + cpuapp_cpucell_ipc_shm_ctrl: memory@0 { + reg = <0x0 0x1000>; + }; + + /* TX heap, user defined */ + cpuapp_cpucell_ipc_shm_heap: memory@1000 { + reg = <0x1000 0x4000>; + }; + + /* RX heap, user defined */ + cpucell_cpuapp_ipc_shm_heap: memory@5000 { + reg = <0x5000 0x4000>; + }; + }; + + /* Shared memory ownership. + * TODO: + * remove these two after https://github.com/zephyrproject-rtos/zephyr/pull/72273 + * and let cpuapp_cpucell_ram0x_region use the `access` binding to describe + * the shared memory ownership. + */ + + cpuapp_cpucell_ipc_shm: memory@2 { + compatible = "nordic,owned-memory"; + reg = <0x2f0d0000 DT_SIZE_K(36)>; + owner-id = <2>; + perm-read; + perm-write; + status = "disabled"; + }; + + cpucell_cpuapp_ipc_shm: memory@4 { + compatible = "nordic,owned-memory"; + reg = <0x2f0d0000 DT_SIZE_K(36)>; + owner-id = <4>; + perm-read; + perm-write; + status = "disabled"; + }; + + shared_ram20_region: memory@2f88f000 { + reg = <0x2f88f000 DT_SIZE_K(4)>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2f88f000 0x1000>; + + cpuapp_cpusys_ipc_shm: memory@ce0 { + reg = <0xce0 0x80>; + }; + + cpusys_cpuapp_ipc_shm: memory@d60 { + reg = <0xd60 0x80>; + }; + + cpurad_cpusys_ipc_shm: memory@e00 { + reg = <0xe00 0x80>; + }; + + cpusys_cpurad_ipc_shm: memory@e80 { + reg = <0xe80 0x80>; + }; + }; + + ram21_region: memory@2f890000 { + compatible = "nordic,owned-memory"; + status = "disabled"; + reg = <0x2f890000 DT_SIZE_K(32)>; + perm-read; + perm-write; + perm-secure; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2f890000 0x8000>; + + dma_fast_region: memory@4000 { + compatible = "zephyr,memory-region"; + reg = <0x4000 DT_SIZE_K(16)>; + status = "disabled"; + #memory-region-cells = <0>; + zephyr,memory-region = "DMA_RAM21"; + zephyr,memory-attr = <( DT_MEM_DMA | DT_MEM_CACHEABLE )>; + }; + }; + + cpuppr_ram3x_region: memory@2fc00000 { + compatible = "nordic,owned-memory"; + reg = <0x2fc00000 DT_SIZE_K(24)>; + status = "disabled"; + perm-read; + perm-write; + perm-execute; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2fc00000 0x6000>; + + cpuppr_code_data: memory@0 { + reg = <0x0 DT_SIZE_K(22)>; + }; + + cpuapp_cpuppr_ipc_shm: memory@5800 { + reg = <0x5800 DT_SIZE_K(1)>; + }; + + cpuppr_cpuapp_ipc_shm: memory@5c00 { + reg = <0x5c00 DT_SIZE_K(1)>; + }; + }; + + shared_ram3x_region: memory@2fc06000 { + compatible = "nordic,owned-memory"; + reg = <0x2fc06000 DT_SIZE_K(8)>; + status = "disabled"; + perm-read; + perm-write; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2fc06000 0x4000>; + + cpuapp_dma_region: memory@0 { + compatible = "zephyr,memory-region"; + reg = <0x0 DT_SIZE_K(4)>; + status = "disabled"; + #memory-region-cells = <0>; + zephyr,memory-region = "DMA_RAM3x_APP"; + zephyr,memory-attr = <( DT_MEM_DMA )>; + }; + + cpurad_dma_region: memory@1000 { + compatible = "zephyr,memory-region"; + reg = <0x1000 0x80>; + status = "disabled"; + #memory-region-cells = <0>; + zephyr,memory-region = "DMA_RAM3x_RAD"; + zephyr,memory-attr = <( DT_MEM_DMA )>; + }; + }; + }; +}; + +&mram1x { + cpurad_rx_partitions: cpurad-rx-partitions { + compatible = "nordic,owned-partitions", "fixed-partitions"; + status = "disabled"; + perm-read; + perm-execute; + perm-secure; + #address-cells = <1>; + #size-cells = <1>; + + cpurad_slot0_partition: partition@402000 { + reg = <0x402000 DT_SIZE_K(256)>; + }; + }; + + cpuapp_rx_partitions: cpuapp-rx-partitions { + compatible = "nordic,owned-partitions", "fixed-partitions"; + status = "disabled"; + perm-read; + perm-execute; + perm-secure; + #address-cells = <1>; + #size-cells = <1>; + + cpuapp_slot0_partition: partition@442000 { + reg = <0x442000 DT_SIZE_K(1024)>; + }; + + cpuppr_code_partition: partition@542000 { + reg = <0x542000 DT_SIZE_K(64)>; + }; + }; + + cpuapp_rw_partitions: cpuapp-rw-partitions { + compatible = "nordic,owned-partitions", "fixed-partitions"; + status = "disabled"; + perm-read; + perm-write; + perm-secure; + #address-cells = <1>; + #size-cells = <1>; + + dfu_partition: partition@600000 { + reg = <0x600000 DT_SIZE_K(512)>; + }; + + storage_partition: partition@680000 { + reg = <0x680000 DT_SIZE_K(24)>; + }; + }; +}; diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-pinctrl.dtsi b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-pinctrl.dtsi new file mode 100644 index 00000000000..48067a7052c --- /dev/null +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-pinctrl.dtsi @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + /omit-if-no-ref/ uart135_default: uart135_default { + group1 { + psels = , + ; + }; + + group3 { + bias-pull-up; + psels = , + ; + }; + }; + + /omit-if-no-ref/ uart135_sleep: uart135_sleep { + group1 { + low-power-enable; + psels = , + , + , + ; + }; + }; + + /omit-if-no-ref/ uart136_default: uart136_default { + group1 { + psels = , + ; + }; + + group3 { + bias-pull-up; + psels = , + ; + }; + }; + + /omit-if-no-ref/ uart136_sleep: uart136_sleep { + group1 { + low-power-enable; + psels = , + , + , + ; + }; + }; + + /omit-if-no-ref/ exmif_default: exmif_default { + group1 { + psels = , + , + ; + nordic,drive-mode = ; + }; + }; + + /omit-if-no-ref/ can120_default: can120_default { + group1 { + psels = , + ; + }; + }; + + /omit-if-no-ref/ pwm130_default: pwm130_default { + group1 { + psels = ; + }; + }; + + /omit-if-no-ref/ pwm130_sleep: pwm130_sleep { + group1 { + psels = ; + low-power-enable; + }; + }; +}; diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts new file mode 100644 index 00000000000..c01824a2297 --- /dev/null +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts @@ -0,0 +1,322 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "nrf9280pdk_nrf9280-memory_map.dtsi" +#include "nrf9280pdk_nrf9280-ipc_conf.dtsi" +#include "nrf9280pdk_nrf9280-pinctrl.dtsi" + +/delete-node/ &cpurad_cpusys_ipc; +/delete-node/ &cpusec_cpurad_ipc; + +/ { + compatible = "nordic,nrf9280pdk_nrf9280-cpuapp"; + model = "Nordic nRF9280 DK nRF9280 Application MCU"; + + chosen { + zephyr,console = &uart136; + zephyr,code-partition = &cpuapp_slot0_partition; + zephyr,flash = &mram1x; + zephyr,sram = &cpuapp_data; + zephyr,shell-uart = &uart136; + zephyr,ieee802154 = &cpuapp_ieee802154; + zephyr,bt-hci = &bt_hci_ipc0; + nordic,802154-spinel-ipc = &ipc0; + zephyr,canbus = &can120; + zephyr,entropy = &prng; + }; + + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + led3 = &led3; + resetinfo = &cpuapp_resetinfo; + pwm-led0 = &pwm_led0; + sw0 = &button0; + sw1 = &button1; + sw2 = &button2; + sw3 = &button3; + ipc-to-cpusys = &cpuapp_cpusys_ipc; + watchdog0 = &wdt010; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 0"; + zephyr,code = ; + }; + + button1: button_1 { + gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 1"; + zephyr,code = ; + }; + + button2: button_2 { + gpios = <&gpio0 10 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 2"; + zephyr,code = ; + }; + + button3: button_3 { + gpios = <&gpio0 11 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 3"; + zephyr,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>; + label = "Green LED 0"; + }; + + led1: led_1 { + gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>; + label = "Green LED 1"; + }; + + led2: led_2 { + gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>; + label = "Green LED 2"; + }; + + led3: led_3 { + gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>; + label = "Green LED 3"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + /* + * LEDs are connected to GPIO Port 9 - pins 2-5. There is no valid hardware + * configuration to pass PWM signal on pins 0 and 1. First valid config is P9.2. + * Signal on PWM130's channel 0 can be passed directly on GPIO Port 9 pin 2. + */ + pwm_led0: pwm_led_0 { + pwms = <&pwm130 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; + + prng: prng { + compatible = "nordic,entropy-prng"; + status = "okay"; + }; +}; + +&cpuapp_ram0x_region { + status = "okay"; +}; + +&cpuapp_cpurad_ram0x_region { + status = "okay"; +}; + +&cpuapp_cpucell_ipc_shm { + status = "okay"; +}; + +&cpucell_cpuapp_ipc_shm { + status = "okay"; +}; + +&shared_ram3x_region { + status = "okay"; +}; + +&ram21_region { + status = "okay"; +}; + +&cpuapp_bellboard { + status = "okay"; + interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "irq0"; + /* The following bells on this bellboard are rang by these cores + * - Bell 0: cpusec + * - Bell 6: cpusys + * - Bell 13: cpuppr + * - Bell 18: cpurad + * - Bells 24, 25, 29, 31: cpucell + */ + nordic,interrupt-mapping = <0xA3042041 0>; +}; + +&cpurad_bellboard { + status = "okay"; +}; + +&cpucell_bellboard { + status = "okay"; +}; + +&cpusys_vevif { + status = "okay"; +}; + +&cpusec_cpuapp_ipc { + mbox-names = "tx", "rx"; + tx-region = <&cpuapp_cpusec_ipc_shm>; + rx-region = <&cpusec_cpuapp_ipc_shm>; +}; + +ipc0: &cpuapp_cpurad_ipc { + status = "okay"; + mbox-names = "rx", "tx"; + tx-region = <&cpuapp_cpurad_ipc_shm>; + rx-region = <&cpurad_cpuapp_ipc_shm>; + tx-blocks = <32>; + rx-blocks = <32>; + + bt_hci_ipc0: bt_hci_ipc0 { + compatible = "zephyr,bt-hci-ipc"; + status = "okay"; + }; +}; + +&cpuapp_cpusys_ipc { + status = "okay"; + mbox-names = "rx", "tx"; + tx-region = <&cpuapp_cpusys_ipc_shm>; + rx-region = <&cpusys_cpuapp_ipc_shm>; +}; + +&cpuapp_cpuppr_ipc { + mbox-names = "rx", "tx"; + tx-region = <&cpuapp_cpuppr_ipc_shm>; + rx-region = <&cpuppr_cpuapp_ipc_shm>; +}; + +&cpuapp_dma_region { + status = "okay"; +}; + +&dma_fast_region { + status = "okay"; +}; + +&cpuapp_rx_partitions { + status = "okay"; +}; + +&cpuapp_rw_partitions { + status = "okay"; +}; + +&cpuppr_vpr { + execution-memory = <&cpuppr_code_data>; + source-memory = <&cpuppr_code_partition>; +}; + +&gpiote130 { + status = "okay"; + owned-channels = <0 1 2 3 4 5 6 7>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio9 { + status = "okay"; +}; + +&grtc { + status = "okay"; + child-owned-channels = <5 6>; + nonsecure-channels = <5 6>; + owned-channels = <4 5 6>; +}; + +&uart135 { + current-speed = <115200>; + pinctrl-0 = <&uart135_default>; + pinctrl-1 = <&uart135_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart136 { + status = "okay"; + memory-regions = <&cpuapp_dma_region>; + current-speed = <115200>; + pinctrl-0 = <&uart136_default>; + pinctrl-1 = <&uart136_sleep>; + pinctrl-names = "default", "sleep"; + hw-flow-control; +}; + +&gpio6 { + status = "okay"; +}; + +&exmif { + cs-gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&exmif_default>; + pinctrl-names = "default"; + status = "okay"; + mx25uw63: mx25uw6345g@0 { + compatible = "jedec,spi-nor"; + status = "disabled"; + reg = <0>; + spi-max-frequency = ; + jedec-id = [c2 84 37]; + sfdp-bfp = [ + e5 20 8a ff ff ff ff 03 00 ff 00 ff 00 ff 00 ff + ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 10 d8 + 00 ff 00 ff 87 79 01 00 84 12 00 c4 cc 04 67 46 + 30 b0 30 b0 f4 bd d5 5c 00 00 00 ff 10 10 00 20 + 00 00 00 00 00 00 7c 23 48 00 00 00 00 00 88 88 + ]; + size = <67108864>; + has-dpd; + t-enter-dpd = <10000>; + t-exit-dpd = <30000>; + }; +}; + +&cpuapp_ieee802154 { + status = "okay"; +}; + +zephyr_udc0: &usbhs { + status = "okay"; +}; + +&canpll { + status = "okay"; +}; + +&can120 { + status = "okay"; + pinctrl-0 = <&can120_default>; + pinctrl-names = "default"; +}; + +&pwm130 { + status = "okay"; + pinctrl-0 = <&pwm130_default>; + pinctrl-1 = <&pwm130_sleep>; + pinctrl-names = "default", "sleep"; + memory-regions = <&cpuapp_dma_region>; +}; + +&adc { + memory-regions = <&cpuapp_dma_region>; + status = "okay"; +}; diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.yaml b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.yaml new file mode 100644 index 00000000000..9c2aff88052 --- /dev/null +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.yaml @@ -0,0 +1,24 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf9280pdk/nrf9280/cpuapp +name: nRF9280-DK-nRF9280-Application +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +sysbuild: true +ram: 512 +flash: 1024 +supported: + - adc + - can + - counter + - gpio + - i2c + - pwm + - spi + - watchdog + - usbd diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp_defconfig b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp_defconfig new file mode 100644 index 00000000000..e1ba596d135 --- /dev/null +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp_defconfig @@ -0,0 +1,28 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_USE_DT_CODE_PARTITION=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# MPU-based null-pointer dereferencing detection cannot be applied +# as the (0x0 - 0x400) region is unmapped for this target. +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y + +# Enable cache +CONFIG_CACHE_MANAGEMENT=y +CONFIG_EXTERNAL_CACHE=y + +# Enable GPIO +CONFIG_GPIO=y diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr.dts b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr.dts new file mode 100644 index 00000000000..5da976ef70d --- /dev/null +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr.dts @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "nrf9280pdk_nrf9280-memory_map.dtsi" +#include "nrf9280pdk_nrf9280-ipc_conf.dtsi" +#include "nrf9280pdk_nrf9280-pinctrl.dtsi" + +/delete-node/ &cpuapp_cpurad_ipc; +/delete-node/ &cpuapp_cpusys_ipc; +/delete-node/ &cpurad_cpusys_ipc; +/delete-node/ &cpusec_cpuapp_ipc; +/delete-node/ &cpusec_cpurad_ipc; + +/ { + compatible = "nordic,nrf9280pdk_nrf9280-cpuppr"; + model = "Nordic nRF9280 DK nRF9280 Peripheral Processor MCU"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &uart135; + zephyr,code-partition = &cpuppr_code_partition; + zephyr,flash = &mram1x; + zephyr,sram = &cpuppr_code_data; + zephyr,shell-uart = &uart135; + }; +}; + +&cpuapp_cpuppr_ipc { + mbox-names = "tx", "rx"; + tx-region = <&cpuppr_cpuapp_ipc_shm>; + rx-region = <&cpuapp_cpuppr_ipc_shm>; +}; + +&grtc { + status = "okay"; + owned-channels = <5>; +}; + +&uart135 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart135_default>; + pinctrl-1 = <&uart135_sleep>; + pinctrl-names = "default", "sleep"; + hw-flow-control; +}; + +&uart136 { + current-speed = <115200>; + pinctrl-0 = <&uart136_default>; + pinctrl-1 = <&uart136_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr.yaml b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr.yaml new file mode 100644 index 00000000000..958b5d462ae --- /dev/null +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf9280pdk/nrf9280/cpuppr +name: nRF9280-DK-nRF9280-PPR +type: mcu +arch: riscv +toolchain: + - zephyr +sysbuild: true +ram: 22 +flash: 22 +supported: + - counter + - gpio + - i2c + - pwm + - spi diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_defconfig b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_defconfig new file mode 100644 index 00000000000..b6ee6107d46 --- /dev/null +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_defconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_USE_DT_CODE_PARTITION=y + +# Execute from RAM +CONFIG_XIP=n diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_xip.dts b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_xip.dts new file mode 100644 index 00000000000..30034d2d4dc --- /dev/null +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_xip.dts @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "nrf9280pdk_nrf9280_cpuppr.dts" diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_xip.yaml b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_xip.yaml new file mode 100644 index 00000000000..d57f9c8d1be --- /dev/null +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_xip.yaml @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf9280pdk/nrf9280/cpuppr/xip +name: nRF9280-DK-nRF9280-PPR (MRAM XIP) +type: mcu +arch: riscv +toolchain: + - zephyr +sysbuild: true +ram: 22 +flash: 64 +supported: + - gpio diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_xip_defconfig b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_xip_defconfig new file mode 100644 index 00000000000..d73f271870b --- /dev/null +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_xip_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_USE_DT_CODE_PARTITION=y + +CONFIG_XIP=y diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad.dts b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad.dts new file mode 100644 index 00000000000..a45a00e5905 --- /dev/null +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad.dts @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "nrf9280pdk_nrf9280-memory_map.dtsi" +#include "nrf9280pdk_nrf9280-ipc_conf.dtsi" +#include "nrf9280pdk_nrf9280-pinctrl.dtsi" + +/delete-node/ &cpuapp_cpuppr_ipc; +/delete-node/ &cpuapp_cpusys_ipc; +/delete-node/ &cpusec_cpuapp_ipc; + +/ { + compatible = "nordic,nrf9280pdk_nrf9280-cpurad"; + model = "Nordic nRF9280 DK nRF9280 Radio MCU"; + + chosen { + zephyr,console = &uart135; + zephyr,code-partition = &cpurad_slot0_partition; + zephyr,flash = &mram1x; + zephyr,sram = &cpurad_ram0; + zephyr,shell-uart = &uart135; + zephyr,ieee802154 = &cpurad_ieee802154; + zephyr,bt-hci-ipc = &ipc0; + nordic,802154-spinel-ipc = &ipc0; + zephyr,entropy = &prng; + }; + prng: prng { + compatible = "nordic,entropy-prng"; + status = "okay"; + }; + aliases { + ipc-to-cpusys = &cpurad_cpusys_ipc; + resetinfo = &cpurad_resetinfo; + }; +}; + +&shared_ram3x_region { + status = "okay"; +}; + +&cpuapp_cpurad_ram0x_region { + status = "okay"; +}; + +&cpurad_bellboard { + status = "okay"; + interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "irq0"; + /* The following bells on this bellboard are rang by these cores + * - Bell 0: cpusec + * - Bell 6: cpusys + * - Bell 12: cpuapp + */ + nordic,interrupt-mapping = <0x00001041 0>; +}; + +&cpuapp_bellboard { + status = "okay"; +}; + +&cpusys_vevif { + status = "okay"; +}; + +&cpusec_cpurad_ipc { + mbox-names = "tx", "rx"; + tx-region = <&cpurad_cpusec_ipc_shm>; + rx-region = <&cpusec_cpurad_ipc_shm>; +}; + +ipc0: &cpuapp_cpurad_ipc { + status = "okay"; + mbox-names = "tx", "rx"; + tx-region = <&cpurad_cpuapp_ipc_shm>; + rx-region = <&cpuapp_cpurad_ipc_shm>; + tx-blocks = <32>; + rx-blocks = <32>; +}; + +&cpurad_cpusys_ipc { + status = "okay"; + mbox-names = "rx", "tx"; + tx-region = <&cpurad_cpusys_ipc_shm>; + rx-region = <&cpusys_cpurad_ipc_shm>; +}; + +&cpurad_dma_region { + status = "okay"; +}; + +&cpurad_rx_partitions { + status = "okay"; +}; + +&grtc { + status = "okay"; +}; + +&uart135 { + status = "okay"; + memory-regions = <&cpurad_dma_region>; + current-speed = <115200>; + pinctrl-0 = <&uart135_default>; + pinctrl-1 = <&uart135_sleep>; + pinctrl-names = "default", "sleep"; + hw-flow-control; +}; + +&uart136 { + current-speed = <115200>; + pinctrl-0 = <&uart136_default>; + pinctrl-1 = <&uart136_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&cpurad_ieee802154 { + status = "okay"; +}; diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad.yaml b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad.yaml new file mode 100644 index 00000000000..543a7377c1d --- /dev/null +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad.yaml @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf9280pdk/nrf9280/cpurad +name: nRF9280-DK-nRF9280-Radio +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +sysbuild: true +ram: 32 +flash: 256 +supported: + - counter + - gpio + - pwm + - spi diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad_defconfig b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad_defconfig new file mode 100644 index 00000000000..27df01dee12 --- /dev/null +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad_defconfig @@ -0,0 +1,25 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_USE_DT_CODE_PARTITION=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# MPU-based null-pointer dereferencing detection cannot be applied +# as the (0x0 - 0x400) region is unmapped for this target. +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y + +# Enable cache +CONFIG_CACHE_MANAGEMENT=y +CONFIG_EXTERNAL_CACHE=y diff --git a/boards/nordic/nrf9280pdk/support/nrf9280_cpuapp.JLinkScript b/boards/nordic/nrf9280pdk/support/nrf9280_cpuapp.JLinkScript new file mode 100644 index 00000000000..ffa1beed1ed --- /dev/null +++ b/boards/nordic/nrf9280pdk/support/nrf9280_cpuapp.JLinkScript @@ -0,0 +1,41 @@ +// Debug Halting Control and Status Register +__constant U32 _DHCSR_ADDR = 0xE000EDF0; +__constant U32 _DHCSR_DBGKEY = (0xA05F << 16); +__constant U32 _DHCSR_C_DEBUGEN = (1 << 0); +__constant U32 _DHCSR_C_HALT = (1 << 1); + +// Debug Exception and Monitor Control Register +__constant U32 _DEMCR_ADDR = 0xE000EDFC; +__constant U32 _DEMCR_VC_CORERESET = (1 << 0); +__constant U32 _DEMCR_TRCENA = (1 << 24); + +// CPU wait enable register +__constant U32 _CPUCONF_CPUWAIT_ADDR = 0x5201150C; + +int ResetTarget(void) { + // ADAC reset + JLINK_CORESIGHT_WriteDP(2, 0x04000010); + JLINK_CORESIGHT_WriteAP(0, 0xA3030000); + JLINK_CORESIGHT_WriteAP(0, 0x00000004); + JLINK_CORESIGHT_WriteAP(0, 0x01020000); + + JLINK_SYS_Sleep(100); + JLINK_CORESIGHT_ReadAP(2); + JLINK_CORESIGHT_ReadAP(2); + JLINK_CORESIGHT_ReadAP(2); + JLINK_CORESIGHT_ReadAP(2); + + // Halt the CPU + JLINK_MEM_WriteU32(_DHCSR_ADDR, (_DHCSR_DBGKEY | _DHCSR_C_HALT | _DHCSR_C_DEBUGEN)); + + // Set vector catch on reset (to halt the CPU immediately after reset) + JLINK_MEM_WriteU32(_DEMCR_ADDR, (_DEMCR_VC_CORERESET | _DEMCR_TRCENA)); + + // Disable CPU wait + JLINK_MEM_WriteU32(_CPUCONF_CPUWAIT_ADDR, 0); + + // Clear vector catch stuff + JLINK_MEM_WriteU32(_DEMCR_ADDR, _DEMCR_TRCENA); + + return 0; +} diff --git a/boards/nordic/nrf9280pdk/support/nrf9280_cpurad.JLinkScript b/boards/nordic/nrf9280pdk/support/nrf9280_cpurad.JLinkScript new file mode 100644 index 00000000000..2f1802801c1 --- /dev/null +++ b/boards/nordic/nrf9280pdk/support/nrf9280_cpurad.JLinkScript @@ -0,0 +1,48 @@ +// Debug Halting Control and Status Register +__constant U32 _DHCSR_ADDR = 0xE000EDF0; +__constant U32 _DHCSR_DBGKEY = (0xA05F << 16); +__constant U32 _DHCSR_C_DEBUGEN = (1 << 0); +__constant U32 _DHCSR_C_HALT = (1 << 1); + +// Debug Exception and Monitor Control Register +__constant U32 _DEMCR_ADDR = 0xE000EDFC; +__constant U32 _DEMCR_VC_CORERESET = (1 << 0); +__constant U32 _DEMCR_TRCENA = (1 << 24); + +// CPU wait enable register +__constant U32 _CPUCONF_CPUWAIT_ADDR = 0x5301150C; + +int ConfigTargetSettings(void) { + JLINK_ExecCommand("CORESIGHT_AddAP = Index=1 Type=AHB-AP"); + CORESIGHT_IndexAHBAPToUse = 1; + + return 0; +} + +int ResetTarget(void) { + // ADAC reset + JLINK_CORESIGHT_WriteDP(2, 0x04000010); + JLINK_CORESIGHT_WriteAP(0, 0xA3030000); + JLINK_CORESIGHT_WriteAP(0, 0x00000004); + JLINK_CORESIGHT_WriteAP(0, 0x01030000); + + JLINK_SYS_Sleep(100); + JLINK_CORESIGHT_ReadAP(2); + JLINK_CORESIGHT_ReadAP(2); + JLINK_CORESIGHT_ReadAP(2); + JLINK_CORESIGHT_ReadAP(2); + + // Halt the CPU + JLINK_MEM_WriteU32(_DHCSR_ADDR, (_DHCSR_DBGKEY | _DHCSR_C_HALT | _DHCSR_C_DEBUGEN)); + + // Set vector catch on reset (to halt the CPU immediately after reset) + JLINK_MEM_WriteU32(_DEMCR_ADDR, (_DEMCR_VC_CORERESET | _DEMCR_TRCENA)); + + // Disable CPU wait + JLINK_MEM_WriteU32(_CPUCONF_CPUWAIT_ADDR, 0); + + // Clear vector catch stuff + JLINK_MEM_WriteU32(_DEMCR_ADDR, _DEMCR_TRCENA); + + return 0; +} diff --git a/cmake/bintools/gnu/target_bintools.cmake b/cmake/bintools/gnu/target_bintools.cmake index f61860b31da..0fa06ea7c32 100644 --- a/cmake/bintools/gnu/target_bintools.cmake +++ b/cmake/bintools/gnu/target_bintools.cmake @@ -44,7 +44,7 @@ set_property(TARGET bintools PROPERTY elfconvert_flag_section_remove "--remove-s set_property(TARGET bintools PROPERTY elfconvert_flag_section_only "--only-section=") set_property(TARGET bintools PROPERTY elfconvert_flag_section_rename "--rename-section;") -set_property(TARGET bintools PROPERTY elfconvert_flag_lma_adjust "--change-section-lma;*+") +set_property(TARGET bintools PROPERTY elfconvert_flag_lma_adjust "--change-section-lma;") # Note, placing a ';' at the end results in the following param to be a list, # and hence space separated. diff --git a/drivers/adc/adc_nrfx_saadc.c b/drivers/adc/adc_nrfx_saadc.c index 01540640035..12ed83e3580 100644 --- a/drivers/adc/adc_nrfx_saadc.c +++ b/drivers/adc/adc_nrfx_saadc.c @@ -19,7 +19,7 @@ LOG_MODULE_REGISTER(adc_nrfx_saadc); #if (NRF_SAADC_HAS_AIN_AS_PIN) -#if defined(CONFIG_SOC_NRF54H20) +#if defined(CONFIG_SOC_NRF54H20) || defined(CONFIG_SOC_NRF9280) static const uint8_t saadc_psels[NRF_SAADC_AIN7 + 1] = { [NRF_SAADC_AIN0] = NRF_PIN_PORT_TO_PIN_NUMBER(0U, 1), [NRF_SAADC_AIN1] = NRF_PIN_PORT_TO_PIN_NUMBER(1U, 1), @@ -62,9 +62,9 @@ BUILD_ASSERT((NRF_SAADC_AIN0 == NRF_SAADC_INPUT_AIN0) && "Definitions from nrf-adc.h do not match those from nrf_saadc.h"); #endif -#ifdef CONFIG_SOC_NRF54H20 +#if defined(CONFIG_SOC_NRF54H20) || defined(CONFIG_SOC_NRF9280) -/* nRF54H20 always uses bounce buffers in RAM */ +/* nRF54H20 and nRF9280 always use bounce buffers in RAM */ #define SAADC_MEMORY_SECTION \ COND_CODE_1(DT_NODE_HAS_PROP(DT_NODELABEL(adc), memory_regions), \ @@ -76,7 +76,7 @@ static uint16_t adc_samples_buffer[SAADC_CH_NUM] SAADC_MEMORY_SECTION; #define ADC_BUFFER_IN_RAM -#endif /* CONFIG_SOC_NRF54H20 */ +#endif /* defined(CONFIG_SOC_NRF54H20) || defined(CONFIG_SOC_NRF9280) */ struct driver_data { struct adc_context ctx; @@ -608,7 +608,7 @@ static const struct adc_driver_api adc_nrfx_driver_api = { #endif #if defined(CONFIG_SOC_NRF54L15) .ref_internal = 900, -#elif defined(CONFIG_SOC_NRF54H20) +#elif defined(CONFIG_SOC_NRF54H20) || defined(CONFIG_SOC_NRF9280) .ref_internal = 1024, #else .ref_internal = 600, diff --git a/drivers/entropy/Kconfig.nrf_prng b/drivers/entropy/Kconfig.nrf_prng index e1b1a9ab4fe..fb78f5ce013 100644 --- a/drivers/entropy/Kconfig.nrf_prng +++ b/drivers/entropy/Kconfig.nrf_prng @@ -9,7 +9,7 @@ config FAKE_ENTROPY_NRF_PRNG bool "A fake nRF entropy driver" default y depends on DT_HAS_NORDIC_ENTROPY_PRNG_ENABLED - depends on SOC_SERIES_NRF54HX + depends on (SOC_SERIES_NRF54HX || SOC_SERIES_NRF92X) select ENTROPY_HAS_DRIVER help This is a super simple PRNG driver that can be used on nRF platforms that diff --git a/drivers/mbox/mbox_nrf_bellboard_rx.c b/drivers/mbox/mbox_nrf_bellboard_rx.c index 8b98d361d0c..54dd21b9624 100644 --- a/drivers/mbox/mbox_nrf_bellboard_rx.c +++ b/drivers/mbox/mbox_nrf_bellboard_rx.c @@ -8,6 +8,7 @@ #include #include #include +#include #include @@ -47,11 +48,20 @@ static void bellboard_rx_isr(const void *parameter) for (uint8_t i = 0U; i < NRF_BELLBOARD_EVENTS_TRIGGERED_COUNT; i++) { nrf_bellboard_event_t event = nrf_bellboard_triggered_event_get(i); - if (nrf_bellboard_event_check(bellboard, event)) { + if ((int_pend & BIT(i)) != 0U) { + /* Only clear those events that have their corresponding bit set + * in INTPEND at the time we read it. Otherwise, if two (or more) + * events are generated in quick succession, INTPEND may be set for + * only one of events, but we clear the EVENTS_TRIGGERED bit for + * all of them, thus losing them. + * + * Assume nrf_bellboard_event_check() is true for the event + * that raised this interrupt. + */ + __ASSERT_NO_MSG(nrf_bellboard_event_check(bellboard, event)); + nrf_bellboard_event_clear(bellboard, event); - } - if ((int_pend & BIT(i)) != 0U) { if (cbs[i] != NULL) { cbs[i](DEVICE_DT_INST_GET(0), i, cbs_ctx[i], NULL); } diff --git a/drivers/serial/Kconfig.nrfx b/drivers/serial/Kconfig.nrfx index 930dd00e3d8..daf185cd7e8 100644 --- a/drivers/serial/Kconfig.nrfx +++ b/drivers/serial/Kconfig.nrfx @@ -32,7 +32,8 @@ config UART_NRFX_UARTE_LEGACY_SHIM bool "Legacy UARTE shim" depends on UART_NRFX_UARTE depends on !SOC_SERIES_NRF54LX - depends on RISCV || !SOC_SERIES_NRF54HX + depends on !SOC_SERIES_NRF54HX || RISCV + depends on !SOC_SERIES_NRF92X || RISCV # New shim takes more ROM. Until it is fixed use legacy shim. default y diff --git a/dts/arm/nordic/nrf9280_cpuapp.dtsi b/dts/arm/nordic/nrf9280_cpuapp.dtsi new file mode 100644 index 00000000000..29edae31051 --- /dev/null +++ b/dts/arm/nordic/nrf9280_cpuapp.dtsi @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +cpu: &cpuapp {}; +systick: &cpuapp_systick {}; +nvic: &cpuapp_nvic {}; +cpuppr_vevif: &cpuppr_vevif_tx {}; +cpusys_vevif: &cpusys_vevif_tx {}; +wdt010: &cpuapp_wdt010 {}; +wdt011: &cpuapp_wdt011 {}; + +/delete-node/ &cpuppr; +/delete-node/ &cpurad; +/delete-node/ &cpurad_peripherals; +/delete-node/ &cpurad_ppb; +/delete-node/ &cpurad_ram0; + +/ { + soc { + compatible = "simple-bus"; + interrupt-parent = <&cpuapp_nvic>; + ranges; + }; +}; + +&cpuapp_ppb { + compatible = "simple-bus"; + ranges; +}; + +&cpusec_bellboard { + compatible = "nordic,nrf-bellboard-tx"; +}; + +&cpuapp_bellboard { + compatible = "nordic,nrf-bellboard-rx"; +}; + +&cpurad_bellboard { + compatible = "nordic,nrf-bellboard-tx"; +}; + +&cpucell_bellboard { + compatible = "nordic,nrf-bellboard-tx"; +}; + +&gpiote130 { + interrupts = <105 NRF_DEFAULT_IRQ_PRIORITY>; +}; + +&gpiote131 { + interrupts = <107 NRF_DEFAULT_IRQ_PRIORITY>; +}; + +&grtc { + interrupts = <109 NRF_DEFAULT_IRQ_PRIORITY>; +}; diff --git a/dts/arm/nordic/nrf9280_cpurad.dtsi b/dts/arm/nordic/nrf9280_cpurad.dtsi new file mode 100644 index 00000000000..265cd623953 --- /dev/null +++ b/dts/arm/nordic/nrf9280_cpurad.dtsi @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +cpu: &cpurad {}; +systick: &cpurad_systick {}; +nvic: &cpurad_nvic {}; +cpuppr_vevif: &cpuppr_vevif_tx {}; +cpusys_vevif: &cpusys_vevif_tx {}; +wdt010: &cpurad_wdt010 {}; +wdt011: &cpurad_wdt011 {}; + +/delete-node/ &cpuapp; +/delete-node/ &cpuapp_peripherals; +/delete-node/ &cpuapp_ppb; +/delete-node/ &cpuapp_ram0; +/delete-node/ &cpuppr; + +/ { + soc { + compatible = "simple-bus"; + interrupt-parent = <&cpurad_nvic>; + ranges; + }; +}; + +&cpurad_ppb { + compatible = "simple-bus"; + ranges; +}; + +&cpusec_bellboard { + compatible = "nordic,nrf-bellboard-tx"; +}; + +&cpuapp_bellboard { + compatible = "nordic,nrf-bellboard-tx"; +}; + +&cpurad_bellboard { + compatible = "nordic,nrf-bellboard-rx"; +}; + +&gpiote130 { + interrupts = <105 NRF_DEFAULT_IRQ_PRIORITY>; +}; + +&grtc { + owned-channels = <7 8 9 10 11 12 13 14 15>; + child-owned-channels = <8 9 10 11 12>; + nonsecure-channels = <8 9 10 11 12>; + interrupts = <109 NRF_DEFAULT_IRQ_PRIORITY>, + <109 NRF_DEFAULT_IRQ_PRIORITY>, + <110 NRF_DEFAULT_IRQ_PRIORITY>; +}; + +&dppic130 { + owned-channels = <0>; + sink-channels = <0>; + nonsecure-channels = <0>; + status = "okay"; +}; + +&dppic132 { + owned-channels = <0>; + source-channels = <0>; + nonsecure-channels = <0>; + status = "okay"; +}; + +&ipct130 { + owned-channels = <0>; + source-channel-links = <0 3 0>; + status = "okay"; +}; diff --git a/dts/common/nordic/nrf9280.dtsi b/dts/common/nordic/nrf9280.dtsi new file mode 100644 index 00000000000..166c8658354 --- /dev/null +++ b/dts/common/nordic/nrf9280.dtsi @@ -0,0 +1,1270 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include +#include +#include + +/delete-node/ &sw_pwm; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpuapp: cpu@2 { + compatible = "arm,cortex-m33"; + reg = <2>; + device_type = "cpu"; + clock-frequency = ; + }; + + cpurad: cpu@3 { + compatible = "arm,cortex-m33"; + reg = <3>; + device_type = "cpu"; + clock-frequency = ; + }; + + cpuppr: cpu@d { + compatible = "nordic,vpr"; + reg = <13>; + device_type = "cpu"; + clock-frequency = ; + riscv,isa = "rv32emc"; + nordic,bus-width = <32>; + + cpuppr_vevif_rx: mailbox { + compatible = "nordic,nrf-vevif-task-rx"; + status = "disabled"; + interrupt-parent = <&cpuppr_clic>; + interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>, + <1 NRF_DEFAULT_IRQ_PRIORITY>, + <2 NRF_DEFAULT_IRQ_PRIORITY>, + <3 NRF_DEFAULT_IRQ_PRIORITY>, + <4 NRF_DEFAULT_IRQ_PRIORITY>, + <5 NRF_DEFAULT_IRQ_PRIORITY>, + <6 NRF_DEFAULT_IRQ_PRIORITY>, + <7 NRF_DEFAULT_IRQ_PRIORITY>, + <8 NRF_DEFAULT_IRQ_PRIORITY>, + <9 NRF_DEFAULT_IRQ_PRIORITY>, + <10 NRF_DEFAULT_IRQ_PRIORITY>, + <11 NRF_DEFAULT_IRQ_PRIORITY>, + <12 NRF_DEFAULT_IRQ_PRIORITY>, + <13 NRF_DEFAULT_IRQ_PRIORITY>, + <14 NRF_DEFAULT_IRQ_PRIORITY>, + <15 NRF_DEFAULT_IRQ_PRIORITY>; + #mbox-cells = <1>; + nordic,tasks = <16>; + nordic,tasks-mask = <0x0000fff0>; + }; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + + cpurad_uicr_ext: memory@e401000 { + reg = <0xe401000 DT_SIZE_K(2)>; + }; + + cpuapp_uicr_ext: memory@e401800 { + reg = <0xe401800 DT_SIZE_K(2)>; + }; + }; + + clocks { + hfxo: hfxo { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = ; + }; + + fll16m: fll16m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = ; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + + mram1x: mram@e000000 { + compatible = "nordic,mram"; + reg = <0xe000000 DT_SIZE_K(8192)>; + erase-block-size = <4096>; + write-block-size = <16>; + }; + + cpuapp_uicr: uicr@fff8000 { + compatible = "nordic,nrf-uicr-v2"; + reg = <0xfff8000 DT_SIZE_K(2)>; + domain = <2>; + ptr-ext-uicr = <&cpuapp_uicr_ext>; + }; + + cpurad_uicr: uicr@fffa000 { + compatible = "nordic,nrf-uicr-v2"; + reg = <0xfffa000 DT_SIZE_K(2)>; + domain = <3>; + ptr-ext-uicr = <&cpurad_uicr_ext>; + }; + + ficr: ficr@fffe000 { + compatible = "nordic,nrf-ficr"; + reg = <0xfffe000 DT_SIZE_K(2)>; + #nordic,ficr-cells = <1>; + }; + + cpuapp_ram0: sram@22000000 { + compatible = "mmio-sram"; + reg = <0x22000000 DT_SIZE_K(32)>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x22000000 0x8000>; + }; + + cpurad_ram0: sram@23000000 { + compatible = "mmio-sram"; + reg = <0x23000000 DT_SIZE_K(192)>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x23000000 0x30000>; + }; + + cpurad_ram1: sram@23040000 { + compatible = "mmio-sram"; + reg = <0x23040000 DT_SIZE_K(32)>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x23040000 0x8000>; + }; + + cpuapp_peripherals: peripheral@52000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x52000000 0x1000000>; + + cpuapp_hsfll: clock@d000 { + compatible = "nordic,nrf-hsfll"; + #clock-cells = <0>; + reg = <0xd000 0x1000>; + clocks = <&fll16m>; + clock-frequency = ; + nordic,ficrs = + <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP>, + <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_0>, + <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_0>; + nordic,ficr-names = "vsup", "coarse", "fine"; + }; + + cpuapp_ipct: ipct@13000 { + compatible = "nordic,nrf-ipct-local"; + reg = <0x13000 0x1000>; + status = "disabled"; + channels = <4>; + interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>, + <65 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + cpuapp_wdt010: watchdog@14000 { + compatible = "nordic,nrf-wdt"; + reg = <0x14000 0x1000>; + status = "disabled"; + interrupts = <20 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + cpuapp_wdt011: watchdog@15000 { + compatible = "nordic,nrf-wdt"; + reg = <0x15000 0x1000>; + status = "disabled"; + interrupts = <21 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + cpuapp_ieee802154: ieee802154 { + compatible = "nordic,nrf-ieee802154"; + status = "disabled"; + }; + + cpuapp_resetinfo: resetinfo@1e000 { + compatible = "nordic,nrf-resetinfo"; + reg = <0x1e000 0x1000>; + }; + }; + + cpurad_peripherals: peripheral@53000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x53000000 0x1000000>; + + cpurad_hsfll: clock@d000 { + compatible = "nordic,nrf-hsfll"; + #clock-cells = <0>; + reg = <0xd000 0x1000>; + clocks = <&fll16m>; + clock-frequency = ; + nordic,ficrs = + <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP>, + <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_1>, + <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_1>; + nordic,ficr-names = "vsup", "coarse", "fine"; + }; + + cpurad_wdt010: watchdog@13000 { + compatible = "nordic,nrf-wdt"; + reg = <0x13000 0x1000>; + status = "disabled"; + interrupts = <19 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + cpurad_wdt011: watchdog@14000 { + compatible = "nordic,nrf-wdt"; + reg = <0x14000 0x1000>; + status = "disabled"; + interrupts = <20 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + cpurad_resetinfo: resetinfo@1e000 { + compatible = "nordic,nrf-resetinfo"; + reg = <0x1e000 0x1000>; + }; + + dppic020: dppic@22000 { + compatible = "nordic,nrf-dppic-local"; + reg = <0x22000 0x1000>; + status = "disabled"; + }; + + cpurad_ipct: ipct@24000 { + compatible = "nordic,nrf-ipct-local"; + reg = <0x24000 0x1000>; + status = "disabled"; + channels = <8>; + interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>, + <65 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + egu020: egu@25000 { + compatible = "nordic,nrf-egu"; + reg = <0x25000 0x1000>; + status = "disabled"; + interrupts = <37 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + timer020: timer@28000 { + compatible = "nordic,nrf-timer"; + reg = <0x28000 0x1000>; + status = "disabled"; + cc-num = <8>; + interrupts = <40 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + max-frequency = ; + prescaler = <0>; + }; + + timer021: timer@29000 { + compatible = "nordic,nrf-timer"; + reg = <0x29000 0x1000>; + status = "disabled"; + cc-num = <8>; + interrupts = <41 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + max-frequency = ; + prescaler = <0>; + }; + + timer022: timer@2a000 { + compatible = "nordic,nrf-timer"; + reg = <0x2a000 0x1000>; + status = "disabled"; + cc-num = <8>; + interrupts = <42 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + max-frequency = ; + prescaler = <0>; + }; + + rtc: rtc@2b000 { + compatible = "nordic,nrf-rtc"; + reg = <0x2b000 0x1000>; + status = "disabled"; + cc-num = <4>; + clock-frequency = <32768>; + interrupts = <43 NRF_DEFAULT_IRQ_PRIORITY>; + prescaler = <1>; + }; + + radio: radio@2c000 { + compatible = "nordic,nrf-radio"; + reg = <0x2c000 0x1000>; + status = "disabled"; + ble-2mbps-supported; + ble-coded-phy-supported; + dfe-supported; + ieee802154-supported; + interrupts = <44 NRF_DEFAULT_IRQ_PRIORITY>; + + cpurad_ieee802154: ieee802154 { + compatible = "nordic,nrf-ieee802154"; + status = "disabled"; + }; + }; + + ccm030: ccm@3a000 { + compatible = "nordic,nrf-ccm"; + reg = <0x3a000 0x1000>; + interrupts = <58 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + ecb030: ecb@3b000 { + compatible = "nordic,nrf-ecb"; + reg = <0x3b000 0x1000>; + interrupts = <59 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + ccm031: ccm@3c000 { + compatible = "nordic,nrf-ccm"; + reg = <0x3c000 0x1000>; + interrupts = <60 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + ecb031: ecb@3d000 { + compatible = "nordic,nrf-ecb"; + reg = <0x3d000 0x1000>; + status = "disabled"; + interrupts = <61 NRF_DEFAULT_IRQ_PRIORITY>; + }; + }; + + global_peripherals: peripheral@5f000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5f000000 0x1000000>; + + usbhs: usbhs@86000 { + compatible = "nordic,nrf-usbhs", "snps,dwc2"; + reg = <0x86000 0x1000>, <0x2f700000 0x40000>; + reg-names = "wrapper", "core"; + interrupts = <134 NRF_DEFAULT_IRQ_PRIORITY>; + num-in-eps = <8>; + num-out-eps = <10>; + ghwcfg1 = <0xaa555000>; + ghwcfg2 = <0x22abfc72>; + ghwcfg4 = <0x1e10aa60>; + status = "disabled"; + }; + + exmif: spi@95000 { + compatible = "nordic,nrf-exmif"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x95000 0x500 0x95500 0xb00>; + reg-names = "wrapper", "core"; + interrupts = <149 NRF_DEFAULT_IRQ_PRIORITY>; + clock-frequency = ; + fifo-depth = <32>; + max-xfer-size = <16>; + status = "disabled"; + }; + + cpusec_bellboard: mailbox@99000 { + reg = <0x99000 0x1000>; + status = "disabled"; + #mbox-cells = <1>; + }; + + cpuapp_bellboard: mailbox@9a000 { + reg = <0x9a000 0x1000>; + status = "disabled"; + #mbox-cells = <1>; + }; + + cpurad_bellboard: mailbox@9b000 { + reg = <0x9b000 0x1000>; + status = "disabled"; + #mbox-cells = <1>; + }; + + cpucell_bellboard: mailbox@9c000 { + reg = <0x9c000 0x1000>; + status = "disabled"; + #mbox-cells = <1>; + }; + + canpll: clock-controller@8c2000{ + compatible = "nordic,nrf-auxpll"; + reg = <0x8c2000 0x1000>; + interrupts = <194 NRF_DEFAULT_IRQ_PRIORITY>; + clocks = <&hfxo>; + #clock-cells = <0>; + nordic,ficrs = <&ficr NRF_FICR_TRIM_GLOBAL_CANPLL_TRIM_CTUNE>; + nordic,frequency = <0>; + nordic,out-div = <2>; + nordic,out-drive = <0>; + nordic,current-tune = <6>; + nordic,sdm-disable; + nordic,range = "high"; + status = "disabled"; + }; + + cpusys_vevif_tx: mailbox@8c8000 { + compatible = "nordic,nrf-vevif-task-tx"; + reg = <0x8c8000 0x1000>; + status = "disabled"; + #mbox-cells = <1>; + nordic,tasks = <32>; + nordic,tasks-mask = <0xfffff0ff>; + }; + + ipct120: ipct@8d1000 { + compatible = "nordic,nrf-ipct-global"; + reg = <0x8d1000 0x1000>; + status = "disabled"; + channels = <8>; + global-domain-id = <12>; + }; + + can120: can@8d8000 { + compatible = "nordic,nrf-can"; + reg = <0x8d8000 0x400>, <0x2fbef800 0x800>, <0x2fbe8000 0x7800>; + reg-names = "wrapper", "m_can", "message_ram"; + interrupts = <216 NRF_DEFAULT_IRQ_PRIORITY>; + clocks = <&canpll>; + bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>; + status = "disabled"; + }; + + can121: can@8db000 { + compatible = "nordic,nrf-can"; + reg = <0x8db000 0x400>, <0x2fbf7800 0x800>, <0x2fbf0000 0x7800>; + reg-names = "wrapper", "m_can", "message_ram"; + interrupts = <219 NRF_DEFAULT_IRQ_PRIORITY>; + clocks = <&canpll>; + bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>; + status = "disabled"; + }; + + dppic120: dppic@8e1000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x8e1000 0x1000>; + status = "disabled"; + }; + + timer120: timer@8e2000 { + compatible = "nordic,nrf-timer"; + reg = <0x8e2000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <226 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + max-frequency = ; + prescaler = <0>; + }; + + timer121: timer@8e3000 { + compatible = "nordic,nrf-timer"; + reg = <0x8e3000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <227 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + max-frequency = ; + prescaler = <0>; + }; + + pwm120: pwm@8e4000 { + compatible = "nordic,nrf-pwm"; + reg = <0x8e4000 0x1000>; + status = "disabled"; + interrupts = <228 NRF_DEFAULT_IRQ_PRIORITY>; + #pwm-cells = <3>; + }; + + spi120: spi@8e6000 { + compatible = "nordic,nrf-spim"; + reg = <0x8e6000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <230 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + rx-delay-supported; + rx-delay = <1>; + nordic,clockpin-enable = , + ; + }; + + uart120: uart@8e6000 { + compatible = "nordic,nrf-uarte"; + reg = <0x8e6000 0x1000>; + status = "disabled"; + interrupts = <230 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + spi121: spi@8e7000 { + compatible = "nordic,nrf-spim"; + reg = <0x8e7000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <231 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + rx-delay-supported; + rx-delay = <1>; + nordic,clockpin-enable = , + ; + }; + + cpuppr_vpr: vpr@908000 { + compatible = "nordic,nrf-vpr-coprocessor"; + reg = <0x908000 0x1000>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x908000 0x1000>; + + cpuppr_vevif_tx: mailbox@0 { + compatible = "nordic,nrf-vevif-task-tx"; + reg = <0x0 0x1000>; + status = "disabled"; + #mbox-cells = <1>; + nordic,tasks = <16>; + nordic,tasks-mask = <0x0000fff0>; + }; + }; + + ipct130: ipct@921000 { + compatible = "nordic,nrf-ipct-global"; + reg = <0x921000 0x1000>; + status = "disabled"; + channels = <8>; + global-domain-id = <13>; + }; + + dppic130: dppic@922000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x922000 0x1000>; + status = "disabled"; + }; + + rtc130: rtc@928000 { + compatible = "nordic,nrf-rtc"; + reg = <0x928000 0x1000>; + status = "disabled"; + cc-num = <4>; + clock-frequency = <32768>; + interrupts = <296 NRF_DEFAULT_IRQ_PRIORITY>; + prescaler = <1>; + }; + + rtc131: rtc@929000 { + compatible = "nordic,nrf-rtc"; + reg = <0x929000 0x1000>; + status = "disabled"; + cc-num = <4>; + clock-frequency = <32768>; + interrupts = <297 NRF_DEFAULT_IRQ_PRIORITY>; + prescaler = <1>; + }; + + wdt131: watchdog@92b000 { + compatible = "nordic,nrf-wdt"; + reg = <0x92b000 0x1000>; + status = "disabled"; + interrupts = <299 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + wdt132: watchdog@92c000 { + compatible = "nordic,nrf-wdt"; + reg = <0x92c000 0x1000>; + status = "disabled"; + interrupts = <300 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + gpiote130: gpiote@934000 { + compatible = "nordic,nrf-gpiote"; + reg = <0x934000 0x1000>; + status = "disabled"; + instance = <130>; + }; + + gpiote131: gpiote@935000 { + compatible = "nordic,nrf-gpiote"; + reg = <0x935000 0x1000>; + status = "disabled"; + instance = <131>; + }; + + gpio0: gpio@938000 { + compatible = "nordic,nrf-gpio"; + reg = <0x938000 0x200>; + status = "disabled"; + #gpio-cells = <2>; + gpio-controller; + gpiote-instance = <&gpiote130>; + ngpios = <13>; + port = <0>; + }; + + gpio1: gpio@938200 { + compatible = "nordic,nrf-gpio"; + reg = <0x938200 0x200>; + status = "disabled"; + #gpio-cells = <2>; + gpio-controller; + gpiote-instance = <&gpiote130>; + ngpios = <12>; + port = <1>; + }; + + gpio2: gpio@938400 { + compatible = "nordic,nrf-gpio"; + reg = <0x938400 0x200>; + status = "disabled"; + #gpio-cells = <2>; + gpio-controller; + gpiote-instance = <&gpiote130>; + ngpios = <12>; + port = <2>; + }; + + gpio6: gpio@938c00 { + compatible = "nordic,nrf-gpio"; + reg = <0x938c00 0x200>; + status = "disabled"; + #gpio-cells = <2>; + gpio-controller; + ngpios = <14>; + port = <6>; + }; + + gpio8: gpio@939000 { + compatible = "nordic,nrf-gpio"; + reg = <0x939000 0x200>; + status = "disabled"; + #gpio-cells = <2>; + gpio-controller; + ngpios = <5>; + port = <8>; + }; + + gpio9: gpio@939200 { + compatible = "nordic,nrf-gpio"; + reg = <0x939200 0x200>; + status = "disabled"; + #gpio-cells = <2>; + gpio-controller; + gpiote-instance = <&gpiote130>; + ngpios = <6>; + port = <9>; + }; + + gpio10: gpio@939400 { + compatible = "nordic,nrf-gpio"; + reg = <0x939400 0x200>; + status = "disabled"; + #gpio-cells = <2>; + gpio-controller; + ngpios = <8>; + port = <10>; + }; + + gpio11: gpio@939600 { + compatible = "nordic,nrf-gpio"; + reg = <0x939600 0x200>; + status = "disabled"; + #gpio-cells = <2>; + gpio-controller; + gpiote-instance = <&gpiote131>; + ngpios = <8>; + port = <11>; + }; + + gpio12: gpio@939800 { + compatible = "nordic,nrf-gpio"; + reg = <0x939800 0x200>; + status = "disabled"; + #gpio-cells = <2>; + gpio-controller; + gpiote-instance = <&gpiote131>; + ngpios = <3>; + port = <12>; + }; + + gpio13: gpio@939a00 { + compatible = "nordic,nrf-gpio"; + reg = <0x939a00 0x200>; + status = "disabled"; + #gpio-cells = <2>; + gpio-controller; + gpiote-instance = <&gpiote131>; + ngpios = <4>; + port = <13>; + }; + + dppic131: dppic@981000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x981000 0x1000>; + status = "disabled"; + }; + + adc: adc@982000 { + compatible = "nordic,nrf-saadc"; + reg = <0x982000 0x1000>; + interrupts = <386 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + #io-channel-cells = <1>; + }; + + comp: comparator@983000 { + compatible = "nordic,nrf-comp"; + reg = <0x983000 0x1000>; + status = "disabled"; + interrupts = <387 NRF_DEFAULT_IRQ_PRIORITY>; + #io-channel-cells = <1>; + }; + + temp: temperature-sensor@984000 { + compatible = "nordic,nrf-temp"; + reg = <0x984000 0x1000>; + interrupts = <388 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + dppic132: dppic@991000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x991000 0x1000>; + status = "disabled"; + }; + + qdec130: qdec@994000 { + compatible = "nordic,nrf-qdec"; + reg = <0x994000 0x1000>; + status = "disabled"; + interrupts = <404 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + qdec131: qdec@995000 { + compatible = "nordic,nrf-qdec"; + reg = <0x995000 0x1000>; + status = "disabled"; + interrupts = <405 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + grtc: grtc@99c000 { + compatible = "nordic,nrf-grtc"; + reg = <0x99c000 0x1000>; + status = "disabled"; + cc-num = <16>; + }; + + dppic133: dppic@9a1000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x9a1000 0x1000>; + status = "disabled"; + }; + + timer130: timer@9a2000 { + compatible = "nordic,nrf-timer"; + reg = <0x9a2000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <418 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + timer131: timer@9a3000 { + compatible = "nordic,nrf-timer"; + reg = <0x9a3000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <419 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + pwm130: pwm@9a4000 { + compatible = "nordic,nrf-pwm"; + reg = <0x9a4000 0x1000>; + status = "disabled"; + interrupts = <420 NRF_DEFAULT_IRQ_PRIORITY>; + #pwm-cells = <3>; + }; + + i2c130: i2c@9a5000 { + compatible = "nordic,nrf-twim"; + reg = <0x9a5000 0x1000>; + status = "disabled"; + interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; + easydma-maxcnt-bits = <15>; + #address-cells = <1>; + #size-cells = <0>; + nordic,clockpin-enable = , + ; + }; + + spi130: spi@9a5000 { + compatible = "nordic,nrf-spim"; + reg = <0x9a5000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + rx-delay-supported; + rx-delay = <1>; + nordic,clockpin-enable = , + , + , + ; + }; + + uart130: uart@9a5000 { + compatible = "nordic,nrf-uarte"; + reg = <0x9a5000 0x1000>; + status = "disabled"; + interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; + nordic,clockpin-enable = ; + }; + + i2c131: i2c@9a6000 { + compatible = "nordic,nrf-twim"; + reg = <0x9a6000 0x1000>; + status = "disabled"; + interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; + easydma-maxcnt-bits = <15>; + #address-cells = <1>; + #size-cells = <0>; + nordic,clockpin-enable = , + ; + }; + + spi131: spi@9a6000 { + compatible = "nordic,nrf-spim"; + reg = <0x9a6000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + rx-delay-supported; + rx-delay = <1>; + nordic,clockpin-enable = , + , + , + ; + }; + + uart131: uart@9a6000 { + compatible = "nordic,nrf-uarte"; + reg = <0x9a6000 0x1000>; + status = "disabled"; + interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; + nordic,clockpin-enable = ; + }; + + dppic134: dppic@9b1000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x9b1000 0x1000>; + status = "disabled"; + }; + + timer132: timer@9b2000 { + compatible = "nordic,nrf-timer"; + reg = <0x9b2000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <434 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + timer133: timer@9b3000 { + compatible = "nordic,nrf-timer"; + reg = <0x9b3000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <435 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + pwm131: pwm@9b4000 { + compatible = "nordic,nrf-pwm"; + reg = <0x9b4000 0x1000>; + status = "disabled"; + interrupts = <436 NRF_DEFAULT_IRQ_PRIORITY>; + #pwm-cells = <3>; + }; + + i2c132: i2c@9b5000 { + compatible = "nordic,nrf-twim"; + reg = <0x9b5000 0x1000>; + status = "disabled"; + interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; + easydma-maxcnt-bits = <15>; + #address-cells = <1>; + #size-cells = <0>; + nordic,clockpin-enable = , + ; + }; + + spi132: spi@9b5000 { + compatible = "nordic,nrf-spim"; + reg = <0x9b5000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + rx-delay-supported; + rx-delay = <1>; + nordic,clockpin-enable = , + , + , + ; + }; + + uart132: uart@9b5000 { + compatible = "nordic,nrf-uarte"; + reg = <0x9b5000 0x1000>; + status = "disabled"; + interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; + nordic,clockpin-enable = ; + }; + + i2c133: i2c@9b6000 { + compatible = "nordic,nrf-twim"; + reg = <0x9b6000 0x1000>; + status = "disabled"; + interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; + easydma-maxcnt-bits = <15>; + #address-cells = <1>; + #size-cells = <0>; + nordic,clockpin-enable = , + ; + }; + + spi133: spi@9b6000 { + compatible = "nordic,nrf-spim"; + reg = <0x9b6000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + rx-delay-supported; + rx-delay = <1>; + nordic,clockpin-enable = , + , + , + ; + }; + + uart133: uart@9b6000 { + compatible = "nordic,nrf-uarte"; + reg = <0x9b6000 0x1000>; + status = "disabled"; + interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; + nordic,clockpin-enable = ; + }; + + dppic135: dppic@9c1000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x9c1000 0x1000>; + status = "disabled"; + }; + + timer134: timer@9c2000 { + compatible = "nordic,nrf-timer"; + reg = <0x9c2000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <450 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + timer135: timer@9c3000 { + compatible = "nordic,nrf-timer"; + reg = <0x9c3000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <451 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + pwm132: pwm@9c4000 { + compatible = "nordic,nrf-pwm"; + reg = <0x9c4000 0x1000>; + status = "disabled"; + interrupts = <452 NRF_DEFAULT_IRQ_PRIORITY>; + #pwm-cells = <3>; + }; + + i2c134: i2c@9c5000 { + compatible = "nordic,nrf-twim"; + reg = <0x9c5000 0x1000>; + status = "disabled"; + interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; + easydma-maxcnt-bits = <15>; + #address-cells = <1>; + #size-cells = <0>; + nordic,clockpin-enable = , + ; + }; + + spi134: spi@9c5000 { + compatible = "nordic,nrf-spim"; + reg = <0x9c5000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + rx-delay-supported; + rx-delay = <1>; + nordic,clockpin-enable = , + , + , + ; + }; + + uart134: uart@9c5000 { + compatible = "nordic,nrf-uarte"; + reg = <0x9c5000 0x1000>; + status = "disabled"; + interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; + nordic,clockpin-enable = ; + }; + + i2c135: i2c@9c6000 { + compatible = "nordic,nrf-twim"; + reg = <0x9c6000 0x1000>; + status = "disabled"; + interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; + easydma-maxcnt-bits = <15>; + #address-cells = <1>; + #size-cells = <0>; + nordic,clockpin-enable = , + ; + }; + + spi135: spi@9c6000 { + compatible = "nordic,nrf-spim"; + reg = <0x9c6000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + rx-delay-supported; + rx-delay = <1>; + nordic,clockpin-enable = , + , + , + ; + }; + + uart135: uart@9c6000 { + compatible = "nordic,nrf-uarte"; + reg = <0x9c6000 0x1000>; + status = "disabled"; + interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; + nordic,clockpin-enable = ; + }; + + dppic136: dppic@9d1000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x9d1000 0x1000>; + status = "disabled"; + }; + + timer136: timer@9d2000 { + compatible = "nordic,nrf-timer"; + reg = <0x9d2000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <466 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + timer137: timer@9d3000 { + compatible = "nordic,nrf-timer"; + reg = <0x9d3000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <467 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + pwm133: pwm@9d4000 { + compatible = "nordic,nrf-pwm"; + reg = <0x9d4000 0x1000>; + status = "disabled"; + interrupts = <468 NRF_DEFAULT_IRQ_PRIORITY>; + #pwm-cells = <3>; + }; + + i2c136: i2c@9d5000 { + compatible = "nordic,nrf-twim"; + reg = <0x9d5000 0x1000>; + status = "disabled"; + interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; + easydma-maxcnt-bits = <15>; + #address-cells = <1>; + #size-cells = <0>; + nordic,clockpin-enable = , + ; + }; + + spi136: spi@9d5000 { + compatible = "nordic,nrf-spim"; + reg = <0x9d5000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + rx-delay-supported; + rx-delay = <1>; + nordic,clockpin-enable = , + , + , + ; + }; + + uart136: uart@9d5000 { + compatible = "nordic,nrf-uarte"; + reg = <0x9d5000 0x1000>; + status = "disabled"; + interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; + nordic,clockpin-enable = ; + }; + + i2c137: i2c@9d6000 { + compatible = "nordic,nrf-twim"; + reg = <0x9d6000 0x1000>; + status = "disabled"; + interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; + easydma-maxcnt-bits = <15>; + #address-cells = <1>; + #size-cells = <0>; + nordic,clockpin-enable = , + ; + }; + + spi137: spi@9d6000 { + compatible = "nordic,nrf-spim"; + reg = <0x9d6000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + rx-delay-supported; + rx-delay = <1>; + nordic,clockpin-enable = , + , + , + ; + }; + + uart137: uart@9d6000 { + compatible = "nordic,nrf-uarte"; + reg = <0x9d6000 0x1000>; + status = "disabled"; + interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; + nordic,clockpin-enable = ; + }; + }; + }; + + cpuapp_ppb: cpuapp-ppb-bus { + #address-cells = <1>; + #size-cells = <1>; + + cpuapp_systick: timer@e000e010 { + compatible = "arm,armv8m-systick"; + reg = <0xe000e010 0x10>; + status = "disabled"; + }; + + cpuapp_nvic: interrupt-controller@e000e100 { + compatible = "arm,v8m-nvic"; + reg = <0xe000e100 0xc00>; + arm,num-irq-priority-bits = <3>; + #interrupt-cells = <2>; + interrupt-controller; + #address-cells = <1>; + }; + }; + + cpurad_ppb: cpurad-ppb-bus { + #address-cells = <1>; + #size-cells = <1>; + + cpurad_systick: timer@e000e010 { + compatible = "arm,armv8m-systick"; + reg = <0xe000e010 0x10>; + status = "disabled"; + }; + + cpurad_nvic: interrupt-controller@e000e100 { + compatible = "arm,v8m-nvic"; + reg = <0xe000e100 0xc00>; + arm,num-irq-priority-bits = <3>; + #interrupt-cells = <2>; + interrupt-controller; + #address-cells = <1>; + }; + }; + + cpuppr_private: cpuppr-private-bus { + #address-cells = <1>; + #size-cells = <1>; + + cpuppr_clic: interrupt-controller@5f909000 { + compatible = "nordic,nrf-clic"; + reg = <0x5f909000 0x3000>; + status = "disabled"; + #interrupt-cells = <2>; + interrupt-controller; + #address-cells = <1>; + }; + }; + + temp_nrfs: temp { + compatible = "nordic,nrf-temp-nrfs"; + status = "disabled"; + }; +}; diff --git a/dts/riscv/nordic/nrf9280_cpuppr.dtsi b/dts/riscv/nordic/nrf9280_cpuppr.dtsi new file mode 100644 index 00000000000..ad5fb3014e7 --- /dev/null +++ b/dts/riscv/nordic/nrf9280_cpuppr.dtsi @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +cpu: &cpuppr {}; +clic: &cpuppr_clic {}; +cpuppr_vevif: &cpuppr_vevif_rx {}; +cpusys_vevif: &cpusys_vevif_tx {}; + +/delete-node/ &cpuapp; +/delete-node/ &cpuapp_peripherals; +/delete-node/ &cpuapp_ppb; +/delete-node/ &cpuapp_ram0; +/delete-node/ &cpurad; +/delete-node/ &cpurad_peripherals; +/delete-node/ &cpurad_ppb; +/delete-node/ &cpurad_ram0; + +/ { + soc { + compatible = "simple-bus"; + interrupt-parent = <&cpuppr_clic>; + ranges; + }; +}; + +&cpuppr_private { + compatible = "simple-bus"; + ranges; +}; + +&cpuppr_clic { + status = "okay"; +}; + +&cpusec_bellboard { + compatible = "nordic,nrf-bellboard-tx"; +}; + +&cpuapp_bellboard { + compatible = "nordic,nrf-bellboard-tx"; +}; + +&cpurad_bellboard { + compatible = "nordic,nrf-bellboard-tx"; +}; + +&gpiote130 { + interrupts = <104 NRF_DEFAULT_IRQ_PRIORITY>; +}; + +&grtc { + interrupts = <108 NRF_DEFAULT_IRQ_PRIORITY>; +}; diff --git a/include/zephyr/dt-bindings/misc/nordic-domain-id-nrf9230.h b/include/zephyr/dt-bindings/misc/nordic-domain-id-nrf9230.h new file mode 100644 index 00000000000..8e4e1759486 --- /dev/null +++ b/include/zephyr/dt-bindings/misc/nordic-domain-id-nrf9230.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_DOMAIN_ID_NRF9280_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_DOMAIN_ID_NRF9280_H_ + +#define NRF_DOMAIN_ID_APPLICATION 2 +#define NRF_DOMAIN_ID_RADIOCORE 3 +#define NRF_DOMAIN_ID_CELLCORE 4 +#define NRF_DOMAIN_ID_GLOBALFAST 12 +#define NRF_DOMAIN_ID_GLOBALSLOW 13 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_DOMAIN_ID_NRF9280_H_ */ diff --git a/include/zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf9230-engb.h b/include/zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf9230-engb.h new file mode 100644 index 00000000000..aec1950025b --- /dev/null +++ b/include/zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf9230-engb.h @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +/* autogenerated using Nordic HAL utils/gen_offsets.py script */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_NRF_FICR_NRF9230_ENGB_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_NRF_FICR_NRF9230_ENGB_H_ + +#define NRF_FICR_BLE_ADDRTYPE 0x00CU +#define NRF_FICR_BLE_ADDR_0 0x010U +#define NRF_FICR_BLE_ADDR_1 0x014U +#define NRF_FICR_BLE_ER_0 0x018U +#define NRF_FICR_BLE_ER_1 0x01CU +#define NRF_FICR_BLE_ER_2 0x020U +#define NRF_FICR_BLE_ER_3 0x024U +#define NRF_FICR_BLE_IR_0 0x028U +#define NRF_FICR_BLE_IR_1 0x02CU +#define NRF_FICR_BLE_IR_2 0x030U +#define NRF_FICR_BLE_IR_3 0x034U +#define NRF_FICR_INFO_CONFIGID 0x050U +#define NRF_FICR_INFO_PART 0x054U +#define NRF_FICR_INFO_VARIANT 0x058U +#define NRF_FICR_INFO_PACKAGE 0x05CU +#define NRF_FICR_INFO_RAM 0x060U +#define NRF_FICR_INFO_MRAM 0x064U +#define NRF_FICR_INFO_CODEPAGESIZE 0x068U +#define NRF_FICR_INFO_CODESIZE 0x06CU +#define NRF_FICR_INFO_DEVICETYPE 0x070U +#define NRF_FICR_SIPINFO_OVERRIDE_LFOSC_CONFIG 0x0A4U +#define NRF_FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG 0x0A8U +#define NRF_FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCAL 0x0ACU +#define NRF_FICR_SIPINFO_OVERRIDE_LFOSC_LFRCAUTOCALCONFIG 0x0B0U +#define NRF_FICR_SIPINFO_OVERRIDE_HFXO64M_CONFIG 0x0B4U +#define NRF_FICR_SIPINFO_PARTNO 0x080U +#define NRF_FICR_SIPINFO_HWREVISION_0 0x084U +#define NRF_FICR_SIPINFO_HWREVISION_1 0x085U +#define NRF_FICR_SIPINFO_HWREVISION_2 0x086U +#define NRF_FICR_SIPINFO_HWREVISION_3 0x087U +#define NRF_FICR_SIPINFO_VARIANT_0 0x088U +#define NRF_FICR_SIPINFO_VARIANT_1 0x089U +#define NRF_FICR_SIPINFO_VARIANT_2 0x08AU +#define NRF_FICR_SIPINFO_VARIANT_3 0x08BU +#define NRF_FICR_SIPINFO_PMICVERSION 0x08CU +#define NRF_FICR_SIPINFO_TESTSITE_0 0x090U +#define NRF_FICR_SIPINFO_TESTSITE_1 0x091U +#define NRF_FICR_SIPINFO_TESTSITE_2 0x092U +#define NRF_FICR_SIPINFO_TESTSITE_3 0x093U +#define NRF_FICR_SIPINFO_LOT 0x094U +#define NRF_FICR_SIPINFO_TESTPROGRAMID_0 0x098U +#define NRF_FICR_SIPINFO_TESTPROGRAMID_1 0x099U +#define NRF_FICR_SIPINFO_TESTPROGRAMID_2 0x09AU +#define NRF_FICR_SIPINFO_TESTPROGRAMID_3 0x09BU +#define NRF_FICR_SIPINFO_OSATPARTNO 0x09CU +#define NRF_FICR_SIPINFO_HWBUILDVERSION_0 0x0A0U +#define NRF_FICR_SIPINFO_HWBUILDVERSION_1 0x0A1U +#define NRF_FICR_SIPINFO_HWBUILDVERSION_2 0x0A2U +#define NRF_FICR_SIPINFO_HWBUILDVERSION_3 0x0A3U +#define NRF_FICR_TRIM_GLOBAL_SAADC_CALVREF 0x344U +#define NRF_FICR_TRIM_GLOBAL_SAADC_CALGAIN_0 0x348U +#define NRF_FICR_TRIM_GLOBAL_SAADC_CALGAIN_1 0x34CU +#define NRF_FICR_TRIM_GLOBAL_SAADC_CALGAIN_2 0x350U +#define NRF_FICR_TRIM_GLOBAL_SAADC_CALOFFSET 0x354U +#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_0 0x358U +#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_1 0x35CU +#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_2 0x360U +#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_3 0x364U +#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_4 0x368U +#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_5 0x36CU +#define NRF_FICR_TRIM_GLOBAL_SAADC_CALIREF 0x370U +#define NRF_FICR_TRIM_GLOBAL_SAADC_CALVREFTC 0x374U +#define NRF_FICR_TRIM_GLOBAL_CANPLL_TRIM_CTUNE 0x380U +#define NRF_FICR_TRIM_GLOBAL_COMP_REFTRIM 0x390U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP 0x398U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_0 0x39CU +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_1 0x3A0U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_2 0x3A4U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_3 0x3A8U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_4 0x3ACU +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_5 0x3B0U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_0 0x3B4U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_1 0x3B8U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_2 0x3BCU +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_3 0x3C0U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_4 0x3C4U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_5 0x3C8U +#define NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_0_TRIM 0x3CCU +#define NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_1_TRIM 0x3D0U +#define NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_2_TRIM 0x3D4U +#define NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_3_TRIM 0x3D8U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP 0x3DCU +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_0 0x3E0U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_1 0x3E4U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_2 0x3E8U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_3 0x3ECU +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_4 0x3F0U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_5 0x3F4U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_0 0x3F8U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_1 0x3FCU +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_2 0x400U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_3 0x404U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_4 0x408U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_5 0x40CU +#define NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_0_TRIM 0x410U +#define NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_1_TRIM 0x414U +#define NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_2_TRIM 0x418U +#define NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_3_TRIM 0x41CU + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_NRF_FICR_NRF9230_ENGB_H_ */ diff --git a/include/zephyr/dt-bindings/misc/nordic-owner-id-nrf9230.h b/include/zephyr/dt-bindings/misc/nordic-owner-id-nrf9230.h new file mode 100644 index 00000000000..6d9a8f28bf2 --- /dev/null +++ b/include/zephyr/dt-bindings/misc/nordic-owner-id-nrf9230.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_OWNER_ID_NRF9280_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_OWNER_ID_NRF9280_H_ + +#define NRF_OWNER_ID_NONE 0 +#define NRF_OWNER_ID_APPLICATION 2 +#define NRF_OWNER_ID_RADIOCORE 3 +#define NRF_OWNER_ID_CELL 4 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_OWNER_ID_NRF9280_H_ */ diff --git a/modules/hal_nordic/Kconfig.nrf_regtool b/modules/hal_nordic/Kconfig.nrf_regtool index 703d02f5605..77944c5bb05 100644 --- a/modules/hal_nordic/Kconfig.nrf_regtool +++ b/modules/hal_nordic/Kconfig.nrf_regtool @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 menu "nrf-regtool options" - depends on SOC_SERIES_NRF54HX + depends on SOC_SERIES_NRF54HX || SOC_SERIES_NRF92X config NRF_REGTOOL_GENERATE_UICR bool "Generate UICR" diff --git a/modules/hal_nordic/nrfs/Kconfig b/modules/hal_nordic/nrfs/Kconfig index d9031f85b68..49ffc2595e1 100644 --- a/modules/hal_nordic/nrfs/Kconfig +++ b/modules/hal_nordic/nrfs/Kconfig @@ -36,7 +36,7 @@ config NRFS_HAS_VBUS_DETECTOR_SERVICE config NRFS bool "nRF Services Support" - select NRFS_LOCAL_DOMAIN if (SOC_NRF54H20_CPUAPP || SOC_NRF54H20_CPURAD) + select NRFS_LOCAL_DOMAIN if (SOC_NRF54H20_CPUAPP || SOC_NRF54H20_CPURAD || SOC_NRF9280_CPUAPP || SOC_NRF9280_CPURAD) depends on HAS_NRFS depends on !MISRA_SANE default y if !ZTEST @@ -98,7 +98,7 @@ config NRFS_PMIC_SERVICE_ENABLED config NRFS_DVFS_SERVICE_ENABLED bool "DVFS service" depends on NRFS_HAS_DVFS_SERVICE - default y if SOC_NRF54H20_CPUAPP + default y if SOC_NRF54H20_CPUAPP || SOC_NRF9280_CPUAPP config NRFS_DIAG_SERVICE_ENABLED bool "System Diagnostics service (only for development purposes)" diff --git a/modules/hal_nordic/nrfs/dvfs/ld_dvfs.c b/modules/hal_nordic/nrfs/dvfs/ld_dvfs.c index 047d961a59c..78c67ffa6a4 100644 --- a/modules/hal_nordic/nrfs/dvfs/ld_dvfs.c +++ b/modules/hal_nordic/nrfs/dvfs/ld_dvfs.c @@ -264,7 +264,7 @@ int32_t ld_dvfs_configure_hsfll(enum dvfs_frequency_setting oppoint) uint8_t freq_trim = get_dvfs_oppoint_data(oppoint)->new_f_trim_entry; -#ifdef CONFIG_SOC_NRF54H20_CPUAPP +#if defined(CONFIG_SOC_NRF54H20_CPUAPP) || defined(CONFIG_SOC_NRF9280_CPUAPP) hsfll_trim.vsup = NRF_FICR->TRIM.APPLICATION.HSFLL.TRIM.VSUP; hsfll_trim.coarse = NRF_FICR->TRIM.APPLICATION.HSFLL.TRIM.COARSE[freq_trim]; hsfll_trim.fine = NRF_FICR->TRIM.APPLICATION.HSFLL.TRIM.FINE[freq_trim]; diff --git a/modules/hal_nordic/nrfx/CMakeLists.txt b/modules/hal_nordic/nrfx/CMakeLists.txt index caa3e85d142..2714d33f86a 100644 --- a/modules/hal_nordic/nrfx/CMakeLists.txt +++ b/modules/hal_nordic/nrfx/CMakeLists.txt @@ -53,6 +53,13 @@ zephyr_compile_definitions_ifdef(CONFIG_SOC_COMPATIBLE_NRF54L15_CPUAPP NRF_APPLI zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9120 NRF9120_XXAA) zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9160 NRF9160_XXAA) +zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9230_ENGB_CPUAPP NRF9230_ENGB_XXAA + NRF_APPLICATION) +zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9230_ENGB_CPURAD NRF9230_ENGB_XXAA + NRF_RADIOCORE) +zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9230_ENGB_CPUPPR NRF9230_ENGB_XXAA + NRF_PPR) + zephyr_compile_definitions_ifdef(CONFIG_NRF_APPROTECT_LOCK ENABLE_APPROTECT) zephyr_compile_definitions_ifdef(CONFIG_NRF_APPROTECT_USER_HANDLING @@ -86,6 +93,7 @@ zephyr_library_sources_ifdef(CONFIG_SOC_NRF5340_CPUNET ${MDK_DIR}/system_nrf5340 zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_NRF54HX ${MDK_DIR}/system_nrf54h.c) zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_NRF54LX ${MDK_DIR}/system_nrf54l.c) zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_NRF91X ${MDK_DIR}/system_nrf91.c) +zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_NRF92X ${MDK_DIR}/system_nrf92.c) zephyr_library_sources(nrfx_glue.c) zephyr_library_sources(${HELPERS_DIR}/nrfx_flag32_allocator.c) @@ -217,3 +225,6 @@ mdk_svd_ifdef(CONFIG_SOC_NRF54L15_CPUAPP nrf54l15_application.svd) mdk_svd_ifdef(CONFIG_SOC_NRF54L15_CPUFLPR nrf54l15_flpr.svd) mdk_svd_ifdef(CONFIG_SOC_NRF9120 nrf9120.svd) mdk_svd_ifdef(CONFIG_SOC_NRF9160 nrf9160.svd) +mdk_svd_ifdef(CONFIG_SOC_NRF9230_ENGB_CPUAPP nrf9230_engb_application.svd) +mdk_svd_ifdef(CONFIG_SOC_NRF9230_ENGB_CPUPPR nrf9230_engb_ppr.svd) +mdk_svd_ifdef(CONFIG_SOC_NRF9230_ENGB_CPURAD nrf9230_engb_radiocore.svd) diff --git a/modules/hal_nordic/nrfx/nrfx_config.h b/modules/hal_nordic/nrfx/nrfx_config.h index c2e558ded24..1e269c1aba8 100644 --- a/modules/hal_nordic/nrfx/nrfx_config.h +++ b/modules/hal_nordic/nrfx/nrfx_config.h @@ -1041,6 +1041,12 @@ #include #elif defined(NRF9120_XXAA) || defined(NRF9160_XXAA) #include +#elif defined(NRF9230_ENGB_XXAA) && defined(NRF_APPLICATION) + #include +#elif defined(NRF9230_ENGB_XXAA) && defined(NRF_RADIOCORE) + #include +#elif defined(NRF9230_ENGB_XXAA) && defined(NRF_PPR) + #include #else #include #endif diff --git a/modules/hal_nordic/nrfx/nrfx_config_nrf9230_engb_application.h b/modules/hal_nordic/nrfx/nrfx_config_nrf9230_engb_application.h new file mode 100644 index 00000000000..a7905c199d2 --- /dev/null +++ b/modules/hal_nordic/nrfx/nrfx_config_nrf9230_engb_application.h @@ -0,0 +1,1973 @@ +/* + * Copyright (c) 2024, Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef NRFX_CONFIG_NRF9230_ENGB_APPLICATION_H__ +#define NRFX_CONFIG_NRF9230_ENGB_APPLICATION_H__ + +#ifndef NRFX_CONFIG_H__ +#error "This file should not be included directly. Include nrfx_config.h instead." +#endif + + +/** + * @brief NRFX_DEFAULT_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_DEFAULT_IRQ_PRIORITY +#define NRFX_DEFAULT_IRQ_PRIORITY 7 +#endif + +/** + * @brief NRFX_BELLBOARD_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD_ENABLED +#define NRFX_BELLBOARD_ENABLED 0 +#endif + +/** + * @brief NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_BELLBOARD0_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD0_ENABLED +#define NRFX_BELLBOARD0_ENABLED 0 +#endif + +/** + * @brief NRFX_BELLBOARD1_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD1_ENABLED +#define NRFX_BELLBOARD1_ENABLED 0 +#endif + +/** + * @brief NRFX_BELLBOARD2_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD2_ENABLED +#define NRFX_BELLBOARD2_ENABLED 0 +#endif + +/** + * @brief NRFX_BELLBOARD3_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD3_ENABLED +#define NRFX_BELLBOARD3_ENABLED 0 +#endif + +/** + * @brief NRFX_COMP_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_COMP_ENABLED +#define NRFX_COMP_ENABLED 0 +#endif + +/** + * @brief NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_COMP_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_COMP_CONFIG_LOG_ENABLED +#define NRFX_COMP_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_COMP_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_COMP_CONFIG_LOG_LEVEL +#define NRFX_COMP_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_DPPI_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI_ENABLED +#define NRFX_DPPI_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI_CONFIG_LOG_ENABLED +#define NRFX_DPPI_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_DPPI_CONFIG_LOG_LEVEL +#define NRFX_DPPI_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000f0 +#endif + +/** + * @brief NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff +#endif + +/** + * @brief NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000001e +#endif + +/** + * @brief NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000020 +#endif + +/** + * @brief NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000040 +#endif + +/** + * @brief NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000081 +#endif + +/** + * @brief NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000f +#endif + +/** + * @brief NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff +#endif + +/** + * @brief NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff +#endif + +/** + * @brief NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000e1 +#endif + +/** + * @brief NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000df +#endif + +/** + * @brief NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000bf +#endif + +/** + * @brief NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e +#endif + +/** + * @brief NRFX_EGU_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_EGU_ENABLED +#define NRFX_EGU_ENABLED 0 +#endif + +/** + * @brief NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_EGU130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_EGU130_ENABLED +#define NRFX_EGU130_ENABLED 0 +#endif + +/** + * @brief NRFX_GPIOTE_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE_ENABLED +#define NRFX_GPIOTE_ENABLED 0 +#endif + +/** + * @brief NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS + * + * Integer value. Minimum: 0. Maximum: 15. + */ +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS +#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 2 +#endif + +/** + * @brief NRFX_GPIOTE_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED +#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_GPIOTE_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL +#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_GPIOTE130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE130_ENABLED +#define NRFX_GPIOTE130_ENABLED 0 +#endif + +/** + * @brief NRFX_GPIOTE131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE131_ENABLED +#define NRFX_GPIOTE131_ENABLED 0 +#endif + +/** + * @brief NRFX_GRTC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_ENABLED +#define NRFX_GRTC_ENABLED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_SLEEP_ALLOWED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_SLEEP_ALLOWED +#define NRFX_GRTC_CONFIG_SLEEP_ALLOWED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_AUTOEN + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_AUTOEN +#define NRFX_GRTC_CONFIG_AUTOEN 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_AUTOSTART + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_AUTOSTART +#define NRFX_GRTC_CONFIG_AUTOSTART 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS + * + * Integer value. + */ +#ifndef NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS +#define NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS 4 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK + */ +#ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK +#define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x000000f0 +#endif + +/** + * @brief NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_GRTC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_LOG_ENABLED +#define NRFX_GRTC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_GRTC_CONFIG_LOG_LEVEL +#define NRFX_GRTC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_I2S_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_I2S_ENABLED +#define NRFX_I2S_ENABLED 0 +#endif + +/** + * @brief NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_I2S_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_I2S_CONFIG_LOG_ENABLED +#define NRFX_I2S_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_I2S_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_I2S_CONFIG_LOG_LEVEL +#define NRFX_I2S_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_I2S130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_I2S130_ENABLED +#define NRFX_I2S130_ENABLED 0 +#endif + +/** + * @brief NRFX_I2S131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_I2S131_ENABLED +#define NRFX_I2S131_ENABLED 0 +#endif + +/** + * @brief NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 +#endif + +/** + * @brief NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c +#endif + +/** + * @brief NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c +#endif + +/** + * @brief NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 +#endif + +/** + * @brief NRFX_LPCOMP_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_LPCOMP_ENABLED +#define NRFX_LPCOMP_ENABLED 0 +#endif + +/** + * @brief NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_LPCOMP_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED +#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_LPCOMP_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL +#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_MVDMA_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_MVDMA_ENABLED +#define NRFX_MVDMA_ENABLED 0 +#endif + +/** + * @brief NRFX_MVDMA120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_MVDMA120_ENABLED +#define NRFX_MVDMA120_ENABLED 0 +#endif + +/** + * @brief NRFX_MVDMA121_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_MVDMA121_ENABLED +#define NRFX_MVDMA121_ENABLED 0 +#endif + +/** + * @brief NRFX_PDM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PDM_ENABLED +#define NRFX_PDM_ENABLED 0 +#endif + +/** + * @brief NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_PDM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PDM_CONFIG_LOG_ENABLED +#define NRFX_PDM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PDM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PDM_CONFIG_LOG_LEVEL +#define NRFX_PDM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PRS_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_ENABLED +#define NRFX_PRS_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_CONFIG_LOG_ENABLED +#define NRFX_PRS_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PRS_CONFIG_LOG_LEVEL +#define NRFX_PRS_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PRS_BOX_0_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_0_ENABLED +#define NRFX_PRS_BOX_0_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_1_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_1_ENABLED +#define NRFX_PRS_BOX_1_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_2_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_2_ENABLED +#define NRFX_PRS_BOX_2_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_3_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_3_ENABLED +#define NRFX_PRS_BOX_3_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_4_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_4_ENABLED +#define NRFX_PRS_BOX_4_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_5_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_5_ENABLED +#define NRFX_PRS_BOX_5_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_6_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_6_ENABLED +#define NRFX_PRS_BOX_6_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_7_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_7_ENABLED +#define NRFX_PRS_BOX_7_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_8_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_8_ENABLED +#define NRFX_PRS_BOX_8_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_9_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_9_ENABLED +#define NRFX_PRS_BOX_9_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM_ENABLED +#define NRFX_PWM_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_PWM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM_CONFIG_LOG_ENABLED +#define NRFX_PWM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PWM_CONFIG_LOG_LEVEL +#define NRFX_PWM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PWM120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM120_ENABLED +#define NRFX_PWM120_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM130_ENABLED +#define NRFX_PWM130_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM131_ENABLED +#define NRFX_PWM131_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM132_ENABLED +#define NRFX_PWM132_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM133_ENABLED +#define NRFX_PWM133_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC_ENABLED +#define NRFX_QDEC_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_QDEC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED +#define NRFX_QDEC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL +#define NRFX_QDEC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_QDEC130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC130_ENABLED +#define NRFX_QDEC130_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC131_ENABLED +#define NRFX_QDEC131_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC_ENABLED +#define NRFX_RTC_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_RTC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC_CONFIG_LOG_ENABLED +#define NRFX_RTC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_RTC_CONFIG_LOG_LEVEL +#define NRFX_RTC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_RTC130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC130_ENABLED +#define NRFX_RTC130_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC131_ENABLED +#define NRFX_RTC131_ENABLED 0 +#endif + +/** + * @brief NRFX_SAADC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SAADC_ENABLED +#define NRFX_SAADC_ENABLED 0 +#endif + +/** + * @brief NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_SAADC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED +#define NRFX_SAADC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_SAADC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL +#define NRFX_SAADC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_SPIM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM_ENABLED +#define NRFX_SPIM_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_SPIM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED +#define NRFX_SPIM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL +#define NRFX_SPIM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_SPIM120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM120_ENABLED +#define NRFX_SPIM120_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM121_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM121_ENABLED +#define NRFX_SPIM121_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM130_ENABLED +#define NRFX_SPIM130_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM131_ENABLED +#define NRFX_SPIM131_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM132_ENABLED +#define NRFX_SPIM132_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM133_ENABLED +#define NRFX_SPIM133_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM134_ENABLED +#define NRFX_SPIM134_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM135_ENABLED +#define NRFX_SPIM135_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM136_ENABLED +#define NRFX_SPIM136_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM137_ENABLED +#define NRFX_SPIM137_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS_ENABLED +#define NRFX_SPIS_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_SPIS_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED +#define NRFX_SPIS_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL +#define NRFX_SPIS_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_SPIS120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS120_ENABLED +#define NRFX_SPIS120_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS130_ENABLED +#define NRFX_SPIS130_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS131_ENABLED +#define NRFX_SPIS131_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS132_ENABLED +#define NRFX_SPIS132_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS133_ENABLED +#define NRFX_SPIS133_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS134_ENABLED +#define NRFX_SPIS134_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS135_ENABLED +#define NRFX_SPIS135_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS136_ENABLED +#define NRFX_SPIS136_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS137_ENABLED +#define NRFX_SPIS137_ENABLED 0 +#endif + +/** + * @brief NRFX_SYSTICK_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SYSTICK_ENABLED +#define NRFX_SYSTICK_ENABLED 0 +#endif + +/** + * @brief NRFX_TEMP_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TEMP_ENABLED +#define NRFX_TEMP_ENABLED 0 +#endif + +/** + * @brief NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TEMP_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TEMP_CONFIG_LOG_ENABLED +#define NRFX_TEMP_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TEMP_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TEMP_CONFIG_LOG_LEVEL +#define NRFX_TEMP_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TIMER_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER_ENABLED +#define NRFX_TIMER_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TIMER_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED +#define NRFX_TIMER_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL +#define NRFX_TIMER_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TIMER120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER120_ENABLED +#define NRFX_TIMER120_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER121_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER121_ENABLED +#define NRFX_TIMER121_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER130_ENABLED +#define NRFX_TIMER130_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER131_ENABLED +#define NRFX_TIMER131_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER132_ENABLED +#define NRFX_TIMER132_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER133_ENABLED +#define NRFX_TIMER133_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER134_ENABLED +#define NRFX_TIMER134_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER135_ENABLED +#define NRFX_TIMER135_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER136_ENABLED +#define NRFX_TIMER136_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER137_ENABLED +#define NRFX_TIMER137_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM_ENABLED +#define NRFX_TWIM_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TWIM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED +#define NRFX_TWIM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL +#define NRFX_TWIM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TWIM130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM130_ENABLED +#define NRFX_TWIM130_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM131_ENABLED +#define NRFX_TWIM131_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM132_ENABLED +#define NRFX_TWIM132_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM133_ENABLED +#define NRFX_TWIM133_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM134_ENABLED +#define NRFX_TWIM134_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM135_ENABLED +#define NRFX_TWIM135_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM136_ENABLED +#define NRFX_TWIM136_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM137_ENABLED +#define NRFX_TWIM137_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_ENABLED +#define NRFX_TWIS_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TWIS_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED +#define NRFX_TWIS_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY + * + * Assume that any instance would be initialized only once. + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY +#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 +#endif + +/** + * @brief NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode. + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_NO_SYNC_MODE +#define NRFX_TWIS_NO_SYNC_MODE 0 +#endif + +/** + * @brief NRFX_TWIS_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL +#define NRFX_TWIS_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TWIS130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS130_ENABLED +#define NRFX_TWIS130_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS131_ENABLED +#define NRFX_TWIS131_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS132_ENABLED +#define NRFX_TWIS132_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS133_ENABLED +#define NRFX_TWIS133_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS134_ENABLED +#define NRFX_TWIS134_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS135_ENABLED +#define NRFX_TWIS135_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS136_ENABLED +#define NRFX_TWIS136_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS137_ENABLED +#define NRFX_TWIS137_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_ENABLED +#define NRFX_UARTE_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG + * + * If enabled, support for configuring GPIO pins is removed from the driver. + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG +#define NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG + * + * If enabled, support for configuring PSEL registers is removed from the driver. + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG +#define NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_TX_LINK - If enabled, driver supports linking of TX transfers. + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_TX_LINK +#define NRFX_UARTE_CONFIG_TX_LINK 1 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_RX_CACHE_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_RX_CACHE_ENABLED +#define NRFX_UARTE_CONFIG_RX_CACHE_ENABLED 1 +#endif + +/** + * @brief NRFX_UARTE_RX_FIFO_FLUSH_WORKAROUND_MAGIC_BYTE + * + * Integer value. Minimum: 0. Maximum: 255. + */ +#ifndef NRFX_UARTE_RX_FIFO_FLUSH_WORKAROUND_MAGIC_BYTE +#define NRFX_UARTE_RX_FIFO_FLUSH_WORKAROUND_MAGIC_BYTE 171 +#endif + +/** + * @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_UARTE_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED +#define NRFX_UARTE_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL +#define NRFX_UARTE_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_UARTE120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE120_ENABLED +#define NRFX_UARTE120_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE130_ENABLED +#define NRFX_UARTE130_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE131_ENABLED +#define NRFX_UARTE131_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE132_ENABLED +#define NRFX_UARTE132_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE133_ENABLED +#define NRFX_UARTE133_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE134_ENABLED +#define NRFX_UARTE134_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE135_ENABLED +#define NRFX_UARTE135_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE136_ENABLED +#define NRFX_UARTE136_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE137_ENABLED +#define NRFX_UARTE137_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT_ENABLED +#define NRFX_WDT_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT_CONFIG_NO_IRQ +#define NRFX_WDT_CONFIG_NO_IRQ 0 +#endif + +/** + * @brief NRFX_WDT_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT_CONFIG_LOG_ENABLED +#define NRFX_WDT_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_WDT_CONFIG_LOG_LEVEL +#define NRFX_WDT_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_WDT010_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT010_ENABLED +#define NRFX_WDT010_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT011_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT011_ENABLED +#define NRFX_WDT011_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT131_ENABLED +#define NRFX_WDT131_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT132_ENABLED +#define NRFX_WDT132_ENABLED 0 +#endif + +#endif /* NRFX_CONFIG_NRF9230_ENGB_APPLICATION_H__ */ diff --git a/modules/hal_nordic/nrfx/nrfx_config_nrf9230_engb_ppr.h b/modules/hal_nordic/nrfx/nrfx_config_nrf9230_engb_ppr.h new file mode 100644 index 00000000000..ae1f931e3da --- /dev/null +++ b/modules/hal_nordic/nrfx/nrfx_config_nrf9230_engb_ppr.h @@ -0,0 +1,1910 @@ +/* + * Copyright (c) 2024, Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef NRFX_CONFIG_NRF9230_ENGB_PPR_H__ +#define NRFX_CONFIG_NRF9230_ENGB_PPR_H__ + +#ifndef NRFX_CONFIG_H__ +#error "This file should not be included directly. Include nrfx_config.h instead." +#endif + + +/** + * @brief NRFX_DEFAULT_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_DEFAULT_IRQ_PRIORITY +#define NRFX_DEFAULT_IRQ_PRIORITY 0 +#endif + +/** + * @brief NRFX_COMP_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_COMP_ENABLED +#define NRFX_COMP_ENABLED 0 +#endif + +/** + * @brief NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_COMP_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_COMP_CONFIG_LOG_ENABLED +#define NRFX_COMP_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_COMP_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_COMP_CONFIG_LOG_LEVEL +#define NRFX_COMP_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_COREDEP_VPR_LEGACY + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_COREDEP_VPR_LEGACY +#define NRFX_COREDEP_VPR_LEGACY 0 +#endif + +/** + * @brief NRFX_DPPI_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI_ENABLED +#define NRFX_DPPI_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI_CONFIG_LOG_ENABLED +#define NRFX_DPPI_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_DPPI_CONFIG_LOG_LEVEL +#define NRFX_DPPI_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000030 +#endif + +/** + * @brief NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff +#endif + +/** + * @brief NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000001e +#endif + +/** + * @brief NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000020 +#endif + +/** + * @brief NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000040 +#endif + +/** + * @brief NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000081 +#endif + +/** + * @brief NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c +#endif + +/** + * @brief NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff +#endif + +/** + * @brief NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff +#endif + +/** + * @brief NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000e1 +#endif + +/** + * @brief NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000df +#endif + +/** + * @brief NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000bf +#endif + +/** + * @brief NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e +#endif + +/** + * @brief NRFX_EGU_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_EGU_ENABLED +#define NRFX_EGU_ENABLED 0 +#endif + +/** + * @brief NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_EGU130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_EGU130_ENABLED +#define NRFX_EGU130_ENABLED 0 +#endif + +/** + * @brief NRFX_GPIOTE_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE_ENABLED +#define NRFX_GPIOTE_ENABLED 0 +#endif + +/** + * @brief NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS + * + * Integer value. Minimum: 0. Maximum: 15. + */ +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS +#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 2 +#endif + +/** + * @brief NRFX_GPIOTE_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED +#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_GPIOTE_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL +#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_GPIOTE130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE130_ENABLED +#define NRFX_GPIOTE130_ENABLED 0 +#endif + +/** + * @brief NRFX_GPIOTE131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE131_ENABLED +#define NRFX_GPIOTE131_ENABLED 0 +#endif + +/** + * @brief NRFX_GRTC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_ENABLED +#define NRFX_GRTC_ENABLED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_SLEEP_ALLOWED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_SLEEP_ALLOWED +#define NRFX_GRTC_CONFIG_SLEEP_ALLOWED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_AUTOEN + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_AUTOEN +#define NRFX_GRTC_CONFIG_AUTOEN 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_AUTOSTART + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_AUTOSTART +#define NRFX_GRTC_CONFIG_AUTOSTART 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS + * + * Integer value. + */ +#ifndef NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS +#define NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS 2 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK + */ +#ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK +#define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x000000c0 +#endif + +/** + * @brief NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_GRTC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_LOG_ENABLED +#define NRFX_GRTC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_GRTC_CONFIG_LOG_LEVEL +#define NRFX_GRTC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_I2S_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_I2S_ENABLED +#define NRFX_I2S_ENABLED 0 +#endif + +/** + * @brief NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_I2S_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_I2S_CONFIG_LOG_ENABLED +#define NRFX_I2S_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_I2S_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_I2S_CONFIG_LOG_LEVEL +#define NRFX_I2S_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_I2S130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_I2S130_ENABLED +#define NRFX_I2S130_ENABLED 0 +#endif + +/** + * @brief NRFX_I2S131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_I2S131_ENABLED +#define NRFX_I2S131_ENABLED 0 +#endif + +/** + * @brief NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c +#endif + +/** + * @brief NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 +#endif + +/** + * @brief NRFX_LPCOMP_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_LPCOMP_ENABLED +#define NRFX_LPCOMP_ENABLED 0 +#endif + +/** + * @brief NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_LPCOMP_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED +#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_LPCOMP_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL +#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_MVDMA_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_MVDMA_ENABLED +#define NRFX_MVDMA_ENABLED 0 +#endif + +/** + * @brief NRFX_MVDMA120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_MVDMA120_ENABLED +#define NRFX_MVDMA120_ENABLED 0 +#endif + +/** + * @brief NRFX_MVDMA121_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_MVDMA121_ENABLED +#define NRFX_MVDMA121_ENABLED 0 +#endif + +/** + * @brief NRFX_PDM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PDM_ENABLED +#define NRFX_PDM_ENABLED 0 +#endif + +/** + * @brief NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_PDM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PDM_CONFIG_LOG_ENABLED +#define NRFX_PDM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PDM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PDM_CONFIG_LOG_LEVEL +#define NRFX_PDM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PRS_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_ENABLED +#define NRFX_PRS_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_CONFIG_LOG_ENABLED +#define NRFX_PRS_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PRS_CONFIG_LOG_LEVEL +#define NRFX_PRS_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PRS_BOX_0_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_0_ENABLED +#define NRFX_PRS_BOX_0_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_1_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_1_ENABLED +#define NRFX_PRS_BOX_1_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_2_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_2_ENABLED +#define NRFX_PRS_BOX_2_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_3_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_3_ENABLED +#define NRFX_PRS_BOX_3_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_4_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_4_ENABLED +#define NRFX_PRS_BOX_4_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_5_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_5_ENABLED +#define NRFX_PRS_BOX_5_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_6_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_6_ENABLED +#define NRFX_PRS_BOX_6_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_7_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_7_ENABLED +#define NRFX_PRS_BOX_7_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_8_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_8_ENABLED +#define NRFX_PRS_BOX_8_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_9_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_9_ENABLED +#define NRFX_PRS_BOX_9_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM_ENABLED +#define NRFX_PWM_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_PWM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM_CONFIG_LOG_ENABLED +#define NRFX_PWM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PWM_CONFIG_LOG_LEVEL +#define NRFX_PWM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PWM120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM120_ENABLED +#define NRFX_PWM120_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM130_ENABLED +#define NRFX_PWM130_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM131_ENABLED +#define NRFX_PWM131_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM132_ENABLED +#define NRFX_PWM132_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM133_ENABLED +#define NRFX_PWM133_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC_ENABLED +#define NRFX_QDEC_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_QDEC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED +#define NRFX_QDEC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL +#define NRFX_QDEC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_QDEC130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC130_ENABLED +#define NRFX_QDEC130_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC131_ENABLED +#define NRFX_QDEC131_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC_ENABLED +#define NRFX_RTC_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_RTC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC_CONFIG_LOG_ENABLED +#define NRFX_RTC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_RTC_CONFIG_LOG_LEVEL +#define NRFX_RTC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_RTC130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC130_ENABLED +#define NRFX_RTC130_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC131_ENABLED +#define NRFX_RTC131_ENABLED 0 +#endif + +/** + * @brief NRFX_SAADC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SAADC_ENABLED +#define NRFX_SAADC_ENABLED 0 +#endif + +/** + * @brief NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_SAADC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED +#define NRFX_SAADC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_SAADC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL +#define NRFX_SAADC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_SPIM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM_ENABLED +#define NRFX_SPIM_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_SPIM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED +#define NRFX_SPIM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL +#define NRFX_SPIM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_SPIM120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM120_ENABLED +#define NRFX_SPIM120_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM121_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM121_ENABLED +#define NRFX_SPIM121_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM130_ENABLED +#define NRFX_SPIM130_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM131_ENABLED +#define NRFX_SPIM131_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM132_ENABLED +#define NRFX_SPIM132_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM133_ENABLED +#define NRFX_SPIM133_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM134_ENABLED +#define NRFX_SPIM134_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM135_ENABLED +#define NRFX_SPIM135_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM136_ENABLED +#define NRFX_SPIM136_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM137_ENABLED +#define NRFX_SPIM137_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS_ENABLED +#define NRFX_SPIS_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_SPIS_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED +#define NRFX_SPIS_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL +#define NRFX_SPIS_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_SPIS120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS120_ENABLED +#define NRFX_SPIS120_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS130_ENABLED +#define NRFX_SPIS130_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS131_ENABLED +#define NRFX_SPIS131_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS132_ENABLED +#define NRFX_SPIS132_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS133_ENABLED +#define NRFX_SPIS133_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS134_ENABLED +#define NRFX_SPIS134_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS135_ENABLED +#define NRFX_SPIS135_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS136_ENABLED +#define NRFX_SPIS136_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS137_ENABLED +#define NRFX_SPIS137_ENABLED 0 +#endif + +/** + * @brief NRFX_TEMP_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TEMP_ENABLED +#define NRFX_TEMP_ENABLED 0 +#endif + +/** + * @brief NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TEMP_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TEMP_CONFIG_LOG_ENABLED +#define NRFX_TEMP_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TEMP_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TEMP_CONFIG_LOG_LEVEL +#define NRFX_TEMP_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TIMER_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER_ENABLED +#define NRFX_TIMER_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TIMER_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED +#define NRFX_TIMER_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL +#define NRFX_TIMER_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TIMER120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER120_ENABLED +#define NRFX_TIMER120_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER121_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER121_ENABLED +#define NRFX_TIMER121_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER130_ENABLED +#define NRFX_TIMER130_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER131_ENABLED +#define NRFX_TIMER131_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER132_ENABLED +#define NRFX_TIMER132_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER133_ENABLED +#define NRFX_TIMER133_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER134_ENABLED +#define NRFX_TIMER134_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER135_ENABLED +#define NRFX_TIMER135_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER136_ENABLED +#define NRFX_TIMER136_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER137_ENABLED +#define NRFX_TIMER137_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM_ENABLED +#define NRFX_TWIM_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TWIM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED +#define NRFX_TWIM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL +#define NRFX_TWIM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TWIM130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM130_ENABLED +#define NRFX_TWIM130_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM131_ENABLED +#define NRFX_TWIM131_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM132_ENABLED +#define NRFX_TWIM132_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM133_ENABLED +#define NRFX_TWIM133_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM134_ENABLED +#define NRFX_TWIM134_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM135_ENABLED +#define NRFX_TWIM135_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM136_ENABLED +#define NRFX_TWIM136_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM137_ENABLED +#define NRFX_TWIM137_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_ENABLED +#define NRFX_TWIS_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TWIS_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED +#define NRFX_TWIS_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY + * + * Assume that any instance would be initialized only once. + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY +#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 +#endif + +/** + * @brief NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode. + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_NO_SYNC_MODE +#define NRFX_TWIS_NO_SYNC_MODE 0 +#endif + +/** + * @brief NRFX_TWIS_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL +#define NRFX_TWIS_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TWIS130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS130_ENABLED +#define NRFX_TWIS130_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS131_ENABLED +#define NRFX_TWIS131_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS132_ENABLED +#define NRFX_TWIS132_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS133_ENABLED +#define NRFX_TWIS133_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS134_ENABLED +#define NRFX_TWIS134_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS135_ENABLED +#define NRFX_TWIS135_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS136_ENABLED +#define NRFX_TWIS136_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS137_ENABLED +#define NRFX_TWIS137_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_ENABLED +#define NRFX_UARTE_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG + * + * If enabled, support for configuring GPIO pins is removed from the driver. + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG +#define NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG + * + * If enabled, support for configuring PSEL registers is removed from the driver. + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG +#define NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_TX_LINK - If enabled, driver supports linking of TX transfers. + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_TX_LINK +#define NRFX_UARTE_CONFIG_TX_LINK 1 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_RX_CACHE_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_RX_CACHE_ENABLED +#define NRFX_UARTE_CONFIG_RX_CACHE_ENABLED 1 +#endif + +/** + * @brief NRFX_UARTE_RX_FIFO_FLUSH_WORKAROUND_MAGIC_BYTE + * + * Integer value. Minimum: 0. Maximum: 255. + */ +#ifndef NRFX_UARTE_RX_FIFO_FLUSH_WORKAROUND_MAGIC_BYTE +#define NRFX_UARTE_RX_FIFO_FLUSH_WORKAROUND_MAGIC_BYTE 171 +#endif + +/** + * @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_UARTE_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED +#define NRFX_UARTE_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL +#define NRFX_UARTE_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_UARTE120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE120_ENABLED +#define NRFX_UARTE120_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE130_ENABLED +#define NRFX_UARTE130_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE131_ENABLED +#define NRFX_UARTE131_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE132_ENABLED +#define NRFX_UARTE132_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE133_ENABLED +#define NRFX_UARTE133_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE134_ENABLED +#define NRFX_UARTE134_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE135_ENABLED +#define NRFX_UARTE135_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE136_ENABLED +#define NRFX_UARTE136_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE137_ENABLED +#define NRFX_UARTE137_ENABLED 0 +#endif + +/** + * @brief NRFX_VEVIF_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_VEVIF_ENABLED +#define NRFX_VEVIF_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT_ENABLED +#define NRFX_WDT_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT_CONFIG_NO_IRQ +#define NRFX_WDT_CONFIG_NO_IRQ 0 +#endif + +/** + * @brief NRFX_WDT_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT_CONFIG_LOG_ENABLED +#define NRFX_WDT_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_WDT_CONFIG_LOG_LEVEL +#define NRFX_WDT_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_WDT131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT131_ENABLED +#define NRFX_WDT131_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT132_ENABLED +#define NRFX_WDT132_ENABLED 0 +#endif + +#endif /* NRFX_CONFIG_NRF9230_ENGB_PPR_H__ */ diff --git a/modules/hal_nordic/nrfx/nrfx_config_nrf9230_engb_radiocore.h b/modules/hal_nordic/nrfx/nrfx_config_nrf9230_engb_radiocore.h new file mode 100644 index 00000000000..84a0a7558e6 --- /dev/null +++ b/modules/hal_nordic/nrfx/nrfx_config_nrf9230_engb_radiocore.h @@ -0,0 +1,2040 @@ +/* + * Copyright (c) 2024, Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef NRFX_CONFIG_NRF9230_ENGB_RADIOCORE_H__ +#define NRFX_CONFIG_NRF9230_ENGB_RADIOCORE_H__ + +#ifndef NRFX_CONFIG_H__ +#error "This file should not be included directly. Include nrfx_config.h instead." +#endif + +#ifndef NRFX_RTC0_ENABLED +#define NRFX_RTC0_ENABLED 1 +#endif + +/** + * @brief NRFX_DEFAULT_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_DEFAULT_IRQ_PRIORITY +#define NRFX_DEFAULT_IRQ_PRIORITY 7 +#endif + +/** + * @brief NRFX_BELLBOARD_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD_ENABLED +#define NRFX_BELLBOARD_ENABLED 0 +#endif + +/** + * @brief NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_BELLBOARD0_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD0_ENABLED +#define NRFX_BELLBOARD0_ENABLED 0 +#endif + +/** + * @brief NRFX_BELLBOARD1_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD1_ENABLED +#define NRFX_BELLBOARD1_ENABLED 0 +#endif + +/** + * @brief NRFX_BELLBOARD2_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD2_ENABLED +#define NRFX_BELLBOARD2_ENABLED 0 +#endif + +/** + * @brief NRFX_BELLBOARD3_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD3_ENABLED +#define NRFX_BELLBOARD3_ENABLED 0 +#endif + +/** + * @brief NRFX_COMP_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_COMP_ENABLED +#define NRFX_COMP_ENABLED 0 +#endif + +/** + * @brief NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_COMP_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_COMP_CONFIG_LOG_ENABLED +#define NRFX_COMP_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_COMP_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_COMP_CONFIG_LOG_LEVEL +#define NRFX_COMP_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_DPPI_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI_ENABLED +#define NRFX_DPPI_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI_CONFIG_LOG_ENABLED +#define NRFX_DPPI_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_DPPI_CONFIG_LOG_LEVEL +#define NRFX_DPPI_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_DPPI020_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI020_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI020_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 +#endif + +/** + * @brief NRFX_DPPI030_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI030_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI030_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 +#endif + +/** + * @brief NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000f0 +#endif + +/** + * @brief NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff +#endif + +/** + * @brief NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000001e +#endif + +/** + * @brief NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000020 +#endif + +/** + * @brief NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000040 +#endif + +/** + * @brief NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000081 +#endif + +/** + * @brief NRFX_DPPI020_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI020_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI020_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c +#endif + +/** + * @brief NRFX_DPPI030_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI030_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI030_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c +#endif + +/** + * @brief NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000f +#endif + +/** + * @brief NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff +#endif + +/** + * @brief NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff +#endif + +/** + * @brief NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000e1 +#endif + +/** + * @brief NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000df +#endif + +/** + * @brief NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000bf +#endif + +/** + * @brief NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e +#endif + +/** + * @brief NRFX_EGU_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_EGU_ENABLED +#define NRFX_EGU_ENABLED 0 +#endif + +/** + * @brief NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_EGU020_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_EGU020_ENABLED +#define NRFX_EGU020_ENABLED 0 +#endif + +/** + * @brief NRFX_EGU130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_EGU130_ENABLED +#define NRFX_EGU130_ENABLED 0 +#endif + +/** + * @brief NRFX_GPIOTE_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE_ENABLED +#define NRFX_GPIOTE_ENABLED 0 +#endif + +/** + * @brief NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS + * + * Integer value. Minimum: 0. Maximum: 15. + */ +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS +#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 2 +#endif + +/** + * @brief NRFX_GPIOTE_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED +#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_GPIOTE_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL +#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_GPIOTE130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE130_ENABLED +#define NRFX_GPIOTE130_ENABLED 0 +#endif + +/** + * @brief NRFX_GPIOTE131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE131_ENABLED +#define NRFX_GPIOTE131_ENABLED 0 +#endif + +/** + * @brief NRFX_GRTC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_ENABLED +#define NRFX_GRTC_ENABLED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_SLEEP_ALLOWED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_SLEEP_ALLOWED +#define NRFX_GRTC_CONFIG_SLEEP_ALLOWED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_AUTOEN + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_AUTOEN +#define NRFX_GRTC_CONFIG_AUTOEN 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_AUTOSTART + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_AUTOSTART +#define NRFX_GRTC_CONFIG_AUTOSTART 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS + * + * Integer value. + */ +#ifndef NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS +#define NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS 4 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK + */ +#ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK +#define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x00000f00 +#endif + +/** + * @brief NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_GRTC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_LOG_ENABLED +#define NRFX_GRTC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_GRTC_CONFIG_LOG_LEVEL +#define NRFX_GRTC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_I2S_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_I2S_ENABLED +#define NRFX_I2S_ENABLED 0 +#endif + +/** + * @brief NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_I2S_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_I2S_CONFIG_LOG_ENABLED +#define NRFX_I2S_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_I2S_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_I2S_CONFIG_LOG_LEVEL +#define NRFX_I2S_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_I2S130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_I2S130_ENABLED +#define NRFX_I2S130_ENABLED 0 +#endif + +/** + * @brief NRFX_I2S131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_I2S131_ENABLED +#define NRFX_I2S131_ENABLED 0 +#endif + +/** + * @brief NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000030 +#endif + +/** + * @brief NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c +#endif + +/** + * @brief NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000c0 +#endif + +/** + * @brief NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 +#endif + +/** + * @brief NRFX_LPCOMP_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_LPCOMP_ENABLED +#define NRFX_LPCOMP_ENABLED 0 +#endif + +/** + * @brief NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_LPCOMP_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED +#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_LPCOMP_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL +#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_MVDMA_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_MVDMA_ENABLED +#define NRFX_MVDMA_ENABLED 0 +#endif + +/** + * @brief NRFX_MVDMA120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_MVDMA120_ENABLED +#define NRFX_MVDMA120_ENABLED 0 +#endif + +/** + * @brief NRFX_MVDMA121_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_MVDMA121_ENABLED +#define NRFX_MVDMA121_ENABLED 0 +#endif + +/** + * @brief NRFX_PDM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PDM_ENABLED +#define NRFX_PDM_ENABLED 0 +#endif + +/** + * @brief NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_PDM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PDM_CONFIG_LOG_ENABLED +#define NRFX_PDM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PDM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PDM_CONFIG_LOG_LEVEL +#define NRFX_PDM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PRS_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_ENABLED +#define NRFX_PRS_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_CONFIG_LOG_ENABLED +#define NRFX_PRS_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PRS_CONFIG_LOG_LEVEL +#define NRFX_PRS_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PRS_BOX_0_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_0_ENABLED +#define NRFX_PRS_BOX_0_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_1_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_1_ENABLED +#define NRFX_PRS_BOX_1_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_2_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_2_ENABLED +#define NRFX_PRS_BOX_2_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_3_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_3_ENABLED +#define NRFX_PRS_BOX_3_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_4_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_4_ENABLED +#define NRFX_PRS_BOX_4_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_5_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_5_ENABLED +#define NRFX_PRS_BOX_5_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_6_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_6_ENABLED +#define NRFX_PRS_BOX_6_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_7_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_7_ENABLED +#define NRFX_PRS_BOX_7_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_8_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_8_ENABLED +#define NRFX_PRS_BOX_8_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_9_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_9_ENABLED +#define NRFX_PRS_BOX_9_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM_ENABLED +#define NRFX_PWM_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_PWM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM_CONFIG_LOG_ENABLED +#define NRFX_PWM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PWM_CONFIG_LOG_LEVEL +#define NRFX_PWM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PWM120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM120_ENABLED +#define NRFX_PWM120_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM130_ENABLED +#define NRFX_PWM130_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM131_ENABLED +#define NRFX_PWM131_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM132_ENABLED +#define NRFX_PWM132_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM133_ENABLED +#define NRFX_PWM133_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC_ENABLED +#define NRFX_QDEC_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_QDEC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED +#define NRFX_QDEC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL +#define NRFX_QDEC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_QDEC130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC130_ENABLED +#define NRFX_QDEC130_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC131_ENABLED +#define NRFX_QDEC131_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC_ENABLED +#define NRFX_RTC_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_RTC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC_CONFIG_LOG_ENABLED +#define NRFX_RTC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_RTC_CONFIG_LOG_LEVEL +#define NRFX_RTC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_RTC130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC130_ENABLED +#define NRFX_RTC130_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC131_ENABLED +#define NRFX_RTC131_ENABLED 0 +#endif + +/** + * @brief NRFX_SAADC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SAADC_ENABLED +#define NRFX_SAADC_ENABLED 0 +#endif + +/** + * @brief NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_SAADC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED +#define NRFX_SAADC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_SAADC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL +#define NRFX_SAADC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_SPIM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM_ENABLED +#define NRFX_SPIM_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_SPIM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED +#define NRFX_SPIM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL +#define NRFX_SPIM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_SPIM120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM120_ENABLED +#define NRFX_SPIM120_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM121_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM121_ENABLED +#define NRFX_SPIM121_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM130_ENABLED +#define NRFX_SPIM130_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM131_ENABLED +#define NRFX_SPIM131_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM132_ENABLED +#define NRFX_SPIM132_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM133_ENABLED +#define NRFX_SPIM133_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM134_ENABLED +#define NRFX_SPIM134_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM135_ENABLED +#define NRFX_SPIM135_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM136_ENABLED +#define NRFX_SPIM136_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM137_ENABLED +#define NRFX_SPIM137_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS_ENABLED +#define NRFX_SPIS_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_SPIS_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED +#define NRFX_SPIS_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL +#define NRFX_SPIS_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_SPIS120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS120_ENABLED +#define NRFX_SPIS120_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS130_ENABLED +#define NRFX_SPIS130_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS131_ENABLED +#define NRFX_SPIS131_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS132_ENABLED +#define NRFX_SPIS132_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS133_ENABLED +#define NRFX_SPIS133_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS134_ENABLED +#define NRFX_SPIS134_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS135_ENABLED +#define NRFX_SPIS135_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS136_ENABLED +#define NRFX_SPIS136_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS137_ENABLED +#define NRFX_SPIS137_ENABLED 0 +#endif + +/** + * @brief NRFX_SYSTICK_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SYSTICK_ENABLED +#define NRFX_SYSTICK_ENABLED 0 +#endif + +/** + * @brief NRFX_TEMP_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TEMP_ENABLED +#define NRFX_TEMP_ENABLED 0 +#endif + +/** + * @brief NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TEMP_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TEMP_CONFIG_LOG_ENABLED +#define NRFX_TEMP_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TEMP_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TEMP_CONFIG_LOG_LEVEL +#define NRFX_TEMP_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TIMER_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER_ENABLED +#define NRFX_TIMER_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TIMER_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED +#define NRFX_TIMER_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL +#define NRFX_TIMER_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TIMER020_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER020_ENABLED +#define NRFX_TIMER020_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER021_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER021_ENABLED +#define NRFX_TIMER021_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER022_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER022_ENABLED +#define NRFX_TIMER022_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER120_ENABLED +#define NRFX_TIMER120_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER121_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER121_ENABLED +#define NRFX_TIMER121_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER130_ENABLED +#define NRFX_TIMER130_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER131_ENABLED +#define NRFX_TIMER131_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER132_ENABLED +#define NRFX_TIMER132_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER133_ENABLED +#define NRFX_TIMER133_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER134_ENABLED +#define NRFX_TIMER134_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER135_ENABLED +#define NRFX_TIMER135_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER136_ENABLED +#define NRFX_TIMER136_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER137_ENABLED +#define NRFX_TIMER137_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM_ENABLED +#define NRFX_TWIM_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TWIM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED +#define NRFX_TWIM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL +#define NRFX_TWIM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TWIM130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM130_ENABLED +#define NRFX_TWIM130_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM131_ENABLED +#define NRFX_TWIM131_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM132_ENABLED +#define NRFX_TWIM132_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM133_ENABLED +#define NRFX_TWIM133_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM134_ENABLED +#define NRFX_TWIM134_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM135_ENABLED +#define NRFX_TWIM135_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM136_ENABLED +#define NRFX_TWIM136_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM137_ENABLED +#define NRFX_TWIM137_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_ENABLED +#define NRFX_TWIS_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TWIS_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED +#define NRFX_TWIS_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY + * + * Assume that any instance would be initialized only once. + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY +#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 +#endif + +/** + * @brief NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode. + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_NO_SYNC_MODE +#define NRFX_TWIS_NO_SYNC_MODE 0 +#endif + +/** + * @brief NRFX_TWIS_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL +#define NRFX_TWIS_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TWIS130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS130_ENABLED +#define NRFX_TWIS130_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS131_ENABLED +#define NRFX_TWIS131_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS132_ENABLED +#define NRFX_TWIS132_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS133_ENABLED +#define NRFX_TWIS133_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS134_ENABLED +#define NRFX_TWIS134_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS135_ENABLED +#define NRFX_TWIS135_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS136_ENABLED +#define NRFX_TWIS136_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS137_ENABLED +#define NRFX_TWIS137_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_ENABLED +#define NRFX_UARTE_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG + * + * If enabled, support for configuring GPIO pins is removed from the driver. + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG +#define NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG + * + * If enabled, support for configuring PSEL registers is removed from the driver. + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG +#define NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_TX_LINK - If enabled, driver supports linking of TX transfers. + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_TX_LINK +#define NRFX_UARTE_CONFIG_TX_LINK 1 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_RX_CACHE_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_RX_CACHE_ENABLED +#define NRFX_UARTE_CONFIG_RX_CACHE_ENABLED 1 +#endif + +/** + * @brief NRFX_UARTE_RX_FIFO_FLUSH_WORKAROUND_MAGIC_BYTE + * + * Integer value. Minimum: 0. Maximum: 255. + */ +#ifndef NRFX_UARTE_RX_FIFO_FLUSH_WORKAROUND_MAGIC_BYTE +#define NRFX_UARTE_RX_FIFO_FLUSH_WORKAROUND_MAGIC_BYTE 171 +#endif + +/** + * @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_UARTE_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED +#define NRFX_UARTE_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL +#define NRFX_UARTE_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_UARTE120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE120_ENABLED +#define NRFX_UARTE120_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE130_ENABLED +#define NRFX_UARTE130_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE131_ENABLED +#define NRFX_UARTE131_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE132_ENABLED +#define NRFX_UARTE132_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE133_ENABLED +#define NRFX_UARTE133_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE134_ENABLED +#define NRFX_UARTE134_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE135_ENABLED +#define NRFX_UARTE135_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE136_ENABLED +#define NRFX_UARTE136_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE137_ENABLED +#define NRFX_UARTE137_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT_ENABLED +#define NRFX_WDT_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT_CONFIG_NO_IRQ +#define NRFX_WDT_CONFIG_NO_IRQ 0 +#endif + +/** + * @brief NRFX_WDT_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT_CONFIG_LOG_ENABLED +#define NRFX_WDT_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_WDT_CONFIG_LOG_LEVEL +#define NRFX_WDT_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_WDT010_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT010_ENABLED +#define NRFX_WDT010_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT011_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT011_ENABLED +#define NRFX_WDT011_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT131_ENABLED +#define NRFX_WDT131_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT132_ENABLED +#define NRFX_WDT132_ENABLED 0 +#endif + +#endif /* NRFX_CONFIG_NRF9230_ENGB_RADIOCORE_H__ */ diff --git a/modules/hal_nordic/nrfx/nrfx_glue.h b/modules/hal_nordic/nrfx/nrfx_glue.h index da0a445e7cb..72764c66f04 100644 --- a/modules/hal_nordic/nrfx/nrfx_glue.h +++ b/modules/hal_nordic/nrfx/nrfx_glue.h @@ -337,7 +337,15 @@ void nrfx_busy_wait(uint32_t usec_to_wait); NRFX_PPI_GROUPS_USED_BY_MPSL) /** @brief Bitmask that defines GPIOTE130 channels reserved for use outside of the nrfx library. */ -#define NRFX_GPIOTE130_CHANNELS_USED ~NRFX_CONFIG_MASK_DT(DT_NODELABEL(gpiote130), owned_channels) +#define NRFX_GPIOTE130_CHANNELS_USED \ + (~NRFX_CONFIG_MASK_DT(DT_NODELABEL(gpiote130), owned_channels) | \ + NRFX_CONFIG_MASK_DT(DT_NODELABEL(gpiote130), child_owned_channels)) + +/** @brief Bitmask that defines GPIOTE131 channels reserved for use outside of the nrfx library. */ +#define NRFX_GPIOTE131_CHANNELS_USED \ + (~NRFX_CONFIG_MASK_DT(DT_NODELABEL(gpiote131), owned_channels) | \ + NRFX_CONFIG_MASK_DT(DT_NODELABEL(gpiote131), child_owned_channels)) + #if defined(CONFIG_BT_CTLR) /* diff --git a/samples/drivers/watchdog/boards/nrf9280pdk_nrf9280_cpuapp.overlay b/samples/drivers/watchdog/boards/nrf9280pdk_nrf9280_cpuapp.overlay new file mode 100644 index 00000000000..94e0d719af4 --- /dev/null +++ b/samples/drivers/watchdog/boards/nrf9280pdk_nrf9280_cpuapp.overlay @@ -0,0 +1,8 @@ +/* + * Copyright 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +&wdt010 { + status = "okay"; +}; diff --git a/scripts/west_commands/runners/nrf_common.py b/scripts/west_commands/runners/nrf_common.py index 7b26885d1ef..b95dd4cf546 100644 --- a/scripts/west_commands/runners/nrf_common.py +++ b/scripts/west_commands/runners/nrf_common.py @@ -70,7 +70,7 @@ def dev_id_help(cls) -> str: def do_add_parser(cls, parser): parser.add_argument('--nrf-family', choices=['NRF51', 'NRF52', 'NRF53', 'NRF54L', - 'NRF54H', 'NRF91'], + 'NRF54H', 'NRF91', 'NRF92'], help='''MCU family; still accepted for compatibility only''') parser.add_argument('--softreset', required=False, @@ -178,6 +178,8 @@ def ensure_family(self): self.family = 'NRF54H_FAMILY' elif self.build_conf.getboolean('CONFIG_SOC_SERIES_NRF91X'): self.family = 'NRF91_FAMILY' + elif self.build_conf.getboolean('CONFIG_SOC_SERIES_NRF92X'): + self.family = 'NRF92_FAMILY' else: raise RuntimeError(f'unknown nRF; update {__file__}') @@ -229,7 +231,7 @@ def flush(self, force=False): def recover_target(self): - if self.family in ('NRF53_FAMILY', 'NRF54H_FAMILY'): + if self.family in ('NRF53_FAMILY', 'NRF54H_FAMILY', 'NRF92_FAMILY'): self.logger.info( 'Recovering and erasing flash memory for both the network ' 'and application cores.') @@ -242,7 +244,7 @@ def recover_target(self): # keeps the debug access port open, recovering the network core last # would result in that small image being deleted from the app core. # In the case of the 54H, the order is indifferent. - if self.family in ('NRF53_FAMILY', 'NRF54H_FAMILY'): + if self.family in ('NRF53_FAMILY', 'NRF54H_FAMILY', 'NRF92_FAMILY'): self.exec_op('recover', core='NRFDL_DEVICE_CORE_NETWORK') self.exec_op('recover') @@ -254,9 +256,12 @@ def program_hex(self): # What type of erase/core arguments should we pass to the tool? core = None - if self.family == 'NRF54H_FAMILY': + if self.family in ('NRF54H_FAMILY', 'NRF92_FAMILY'): erase_arg = 'ERASE_NONE' + cpuapp = self.build_conf.getboolean('CONFIG_SOC_NRF54H20_CPUAPP') or self.build_conf.getboolean('CONFIG_SOC_NRF9280_CPUAPP') + cpurad = self.build_conf.getboolean('CONFIG_SOC_NRF54H20_CPURAD') or self.build_conf.getboolean('CONFIG_SOC_NRF9280_CPURAD') + if self.erase: self.exec_op('erase', core='NRFDL_DEVICE_CORE_APPLICATION') self.exec_op('erase', core='NRFDL_DEVICE_CORE_NETWORK') @@ -279,18 +284,18 @@ def program_hex(self): # Handle SUIT root manifest if application manifests are not used. # If an application firmware is built, the root envelope is merged with other application manifests # as well as the output HEX file. - if not self.build_conf.getboolean('CONFIG_SOC_NRF54H20_CPUAPP') and self.sysbuild_conf.get('SB_CONFIG_SUIT_ENVELOPE'): + if not cpuapp and self.sysbuild_conf.get('SB_CONFIG_SUIT_ENVELOPE'): app_root_envelope_hex_file = os.fspath( mpi_hex_dir / 'suit_installed_envelopes_application_merged.hex') self.op_program(app_root_envelope_hex_file, 'ERASE_NONE', None, defer=True, core='NRFDL_DEVICE_CORE_APPLICATION') - if self.build_conf.getboolean('CONFIG_SOC_NRF54H20_CPUAPP'): + if cpuapp: if not self.erase and self.build_conf.getboolean('CONFIG_NRF_REGTOOL_GENERATE_UICR'): self.exec_op('erase', core='NRFDL_DEVICE_CORE_APPLICATION', chip_erase_mode='ERASE_UICR', qspi_erase_mode='ERASE_NONE') core = 'NRFDL_DEVICE_CORE_APPLICATION' - elif self.build_conf.getboolean('CONFIG_SOC_NRF54H20_CPURAD'): + elif cpurad: if not self.erase and self.build_conf.getboolean('CONFIG_NRF_REGTOOL_GENERATE_UICR'): self.exec_op('erase', core='NRFDL_DEVICE_CORE_NETWORK', chip_erase_mode='ERASE_UICR', diff --git a/snippets/nordic-ppr-xip/boards/nrf9280pdk_nrf9280_cpuapp.overlay b/snippets/nordic-ppr-xip/boards/nrf9280pdk_nrf9280_cpuapp.overlay new file mode 100644 index 00000000000..4d02921660b --- /dev/null +++ b/snippets/nordic-ppr-xip/boards/nrf9280pdk_nrf9280_cpuapp.overlay @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * SPDX-License-Identifier: Apache-2.0 + */ + +&cpuppr_ram3x_region { + status = "okay"; +}; + +&cpuppr_vpr { + execution-memory = <&cpuppr_code_partition>; + /delete-property/ source-memory; +}; + +&uart135 { + status = "reserved"; +}; diff --git a/snippets/nordic-ppr-xip/snippet.yml b/snippets/nordic-ppr-xip/snippet.yml index 4fa136b20e2..09b42719c47 100644 --- a/snippets/nordic-ppr-xip/snippet.yml +++ b/snippets/nordic-ppr-xip/snippet.yml @@ -6,3 +6,6 @@ boards: nrf54h20dk/nrf54h20/cpuapp: append: EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20dk_nrf54h20_cpuapp.overlay + nrf9280pdk/nrf9280/cpuapp: + append: + EXTRA_DTC_OVERLAY_FILE: boards/nrf9280pdk_nrf9280_cpuapp.overlay diff --git a/snippets/nordic-ppr/boards/nrf9280pdk_nrf9280_cpuapp.overlay b/snippets/nordic-ppr/boards/nrf9280pdk_nrf9280_cpuapp.overlay new file mode 100644 index 00000000000..75128f42a13 --- /dev/null +++ b/snippets/nordic-ppr/boards/nrf9280pdk_nrf9280_cpuapp.overlay @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * SPDX-License-Identifier: Apache-2.0 + */ + +&cpuppr_ram3x_region { + status = "okay"; +}; + +&uart135 { + status = "reserved"; +}; diff --git a/snippets/nordic-ppr/snippet.yml b/snippets/nordic-ppr/snippet.yml index 8257e6f0a22..48caac253a8 100644 --- a/snippets/nordic-ppr/snippet.yml +++ b/snippets/nordic-ppr/snippet.yml @@ -6,3 +6,6 @@ boards: nrf54h20dk/nrf54h20/cpuapp: append: EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20dk_nrf54h20_cpuapp.overlay + nrf9280pdk/nrf9280/cpuapp: + append: + EXTRA_DTC_OVERLAY_FILE: boards/nrf9280pdk_nrf9280_cpuapp.overlay diff --git a/soc/nordic/Kconfig b/soc/nordic/Kconfig index bb68a3f6110..906116e606a 100644 --- a/soc/nordic/Kconfig +++ b/soc/nordic/Kconfig @@ -18,6 +18,7 @@ rsource "*/Kconfig" config NRF_SOC_SECURE_SUPPORTED def_bool !TRUSTED_EXECUTION_NONSECURE || (BUILD_WITH_TFM && TFM_PARTITION_PLATFORM) depends on !SOC_SERIES_NRF54HX + depends on !SOC_SERIES_NRF92X help Hidden function to indicate that that the soc_secure functions are available. @@ -170,4 +171,11 @@ config NRF_TRACE_PORT Unit) for tracing using a hardware probe. If disabled, the trace pins will be used as GPIO. +config NRF_PLATFORM_HALTIUM + bool + help + SoC series based on the Nordic nRF Haltium platform need to select + this option. This allows to easily enable common functionality on + SoCs based on the Haltium platform. + endif # SOC_FAMILY_NORDIC_NRF diff --git a/soc/nordic/Kconfig.defconfig b/soc/nordic/Kconfig.defconfig index 513d1240d53..b733eaeed03 100644 --- a/soc/nordic/Kconfig.defconfig +++ b/soc/nordic/Kconfig.defconfig @@ -11,7 +11,7 @@ rsource "*/Kconfig.defconfig" if SYS_CLOCK_EXISTS config CLOCK_CONTROL - default y + default y if !SOC_SERIES_NRF92X endif # SYS_CLOCK_EXISTS diff --git a/soc/nordic/Kconfig.soc b/soc/nordic/Kconfig.soc index 2e47fcb4736..6851c25becf 100644 --- a/soc/nordic/Kconfig.soc +++ b/soc/nordic/Kconfig.soc @@ -14,6 +14,7 @@ config SOC_SERIES default "nrf54h" if SOC_SERIES_NRF54HX default "nrf54l" if SOC_SERIES_NRF54LX default "nrf91" if SOC_SERIES_NRF91X + default "nrf92" if SOC_SERIES_NRF92X config SOC_FAMILY_NORDIC_NRF bool @@ -56,4 +57,10 @@ config SOC_SERIES_NRF91X help Enable support for NRF91 MCU series +config SOC_SERIES_NRF92X + bool + select SOC_FAMILY_NORDIC_NRF + help + Enable support for NRF92 MCU series + rsource "*/Kconfig.soc" diff --git a/soc/nordic/common/CMakeLists.txt b/soc/nordic/common/CMakeLists.txt index 805113f53d6..fe4b8b92a0b 100644 --- a/soc/nordic/common/CMakeLists.txt +++ b/soc/nordic/common/CMakeLists.txt @@ -7,8 +7,16 @@ zephyr_linker_sources_ifdef(CONFIG_ARM SECTIONS arm_platform_init.ld) zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) +if((CONFIG_SOC_SERIES_NRF54HX OR CONFIG_SOC_SERIES_NRF92X) AND CONFIG_CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS) + zephyr_library_sources(nrf54hx_nrf92x_mpu_regions.c) +endif() + zephyr_include_directories(.) +if(CONFIG_HAS_NORDIC_DMM) + zephyr_library_sources(dmm.c) +endif() + if(CONFIG_TFM_PARTITION_PLATFORM) zephyr_library_sources(soc_secure.c) zephyr_library_include_directories( diff --git a/soc/nordic/common/Kconfig b/soc/nordic/common/Kconfig index 54e2356c6af..8de20c37dd4 100644 --- a/soc/nordic/common/Kconfig +++ b/soc/nordic/common/Kconfig @@ -1,4 +1,7 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 +config HAS_NORDIC_DMM + bool + rsource "vpr/Kconfig" diff --git a/soc/nordic/common/dmm.c b/soc/nordic/common/dmm.c new file mode 100644 index 00000000000..cfb3f3ad25f --- /dev/null +++ b/soc/nordic/common/dmm.c @@ -0,0 +1,297 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include "dmm.h" + +#define _FILTER_MEM(node_id, fn) \ + COND_CODE_1(DT_NODE_HAS_PROP(node_id, zephyr_memory_attr), (fn(node_id)), ()) +#define DT_MEMORY_REGION_FOREACH_STATUS_OKAY_NODE(fn) \ + DT_FOREACH_STATUS_OKAY_NODE_VARGS(_FILTER_MEM, fn) + +#define __BUILD_LINKER_END_VAR(_name) DT_CAT3(__, _name, _end) +#define _BUILD_LINKER_END_VAR(node_id) \ + __BUILD_LINKER_END_VAR(DT_STRING_UNQUOTED(node_id, zephyr_memory_region)) + +#define _BUILD_MEM_REGION(node_id) \ + {.dt_addr = DT_REG_ADDR(node_id), \ + .dt_size = DT_REG_SIZE(node_id), \ + .dt_attr = DT_PROP(node_id, zephyr_memory_attr), \ + .dt_align = DMM_REG_ALIGN_SIZE(node_id), \ + .dt_allc = &_BUILD_LINKER_END_VAR(node_id)}, + +/* Generate declarations of linker variables used to determine size of preallocated variables + * stored in memory sections spanning over memory regions. + * These are used to determine memory left for dynamic bounce buffer allocator to work with. + */ +#define _DECLARE_LINKER_VARS(node_id) extern uint32_t _BUILD_LINKER_END_VAR(node_id); +DT_MEMORY_REGION_FOREACH_STATUS_OKAY_NODE(_DECLARE_LINKER_VARS); + +struct dmm_region { + uintptr_t dt_addr; + size_t dt_size; + uint32_t dt_attr; + uint32_t dt_align; + void *dt_allc; +}; + +struct dmm_heap { + struct sys_heap heap; + const struct dmm_region *region; +}; + +static const struct dmm_region dmm_regions[] = { + DT_MEMORY_REGION_FOREACH_STATUS_OKAY_NODE(_BUILD_MEM_REGION) +}; + +struct { + struct dmm_heap dmm_heaps[ARRAY_SIZE(dmm_regions)]; +} dmm_heaps_data; + +static struct dmm_heap *dmm_heap_find(void *region) +{ + struct dmm_heap *dh; + + for (size_t idx = 0; idx < ARRAY_SIZE(dmm_heaps_data.dmm_heaps); idx++) { + dh = &dmm_heaps_data.dmm_heaps[idx]; + if (dh->region->dt_addr == (uintptr_t)region) { + return dh; + } + } + + return NULL; +} + +static bool is_region_cacheable(const struct dmm_region *region) +{ + return (IS_ENABLED(CONFIG_DCACHE) && (region->dt_attr & DT_MEM_CACHEABLE)); +} + +static bool is_buffer_within_region(uintptr_t start, size_t size, + uintptr_t reg_start, size_t reg_size) +{ + return ((start >= reg_start) && ((start + size) <= (reg_start + reg_size))); +} + +static bool is_user_buffer_correctly_preallocated(void const *user_buffer, size_t user_length, + const struct dmm_region *region) +{ + uintptr_t addr = (uintptr_t)user_buffer; + + if (!is_buffer_within_region(addr, user_length, region->dt_addr, region->dt_size)) { + return false; + } + + if (!is_region_cacheable(region)) { + /* Buffer is contained within non-cacheable region - use it as it is. */ + return true; + } + + if (IS_ALIGNED(addr, region->dt_align)) { + /* If buffer is in cacheable region it must be aligned to data cache line size. */ + return true; + } + + return false; +} + +static size_t dmm_heap_start_get(struct dmm_heap *dh) +{ + return ROUND_UP(dh->region->dt_allc, dh->region->dt_align); +} + +static size_t dmm_heap_size_get(struct dmm_heap *dh) +{ + return (dh->region->dt_size - (dmm_heap_start_get(dh) - dh->region->dt_addr)); +} + +static void *dmm_buffer_alloc(struct dmm_heap *dh, size_t length) +{ + length = ROUND_UP(length, dh->region->dt_align); + return sys_heap_aligned_alloc(&dh->heap, dh->region->dt_align, length); +} + +static void dmm_buffer_free(struct dmm_heap *dh, void *buffer) +{ + sys_heap_free(&dh->heap, buffer); +} + +int dmm_buffer_out_prepare(void *region, void const *user_buffer, size_t user_length, + void **buffer_out) +{ + struct dmm_heap *dh; + + if (user_length == 0) { + /* Assume that zero-length buffers are correct as they are. */ + *buffer_out = (void *)user_buffer; + return 0; + } + + /* Get memory region that specified device can perform DMA transfers from */ + dh = dmm_heap_find(region); + if (dh == NULL) { + return -EINVAL; + } + + /* Check if: + * - provided user buffer is already in correct memory region, + * - provided user buffer is aligned and padded to cache line, + * if it is located in cacheable region. + */ + if (is_user_buffer_correctly_preallocated(user_buffer, user_length, dh->region)) { + /* If yes, assign buffer_out to user_buffer*/ + *buffer_out = (void *)user_buffer; + } else { + /* If no: + * - dynamically allocate buffer in correct memory region that respects cache line + * alignment and padding + */ + *buffer_out = dmm_buffer_alloc(dh, user_length); + /* Return error if dynamic allocation fails */ + if (*buffer_out == NULL) { + return -ENOMEM; + } + /* - copy user buffer contents into allocated buffer */ + memcpy(*buffer_out, user_buffer, user_length); + } + + /* Check if device memory region is cacheable + * If yes, writeback all cache lines associated with output buffer + * (either user or allocated) + */ + if (is_region_cacheable(dh->region)) { + sys_cache_data_flush_range(*buffer_out, user_length); + } + /* If no, no action is needed */ + + return 0; +} + +int dmm_buffer_out_release(void *region, void *buffer_out) +{ + struct dmm_heap *dh; + uintptr_t addr = (uintptr_t)buffer_out; + + /* Get memory region that specified device can perform DMA transfers from */ + dh = dmm_heap_find(region); + if (dh == NULL) { + return -EINVAL; + } + + /* Check if output buffer is contained within memory area + * managed by dynamic memory allocator + */ + if (is_buffer_within_region(addr, 0, dmm_heap_start_get(dh), dmm_heap_size_get(dh))) { + /* If yes, free the buffer */ + dmm_buffer_free(dh, buffer_out); + } + /* If no, no action is needed */ + + return 0; +} + +int dmm_buffer_in_prepare(void *region, void *user_buffer, size_t user_length, void **buffer_in) +{ + struct dmm_heap *dh; + + if (user_length == 0) { + /* Assume that zero-length buffers are correct as they are. */ + *buffer_in = (void *)user_buffer; + return 0; + } + + /* Get memory region that specified device can perform DMA transfers to */ + dh = dmm_heap_find(region); + if (dh == NULL) { + return -EINVAL; + } + + /* Check if: + * - provided user buffer is already in correct memory region, + * - provided user buffer is aligned and padded to cache line, + * if it is located in cacheable region. + */ + if (is_user_buffer_correctly_preallocated(user_buffer, user_length, dh->region)) { + /* If yes, assign buffer_in to user_buffer */ + *buffer_in = user_buffer; + } else { + /* If no, dynamically allocate buffer in correct memory region that respects cache + * line alignment and padding + */ + *buffer_in = dmm_buffer_alloc(dh, user_length); + /* Return error if dynamic allocation fails */ + if (*buffer_in == NULL) { + return -ENOMEM; + } + } + + /* Check if device memory region is cacheable + * If yes, invalidate all cache lines associated with input buffer + * (either user or allocated) to clear potential dirty bits. + */ + if (is_region_cacheable(dh->region)) { + sys_cache_data_invd_range(*buffer_in, user_length); + } + /* If no, no action is needed */ + + return 0; +} + +int dmm_buffer_in_release(void *region, void *user_buffer, size_t user_length, void *buffer_in) +{ + struct dmm_heap *dh; + uintptr_t addr = (uintptr_t)buffer_in; + + /* Get memory region that specified device can perform DMA transfers to, using devicetree */ + dh = dmm_heap_find(region); + if (dh == NULL) { + return -EINVAL; + } + + /* Check if device memory region is cacheable + * If yes, invalidate all cache lines associated with input buffer + * (either user or allocated) + */ + if (is_region_cacheable(dh->region)) { + sys_cache_data_invd_range(buffer_in, user_length); + } + /* If no, no action is needed */ + + /* Check if user buffer and allocated buffer points to the same memory location + * If no, copy allocated buffer to the user buffer + */ + if (buffer_in != user_buffer) { + memcpy(user_buffer, buffer_in, user_length); + } + /* If yes, no action is needed */ + + /* Check if input buffer is contained within memory area + * managed by dynamic memory allocator + */ + if (is_buffer_within_region(addr, 0, dmm_heap_start_get(dh), dmm_heap_size_get(dh))) { + /* If yes, free the buffer */ + dmm_buffer_free(dh, buffer_in); + } + /* If no, no action is needed */ + + return 0; +} + +int dmm_init(void) +{ + struct dmm_heap *dh; + + for (size_t idx = 0; idx < ARRAY_SIZE(dmm_regions); idx++) { + dh = &dmm_heaps_data.dmm_heaps[idx]; + dh->region = &dmm_regions[idx]; + sys_heap_init(&dh->heap, (void *)dmm_heap_start_get(dh), dmm_heap_size_get(dh)); + } + + return 0; +} diff --git a/soc/nordic/common/dmm.h b/soc/nordic/common/dmm.h new file mode 100644 index 00000000000..e92f01d07b8 --- /dev/null +++ b/soc/nordic/common/dmm.h @@ -0,0 +1,216 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * nRF SoC specific public APIs for Device Memory Management (dmm) subsystem + */ + +#ifndef SOC_NORDIC_COMMON_DMM_H_ +#define SOC_NORDIC_COMMON_DMM_H_ + +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** @cond INTERNAL_HIDDEN */ + +/* Determine if memory region is cacheable. */ +#define DMM_IS_REG_CACHEABLE(node_id) \ + COND_CODE_1(CONFIG_DCACHE, \ + (COND_CODE_1(DT_NODE_HAS_PROP(node_id, zephyr_memory_attr), \ + ((DT_PROP(node_id, zephyr_memory_attr) & DT_MEM_CACHEABLE)), \ + (0))), (0)) + +/* Determine required alignment of the data buffers in specified memory region. + * Cache line alignment is required if region is cacheable and data cache is enabled. + */ +#define DMM_REG_ALIGN_SIZE(node_id) \ + (DMM_IS_REG_CACHEABLE(node_id) ? CONFIG_DCACHE_LINE_SIZE : sizeof(uint8_t)) + +/* Determine required alignment of the data buffers in memory region + * associated with specified device node. + */ +#define DMM_ALIGN_SIZE(node_id) DMM_REG_ALIGN_SIZE(DT_PHANDLE(node_id, memory_regions)) + +/** + * @brief Get reference to memory region associated with the specified device node + * + * @param node_id Device node. + * + * @return Reference to memory region. NULL if not defined for given device node. + */ +#define DMM_DEV_TO_REG(node_id) \ + COND_CODE_1(DT_NODE_HAS_PROP(node_id, memory_regions), \ + ((void *)DT_REG_ADDR(DT_PHANDLE(node_id, memory_regions))), (NULL)) + +/** + * @brief Preallocate buffer in memory region associated with the specified device node + * + * @param node_id Device node. + */ +#define DMM_MEMORY_SECTION(node_id) \ + COND_CODE_1(DT_NODE_HAS_PROP(node_id, memory_regions), \ + (__attribute__((__section__(LINKER_DT_NODE_REGION_NAME( \ + DT_PHANDLE(node_id, memory_regions))))) \ + __aligned(DMM_ALIGN_SIZE(node_id))), \ + ()) + +#ifdef CONFIG_HAS_NORDIC_DMM + +/** + * @brief Prepare a DMA output buffer for the specified device + * + * Allocate an output buffer in memory region that given device can perform DMA transfers from. + * Copy @p user_buffer contents into it. + * Writeback data cache lines associated with output buffer, if needed. + * + * @note Depending on provided user buffer parameters and SoC architecture, + * dynamic allocation and cache operations might be skipped. + * + * @note @p buffer_out can be released using @ref dmm_buffer_in_release() + * to support transmitting and receiving data to the same buffer. + * + * @warning It is prohibited to read or write @p user_buffer or @p buffer_out contents + * from the time this function is called until @ref dmm_buffer_out_release() + * or @ref dmm_buffer_in_release is called on the same buffer + * or until this function returns with an error. + * + * @param region Memory region associated with device to prepare the buffer for. + * @param user_buffer CPU address (virtual if applicable) of the buffer containing data + * to be processed by the given device. + * @param user_length Length of the buffer containing data to be processed by the given device. + * @param buffer_out Pointer to a bus address of a buffer containing the prepared DMA buffer. + * + * @retval 0 If succeeded. + * @retval -ENOMEM If output buffer could not be allocated. + * @retval -errno Negative errno for other failures. + */ +int dmm_buffer_out_prepare(void *region, void const *user_buffer, size_t user_length, + void **buffer_out); + +/** + * @brief Release the previously prepared DMA output buffer + * + * @param region Memory region associated with device to release the buffer for. + * @param buffer_out Bus address of the DMA output buffer previously prepared + * with @ref dmm_buffer_out_prepare(). + * + * @retval 0 If succeeded. + * @retval -errno Negative errno code on failure. + */ +int dmm_buffer_out_release(void *region, void *buffer_out); + +/** + * @brief Prepare a DMA input buffer for the specified device + * + * Allocate an input buffer in memory region that given device can perform DMA transfers to. + * + * @note Depending on provided user buffer parameters and SoC architecture, + * dynamic allocation might be skipped. + * + * @warning It is prohibited to read or write @p user_buffer or @p buffer_in contents + * from the time this function is called until @ref dmm_buffer_in_release() + * is called on the same buffer or until this function returns with an error. + * + * @param region Memory region associated with device to prepare the buffer for. + * @param user_buffer CPU address (virtual if applicable) of the buffer to be filled with data + * from the given device. + * @param user_length Length of the buffer to be filled with data from the given device. + * @param buffer_in Pointer to a bus address of a buffer containing the prepared DMA buffer. + * + * @retval 0 If succeeded. + * @retval -ENOMEM If input buffer could not be allocated. + * @retval -errno Negative errno for other failures. + */ +int dmm_buffer_in_prepare(void *region, void *user_buffer, size_t user_length, void **buffer_in); + +/** + * @brief Release the previously prepared DMA input buffer + * + * Invalidate data cache lines associated with input buffer, if needed. + * Copy @p buffer_in contents into @p user_buffer, if needed. + * + * @param region Memory region associated with device to release the buffer for. + * @param user_buffer CPU address (virtual if applicable) of the buffer to be filled with data + * from the given device. + * @param user_length Length of the buffer to be filled with data from the given device. + * @param buffer_in Bus address of the DMA input buffer previously prepared + * with @ref dmm_buffer_in_prepare(). + * + * @note @p user_buffer and @p buffer_in arguments pair provided in this function call must match + * the arguments pair provided in prior call to @ref dmm_buffer_out_prepare() + * or @ref dmm_buffer_in_prepare(). + * + * @retval 0 If succeeded. + * @retval -errno Negative errno code on failure. + */ +int dmm_buffer_in_release(void *region, void *user_buffer, size_t user_length, void *buffer_in); + +/** + * @brief Initialize DMM. + * + * @retval 0 If succeeded. + * @retval -errno Negative errno code on failure. + */ +int dmm_init(void); + +/** @endcond */ + +#else + +static ALWAYS_INLINE int dmm_buffer_out_prepare(void *region, void const *user_buffer, + size_t user_length, void **buffer_out) +{ + ARG_UNUSED(region); + ARG_UNUSED(user_length); + *buffer_out = (void *)user_buffer; + return 0; +} + +static ALWAYS_INLINE int dmm_buffer_out_release(void *region, void *buffer_out) +{ + ARG_UNUSED(region); + ARG_UNUSED(buffer_out); + return 0; +} + +static ALWAYS_INLINE int dmm_buffer_in_prepare(void *region, void *user_buffer, size_t user_length, + void **buffer_in) +{ + ARG_UNUSED(region); + ARG_UNUSED(user_length); + *buffer_in = user_buffer; + return 0; +} + +static ALWAYS_INLINE int dmm_buffer_in_release(void *region, void *user_buffer, size_t user_length, + void *buffer_in) +{ + ARG_UNUSED(region); + ARG_UNUSED(user_buffer); + ARG_UNUSED(user_length); + ARG_UNUSED(buffer_in); + return 0; +} + +static ALWAYS_INLINE int dmm_init(void) +{ + return 0; +} + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* SOC_NORDIC_COMMON_DMM_H_ */ diff --git a/soc/nordic/nrf54h/mpu_regions.c b/soc/nordic/common/nrf54hx_nrf92x_mpu_regions.c similarity index 77% rename from soc/nordic/nrf54h/mpu_regions.c rename to soc/nordic/common/nrf54hx_nrf92x_mpu_regions.c index a86161f3cbe..66659588411 100644 --- a/soc/nordic/nrf54h/mpu_regions.c +++ b/soc/nordic/common/nrf54hx_nrf92x_mpu_regions.c @@ -14,6 +14,10 @@ #define CAN120_SIZE DT_REG_SIZE_BY_NAME(DT_NODELABEL(can120), message_ram) + \ DT_REG_SIZE_BY_NAME(DT_NODELABEL(can120), m_can) +#define CAN121_BASE DT_REG_ADDR_BY_NAME(DT_NODELABEL(can121), message_ram) +#define CAN121_SIZE DT_REG_SIZE_BY_NAME(DT_NODELABEL(can121), message_ram) + \ + DT_REG_SIZE_BY_NAME(DT_NODELABEL(can121), m_can) + static struct arm_mpu_region mpu_regions[] = { MPU_REGION_ENTRY("FLASH_0", CONFIG_FLASH_BASE_ADDRESS, @@ -32,6 +36,10 @@ static struct arm_mpu_region mpu_regions[] = { MPU_REGION_ENTRY("CAN120_MCAN", CAN120_BASE, REGION_RAM_NOCACHE_ATTR(CAN120_BASE, CAN120_SIZE)), #endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(can121), okay) + MPU_REGION_ENTRY("CAN121_MCAN", CAN121_BASE, + REGION_RAM_NOCACHE_ATTR(CAN121_BASE, CAN121_SIZE)), +#endif }; const struct arm_mpu_config mpu_config = { diff --git a/soc/nordic/nrf54h/CMakeLists.txt b/soc/nordic/nrf54h/CMakeLists.txt index 1d1867fb1e7..0496841ffe7 100644 --- a/soc/nordic/nrf54h/CMakeLists.txt +++ b/soc/nordic/nrf54h/CMakeLists.txt @@ -8,7 +8,6 @@ if(CONFIG_ARM) endif() endif() -zephyr_library_sources_ifdef(CONFIG_CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS mpu_regions.c) zephyr_library_sources_ifdef(CONFIG_PM_S2RAM pm_s2ram.c) zephyr_include_directories(.) diff --git a/soc/nordic/nrf54h/Kconfig b/soc/nordic/nrf54h/Kconfig index a9fe5f9863e..db62be6eb51 100644 --- a/soc/nordic/nrf54h/Kconfig +++ b/soc/nordic/nrf54h/Kconfig @@ -7,6 +7,7 @@ config SOC_SERIES_NRF54HX select HAS_NRFS select HAS_NRFX select HAS_NORDIC_DRIVERS + select NRF_PLATFORM_HALTIUM config SOC_NRF54H20_CPUAPP select ARM @@ -18,6 +19,7 @@ config SOC_NRF54H20_CPUAPP select CPU_HAS_ICACHE select CPU_HAS_FPU select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS + select HAS_NORDIC_DMM select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE select NRFS_HAS_CLOCK_SERVICE select NRFS_HAS_DVFS_SERVICE @@ -41,6 +43,7 @@ config SOC_NRF54H20_CPURAD select NRFS_HAS_CLOCK_SERVICE select NRFS_HAS_MRAM_SERVICE select NRFS_HAS_TEMP_SERVICE + select HAS_NORDIC_DMM select HAS_PM select HAS_POWEROFF diff --git a/soc/nordic/nrf54h/soc.c b/soc/nordic/nrf54h/soc.c index 9c27e7b2199..b93658b55d4 100644 --- a/soc/nordic/nrf54h/soc.c +++ b/soc/nordic/nrf54h/soc.c @@ -19,6 +19,7 @@ #include #include #include +#include LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); @@ -128,6 +129,8 @@ bool z_arm_on_enter_cpu_idle(void) static int nordicsemi_nrf54h_init(void) { + int err; + sys_cache_instr_enable(); sys_cache_data_enable(); @@ -135,6 +138,11 @@ static int nordicsemi_nrf54h_init(void) trim_hsfll(); + err = dmm_init(); + if (err < 0) { + return err; + } + #if DT_NODE_HAS_STATUS(DT_NODELABEL(ccm030), okay) /* DMASEC is set to non-secure by default, which prevents CCM from * accessing secure memory. Change DMASEC to secure. diff --git a/soc/nordic/nrf92/CMakeLists.txt b/soc/nordic/nrf92/CMakeLists.txt new file mode 100644 index 00000000000..1aa4723814f --- /dev/null +++ b/soc/nordic/nrf92/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_ARM) + zephyr_library_sources(soc.c) +endif() + +zephyr_include_directories(.) + +# Ensure that image size aligns with 16 bytes so that MRAMC finalizes all writes +# for the image correctly +zephyr_linker_sources(SECTIONS SORT_KEY zzz_place_align_at_end align.ld) diff --git a/soc/nordic/nrf92/Kconfig b/soc/nordic/nrf92/Kconfig new file mode 100644 index 00000000000..f6efecb6ad0 --- /dev/null +++ b/soc/nordic/nrf92/Kconfig @@ -0,0 +1,48 @@ +# Nordic Semiconductor nRF92 MCU line + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NRF92X + select HAS_NRFS + select HAS_NRFX + select HAS_NORDIC_DRIVERS + select NRF_PLATFORM_HALTIUM + +config SOC_NRF9230_ENGB_CPUAPP + select ARM + select ARMV8_M_DSP + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + select CPU_HAS_ARM_SAU + select CPU_HAS_DCACHE + select CPU_HAS_ICACHE + select CPU_HAS_FPU + select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS + select HAS_NORDIC_DMM + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select NRFS_HAS_CLOCK_SERVICE + select NRFS_HAS_MRAM_SERVICE + select NRFS_HAS_PMIC_SERVICE + select NRFS_HAS_TEMP_SERVICE + select NRFS_HAS_VBUS_DETECTOR_SERVICE + +config SOC_NRF9230_ENGB_CPURAD + select ARM + select ARMV8_M_DSP + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + select CPU_HAS_ARM_SAU + select CPU_HAS_DCACHE + select CPU_HAS_ICACHE + select CPU_HAS_FPU + select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS + select HAS_NORDIC_DMM + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select NRFS_HAS_CLOCK_SERVICE + select NRFS_HAS_MRAM_SERVICE + select NRFS_HAS_PMIC_SERVICE + select NRFS_HAS_TEMP_SERVICE + +config SOC_NRF9230_ENGB_CPUPPR + depends on RISCV_CORE_NORDIC_VPR diff --git a/soc/nordic/nrf92/Kconfig.defconfig b/soc/nordic/nrf92/Kconfig.defconfig new file mode 100644 index 00000000000..5d1b6385a05 --- /dev/null +++ b/soc/nordic/nrf92/Kconfig.defconfig @@ -0,0 +1,41 @@ +# Nordic Semiconductor nRF92 MCU line + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_NRF92X + +rsource "Kconfig.defconfig.nrf92*" + +if ARM + +config CACHE_NRF_CACHE + default y if EXTERNAL_CACHE + +endif # ARM + +if RISCV + +DT_CHOSEN_Z_SRAM = zephyr,sram +DT_CHOSEN_Z_CODE = zephyr,code-partition + +config BUILD_OUTPUT_ADJUST_LMA + depends on !XIP + default "$(dt_chosen_partition_addr_hex,$(DT_CHOSEN_Z_CODE)) - \ + $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM))" + +config BUILD_OUTPUT_HEX + default y + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1000000 if NRF_GRTC_TIMER + +endif # RISCV + +config SPI_DW_HSSI + default y if SPI_DW + +config SPI_DW_ACCESS_WORD_ONLY + default y if SPI_DW + +endif # SOC_SERIES_NRF92X diff --git a/soc/nordic/nrf92/Kconfig.defconfig.nrf9280_cpuapp b/soc/nordic/nrf92/Kconfig.defconfig.nrf9280_cpuapp new file mode 100644 index 00000000000..350f44b5c24 --- /dev/null +++ b/soc/nordic/nrf92/Kconfig.defconfig.nrf9280_cpuapp @@ -0,0 +1,14 @@ +# Nordic Semiconductor nRF9280 Application MCU + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_NRF9280_CPUAPP + +config NUM_IRQS + default 471 + +config NRF_REGTOOL_GENERATE_UICR + default y + +endif # SOC_NRF9280_CPUAPP diff --git a/soc/nordic/nrf92/Kconfig.defconfig.nrf9280_cpuppr b/soc/nordic/nrf92/Kconfig.defconfig.nrf9280_cpuppr new file mode 100644 index 00000000000..1bef8de61ca --- /dev/null +++ b/soc/nordic/nrf92/Kconfig.defconfig.nrf9280_cpuppr @@ -0,0 +1,15 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_NRF9280_CPUPPR + +config NUM_IRQS + default 496 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +config RV_BOOT_HART + default 13 if SOC_NRF9230_ENGB + +endif # SOC_NRF9280_CPUPPR diff --git a/soc/nordic/nrf92/Kconfig.defconfig.nrf9280_cpurad b/soc/nordic/nrf92/Kconfig.defconfig.nrf9280_cpurad new file mode 100644 index 00000000000..9b17a6b988c --- /dev/null +++ b/soc/nordic/nrf92/Kconfig.defconfig.nrf9280_cpurad @@ -0,0 +1,14 @@ +# Nordic Semiconductor nRF9280 Radio MCU + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_NRF9280_CPURAD + +config NUM_IRQS + default 471 + +config NRF_REGTOOL_GENERATE_UICR + default y + +endif # SOC_NRF9280_CPURAD diff --git a/soc/nordic/nrf92/Kconfig.soc b/soc/nordic/nrf92/Kconfig.soc new file mode 100644 index 00000000000..99fc28643b7 --- /dev/null +++ b/soc/nordic/nrf92/Kconfig.soc @@ -0,0 +1,66 @@ +# Nordic Semiconductor nRF9280 MCU line + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Similarly to other nRF91 family products, the nRF9280 is a +# SiP (System-in-Package) consisting of the nRF9230 SoC and +# additional components such as PMIC and others. +# Additionally, the nRF9230 contains several CPUs, similarly +# to the nRF54h20 SoC. +# +# Like it's done for the nRF91 family, let the nRF9280 SiP +# be represented by nRF9280 "SoC" in top-level SoC definitions +# and user-configurable Kconfigs, since that's what visible to users. +# +# Keep a nRF9230 Kconfig for the SoC under the hood, complete with +# the engineering version, because that's what the MDK/nrfx expects +# as build target, and so that its definition can also be re-used +# for other SiPs. + +config SOC_NRF9230_ENGB + bool + select SOC_SERIES_NRF92X + +config SOC_NRF9230_ENGB_CPUAPP + bool + select SOC_NRF9230_ENGB + +config SOC_NRF9230_ENGB_CPURAD + bool + select SOC_NRF9230_ENGB + +config SOC_NRF9230_ENGB_CPUPPR + bool + select SOC_NRF9230_ENGB + +# The SiP selects the actual SoC complete with engineer revision and appropriate CPU +config SOC_NRF9280 + bool + select SOC_NRF9230_ENGB_CPUAPP if SOC_NRF9280_CPUAPP + select SOC_NRF9230_ENGB_CPURAD if SOC_NRF9280_CPURAD + select SOC_NRF9230_ENGB_CPUPPR if SOC_NRF9280_CPUPPR + help + nRF9280 SiP + +# The CPU select the "SoC" (SiP) +config SOC_NRF9280_CPUAPP + bool + select SOC_NRF9280 + help + nRF9280 CPUAPP + +config SOC_NRF9280_CPURAD + bool + select SOC_NRF9280 + help + nRF9280 CPURAD + +config SOC_NRF9280_CPUPPR + bool + select SOC_NRF9280 + help + nRF9280 CPUPPR + +config SOC + default "nrf9280" if SOC_NRF9280 diff --git a/soc/nordic/nrf92/align.ld b/soc/nordic/nrf92/align.ld new file mode 100644 index 00000000000..0905aa7f7bc --- /dev/null +++ b/soc/nordic/nrf92/align.ld @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA. + * SPDX-License-Identifier: Apache-2.0 + */ + +SECTION_PROLOGUE(.align16,,) +{ + . = (ALIGN(16) > 0 ? ALIGN(16) : 16) - 1; + BYTE(0); +} GROUP_LINK_IN(ROMABLE_REGION) diff --git a/soc/nordic/nrf92/soc.c b/soc/nordic/nrf92/soc.c new file mode 100644 index 00000000000..1a40bb58dda --- /dev/null +++ b/soc/nordic/nrf92/soc.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); + +#if defined(NRF_APPLICATION) +#define HSFLL_NODE DT_NODELABEL(cpuapp_hsfll) +#elif defined(NRF_RADIOCORE) +#define HSFLL_NODE DT_NODELABEL(cpurad_hsfll) +#endif + +#define FICR_ADDR_GET(node_id, name) \ + DT_REG_ADDR(DT_PHANDLE_BY_NAME(node_id, nordic_ficrs, name)) + \ + DT_PHA_BY_NAME(node_id, nordic_ficrs, name, offset) + +#define SPU_INSTANCE_GET(p_addr) \ + ((NRF_SPU_Type *)((p_addr) & (ADDRESS_REGION_Msk | \ + ADDRESS_SECURITY_Msk | \ + ADDRESS_DOMAIN_Msk | \ + ADDRESS_BUS_Msk))) + +static void power_domain_init(void) +{ + /* + * Set: + * - LRCCONF010.POWERON.MAIN: 1 + * - LRCCONF010.POWERON.ACT: 1 + * - LRCCONF010.RETAIN.MAIN: 1 + * - LRCCONF010.RETAIN.ACT: 1 + * + * This is done here at boot so that when the idle routine will hit + * WFI the power domain will be correctly retained. + */ + + nrf_lrcconf_poweron_force_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_MAIN, true); + nrf_lrcconf_poweron_force_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_DOMAIN_0, true); + + nrf_lrcconf_retain_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_MAIN, true); + nrf_lrcconf_retain_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_DOMAIN_0, true); +} + +static int trim_hsfll(void) +{ +#if defined(HSFLL_NODE) + + NRF_HSFLL_Type *hsfll = (NRF_HSFLL_Type *)DT_REG_ADDR(HSFLL_NODE); + nrf_hsfll_trim_t trim = { + .vsup = sys_read32(FICR_ADDR_GET(HSFLL_NODE, vsup)), + .coarse = sys_read32(FICR_ADDR_GET(HSFLL_NODE, coarse)), + .fine = sys_read32(FICR_ADDR_GET(HSFLL_NODE, fine)) + }; + + LOG_DBG("Trim: HSFLL VSUP: 0x%.8x", trim.vsup); + LOG_DBG("Trim: HSFLL COARSE: 0x%.8x", trim.coarse); + LOG_DBG("Trim: HSFLL FINE: 0x%.8x", trim.fine); + + nrf_hsfll_clkctrl_mult_set(hsfll, + DT_PROP(HSFLL_NODE, clock_frequency) / + DT_PROP(DT_CLOCKS_CTLR(HSFLL_NODE), clock_frequency)); + nrf_hsfll_trim_set(hsfll, &trim); + + nrf_hsfll_task_trigger(hsfll, NRF_HSFLL_TASK_FREQ_CHANGE); + + LOG_DBG("NRF_HSFLL->TRIM.VSUP = %d", hsfll->TRIM.VSUP); + LOG_DBG("NRF_HSFLL->TRIM.COARSE = %d", hsfll->TRIM.COARSE); + LOG_DBG("NRF_HSFLL->TRIM.FINE = %d", hsfll->TRIM.FINE); + +#endif /* defined(HSFLL_NODE) */ + + return 0; +} + +static int nordicsemi_nrf92_init(void) +{ + sys_cache_instr_enable(); + sys_cache_data_enable(); + + power_domain_init(); + + trim_hsfll(); + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(ccm030), okay) + /* DMASEC is set to non-secure by default, which prevents CCM from + * accessing secure memory. Change DMASEC to secure. + */ + uint32_t ccm030_addr = DT_REG_ADDR(DT_NODELABEL(ccm030)); + NRF_SPU_Type *spu = SPU_INSTANCE_GET(ccm030_addr); + + nrf_spu_periph_perm_dmasec_set(spu, nrf_address_slave_get(ccm030_addr), true); +#endif + + return 0; +} + +void arch_busy_wait(uint32_t time_us) +{ + nrfx_coredep_delay_us(time_us); +} + +SYS_INIT(nordicsemi_nrf92_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); diff --git a/soc/nordic/nrf92/soc.h b/soc/nordic/nrf92/soc.h new file mode 100644 index 00000000000..4a495cfcaa1 --- /dev/null +++ b/soc/nordic/nrf92/soc.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef SOC_ARM_NORDIC_NRF_NRF9280_SOC_H_ +#define SOC_ARM_NORDIC_NRF_NRF9280_SOC_H_ + +#include + +#endif /* SOC_ARM_NORDIC_NRF_NRF9280_SOC_H_ */ diff --git a/soc/nordic/soc.yml b/soc/nordic/soc.yml index 73e4aea0474..2f0b5caab16 100644 --- a/soc/nordic/soc.yml +++ b/soc/nordic/soc.yml @@ -38,6 +38,13 @@ family: - name: nrf9151 - name: nrf9160 - name: nrf9161 + - name: nrf92 + socs: + - name: nrf9280 + cpuclusters: + - name: cpuapp + - name: cpurad + - name: cpuppr # Recovery/erase is only needed once per core. Prevent resetting the cores whilst flashing # multiple images until all images for each core have been flashed, this allows security @@ -69,6 +76,10 @@ runners: - nrf54h20/cpuapp - nrf54h20/cpurad - nrf54h20/cpuppr + - qualifiers: + - nrf9280/cpuapp + - nrf9280/cpurad + - nrf9280/cpuppr '--erase': - runners: - nrfjprog @@ -95,6 +106,10 @@ runners: - nrf54h20/cpuapp - nrf54h20/cpurad - nrf54h20/cpuppr + - qualifiers: + - nrf9280/cpuapp + - nrf9280/cpurad + - nrf9280/cpuppr '--reset': - runners: - nrfjprog @@ -121,3 +136,7 @@ runners: - nrf54h20/cpuapp - nrf54h20/cpurad - nrf54h20/cpuppr + - qualifiers: + - nrf9280/cpuapp + - nrf9280/cpurad + - nrf9280/cpuppr diff --git a/soc/nordic/validate_base_addresses.c b/soc/nordic/validate_base_addresses.c index cb398b8783d..ece2934503e 100644 --- a/soc/nordic/validate_base_addresses.c +++ b/soc/nordic/validate_base_addresses.c @@ -335,7 +335,7 @@ CHECK_DT_REG(vmc, NRF_VMC); CHECK_DT_REG(cpuflpr_clic, NRF_FLPR_VPRCLIC); #if defined(CONFIG_SOC_NRF54L15) CHECK_DT_REG(cpuflpr_vpr, NRF_VPR00); -#elif defined(CONFIG_SOC_NRF54H20) +#elif defined(CONFIG_NRF_PLATFORM_HALTIUM) CHECK_DT_REG(cpuflpr_vpr, NRF_VPR121); CHECK_DT_REG(cpuppr_vpr, NRF_VPR130); #endif diff --git a/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c b/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c index eaf9ddd2a6d..381b10a8a03 100644 --- a/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c +++ b/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c @@ -27,8 +27,8 @@ #elif defined(CONFIG_SOC_SERIES_NRF54LX) /* For nRF54L Series, use SWI00-02 interrupt lines. */ #define _ISR_OFFSET SWI00_IRQn -#elif defined(CONFIG_SOC_SERIES_NRF54HX) -/* For nRF54H Series, use BELLBOARD_0-2 interrupt lines. */ +#elif defined(CONFIG_SOC_SERIES_NRF54HX) || defined(CONFIG_SOC_SERIES_NRF92X) +/* For nRF54H and nRF92 Series, use BELLBOARD_0-2 interrupt lines. */ #define _ISR_OFFSET BELLBOARD_0_IRQn #else /* For other nRF targets, use TIMER0-2 interrupt lines. */ @@ -144,7 +144,7 @@ typedef void (*vth)(void); /* Vector Table Handler */ void nrfx_power_clock_irq_handler(void); #if defined(CONFIG_SOC_SERIES_NRF51X) || defined(CONFIG_SOC_SERIES_NRF52X) #define POWER_CLOCK_IRQ_NUM POWER_CLOCK_IRQn -#elif defined(CONFIG_SOC_SERIES_NRF54HX) +#elif defined(CONFIG_SOC_SERIES_NRF54HX) || defined(CONFIG_SOC_SERIES_NRF92X) #define POWER_CLOCK_IRQ_NUM -1 /* not needed */ #else #define POWER_CLOCK_IRQ_NUM CLOCK_POWER_IRQn @@ -154,7 +154,8 @@ void nrfx_power_clock_irq_handler(void); void timer0_nrf_isr(void); #define TIMER_IRQ_HANDLER timer0_nrf_isr #define TIMER_IRQ_NUM TIMER0_IRQn -#elif defined(CONFIG_SOC_SERIES_NRF54LX) || defined(CONFIG_SOC_SERIES_NRF54HX) +#elif defined(CONFIG_SOC_SERIES_NRF54LX) || defined(CONFIG_SOC_SERIES_NRF54HX) || \ + defined(CONFIG_SOC_SERIES_NRF92X) void nrfx_grtc_irq_handler(void); #define TIMER_IRQ_HANDLER nrfx_grtc_irq_handler #define TIMER_IRQ_NUM GRTC_0_IRQn diff --git a/tests/boards/nrf/dmm/CMakeLists.txt b/tests/boards/nrf/dmm/CMakeLists.txt new file mode 100644 index 00000000000..3d047c94898 --- /dev/null +++ b/tests/boards/nrf/dmm/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) + +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(dmm) + +FILE(GLOB app_sources src/*.c) + +target_sources(app PRIVATE ${app_sources}) diff --git a/tests/boards/nrf/dmm/boards/nrf5340dk_nrf5340_cpuapp.overlay b/tests/boards/nrf/dmm/boards/nrf5340dk_nrf5340_cpuapp.overlay new file mode 100644 index 00000000000..9d2eceba667 --- /dev/null +++ b/tests/boards/nrf/dmm/boards/nrf5340dk_nrf5340_cpuapp.overlay @@ -0,0 +1,56 @@ +/ { + aliases { + dut-cache = &spi1; + dut-nocache= &spi3; + }; +}; + +&pinctrl { + spi1_default_alt: spi1_default_alt { + group1 { + psels = , + ; + }; + }; + + spi1_sleep_alt: spi1_sleep_alt { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + spi3_default_alt: spi3_default_alt { + group1 { + psels = , + ; + }; + }; + + spi3_sleep_alt: spi3_sleep_alt { + group1 { + psels = , + ; + low-power-enable; + }; + }; +}; + +&spi1 +{ + compatible = "nordic,nrf-spim"; + status = "okay"; + pinctrl-0 = <&spi1_default_alt>; + pinctrl-1 = <&spi1_sleep_alt>; + pinctrl-names = "default", "sleep"; +}; + +&spi3 +{ + compatible = "nordic,nrf-spim"; + status = "okay"; + pinctrl-0 = <&spi3_default_alt>; + pinctrl-1 = <&spi3_sleep_alt>; + pinctrl-names = "default", "sleep"; +}; diff --git a/tests/boards/nrf/dmm/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/boards/nrf/dmm/boards/nrf54h20dk_nrf54h20_cpuapp.overlay new file mode 100644 index 00000000000..513ef21776f --- /dev/null +++ b/tests/boards/nrf/dmm/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -0,0 +1,58 @@ +/ { + aliases { + dut-cache = &spi120; + dut-nocache = &spi130; + }; +}; + +&pinctrl { + spi130_default_alt: spi130_default_alt { + group1 { + psels = , + ; + }; + }; + + spi130_sleep_alt: spi130_sleep_alt { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + spi120_default_alt: spi120_default_alt { + group1 { + psels = , + ; + }; + }; + + spi120_sleep_alt: spi120_sleep_alt { + group1 { + psels = , + ; + low-power-enable; + }; + }; +}; + +&spi130 +{ + compatible = "nordic,nrf-spim"; + status = "okay"; + pinctrl-0 = <&spi130_default_alt>; + pinctrl-1 = <&spi130_sleep_alt>; + pinctrl-names = "default", "sleep"; + memory-regions = <&cpuapp_dma_region>; +}; + +&spi120 +{ + compatible = "nordic,nrf-spim"; + status = "okay"; + pinctrl-0 = <&spi120_default_alt>; + pinctrl-1 = <&spi120_sleep_alt>; + pinctrl-names = "default", "sleep"; + memory-regions = <&dma_fast_region>; +}; diff --git a/tests/boards/nrf/dmm/prj.conf b/tests/boards/nrf/dmm/prj.conf new file mode 100644 index 00000000000..9467c292689 --- /dev/null +++ b/tests/boards/nrf/dmm/prj.conf @@ -0,0 +1 @@ +CONFIG_ZTEST=y diff --git a/tests/boards/nrf/dmm/src/main.c b/tests/boards/nrf/dmm/src/main.c new file mode 100644 index 00000000000..078edcdd39f --- /dev/null +++ b/tests/boards/nrf/dmm/src/main.c @@ -0,0 +1,231 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +#include + +#define DUT_CACHE DT_ALIAS(dut_cache) +#define DUT_NOCACHE DT_ALIAS(dut_nocache) + +#define DMM_TEST_GET_REG_START(node_id) \ + COND_CODE_1(DT_NODE_HAS_PROP(node_id, memory_regions), \ + (DT_REG_ADDR(DT_PHANDLE(node_id, memory_regions))), (0)) + +#define DMM_TEST_GET_REG_SIZE(node_id) \ + COND_CODE_1(DT_NODE_HAS_PROP(node_id, memory_regions), \ + (DT_REG_SIZE(DT_PHANDLE(node_id, memory_regions))), (0)) + +#if CONFIG_DCACHE +BUILD_ASSERT(DMM_ALIGN_SIZE(DUT_CACHE) == CONFIG_DCACHE_LINE_SIZE); +BUILD_ASSERT(DMM_ALIGN_SIZE(DUT_NOCACHE) == 1); +#endif + +struct dmm_test_region { + void *mem_reg; + uintptr_t start; + size_t size; +}; + +enum { + DMM_TEST_REGION_CACHE, + DMM_TEST_REGION_NOCACHE, + DMM_TEST_REGION_COUNT +}; + +struct dmm_fixture { + struct dmm_test_region regions[DMM_TEST_REGION_COUNT]; + uint32_t fill_value; +}; + +static const struct dmm_test_region dmm_test_regions[DMM_TEST_REGION_COUNT] = { + [DMM_TEST_REGION_CACHE] = { + .mem_reg = DMM_DEV_TO_REG(DUT_CACHE), + .start = DMM_TEST_GET_REG_START(DUT_CACHE), + .size = DMM_TEST_GET_REG_SIZE(DUT_CACHE) + }, + [DMM_TEST_REGION_NOCACHE] = { + .mem_reg = DMM_DEV_TO_REG(DUT_NOCACHE), + .start = DMM_TEST_GET_REG_START(DUT_NOCACHE), + .size = DMM_TEST_GET_REG_SIZE(DUT_NOCACHE) + }, +}; + +static void *test_setup(void) +{ + static struct dmm_fixture fixture; + + memcpy(fixture.regions, dmm_test_regions, sizeof(dmm_test_regions)); + fixture.fill_value = 0x1; + return &fixture; +} + +static void test_cleanup(void *argc) +{ +} + +static bool dmm_buffer_in_region_check(struct dmm_test_region *dtr, void *buf, size_t size) +{ + uintptr_t start = (uintptr_t)buf; + + return ((start >= dtr->start) && ((start + size) <= (dtr->start + dtr->size))); +} + +static void dmm_check_output_buffer(struct dmm_test_region *dtr, uint32_t *fill_value, + void *data, size_t size, bool was_prealloc, bool is_cached) +{ + void *buf; + int retval; + + memset(data, (*fill_value)++, size); + retval = dmm_buffer_out_prepare(dtr->mem_reg, data, size, &buf); + zassert_ok(retval); + if (IS_ENABLED(CONFIG_DCACHE) && is_cached) { + zassert_true(IS_ALIGNED(buf, CONFIG_DCACHE_LINE_SIZE)); + } + + if (IS_ENABLED(CONFIG_HAS_NORDIC_DMM)) { + if (was_prealloc) { + zassert_equal(data, buf); + } else { + zassert_not_equal(data, buf); + } + zassert_true(dmm_buffer_in_region_check(dtr, buf, size)); + } else { + zassert_equal(data, buf); + } + sys_cache_data_invd_range(buf, size); + zassert_mem_equal(buf, data, size); + + retval = dmm_buffer_out_release(dtr->mem_reg, buf); + zassert_ok(retval); +} + +static void dmm_check_input_buffer(struct dmm_test_region *dtr, uint32_t *fill_value, + void *data, size_t size, bool was_prealloc, bool is_cached) +{ + void *buf; + int retval; + uint8_t intermediate_buf[128]; + + zassert_true(size < sizeof(intermediate_buf)); + + retval = dmm_buffer_in_prepare(dtr->mem_reg, data, size, &buf); + zassert_ok(retval); + if (IS_ENABLED(CONFIG_DCACHE) && is_cached) { + zassert_true(IS_ALIGNED(buf, CONFIG_DCACHE_LINE_SIZE)); + } + + if (IS_ENABLED(CONFIG_HAS_NORDIC_DMM)) { + if (was_prealloc) { + zassert_equal(data, buf); + } else { + zassert_not_equal(data, buf); + } + zassert_true(dmm_buffer_in_region_check(dtr, buf, size)); + } else { + zassert_equal(data, buf); + } + + /* Simulate external bus master writing to memory region */ + memset(buf, (*fill_value)++, size); + sys_cache_data_flush_range(buf, size); + /* Preserve actual memory region contents before polluting the cache */ + memcpy(intermediate_buf, buf, size); + if (IS_ENABLED(CONFIG_DCACHE) && is_cached) { + /* Purposefully pollute the cache to make sure library manages cache properly */ + memset(buf, (*fill_value)++, size); + } + + retval = dmm_buffer_in_release(dtr->mem_reg, data, size, buf); + zassert_ok(retval); + + zassert_mem_equal(data, intermediate_buf, size); +} + +ZTEST_USER_F(dmm, test_check_dev_cache_in_allocate) +{ + uint8_t user_data[16]; + + dmm_check_input_buffer(&fixture->regions[DMM_TEST_REGION_CACHE], &fixture->fill_value, + user_data, sizeof(user_data), false, true); +} + +ZTEST_USER_F(dmm, test_check_dev_cache_in_preallocate) +{ + static uint8_t user_data[16] DMM_MEMORY_SECTION(DUT_CACHE); + + dmm_check_input_buffer(&fixture->regions[DMM_TEST_REGION_CACHE], &fixture->fill_value, + user_data, sizeof(user_data), true, true); +} + +ZTEST_USER_F(dmm, test_check_dev_cache_out_allocate) +{ + uint8_t user_data[16]; + + dmm_check_output_buffer(&fixture->regions[DMM_TEST_REGION_CACHE], &fixture->fill_value, + user_data, sizeof(user_data), false, true); +} + +ZTEST_USER_F(dmm, test_check_dev_cache_out_preallocate) +{ + static uint8_t user_data[16] DMM_MEMORY_SECTION(DUT_CACHE); + + dmm_check_output_buffer(&fixture->regions[DMM_TEST_REGION_CACHE], &fixture->fill_value, + user_data, sizeof(user_data), true, true); +} + +ZTEST_USER_F(dmm, test_check_dev_nocache_in_allocate) +{ + uint8_t user_data[16]; + + dmm_check_input_buffer(&fixture->regions[DMM_TEST_REGION_NOCACHE], &fixture->fill_value, + user_data, sizeof(user_data), false, false); +} + +ZTEST_USER_F(dmm, test_check_dev_nocache_in_preallocate) +{ + static uint8_t user_data[16] DMM_MEMORY_SECTION(DUT_NOCACHE); + + dmm_check_input_buffer(&fixture->regions[DMM_TEST_REGION_NOCACHE], &fixture->fill_value, + user_data, sizeof(user_data), true, false); +} + +ZTEST_USER_F(dmm, test_check_dev_nocache_out_allocate) +{ + uint8_t user_data[16]; + + dmm_check_output_buffer(&fixture->regions[DMM_TEST_REGION_NOCACHE], &fixture->fill_value, + user_data, sizeof(user_data), false, false); +} + +ZTEST_USER_F(dmm, test_check_dev_nocache_out_preallocate) +{ + static uint8_t user_data[16] DMM_MEMORY_SECTION(DUT_NOCACHE); + + dmm_check_output_buffer(&fixture->regions[DMM_TEST_REGION_NOCACHE], &fixture->fill_value, + user_data, sizeof(user_data), true, false); +} + +ZTEST_SUITE(dmm, NULL, test_setup, NULL, test_cleanup, NULL); + +int dmm_test_prepare(void) +{ + const struct dmm_test_region *dtr; + + for (size_t i = 0; i < ARRAY_SIZE(dmm_test_regions); i++) { + dtr = &dmm_test_regions[i]; + memset((void *)dtr->start, 0x00, dtr->size); + } + + return 0; +} + +SYS_INIT(dmm_test_prepare, PRE_KERNEL_1, 0); diff --git a/tests/boards/nrf/dmm/testcase.yaml b/tests/boards/nrf/dmm/testcase.yaml new file mode 100644 index 00000000000..b5f41f281a5 --- /dev/null +++ b/tests/boards/nrf/dmm/testcase.yaml @@ -0,0 +1,18 @@ +common: + tags: drivers + harness: ztest + +tests: + boards.nrf.dmm: + platform_allow: + - nrf54h20dk/nrf54h20/cpuapp + - nrf5340dk/nrf5340/cpuapp + integration_platforms: + - nrf5340dk/nrf5340/cpuapp + - nrf54h20dk/nrf54h20/cpuapp + + boards.nrf.dmm.cache_disabled: + extra_configs: + - CONFIG_DCACHE=n + platform_allow: + - nrf54h20dk/nrf54h20/cpuapp diff --git a/tests/drivers/adc/adc_api/boards/nrf9280pdk_nrf9280_cpuapp.overlay b/tests/drivers/adc/adc_api/boards/nrf9280pdk_nrf9280_cpuapp.overlay new file mode 100644 index 00000000000..d9c1f965add --- /dev/null +++ b/tests/drivers/adc/adc_api/boards/nrf9280pdk_nrf9280_cpuapp.overlay @@ -0,0 +1,43 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Nordic Semiconductor ASA + */ + +/ { + zephyr,user { + io-channels = <&adc 0>, <&adc 1>, <&adc 2>; + }; +}; + +&adc { + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1_2"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,input-positive = ; + zephyr,resolution = <10>; + }; + + channel@1 { + reg = <1>; + zephyr,gain = "ADC_GAIN_2"; + zephyr,reference = "ADC_REF_EXTERNAL0"; + zephyr,acquisition-time = ; + zephyr,input-positive = ; + zephyr,resolution = <10>; + }; + + channel@2 { + reg = <2>; + zephyr,gain = "ADC_GAIN_1_2"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,input-positive = ; + zephyr,resolution = <10>; + }; +}; diff --git a/tests/drivers/spi/spi_controller_peripheral/boards/nrf54h20dk_nrf54h20_cpurad.overlay b/tests/drivers/spi/spi_controller_peripheral/boards/nrf54h20dk_nrf54h20_cpurad.overlay index 84edfb2b6f1..73ec4c1dc08 100644 --- a/tests/drivers/spi/spi_controller_peripheral/boards/nrf54h20dk_nrf54h20_cpurad.overlay +++ b/tests/drivers/spi/spi_controller_peripheral/boards/nrf54h20dk_nrf54h20_cpurad.overlay @@ -5,6 +5,11 @@ */ #include "nrf54h20dk_nrf54h20_common.dtsi" +/* Increase dma region to fit dmm heap. */ +&cpurad_dma_region { + reg = <0x1e80 0x100>; +}; + &spi130 { memory-regions = <&cpurad_dma_region>; }; diff --git a/tests/drivers/watchdog/wdt_basic_api/boards/nrf9280pdk_nrf9280_cpuapp.overlay b/tests/drivers/watchdog/wdt_basic_api/boards/nrf9280pdk_nrf9280_cpuapp.overlay new file mode 100644 index 00000000000..94e0d719af4 --- /dev/null +++ b/tests/drivers/watchdog/wdt_basic_api/boards/nrf9280pdk_nrf9280_cpuapp.overlay @@ -0,0 +1,8 @@ +/* + * Copyright 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +&wdt010 { + status = "okay"; +}; diff --git a/tests/drivers/watchdog/wdt_basic_api/boards/nrf9280pdk_nrf9280_cpurad.overlay b/tests/drivers/watchdog/wdt_basic_api/boards/nrf9280pdk_nrf9280_cpurad.overlay new file mode 100644 index 00000000000..94e0d719af4 --- /dev/null +++ b/tests/drivers/watchdog/wdt_basic_api/boards/nrf9280pdk_nrf9280_cpurad.overlay @@ -0,0 +1,8 @@ +/* + * Copyright 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +&wdt010 { + status = "okay"; +}; diff --git a/tests/drivers/watchdog/wdt_error_cases/boards/nrf9280pdk_nrf9280_cpuapp.overlay b/tests/drivers/watchdog/wdt_error_cases/boards/nrf9280pdk_nrf9280_cpuapp.overlay new file mode 100644 index 00000000000..d540137dadb --- /dev/null +++ b/tests/drivers/watchdog/wdt_error_cases/boards/nrf9280pdk_nrf9280_cpuapp.overlay @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&wdt010 { + status = "okay"; +}; + +&wdt011 { + status = "disabled"; +}; + +&wdt131 { + status = "disabled"; +}; + +&wdt132 { + status = "disabled"; +}; diff --git a/tests/drivers/watchdog/wdt_error_cases/boards/nrf9280pdk_nrf9280_cpurad.overlay b/tests/drivers/watchdog/wdt_error_cases/boards/nrf9280pdk_nrf9280_cpurad.overlay new file mode 100644 index 00000000000..7793fed2b8e --- /dev/null +++ b/tests/drivers/watchdog/wdt_error_cases/boards/nrf9280pdk_nrf9280_cpurad.overlay @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&wdt010 { + status = "disabled"; +}; + +&wdt011 { + status = "okay"; +}; + +&wdt131 { + status = "disabled"; +}; + +&wdt132 { + status = "disabled"; +}; diff --git a/tests/drivers/watchdog/wdt_error_cases/src/main.c b/tests/drivers/watchdog/wdt_error_cases/src/main.c index b16daccb2e3..c1adc43eea3 100644 --- a/tests/drivers/watchdog/wdt_error_cases/src/main.c +++ b/tests/drivers/watchdog/wdt_error_cases/src/main.c @@ -42,7 +42,7 @@ #define DEFAULT_WINDOW_MIN (0U) /* Align tests to the specific target: */ -#if defined(CONFIG_SOC_NRF54L15) || defined(CONFIG_SOC_NRF54H20) +#if defined(CONFIG_SOC_NRF54L15) || defined(CONFIG_SOC_NRF54H20) || defined(CONFIG_SOC_NRF9280) #define WDT_TEST_FLAGS \ (WDT_DISABLE_SUPPORTED | WDT_FLAG_RESET_SOC_SUPPORTED | \ WDT_FLAG_ONLY_ONE_TIMEOUT_VALUE_SUPPORTED | WDT_OPT_PAUSE_IN_SLEEP_SUPPORTED | \ diff --git a/tests/drivers/watchdog/wdt_error_cases/testcase.yaml b/tests/drivers/watchdog/wdt_error_cases/testcase.yaml index 4fdbfaa1a4c..738008c754e 100644 --- a/tests/drivers/watchdog/wdt_error_cases/testcase.yaml +++ b/tests/drivers/watchdog/wdt_error_cases/testcase.yaml @@ -11,5 +11,7 @@ tests: - nrf54l15pdk/nrf54l15/cpuapp - nrf54h20dk/nrf54h20/cpuapp - nrf54h20dk/nrf54h20/cpurad + - nrf9280pdk/nrf9280/cpuapp + - nrf9280pdk/nrf9280/cpurad integration_platforms: - nrf54l15pdk/nrf54l15/cpuapp diff --git a/tests/lib/cpp/cxx/testcase.yaml b/tests/lib/cpp/cxx/testcase.yaml index d0d29c37018..736452cc6d1 100644 --- a/tests/lib/cpp/cxx/testcase.yaml +++ b/tests/lib/cpp/cxx/testcase.yaml @@ -34,12 +34,14 @@ tests: # -std=c++98) cpp.main.cpp98: arch_exclude: posix - # Exclude nRF54L15 and nRF54H20 as Nordic HAL is not compatible with C++98. + # Exclude nRF54L15, nRF54H20 and nRF9280 as Nordic HAL is not compatible with C++98. platform_exclude: - nrf54l15pdk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54h20dk/nrf54h20/cpuapp - nrf54h20dk/nrf54h20/cpurad + - nrf9280pdk/nrf9280/cpuapp + - nrf9280pdk/nrf9280/cpurad build_only: true extra_configs: - CONFIG_STD_CPP98=y