diff --git a/snippets/nordic-flpr/snippet.yml b/snippets/nordic-flpr/snippet.yml
index f7578eccaac..dbeaf313df0 100644
--- a/snippets/nordic-flpr/snippet.yml
+++ b/snippets/nordic-flpr/snippet.yml
@@ -9,3 +9,6 @@ boards:
   /.*/nrf54h20/cpuapp/:
     append:
       EXTRA_DTC_OVERLAY_FILE: soc/nrf54h20_cpuapp.overlay
+  /.*/nrf54l20/cpuapp/:
+    append:
+      EXTRA_DTC_OVERLAY_FILE: soc/nrf54l20_cpuapp.overlay
diff --git a/snippets/nordic-flpr/soc/nrf54l20_cpuapp.overlay b/snippets/nordic-flpr/soc/nrf54l20_cpuapp.overlay
new file mode 100644
index 00000000000..c5f342e68a3
--- /dev/null
+++ b/snippets/nordic-flpr/soc/nrf54l20_cpuapp.overlay
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	soc {
+		reserved-memory {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			cpuflpr_code_partition: image@1ed000 {
+				/* FLPR core code partition */
+				reg = <0x1ed000 DT_SIZE_K(64)>;
+			};
+		};
+
+		cpuflpr_sram_code_data: memory@2006fc00 {
+			compatible = "mmio-sram";
+			reg = <0x2006fc00 DT_SIZE_K(64)>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x2006fc00 0x10000>;
+		};
+	};
+};
+
+&uart30 {
+	status = "reserved";
+};
+
+&cpuflpr_vpr {
+	execution-memory = <&cpuflpr_sram_code_data>;
+	source-memory = <&cpuflpr_code_partition>;
+};
+
+&cpuapp_vevif_tx {
+	status = "okay";
+};