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applications: sdp: fix surplus clock edge #20017
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CI InformationTo view the history of this post, clich the 'edited' button above Inputs:Sources:sdk-nrf: PR head: 4dc1ada1702facbf7f8ed2bc564c617c535edb81 more detailssdk-nrf:
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List of changed files detected by CI (4)
Outputs:ToolchainVersion: 342151af73 Test Spec & Results: ✅ Success; ❌ Failure; 🟠 Queued; 🟡 Progress; ◻️ Skipped;
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@mif1-nordic please rebase |
Fixed bug where after increasing bus width using buffered registers, in first clock cycle the mask for previous bus width was still present. Signed-off-by: Michal Frankiewicz <[email protected]>
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applications/sdp/mspi/src/main.c
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/* Hardware issue workaround for MSPI_CPP_MODE_2, | ||
* additional clock edge when transmitting in modes other than MSPI_CPP_MODE_0. |
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Is it for modes other than 0 or only for 2?
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this is for mode 2, 2-nd line of the comment is description of hardwaare issue.
Additional clock edge for modes other than 0 includes also mode 2
Added workarounds to hardware issue causing, additional clock edge in spi modes 1-3. Signed-off-by: Michal Frankiewicz <[email protected]>
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depends on #19877