diff --git a/doc/nrf/releases_and_maturity/releases/release-notes-changelog.rst b/doc/nrf/releases_and_maturity/releases/release-notes-changelog.rst
index 9a2b1b87ba7..1b0a2dfa7bf 100644
--- a/doc/nrf/releases_and_maturity/releases/release-notes-changelog.rst
+++ b/doc/nrf/releases_and_maturity/releases/release-notes-changelog.rst
@@ -577,7 +577,7 @@ Other samples
   * Added:
 
     * Support for the nRF54L05 and nRF54L10 SoCs (emulated on nRF54L15 DK).
-    * FLPR core support for the :ref:`zephyr:nrf54l15dk_nrf54l15` board target.
+    * FLPR core support for the :ref:`zephyr:nrf54l15dk_nrf54l15` and the :ref:`zephyr:nrf54h20dk_nrf54h20` board target.
 
 Drivers
 =======
diff --git a/samples/benchmarks/coremark/Kconfig.sysbuild b/samples/benchmarks/coremark/Kconfig.sysbuild
index fe5ce874207..dbd38362fdb 100644
--- a/samples/benchmarks/coremark/Kconfig.sysbuild
+++ b/samples/benchmarks/coremark/Kconfig.sysbuild
@@ -8,7 +8,7 @@ source "share/sysbuild/Kconfig"
 
 config APP_CPUFLPR_RUN
 	bool "Run the CoreMark benchmark on the FLPR core"
-	depends on SUPPORT_FLPRCORE && !SOC_NRF54H20_CPUAPP
+	depends on SUPPORT_FLPRCORE
 	default y
 
 config APP_CPUNET_RUN
diff --git a/samples/benchmarks/coremark/README.rst b/samples/benchmarks/coremark/README.rst
index 2b331f702cf..6cb8aa2714f 100644
--- a/samples/benchmarks/coremark/README.rst
+++ b/samples/benchmarks/coremark/README.rst
@@ -167,8 +167,8 @@ CONFIG_APP_MODE_FLASH_AND_RUN - Start CoreMark sample automatically after flashi
    Otherwise, it will wait for the button press.
 
 .. note::
-   The :kconfig:option:`CONFIG_APP_MODE_FLASH_AND_RUN` Kconfig option is always enabled for the PPR core on the ``nrf54h20dk/nrf54h20/cpuapp`` board target.
-   This core on the ``nrf54h20dk/nrf54h20/cpuapp`` board target does not use the on-board buttons and LEDs.
+   The :kconfig:option:`CONFIG_APP_MODE_FLASH_AND_RUN` Kconfig option is always enabled for the PPR and FLPR cores on the ``nrf54h20dk/nrf54h20/cpuapp`` board target.
+   These cores on the ``nrf54h20dk/nrf54h20/cpuapp`` board target do not use the on-board buttons and LEDs.
 
 .. _SB_CONFIG_APP_CPUFLPR_RUN:
 
@@ -180,7 +180,6 @@ SB_CONFIG_APP_CPUFLPR_RUN - Enable the benchmark execution also for the FLPR cor
 
    This option is not supported for the following board targets that include an SoC with the FLPR core:
 
-     * ``nrf54h20dk/nrf54h20/cpuapp``
      * ``nrf54l15dk/nrf54l05/cpuapp``
      * ``nrf54l15dk/nrf54l10/cpuapp``
 
diff --git a/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
index 46a4b9640a1..f1f688bb29f 100644
--- a/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
+++ b/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
@@ -30,6 +30,11 @@
 	status = "okay";
 };
 
+/* DTS nodes required to run the cpuflpr target. */
+&cpuflpr_vpr {
+	status = "okay";
+};
+
 /* DTS nodes required to run the cpuppr target. */
 &cpuppr_vpr {
 	status = "okay";
@@ -46,7 +51,8 @@
 
 &tddconf {
 	status = "okay";
-	etrsources = <(NRF_TDDCONF_SOURCE_STMMAINCORE | NRF_TDDCONF_SOURCE_STMPPR)>;
+	etrsources = <(NRF_TDDCONF_SOURCE_STMMAINCORE | NRF_TDDCONF_SOURCE_STMPPR |
+		       NRF_TDDCONF_SOURCE_STMFLPR)>;
 	portconfig = <0>;
 	etrbuffer = <&etr_buffer>;
 };
diff --git a/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuflpr.conf b/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuflpr.conf
new file mode 100644
index 00000000000..826748c33de
--- /dev/null
+++ b/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuflpr.conf
@@ -0,0 +1,25 @@
+#
+# Copyright (c) 2025 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+
+CONFIG_COREMARK_ITERATIONS=10000
+
+# Disable the UART console Kconfig to make Kconfig configuration with the DTS configuration.
+CONFIG_UART_CONSOLE=n
+
+# Kconfigs required for the STM standalone logging, imported from the nordic-log-stm snippet.
+CONFIG_TEST_LOGGING_DEFAULTS=n
+CONFIG_LOG_FRONTEND=y
+CONFIG_LOG_FRONTEND_ONLY=y
+CONFIG_LOG_FRONTEND_STMESP=y
+CONFIG_LOG_FRONTEND_STMESP_FSC=y
+
+# Disable the NCS boot banner - the application core is responsible for printing the boot banner.
+CONFIG_NCS_BOOT_BANNER=n
+CONFIG_BOOT_BANNER=n
+
+# Reduce speed optimizations to fit the sample into the TCM of the FLPR core.
+# Removed the following options from the default configuration (prj.conf):
+# -funroll-loops
+CONFIG_COMPILER_OPT="-O3 -fno-lto -fno-pie -fno-pic -ffunction-sections -fdata-sections"
diff --git a/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuflpr.overlay b/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuflpr.overlay
new file mode 100644
index 00000000000..ff23bd1723d
--- /dev/null
+++ b/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuflpr.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+/* Disable the default UART node for the FLPR core, as logs are forwarded
+ * with STM and the application core UART. This setting also prevents access
+ * issues to the same UART instance from two or more different cores.
+ */
+&uart120 {
+	status = "disabled";
+};