diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt index 7c70f2ad9942..ca82b3547dce 100644 --- a/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt +++ b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt @@ -9,7 +9,8 @@ Required properties: Optional properties: - vbus-supply: A phandle to the regulator for USB VBUS. - +- vbus-power-supply: A phandle to the vbus power supply provider, used to + to detect the possible BC charger type of it. Example: usb3_phy0: phy@381f0040 { compatible = "fsl,imx8mq-usb-phy"; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 0f428e36dac8..8903c9b04ffe 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -724,6 +724,8 @@ clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, <&clks IMX7D_ECSPI4_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 6 7 1>, <&sdma 7 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -857,6 +859,8 @@ clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, <&clks IMX7D_ECSPI1_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 0 7 1>, <&sdma 1 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -869,6 +873,8 @@ clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, <&clks IMX7D_ECSPI2_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 2 7 1>, <&sdma 3 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -881,6 +887,8 @@ clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, <&clks IMX7D_ECSPI3_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 4 7 1>, <&sdma 5 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts index 51bc963dc57a..a625cff254f8 100644 --- a/arch/arm/boot/dts/imx7ulp-evk.dts +++ b/arch/arm/boot/dts/imx7ulp-evk.dts @@ -292,6 +292,7 @@ &lpi2c5 { #address-cells = <1>; #size-cells = <0>; + clock-frequency = <100000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_lpi2c5>; pinctrl-1 = <&pinctrl_lpi2c5>; @@ -370,6 +371,7 @@ &lpi2c7 { #address-cells = <1>; #size-cells = <0>; + clock-frequency = <100000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_lpi2c7 &pinctrl_touch_io>; pinctrl-1 = <&pinctrl_lpi2c7 &pinctrl_touch_io>; diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig index 9c922cf44e3e..2d1c0fba291e 100644 --- a/arch/arm/configs/imx_v7_defconfig +++ b/arch/arm/configs/imx_v7_defconfig @@ -151,6 +151,10 @@ CONFIG_ATA=y CONFIG_SATA_AHCI_PLATFORM=y CONFIG_AHCI_IMX=y CONFIG_PATA_IMX=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_CRYPT=m CONFIG_NETDEVICES=y # CONFIG_NET_VENDOR_BROADCOM is not set CONFIG_CS89x0=y diff --git a/arch/arm/mach-imx/mach-imx7ulp.c b/arch/arm/mach-imx/mach-imx7ulp.c index 419c7905fe05..410f0d745c9d 100644 --- a/arch/arm/mach-imx/mach-imx7ulp.c +++ b/arch/arm/mach-imx/mach-imx7ulp.c @@ -55,6 +55,9 @@ static void __init imx7ulp_set_revision(void) case 2: imx_set_soc_revision(IMX_CHIP_REVISION_2_1); break; + case 3: + imx_set_soc_revision(IMX_CHIP_REVISION_2_2); + break; default: imx_set_soc_revision(IMX_CHIP_REVISION_1_0); break; diff --git a/arch/arm/mach-imx/pm-imx7ulp.c b/arch/arm/mach-imx/pm-imx7ulp.c index c821642317ec..0a6139d2d495 100644 --- a/arch/arm/mach-imx/pm-imx7ulp.c +++ b/arch/arm/mach-imx/pm-imx7ulp.c @@ -117,6 +117,13 @@ #define ADDR_1M_MASK 0xFFF00000 +#define WDOG_CS 0x0 +#define WDOG_CS_CMD32EN BIT(13) +#define WDOG_CNT 0x4 +#define REFRESH_SEQ0 0xA602 +#define REFRESH_SEQ1 0xB480 +#define REFRESH ((REFRESH_SEQ1 << 16) | REFRESH_SEQ0) + static void __iomem *smc1_base; static void __iomem *pmc0_base; static void __iomem *pmc1_base; @@ -127,6 +134,7 @@ static void __iomem *pcc2_base; static void __iomem *pcc3_base; static void __iomem *mu_base; static void __iomem *scg1_base; +static void __iomem *wdog1_base; static void __iomem *gpio_base[4]; static void __iomem *suspend_ocram_base; static void (*imx7ulp_suspend_in_ocram_fn)(void __iomem *sram_base); @@ -462,6 +470,20 @@ static int imx7ulp_suspend_finish(unsigned long val) return 0; } +static void imx7ulp_wdog_refresh(void) +{ + /* + * On revision 2.2, wdog2 is by default disabled when out of + * reset, so here, we ONLY refresh wdog1. + */ + if (readl_relaxed(wdog1_base + WDOG_CS) & WDOG_CS_CMD32EN) { + writel(REFRESH, wdog1_base + WDOG_CNT); + } else { + writel_relaxed(REFRESH_SEQ0, wdog1_base + WDOG_CNT); + writel_relaxed(REFRESH_SEQ1, wdog1_base + WDOG_CNT); + } +} + static int imx7ulp_pm_enter(suspend_state_t state) { switch (state) { @@ -515,6 +537,8 @@ static int imx7ulp_pm_enter(suspend_state_t state) return -EINVAL; } + imx7ulp_wdog_refresh(); + return 0; } @@ -704,6 +728,10 @@ void __init imx7ulp_pm_common_init(const struct imx7ulp_pm_socdata scg1_base = of_iomap(np, 0); WARN_ON(!scg1_base); + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-wdt"); + wdog1_base = of_iomap(np, 0); + WARN_ON(!wdog1_base); + np = NULL; for (i = 0; i < 4; i++) { np = of_find_compatible_node(np, NULL, "fsl,vf610-gpio"); diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 12c26eb88afb..bc632a3ed9b5 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -867,6 +867,11 @@ static int __init __l2c_init(const struct l2c_init_data *data, l2x0_saved_regs.aux_ctrl = aux; data->enable(l2x0_base, data->num_lock); + } else { + pr_info("%s cache controller enabled try to unlock\n", + data->type); + + data->unlock(l2x0_base, data->num_lock); } outer_cache = fns; diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index cd2a6b1a61b7..ada5bc979059 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -58,7 +58,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-ak4497.dtb imx8mm-evk-ak5558.dtb imx8mm-evk imx8mm-ddr4-evk-no-dynamic_partition.dtb imx8mm-ddr4-evk-no-product-no-dynamic_partition.dtb \ imx8mm-evk-no-dynamic_partition.dtb imx8mm-evk-no-product-no-dynamic_partition.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-8mic-revE.dtb imx8mm-evk-8mic-swpdm.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-ab2.dtb imx8mm-ab2-m4.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-ab2.dtb imx8mm-ab2-m4.dtb imx8mm-ddr4-ab2.dtb imx8mm-ddr4-ab2-m4.dtb \ + imx8mm-ddr4-ab2-revb.dtb imx8mm-ddr4-ab2-m4-revb.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb imx8mn-evk-rm67191.dtb imx8mn-ddr4-evk.dtb imx8mn-ddr4-evk-ak5558.dtb \ imx8mn-ddr4-evk-rm67191.dtb imx8mn-ddr4-evk-rpmsg.dtb imx8mn-ddr4-evk-usd-wifi.dtb \ imx8mn-evk-ak5558.dtb imx8mn-evk-rpmsg.dtb imx8mn-evk-8mic-revE.dtb \ diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ddr3-val.dts b/arch/arm64/boot/dts/freescale/imx8dxl-ddr3-val.dts index d4b80f4a49c7..5d0fe1cd2e08 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ddr3-val.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ddr3-val.dts @@ -8,7 +8,7 @@ #include "imx8dxl.dtsi" / { - model = "Freescale i.MX8DXL DDR3 EVK"; + model = "Freescale i.MX8DXL DDR3 VAL"; compatible = "fsl,imx8dxl-mek", "fsl,imx8dxl"; chosen { diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk-pcie-ep.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk-pcie-ep.dts index 0eed1d52632d..4d7b4ad553ec 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk-pcie-ep.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk-pcie-ep.dts @@ -5,7 +5,7 @@ /dts-v1/; -#include "imx8dxl-evk.dts" +#include "imx8dxl-evk-rpmsg.dts" &pcieb { status = "disabled"; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index 32f8e8994267..c8378012afb1 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -186,6 +186,7 @@ regulator-max-microvolt = <3300000>; regulator-name = "clk_ext_sel"; gpio = <&pca6416_1 10 GPIO_ACTIVE_HIGH>; + enable-active-high; regulator-always-on; }; @@ -892,7 +893,7 @@ fsl,pins = < IMX8DXL_FLEXCAN0_RX_ADMA_SAI1_TXC 0x06000040 IMX8DXL_FLEXCAN0_TX_ADMA_SAI1_TXFS 0x06000040 - IMX8DXL_FLEXCAN1_RX_ADMA_SAI1_TXD 0x06000040 + IMX8DXL_FLEXCAN1_RX_ADMA_SAI1_TXD 0x06000060 IMX8DXL_FLEXCAN1_TX_ADMA_SAI1_RXD 0x06000060 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ab2-m4.dts b/arch/arm64/boot/dts/freescale/imx8mm-ab2-m4.dts index ad4f72b691f5..05609e802e6a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-ab2-m4.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-ab2-m4.dts @@ -14,7 +14,7 @@ ranges; m4_reserved: m4@0x80000000 { - reg = <0 0x80000000 0 0x1000000>; + reg = <0 0x80000000 0 0x0101E400>; no-map; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mm-ab2.dts index a09d3aac7a78..4897193a954d 100755 --- a/arch/arm64/boot/dts/freescale/imx8mm-ab2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-ab2.dts @@ -585,6 +585,13 @@ }; }; +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "disabled"; +}; + &iomuxc { pinctrl-names = "default"; @@ -647,6 +654,13 @@ >; }; + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + pinctrl_mipi_dsi_en: mipi_dsi_en { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 @@ -697,6 +711,12 @@ MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0xd6 >; }; @@ -713,6 +733,12 @@ MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0xd6 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4-revb.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4-revb.dts new file mode 100644 index 000000000000..6ff765cb4696 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4-revb.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mm-ddr4-ab2-m4.dts" + +/ { + model = "FSL i.MX8MM DDR4 RevB Audio Board 2.0"; +}; + +/* + * External OSC is used as PCIe REFCLK on RevC board. + * Use the -revb.dts file to distiguish the different + * HW design. + */ +&pcie0 { + ext_osc = <0>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4.dts new file mode 100644 index 000000000000..b8ec04c4cdcc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4.dts @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mm-ddr4-ab2.dts" + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m4_reserved: m4@0x80000000 { + reg = <0 0x80000000 0 0x0101E400>; + no-map; + }; + + vdev0vring0: vdev0vring0@b8000000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@b8008000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8008000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@b8400000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8400000 0 0x100000>; + no-map; + }; + }; + + leds { + panel { + status = "disabled"; + }; + }; + + imx8mm-cm4 { + compatible = "fsl,imx8mm-cm4"; + rsc-da = <0xb8000000>; + clocks = <&clk IMX8MM_CLK_M4_DIV>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>; + syscon = <&src>; + }; +}; + +&clk { + init-on-array = < + IMX8MM_CLK_UART4_ROOT + IMX8MM_CLK_AHB IMX8MM_CLK_DRAM_CORE + IMX8MM_CLK_NOC IMX8MM_CLK_NOC_APB + IMX8MM_CLK_MAIN_AXI IMX8MM_CLK_AUDIO_AHB + IMX8MM_CLK_DRAM_APB IMX8MM_CLK_A53_DIV + IMX8MM_ARM_PLL_OUT + >; +}; + +&i2c2 { + status = "disabled"; +}; + +&uart4 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-revb.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-revb.dts new file mode 100644 index 000000000000..833c0f0a8cdd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-revb.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mm-ddr4-ab2.dts" + +/ { + model = "FSL i.MX8MM DDR4 RevB Audio Board 2.0"; +}; + +/* + * External OSC is used as PCIe REFCLK on RevC board. + * Use the -revb.dts file to distiguish the different + * HW design. + */ +&pcie0 { + ext_osc = <0>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2.dts new file mode 100644 index 000000000000..3e5cec4e1359 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mm-ab2.dts" + +/ { + model = "FSL i.MX8MM DDR4 Audio Board 2.0"; + + leds { + pinctrl-0 = <&pinctrl_gpio_led_2>; + + status { + gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; + }; + }; + + bt_sco_codec: bt_sco_codec { + status = "disabled"; + }; + + sound-bt-sco { + status = "disabled"; + }; +}; + +&iomuxc { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 + MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 + MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x00000096 + MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 + MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 + MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 + MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 + MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 + MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 + MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 + MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 + MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 + MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 + MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 + MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 + MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 + >; + }; + + pinctrl_gpio_led_2: gpioled2grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 + >; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +®_sd1_vmmc { + status = "disabled"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&usdhc1 { + status = "disabled"; +}; + +&usdhc3 { + status = "disabled"; +}; + +&flexspi { + status = "disabled"; +}; + +&sai2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts index f7f604f4c269..69eab3b4e3f6 100755 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts @@ -149,6 +149,13 @@ status ="okay"; }; + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ir_recv>; + }; + pcie0_refclk: pcie0-refclk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -783,6 +790,12 @@ >; }; + pinctrl_ir_recv: ir-recv { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mn-ab2.dts index ac7c04029533..541d7f83453a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-ab2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-ab2.dts @@ -59,46 +59,90 @@ reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <12000>; + enable-active-high; + }; - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100>; - off-on-delay-us = <12000>; - }; - - reg_ab2_ana_pwr: regulator-ab2-ana-pwr { - compatible = "regulator-fixed"; - regulator-name = "ab2_ana_pwr"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ab2_ana_pwr>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { - compatible = "regulator-fixed"; - regulator-name = "ab2_vdd_pwr_5v0"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; + reg_ab2_ana_pwr: regulator-ab2-ana-pwr { + compatible = "regulator-fixed"; + regulator-name = "ANA_12V0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_ana_pwr>; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + vin-supply = <&buck5_reg>; + enable-active-high; + }; + + reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + vin-supply = <&buck5_reg>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + reg_adc_dvdd_3v3: reg-adc-dvdd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "ADC_DVDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_ab2_ana_pwr>; + }; + + reg_adc_avdd_5v0: reg-adc-avdd-5v0 { + compatible = "regulator-fixed"; + regulator-name = "ADC_AVDD_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_ab2_ana_pwr>; + }; + + reg_dac_dvdd_3v3: reg-dac-dvdd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "DAC_DVDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_ab2_ana_pwr>; + }; + + reg_dac_avdd_5v0: reg-dac-avdd-5v0 { + compatible = "regulator-fixed"; + regulator-name = "DAC_AVDD_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_ab2_ana_pwr>; + }; + + reg_cph_3v3: reg-cph-3v3 { + compatible = "regulator-fixed"; + regulator-name = "CPH_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_ab2_vdd_pwr_5v0>; + }; + + reg_cph_1v8: reg-cph-1v8 { + compatible = "regulator-fixed"; + regulator-name = "CPH_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <®_cph_3v3>; }; sound-ak5552 { @@ -215,6 +259,13 @@ >; }; + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + pinctrl_i2c1_gpio: i2c1grp-gpio { fsl,pins = < MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3 @@ -236,6 +287,13 @@ >; }; + pinctrl_i2c4_gpio: i2c4grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1c3 + MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1c3 + >; + }; + pinctrl_pmic: pmicirq { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 @@ -644,7 +702,7 @@ reg = <0x20>; gpio-controller; #gpio-cells = <2>; - vcc-supply = <&buck5_reg>; + vcc-supply = <&buck4_reg>; }; pca6416_2: gpio@21 { @@ -677,11 +735,21 @@ compatible = "asahi-kasei,ak5552"; reg = <0x13>; reset-gpios = <&pca6416 2 GPIO_ACTIVE_HIGH>; - AVDD-supply = <®_ab2_ana_pwr>; - DVDD-supply = <®_ab2_vdd_pwr_5v0>; + AVDD-supply = <®_adc_avdd_5v0>; + DVDD-supply = <®_adc_dvdd_3v3>; }; }; +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-ab2.dts index 463319e93f8f..442d34950e03 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-ab2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-ab2.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright 2019 NXP + * Copyright 2020 NXP */ /dts-v1/; @@ -63,32 +63,82 @@ reg_ab2_ana_pwr: regulator-ab2-ana-pwr { compatible = "regulator-fixed"; - regulator-name = "ab2_ana_pwr"; + regulator-name = "ANA_12V0"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ab2_ana_pwr>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + vin-supply = <&buck5_reg>; enable-active-high; - regulator-always-on; }; reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { compatible = "regulator-fixed"; - regulator-name = "ab2_vdd_pwr_5v0"; + regulator-name = "VDD_5V0"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + vin-supply = <&buck5_reg>; enable-active-high; regulator-always-on; + regulator-boot-on; + }; + + reg_adc_dvdd_3v3: reg-adc-dvdd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "ADC_DVDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_ab2_ana_pwr>; + }; + + reg_adc_avdd_5v0: reg-adc-avdd-5v0 { + compatible = "regulator-fixed"; + regulator-name = "ADC_AVDD_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_ab2_ana_pwr>; + }; + + reg_dac_dvdd_3v3: reg-dac-dvdd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "DAC_DVDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_ab2_ana_pwr>; + }; + + reg_dac_avdd_5v0: reg-dac-avdd-5v0 { + compatible = "regulator-fixed"; + regulator-name = "DAC_AVDD_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_ab2_ana_pwr>; + }; + + reg_cph_3v3: reg-cph-3v3 { + compatible = "regulator-fixed"; + regulator-name = "CPH_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_ab2_vdd_pwr_5v0>; + }; + + reg_cph_1v8: reg-cph-1v8 { + compatible = "regulator-fixed"; + regulator-name = "CPH_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <®_cph_3v3>; }; sound-ak5552 { compatible = "fsl,imx-audio-ak5552"; model = "ak5552-audio"; - audio-cpu = <&sai3>; + audio-cpu = <&sai6>; audio-codec = <&ak5552>; }; @@ -206,6 +256,13 @@ >; }; + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + pinctrl_i2c2_gpio: i2c2grp-gpio { fsl,pins = < MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 @@ -220,6 +277,13 @@ >; }; + pinctrl_i2c4_gpio: i2c4grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1c3 + MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1c3 + >; + }; + pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 @@ -235,6 +299,15 @@ >; }; + pinctrl_sai6: sai6grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_TX_CTL_SAI6_MCLK 0xd6 + MX8MN_IOMUXC_ENET_TD1_SAI6_RX_SYNC 0xd6 + MX8MN_IOMUXC_ENET_TD0_SAI6_RX_BCLK 0xd6 + MX8MN_IOMUXC_ENET_TD2_SAI6_RX_DATA0 0xd6 + >; + }; + pinctrl_spdif1: spdif1grp { fsl,pins = < MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 @@ -242,6 +315,12 @@ >; }; + pinctrl_typec1: typec1grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 @@ -434,6 +513,35 @@ }; }; + ptn5110_1: tcpc@50 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec1>; + reg = <0x50>; + interrupt-parent = <&gpio2>; + interrupts = <11 8>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; + pca6408_2: gpio@20 { compatible = "ti,tca6408"; reg = <0x20>; @@ -472,11 +580,21 @@ compatible = "asahi-kasei,ak5552"; reg = <0x13>; reset-gpios = <&pca6416 2 GPIO_ACTIVE_HIGH>; - AVDD-supply = <®_ab2_ana_pwr>; - DVDD-supply = <®_ab2_vdd_pwr_5v0>; + AVDD-supply = <®_adc_avdd_5v0>; + DVDD-supply = <®_adc_dvdd_3v3>; }; }; +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; @@ -655,6 +773,23 @@ status = "okay"; }; +&usbotg1 { + dr_mode = "host"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + picophy,pre-emp-curr-control = <3>; + picophy,dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + &usdhc1 { #address-cells = <1>; #size-cells = <0>; @@ -736,6 +871,21 @@ <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>, <&clk IMX8MN_AUDIO_PLL2_OUT>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + status = "disabled"; +}; + +&sai6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai6>; + assigned-clocks = <&clk IMX8MN_CLK_SAI6>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <0>, <24576000>; + clocks = <&clk IMX8MN_CLK_SAI6_IPG>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI6_ROOT>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>, + <&clk IMX8MN_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-asynchronous; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-ak5558.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-ak5558.dts index d628182a4f7b..4db0e3418e60 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-ak5558.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-ak5558.dts @@ -34,3 +34,7 @@ &sai5 { status = "okay"; }; + +&ak5558 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts index 366266791dd3..e6ae1127b07a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts @@ -547,6 +547,7 @@ reg = <0x10>; AVDD-supply = <®_audio_board>; DVDD-supply = <®_audio_board>; + status = "disabled"; }; ak4458_2: ak4458@12 { @@ -554,6 +555,7 @@ reg = <0x12>; AVDD-supply = <®_audio_board>; DVDD-supply = <®_audio_board>; + status = "disabled"; }; ak5558: ak5558@13 { @@ -562,6 +564,7 @@ ak5558,pdn-gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; AVDD-supply = <®_audio_board>; DVDD-supply = <®_audio_board>; + status = "disabled"; }; ak4497: ak4497@11 { @@ -570,6 +573,7 @@ ak4497,pdn-gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; AVDD-supply = <®_audio_board>; DVDD-supply = <®_audio_board>; + status = "disabled"; }; ov5640_mipi_0: ov5640_mipi@3c { diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts index a106df8e8293..c47d2147a314 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts @@ -63,6 +63,13 @@ }; }; + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ir_recv>; + }; + usdhc1_pwrseq: usdhc1_pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; @@ -188,6 +195,12 @@ >; }; + pinctrl_ir_recv: ir-recv { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index b89a2c428e23..0568fb06b921 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -1227,6 +1227,12 @@ interrupt-controller; interrupts = ; }; + + ddr-pmu@3d800000 { + compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu"; + reg = <0x3d800000 0x400000>; + interrupts = ; + }; }; gpu: gpu@38000000 { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index b2cd290da3d6..b545e1702539 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -184,6 +184,7 @@ regulator-max-microvolt = <3300000>; gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; enable-active-high; + regulator-always-on; }; cbtl04gp { @@ -861,6 +862,7 @@ }; &usb3_phy0 { + vbus-power-supply = <&ptn5110>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 9dc079f70b23..156cee3748ab 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1859,7 +1859,6 @@ assigned-clock-rates = <500000000>; bus-width = <4>; csi-gpr = <&mediamix_gasket0>; - csi-gpr2 = <&mediamix_gpr>; gpr = <&mediamix_blk_ctl>; no-reset-control; power-domains = <&mipi_phy1_pd>; @@ -1880,7 +1879,6 @@ assigned-clock-rates = <266000000>; bus-width = <4>; csi-gpr = <&mediamix_gasket1>; - csi-gpr2 = <&mediamix_gpr>; gpr = <&mediamix_blk_ctl>; no-reset-control; power-domains = <&mipi_phy2_pd>; @@ -2049,8 +2047,9 @@ usb3_0: usb@32f10100 { compatible = "fsl,imx8mp-dwc3"; reg = <0 0x32f10100 0 0x8>; - clocks = <&clk IMX8MP_CLK_HSIO_ROOT>; - clock-names = "hsio"; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_USB_ROOT>; + clock-names = "hsio", "suspend"; interrupts = ; power-domains = <&hsiomix_pd>; #address-cells = <2>; @@ -2071,10 +2070,7 @@ interrupts = ; phys = <&usb3_phy0>, <&usb3_phy0>; phy-names = "usb2-phy", "usb3-phy"; - xhci-no-64bit-support; - usb3-resume-missing-cas; snps,dis-u2-freeclk-exists-quirk; - snps,soft-itp-sync; status = "disabled"; }; @@ -2094,8 +2090,9 @@ usb3_1: usb@32f10108 { compatible = "fsl,imx8mp-dwc3"; reg = <0 0x32f10108 0 0x8>; - clocks = <&clk IMX8MP_CLK_HSIO_ROOT>; - clock-names = "hsio"; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_USB_ROOT>; + clock-names = "hsio", "suspend"; interrupts = ; power-domains = <&hsiomix_pd>; #address-cells = <2>; @@ -2116,10 +2113,7 @@ interrupts = ; phys = <&usb3_phy1>, <&usb3_phy1>; phy-names = "usb2-phy", "usb3-phy"; - xhci-no-64bit-support; - usb3-resume-missing-cas; snps,dis-u2-freeclk-exists-quirk; - snps,soft-itp-sync; status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 49fc612e825a..31a071fda7be 100755 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -118,6 +118,13 @@ }; }; + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ir_recv>; + }; + resmem: reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -799,6 +806,7 @@ }; &usb3_phy0 { + vbus-power-supply = <&ptn5110>; status = "okay"; }; @@ -879,6 +887,12 @@ }; + pinctrl_ir_recv: ir-recv { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f + >; + }; + pinctrl_csi1_pwn: csi1_pwn_grp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 0c0457c7729b..43e3e605618c 100755 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -883,6 +883,8 @@ clocks = <&clk IMX8MQ_CLK_UART3_ROOT>, <&clk IMX8MQ_CLK_UART3_ROOT>; clock-names = "ipg", "per"; + dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -894,6 +896,8 @@ clocks = <&clk IMX8MQ_CLK_UART2_ROOT>, <&clk IMX8MQ_CLK_UART2_ROOT>; clock-names = "ipg", "per"; + dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -1083,6 +1087,8 @@ clocks = <&clk IMX8MQ_CLK_UART4_ROOT>, <&clk IMX8MQ_CLK_UART4_ROOT>; clock-names = "ipg", "per"; + dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-dom0.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-dom0.dts index d328a4daabb8..f1cc636664f7 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek-dom0.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-dom0.dts @@ -780,3 +780,7 @@ &pwm_lvds0 { status = "disabled"; }; + +&uart0_lpcg { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-pcie-ep.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-pcie-ep.dts index a1d9e6e19da6..5127d82ff5b9 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek-pcie-ep.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-pcie-ep.dts @@ -5,7 +5,7 @@ /dts-v1/; -#include "imx8qm-mek.dts" +#include "imx8qm-mek-rpmsg.dts" &pciea{ status = "disabled"; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 1fb440dc573f..902d72c7a078 100755 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -1581,7 +1581,6 @@ IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x0600004c IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x0600004c IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x0600004c - IMX8QM_SPI2_CS0_DMA_SPI2_CS0 0x0600004c >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi index 4de4481eee18..4432fc163072 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi @@ -87,6 +87,10 @@ &edma2 { reg = <0x5a200000 0x10000>, /* channel0 LPSPI0 rx */ <0x5a210000 0x10000>, /* channel1 LPSPI0 tx */ + <0x5a220000 0x10000>, /* channel2 LPSPI1 rx */ + <0x5a230000 0x10000>, /* channel3 LPSPI1 tx */ + <0x5a240000 0x10000>, /* channel4 LPSPI2 rx */ + <0x5a250000 0x10000>, /* channel5 LPSPI2 tx */ <0x5a260000 0x10000>, /* channel6 LPSPI3 rx */ <0x5a270000 0x10000>, /* channel7 LPSPI3 tx */ <0x5a2c0000 0x10000>, /* channel12 UART0 rx */ @@ -100,9 +104,13 @@ <0x5a340000 0x10000>, /* channel20 UART4 rx */ <0x5a350000 0x10000>; /* channel21 UART4 tx */ #dma-cells = <3>; - dma-channels = <14>; + dma-channels = <18>; interrupts = , , + , + , + , + , , , , @@ -116,6 +124,8 @@ , ; interrupt-names = "edma0-chan0-rx", "edma0-chan1-tx", + "edma0-chan2-rx", "edma0-chan3-tx", + "edma0-chan4-rx", "edma0-chan5-tx", "edma0-chan6-rx", "edma0-chan7-tx", "edma0-chan12-rx", "edma0-chan13-tx", "edma0-chan14-rx", "edma0-chan15-tx", @@ -124,6 +134,10 @@ "edma0-chan20-rx", "edma0-chan21-tx"; power-domains = <&pd IMX_SC_R_DMA_0_CH0>, <&pd IMX_SC_R_DMA_0_CH1>, + <&pd IMX_SC_R_DMA_0_CH2>, + <&pd IMX_SC_R_DMA_0_CH3>, + <&pd IMX_SC_R_DMA_0_CH4>, + <&pd IMX_SC_R_DMA_0_CH5>, <&pd IMX_SC_R_DMA_0_CH6>, <&pd IMX_SC_R_DMA_0_CH7>, <&pd IMX_SC_R_DMA_0_CH12>, @@ -137,6 +151,8 @@ <&pd IMX_SC_R_DMA_0_CH20>, <&pd IMX_SC_R_DMA_0_CH21>; power-domain-names = "edma0-chan0", "edma0-chan1", + "edma0-chan2", "edma0-chan3", + "edma0-chan4", "edma0-chan5", "edma0-chan6", "edma0-chan7", "edma0-chan12", "edma0-chan13", "edma0-chan14", "edma0-chan15", diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi index 788250766632..03786f8e0f5d 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi @@ -163,9 +163,23 @@ status = "disabled"; }; + i2c0_lvds0: i2c@56246000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x56246000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_lvds0>; + clocks = <&lvds0_i2c0_lpcg 0>, + <&lvds0_i2c0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>; + status = "disabled"; + }; + i2c1_lvds0: i2c@56247000 { compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x56247000 0x4000>; + reg = <0x56247000 0x1000>; interrupts = <9>; interrupt-parent = <&irqsteer_lvds0>; clocks = <&lvds0_i2c0_lpcg 0>, @@ -336,9 +350,23 @@ status = "disabled"; }; + i2c0_lvds1: i2c@57246000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x57246000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_lvds1>; + clocks = <&lvds1_i2c0_lpcg 0>, + <&lvds1_i2c0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>; + status = "disabled"; + }; + i2c1_lvds1: i2c@57247000 { compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x57247000 0x4000>; + reg = <0x57247000 0x1000>; interrupts = <9>; interrupt-parent = <&irqsteer_lvds1>; clocks = <&lvds1_i2c0_lpcg 0>, diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dts index 6ba20843619b..3651ec1d37a4 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dts @@ -5,7 +5,7 @@ /dts-v1/; -#include "imx8qxp-mek.dts" +#include "imx8qxp-mek-rpmsg.dts" &pcieb{ status = "disabled"; diff --git a/arch/arm64/configs/imx_v8_defconfig b/arch/arm64/configs/imx_v8_defconfig index 5255fe38a5a0..3880e92ba5cc 100644 --- a/arch/arm64/configs/imx_v8_defconfig +++ b/arch/arm64/configs/imx_v8_defconfig @@ -248,6 +248,7 @@ CONFIG_PATA_OF_PLATFORM=y CONFIG_MD=y CONFIG_BLK_DEV_MD=m CONFIG_BLK_DEV_DM=m +CONFIG_DM_CRYPT=m CONFIG_DM_MIRROR=m CONFIG_DM_ZERO=m CONFIG_NETDEVICES=y @@ -317,6 +318,7 @@ CONFIG_HOSTAP=y CONFIG_MXMWIFIEX=m CONFIG_WL18XX=m CONFIG_WLCORE_SDIO=m +CONFIG_XEN_NETDEV_BACKEND=m CONFIG_IVSHMEM_NET=y CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_ADC=m @@ -458,7 +460,19 @@ CONFIG_REGULATOR_S2MPS11=y CONFIG_REGULATOR_VCTRL=m CONFIG_RC_CORE=m CONFIG_RC_DECODERS=y +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_XMP_DECODER=m +CONFIG_IR_IMON_DECODER=m +CONFIG_IR_RCMM_DECODER=m CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=m CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_ANALOG_TV_SUPPORT=y @@ -858,7 +872,7 @@ CONFIG_MEMTEST=y CONFIG_CORESIGHT=y CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y CONFIG_CORESIGHT_SOURCE_ETM4X=y -CONFIG_IMX8_MEDIA_DEVICE=y +CONFIG_IMX8_MEDIA_DEVICE=m CONFIG_IMX8_ISI_HW=y CONFIG_IMX8_ISI_CORE=y CONFIG_IMX8_ISI_CAPTURE=y diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c index ce2ebbc80695..0ea621fb7483 100644 --- a/drivers/crypto/caam/caamalg.c +++ b/drivers/crypto/caam/caamalg.c @@ -747,9 +747,6 @@ static int skcipher_setkey(struct crypto_skcipher *skcipher, const u8 *key, u32 *desc; const bool is_rfc3686 = alg->caam.rfc3686; - print_hex_dump_debug("key in @"__stringify(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); - /* * If the algorithm has support for tagged key, * this is already set in tk_skcipher_setkey(). @@ -761,6 +758,9 @@ static int skcipher_setkey(struct crypto_skcipher *skcipher, const u8 *key, ctx->cdata.key_inline = true; } + print_hex_dump_debug("key in @" __stringify(__LINE__) ": ", + DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); + /* skcipher_encrypt shared descriptor */ desc = ctx->sh_desc_enc; cnstr_shdsc_skcipher_encap(desc, &ctx->cdata, ivsize, is_rfc3686, @@ -853,19 +853,28 @@ static int tk_skcipher_setkey(struct crypto_skcipher *skcipher, struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher); struct device *jrdev = ctx->jrdev; struct header_conf *header; + struct tagged_object *tag_obj; int ret; - ctx->cdata.keylen = keylen; - ctx->cdata.key_virt = key; ctx->cdata.key_inline = true; - /* Retrieve the address of the tag object configuration */ - ret = get_tag_object_header_conf(ctx->cdata.key_virt, - ctx->cdata.keylen, &header); - if (ret) { + /* Check if one can retrieve the tag object header configuration */ + if (keylen <= TAG_OVERHEAD_SIZE) + return -EINVAL; + + /* Retrieve the tag object */ + tag_obj = (struct tagged_object *)key; + + /* + * Check tag object header configuration + * and retrieve the tag object header configuration + */ + if (is_valid_header_conf(&tag_obj->header)) { + header = &tag_obj->header; + } else { dev_err(jrdev, "unable to get tag object header configuration\n"); - return ret; + return -EINVAL; } /* Check if the tag object header is a black key */ @@ -878,21 +887,21 @@ static int tk_skcipher_setkey(struct crypto_skcipher *skcipher, /* Retrieve the black key configuration */ get_key_conf(header, &ctx->cdata.key_real_len, + &ctx->cdata.keylen, &ctx->cdata.key_cmd_opt); - /* - * Retrieve the address of the data - * and size of the tagged object - */ - ret = get_tagged_data(ctx->cdata.key_virt, ctx->cdata.keylen, - &ctx->cdata.key_virt, &ctx->cdata.keylen); + /* Retrieve the address of the data of the tagged object */ + ctx->cdata.key_virt = &tag_obj->object; + + /* Validate key length for AES algorithms */ + ret = aes_check_keylen(ctx->cdata.key_real_len); if (ret) { - dev_err(jrdev, - "unable to get data from tagged object\n"); + crypto_skcipher_set_flags(skcipher, + CRYPTO_TFM_RES_BAD_KEY_LEN); return ret; } - return skcipher_setkey(skcipher, key, keylen, 0); + return skcipher_setkey(skcipher, NULL, 0, 0); } #endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API */ diff --git a/drivers/crypto/caam/caamkeyblob.c b/drivers/crypto/caam/caamkeyblob.c index 9ef30f5e7fef..5551f6725d79 100644 --- a/drivers/crypto/caam/caamkeyblob.c +++ b/drivers/crypto/caam/caamkeyblob.c @@ -210,8 +210,8 @@ int generate_black_key(struct device *dev, struct keyblob_info *info) u8 trusted_key, key_enc; u32 *desc = NULL; size_t black_key_length_req = 0; - dma_addr_t key_dma, black_key_dma; - u8 *tmp_key = NULL, *tmp_black_key = NULL; + dma_addr_t black_key_dma; + u8 *tmp_black_key = NULL; /* Validate device */ if (!dev) @@ -281,27 +281,17 @@ int generate_black_key(struct device *dev, struct keyblob_info *info) __func__, info->key_len, info->black_key, info->black_key_len); dev_dbg(dev, "req:%zu, key_enc: 0x%x]\n", black_key_length_req, key_enc); - if (not_random) { - /* Map input key, this will be sent to CAAM */ - if (map_write_data(dev, info->key, info->key_len, - &key_dma, &tmp_key)) { - dev_err(dev, "Unable to map input key\n"); - ret = -ENOMEM; - goto exit; - } - } - /* Map black key, this will be read from CAAM */ if (map_read_data(dev, black_key_length_req, &black_key_dma, &tmp_black_key)) { dev_err(dev, "Unable to map black key\n"); ret = -ENOMEM; - goto unmap_input_key; + goto exit; } /* Construct descriptor for black key */ if (not_random) - ret = cnstr_desc_black_key(&desc, key_dma, info->key_len, + ret = cnstr_desc_black_key(&desc, info->key, info->key_len, black_key_dma, info->black_key_len, key_enc, trusted_key); else @@ -338,11 +328,6 @@ int generate_black_key(struct device *dev, struct keyblob_info *info) unmap_read_write_data(dev, black_key_dma, tmp_black_key, black_key_length_req, DMA_FROM_DEVICE); -unmap_input_key: - if (not_random) - unmap_read_write_data(dev, key_dma, tmp_key, info->key_len, - DMA_TO_DEVICE); - exit: return ret; } @@ -374,10 +359,11 @@ int caam_blob_encap(struct device *dev, struct keyblob_info *info) int ret = 0; u32 *desc = NULL; size_t black_key_real_len = 0; + size_t blob_req_len = 0; u8 mem_type, color, key_enc, trusted_key; - dma_addr_t black_key_dma, key_mod_dma, blob_dma; - unsigned char *blob = info->blob + BLOB_HEADER_SIZE; - u8 *tmp_black_key = NULL, *tmp_key_mod = NULL, *tmp_blob = NULL; + dma_addr_t black_key_dma, blob_dma; + unsigned char *blob = info->blob; + u8 *tmp_black_key = NULL, *tmp_blob = NULL; /* Validate device */ if (!dev) @@ -393,7 +379,7 @@ int caam_blob_encap(struct device *dev, struct keyblob_info *info) trusted_key = (info->type >> TAG_OBJ_TK_OFFSET) & 0x1; /* Validate input data*/ - if (!info->black_key || !info->key_mod || !blob) + if (!info->key_mod || !blob) return -EINVAL; /* Validate object type - only JDKEK keys are supported */ @@ -417,12 +403,14 @@ int caam_blob_encap(struct device *dev, struct keyblob_info *info) /* Adapt the size of the black key */ black_key_real_len = info->black_key_len; + blob_req_len = CCM_BLACK_KEY_SIZE(info->key_len); + /* Check if the blob can be stored */ - if (info->blob_len < (black_key_real_len + BLOB_OVERHEAD)) + if (info->blob_len < (blob_req_len + BLOB_OVERHEAD)) return -EINVAL; /* Update the blob length */ - info->blob_len = black_key_real_len + BLOB_OVERHEAD; + info->blob_len = blob_req_len + BLOB_OVERHEAD; dev_dbg(dev, "%s processing: [black_key: %p (%zu) cnstr: %zu", __func__, info->black_key, info->black_key_len, @@ -446,26 +434,12 @@ int caam_blob_encap(struct device *dev, struct keyblob_info *info) return -ENOMEM; } - /* Map key modifier, this will be sent to CAAM */ - if (mem_type == DATA_GENMEM) { - if (map_write_data(dev, info->key_mod, info->key_mod_len, - &key_mod_dma, &tmp_key_mod)) { - dev_err(dev, "Unable to map key_mod for blob\n"); - ret = -ENOMEM; - goto unmap_black_key; - } - } else { - key_mod_dma = get_caam_dma_addr(info->key_mod); - if (!key_mod_dma) - return -ENOMEM; - } - /* Map blob, this will be read to CAAM */ if (mem_type == DATA_GENMEM) { if (map_read_data(dev, info->blob_len, &blob_dma, &tmp_blob)) { dev_err(dev, "Unable to map blob\n"); ret = -ENOMEM; - goto unmap_key_mod; + goto unmap_black_key; } } else { blob_dma = get_caam_dma_addr(info->blob); @@ -474,9 +448,9 @@ int caam_blob_encap(struct device *dev, struct keyblob_info *info) } /* Construct descriptor for blob encapsulation */ - ret = cnstr_desc_blob_encap(&desc, black_key_dma, black_key_real_len, + ret = cnstr_desc_blob_encap(&desc, black_key_dma, info->key_len, color, key_enc, trusted_key, mem_type, - key_mod_dma, info->key_mod_len, + info->key_mod, info->key_mod_len, blob_dma, info->blob_len); if (ret) { dev_err(dev, @@ -507,11 +481,6 @@ int caam_blob_encap(struct device *dev, struct keyblob_info *info) unmap_read_write_data(dev, blob_dma, tmp_blob, info->blob_len, DMA_FROM_DEVICE); -unmap_key_mod: - if (mem_type == DATA_GENMEM) - unmap_read_write_data(dev, key_mod_dma, tmp_key_mod, - info->key_mod_len, DMA_TO_DEVICE); - unmap_black_key: if (mem_type == DATA_GENMEM) unmap_read_write_data(dev, black_key_dma, tmp_black_key, @@ -544,9 +513,9 @@ int caam_blob_decap(struct device *dev, struct keyblob_info *info) u32 *desc = NULL; u8 mem_type, color, key_enc, trusted_key; size_t black_key_real_len; - dma_addr_t key_mod_dma, black_key_dma, blob_dma; - unsigned char *blob = info->blob + BLOB_HEADER_SIZE; - u8 *tmp_black_key = NULL, *tmp_key_mod = NULL, *tmp_blob = NULL; + dma_addr_t black_key_dma, blob_dma; + unsigned char *blob = info->blob + TAG_OVERHEAD_SIZE; + u8 *tmp_black_key = NULL, *tmp_blob = NULL; /* Validate device */ if (!dev) @@ -562,7 +531,7 @@ int caam_blob_decap(struct device *dev, struct keyblob_info *info) trusted_key = (info->type >> TAG_OBJ_TK_OFFSET) & 0x1; /* Validate input data*/ - if (!info->black_key || !info->key_mod || !blob) + if (!info->key_mod || !blob) return -EINVAL; dev_dbg(dev, "%s input: [blob: %p (%zu), mem_type: %x, color: %x", @@ -599,6 +568,30 @@ int caam_blob_decap(struct device *dev, struct keyblob_info *info) if (info->black_key_len < black_key_real_len) return -EINVAL; + /* + * Based on key encryption type (ecb or ccm), + * compute the black key size + */ + if (key_enc == KEY_COVER_ECB) + /* + * ECB-Black Key will be padded with zeros to make it a + * multiple of 16 bytes long before it is encrypted, + * and the resulting Black Key will be this length. + */ + black_key_real_len = ECB_BLACK_KEY_SIZE(info->key_len); + else if (key_enc == KEY_COVER_CCM) + /* + * CCM-Black Key will always be at least 12 bytes longer, + * since the encapsulation uses a 6-byte nonce and adds + * a 6-byte ICV. But first, the key is padded as necessary so + * that CCM-Black Key is a multiple of 8 bytes long. + */ + black_key_real_len = CCM_BLACK_KEY_SIZE(info->key_len); + + /* Check if there is enough space for black key */ + if (info->black_key_len < black_key_real_len) + return -EINVAL; + /* Update black key length with the one computed based on key_enc */ info->black_key_len = black_key_real_len; @@ -622,27 +615,13 @@ int caam_blob_decap(struct device *dev, struct keyblob_info *info) return -ENOMEM; } - /* Map key modifier, this will be sent to CAAM */ - if (mem_type == DATA_GENMEM) { - if (map_write_data(dev, info->key_mod, info->key_mod_len, - &key_mod_dma, &tmp_key_mod)) { - dev_err(dev, "Unable to map key_mod for blob decap\n"); - ret = -ENOMEM; - goto unmap_blob; - } - } else { - key_mod_dma = get_caam_dma_addr(info->key_mod); - if (!key_mod_dma) - return -ENOMEM; - } - /* Map black key, this will be read from CAAM */ if (mem_type == DATA_GENMEM) { if (map_read_data(dev, info->black_key_len, &black_key_dma, &tmp_black_key)) { dev_err(dev, "Unable to map black key for blob decap\n"); ret = -ENOMEM; - goto unmap_key_mod; + goto unmap_blob; } } else { black_key_dma = get_caam_dma_addr(info->black_key); @@ -651,8 +630,8 @@ int caam_blob_decap(struct device *dev, struct keyblob_info *info) } ret = cnstr_desc_blob_decap(&desc, blob_dma, info->blob_len, - key_mod_dma, info->key_mod_len, - black_key_dma, black_key_real_len, + info->key_mod, info->key_mod_len, + black_key_dma, info->key_len, color, key_enc, trusted_key, mem_type); if (ret) { dev_err(dev, @@ -680,11 +659,6 @@ int caam_blob_decap(struct device *dev, struct keyblob_info *info) unmap_read_write_data(dev, black_key_dma, tmp_black_key, info->black_key_len, DMA_FROM_DEVICE); -unmap_key_mod: - if (mem_type == DATA_GENMEM) - unmap_read_write_data(dev, key_mod_dma, tmp_key_mod, - info->key_mod_len, DMA_TO_DEVICE); - unmap_blob: if (mem_type == DATA_GENMEM) unmap_read_write_data(dev, blob_dma, tmp_blob, diff --git a/drivers/crypto/caam/caamkeyblob.h b/drivers/crypto/caam/caamkeyblob.h index a1b21b95072f..495b74c290d8 100644 --- a/drivers/crypto/caam/caamkeyblob.h +++ b/drivers/crypto/caam/caamkeyblob.h @@ -14,7 +14,7 @@ /* * Minimum key size to be used is 16 bytes and maximum key size fixed * is 64 bytes. - * Blob size to be kept is Maximum key size + blob header added by CAAM. + * Blob size to be kept is Maximum key size + tag object header added by CAAM. */ #define MIN_KEY_SIZE 16 @@ -23,9 +23,14 @@ #define MAX_BLACK_KEY_SIZE (MAX_KEY_SIZE + CCM_OVERHEAD +\ TAG_OVERHEAD_SIZE) -#define BLOB_HEADER_SIZE 4 -#define MAX_BLOB_SIZE (MAX_KEY_SIZE + BLOB_OVERHEAD +\ - BLOB_HEADER_SIZE) +/* + * For blobs a randomly-generated, 256-bit blob key is used to + * encrypt the data using the AES-CCM cryptographic algorithm. + * Therefore, blob size is max key size, CCM_OVERHEAD, blob header + * added by CAAM and the tagged object header size. + */ +#define MAX_BLOB_SIZE (MAX_KEY_SIZE + CCM_OVERHEAD +\ + BLOB_OVERHEAD + TAG_OVERHEAD_SIZE) /* Key modifier for CAAM blobs, used as a revision number */ static const char caam_key_modifier[KEYMOD_SIZE_GM] = { diff --git a/drivers/crypto/caam/caamkeyblob_desc.c b/drivers/crypto/caam/caamkeyblob_desc.c index a65cc46d7130..7b570fb585e3 100644 --- a/drivers/crypto/caam/caamkeyblob_desc.c +++ b/drivers/crypto/caam/caamkeyblob_desc.c @@ -8,7 +8,7 @@ #include "caamkeyblob_desc.h" /* Size of tmp buffer for descriptor const. */ -#define INITIAL_DESCSZ 16 +#define INITIAL_DESCSZ 64 /* * Construct a black key conversion job descriptor @@ -19,7 +19,7 @@ * @desc : Pointer to a pointer to the descriptor generated by this * function. Caller will be responsible to kfree() this * descriptor after execution. - * @key : Physical pointer to the plaintext, which will also hold + * @key : Pointer to the plaintext, which will also hold * the result. Since encryption occurs in place, caller must * ensure that the space is large enough to accommodate the * blackened key @@ -33,12 +33,13 @@ * * Return : '0' on success, error code otherwise */ -int cnstr_desc_black_key(u32 **desc, dma_addr_t key, size_t key_len, +int cnstr_desc_black_key(u32 **desc, char *key, size_t key_len, dma_addr_t black_key, size_t black_key_len, u8 key_enc, u8 trusted_key) { u32 *tdesc, tmpdesc[INITIAL_DESCSZ]; - u16 dsize, idx; + u16 dsize; + u32 bk_store; u32 key_length_for_desc = key_len; /* Trusted key not supported */ @@ -46,7 +47,8 @@ int cnstr_desc_black_key(u32 **desc, dma_addr_t key, size_t key_len, return -ENOTSUPP; memset(tmpdesc, 0, sizeof(tmpdesc)); - idx = 1; + + init_job_desc(tmpdesc, 0); /* * KEY commands seems limited to 32 bytes, so we should use the load @@ -61,30 +63,23 @@ int cnstr_desc_black_key(u32 **desc, dma_addr_t key, size_t key_len, */ /* Load key to class 1 key register */ - tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_1_CCB | LDST_SRCDST_BYTE_KEY | - key_length_for_desc; - tmpdesc[idx++] = (uintptr_t)key; + append_load_as_imm(tmpdesc, (void *)key, key_length_for_desc, + LDST_CLASS_1_CCB | LDST_SRCDST_BYTE_KEY); + /* Load the size of the key */ - tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_1_CCB | LDST_IMM | - LDST_SRCDST_WORD_KEYSZ_REG | - sizeof(key_length_for_desc); - tmpdesc[idx++] = key_length_for_desc; + append_load_imm_u32(tmpdesc, key_length_for_desc, LDST_CLASS_1_CCB | + LDST_IMM | LDST_SRCDST_WORD_KEYSZ_REG); /* ...and write back out via FIFO store*/ - tmpdesc[idx] = CMD_FIFO_STORE | CLASS_1 | - (black_key_len & KEY_LENGTH_MASK); - - /* Plus account for ECB/CCM option in FIFO_STORE */ + bk_store = CLASS_1; if (key_enc == KEY_COVER_ECB) - tmpdesc[idx] |= FIFOST_TYPE_KEY_KEK; + bk_store |= FIFOST_TYPE_KEY_KEK; else - tmpdesc[idx] |= FIFOST_TYPE_KEY_CCM_JKEK; + bk_store |= FIFOST_TYPE_KEY_CCM_JKEK; - idx++; - tmpdesc[idx++] = (uintptr_t)black_key; + /* Save the key as black key in memory */ + append_fifo_store(tmpdesc, black_key, black_key_len, bk_store); - /* Finish off the job header */ - tmpdesc[0] = CMD_DESC_HDR | HDR_ONE | (idx & HDR_DESCLEN_MASK); dsize = desc_bytes(&tmpdesc); /* Now allocate execution buffer and coat it with executable */ @@ -131,7 +126,7 @@ int cnstr_desc_random_black_key(u32 **desc, size_t key_len, memset(tmpdesc, 0, sizeof(tmpdesc)); - init_job_desc(tmpdesc, CMD_DESC_HDR); + init_job_desc(tmpdesc, 0); /* Prepare RNG */ append_operation(tmpdesc, OP_ALG_ALGSEL_RNG | OP_TYPE_CLASS1_ALG); @@ -199,7 +194,7 @@ EXPORT_SYMBOL(cnstr_desc_random_black_key); * @mem_type : Determine if encapsulated blob should be a secure memory * blob (DATA_SECMEM), with partition data embedded with key * material, or a general memory blob (DATA_GENMEM). - * @key_mod : Physical pointer to a key modifier, which must reside in a + * @key_mod : Pointer to a key modifier, which must reside in a * contiguous piece of memory. Modifier will be assumed to be * 8 bytes long for a blob of type DATA_SECMEM, or 16 bytes * long for a blob of type DATA_GENMEM @@ -247,19 +242,21 @@ EXPORT_SYMBOL(cnstr_desc_random_black_key); * format=normal */ int cnstr_desc_blob_encap(u32 **desc, dma_addr_t black_key, - size_t black_key_len, u8 keycolor, u8 key_enc, - u8 trusted_key, u8 mem_type, dma_addr_t key_mod, + size_t key_len, u8 keycolor, u8 key_enc, + u8 trusted_key, u8 mem_type, const void *key_mod, size_t key_mod_len, dma_addr_t blob, size_t blob_len) { u32 *tdesc, tmpdesc[INITIAL_DESCSZ]; - u16 dsize, idx; + u16 dsize; + u32 bk_store; /* Trusted key not supported */ if (trusted_key != UNTRUSTED_KEY) return -ENOTSUPP; memset(tmpdesc, 0, sizeof(tmpdesc)); - idx = 1; + + init_job_desc(tmpdesc, 0); /* * Key modifier works differently for secure/general memory blobs @@ -267,43 +264,38 @@ int cnstr_desc_blob_encap(u32 **desc, dma_addr_t black_key, * within the blob if a secure memory blob is requested */ if (mem_type == DATA_SECMEM) - tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB | - LDST_SRCDST_BYTE_KEY | - ((12 << LDST_OFFSET_SHIFT) & LDST_OFFSET_MASK) - | (key_mod_len & LDST_LEN_MASK); + append_load_as_imm(tmpdesc, key_mod, key_mod_len, + LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_KEY | + ((12 << LDST_OFFSET_SHIFT) & + LDST_OFFSET_MASK)); else /* is general memory blob */ - tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB - | LDST_SRCDST_BYTE_KEY - | (key_mod_len & LDST_LEN_MASK); + append_load_as_imm(tmpdesc, key_mod, key_mod_len, + LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_KEY); - tmpdesc[idx++] = (u32)key_mod; + /* Input data, should be somewhere in secure memory */ + append_seq_in_ptr_intlen(tmpdesc, black_key, key_len, 0); /* * Encapsulation output must include space for blob key encryption * key and MAC tag */ - tmpdesc[idx++] = CMD_SEQ_OUT_PTR | (black_key_len + BLOB_OVERHEAD); - tmpdesc[idx++] = (u32)blob; - - /* Input data, should be somewhere in secure memory */ - tmpdesc[idx++] = CMD_SEQ_IN_PTR | black_key_len; - tmpdesc[idx++] = (uintptr_t)black_key; - - /* Set blob encap, then color */ - tmpdesc[idx] = CMD_OPERATION | OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB; + append_seq_out_ptr_intlen(tmpdesc, blob, CCM_BLACK_KEY_SIZE(key_len) + + BLOB_OVERHEAD, 0); + bk_store = OP_PCLID_BLOB; if (mem_type == DATA_SECMEM) - tmpdesc[idx] |= OP_PCL_BLOB_PTXT_SECMEM; + bk_store |= OP_PCL_BLOB_PTXT_SECMEM; if (key_enc == KEY_COVER_CCM) - tmpdesc[idx] |= OP_PCL_BLOB_EKT; + bk_store |= OP_PCL_BLOB_EKT; /* An input black key cannot be stored in a red blob */ if (keycolor == BLACK_KEY) - tmpdesc[idx] |= OP_PCL_BLOB_BLACK; + bk_store |= OP_PCL_BLOB_BLACK; + + /* Set blob encap, then color */ + append_operation(tmpdesc, OP_TYPE_ENCAP_PROTOCOL | bk_store); - idx++; - tmpdesc[0] = CMD_DESC_HDR | HDR_ONE | (idx & HDR_DESCLEN_MASK); dsize = desc_bytes(&tmpdesc); tdesc = kmemdup(tmpdesc, dsize, GFP_KERNEL | GFP_DMA); @@ -332,7 +324,7 @@ EXPORT_SYMBOL(cnstr_desc_blob_encap); * be decapsulated. Blob must reside in a contiguous memory * segment. * @blob_len : Size of the blob buffer to be decapsulated. - * @key_mod : Physical pointer to a key modifier, which must reside in a + * @key_mod : Pointer to a key modifier, which must reside in a * contiguous piece of memory. Modifier will be assumed to be * 8 bytes long for a blob of type DATA_SECMEM, or 16 bytes * long for a blob of type DATA_GENMEM @@ -386,54 +378,53 @@ EXPORT_SYMBOL(cnstr_desc_blob_encap); * format=normal */ int cnstr_desc_blob_decap(u32 **desc, dma_addr_t blob, size_t blob_len, - dma_addr_t key_mod, size_t key_mod_len, - dma_addr_t black_key, size_t black_key_len, + const void *key_mod, size_t key_mod_len, + dma_addr_t black_key, size_t plaintext_len, u8 keycolor, u8 key_enc, u8 trusted_key, u8 mem_type) { u32 *tdesc, tmpdesc[INITIAL_DESCSZ]; - u16 dsize, idx; + u16 dsize; + u32 bk_store; /* Trusted key not supported */ if (trusted_key != UNTRUSTED_KEY) return -ENOTSUPP; memset(tmpdesc, 0, sizeof(tmpdesc)); - idx = 1; + + init_job_desc(tmpdesc, 0); /* Load key modifier */ if (mem_type == DATA_SECMEM) - tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB | - LDST_SRCDST_BYTE_KEY | - ((12 << LDST_OFFSET_SHIFT) & LDST_OFFSET_MASK) - | (key_mod_len & LDST_LEN_MASK); + append_load_as_imm(tmpdesc, key_mod, key_mod_len, + LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_KEY | + ((12 << LDST_OFFSET_SHIFT) & + LDST_OFFSET_MASK)); else /* is general memory blob */ - tmpdesc[idx++] = CMD_LOAD - | LDST_CLASS_2_CCB - | LDST_SRCDST_BYTE_KEY - | (key_mod_len & LDST_LEN_MASK); + append_load_as_imm(tmpdesc, key_mod, key_mod_len, + LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_KEY); - tmpdesc[idx++] = (u32)key_mod; + /* Compensate blob header + MAC tag over size of encapsulated secret */ + append_seq_in_ptr_intlen(tmpdesc, blob, plaintext_len + BLOB_OVERHEAD, + 0); - /* Compensate BKEK + MAC tag over size of encapsulated secret */ - tmpdesc[idx++] = CMD_SEQ_IN_PTR | blob_len; - tmpdesc[idx++] = (u32)blob; - tmpdesc[idx++] = CMD_SEQ_OUT_PTR | black_key_len; - tmpdesc[idx++] = (uintptr_t)black_key; + append_seq_out_ptr_intlen(tmpdesc, black_key, plaintext_len, 0); /* Decapsulate from secure memory partition to black blob */ - tmpdesc[idx] = CMD_OPERATION | OP_TYPE_DECAP_PROTOCOL | OP_PCLID_BLOB; - + bk_store = OP_PCLID_BLOB; if (mem_type == DATA_SECMEM) - tmpdesc[idx] |= OP_PCL_BLOB_PTXT_SECMEM; + bk_store |= OP_PCL_BLOB_PTXT_SECMEM; if (key_enc == KEY_COVER_CCM) - tmpdesc[idx] |= OP_PCL_BLOB_EKT; + bk_store |= OP_PCL_BLOB_EKT; + /* An input black key cannot be stored in a red blob */ if (keycolor == BLACK_KEY) - tmpdesc[idx] |= OP_PCL_BLOB_BLACK; + bk_store |= OP_PCL_BLOB_BLACK; + + /* Set blob encap, then color */ + append_operation(tmpdesc, OP_TYPE_DECAP_PROTOCOL | bk_store); - idx++; - tmpdesc[0] = CMD_DESC_HDR | HDR_ONE | (idx & HDR_DESCLEN_MASK); dsize = desc_bytes(&tmpdesc); tdesc = kmemdup(tmpdesc, dsize, GFP_KERNEL | GFP_DMA); diff --git a/drivers/crypto/caam/caamkeyblob_desc.h b/drivers/crypto/caam/caamkeyblob_desc.h index 1cbc8126a847..0affbb184ee4 100644 --- a/drivers/crypto/caam/caamkeyblob_desc.h +++ b/drivers/crypto/caam/caamkeyblob_desc.h @@ -77,7 +77,7 @@ static inline int secret_size_in_ccm_black_key(int key_size) #define KEYMOD_SIZE_GM 16 /* Create job descriptor to cover key */ -int cnstr_desc_black_key(u32 **desc, dma_addr_t key, size_t key_len, +int cnstr_desc_black_key(u32 **desc, char *key, size_t key_len, dma_addr_t black_key, size_t black_key_len, u8 key_enc, u8 trusted_key); @@ -89,12 +89,12 @@ int cnstr_desc_random_black_key(u32 **desc, size_t key_len, /* Encapsulate data in a blob */ int cnstr_desc_blob_encap(u32 **desc, dma_addr_t black_key, size_t black_key_len, u8 color, u8 key_enc, - u8 trusted_key, u8 mem_type, dma_addr_t key_mod, + u8 trusted_key, u8 mem_type, const void *key_mod, size_t key_mod_len, dma_addr_t blob, size_t blob_len); /* Decapsulate data from a blob */ int cnstr_desc_blob_decap(u32 **desc, dma_addr_t blob, size_t blob_len, - dma_addr_t key_mod, size_t key_mod_len, + const void *key_mod, size_t key_mod_len, dma_addr_t black_key, size_t black_key_len, u8 keycolor, u8 key_enc, u8 trusted_key, u8 mem_type); diff --git a/drivers/crypto/caam/caamkeygen.c b/drivers/crypto/caam/caamkeygen.c index 55cabbf0d1d1..04db6e044b8a 100644 --- a/drivers/crypto/caam/caamkeygen.c +++ b/drivers/crypto/caam/caamkeygen.c @@ -22,42 +22,54 @@ static long caam_keygen_ioctl(struct file *file, unsigned int cmd, unsigned long arg); /** - * tag_black_key - Tag a black key with a tag object header. + * tag_black_obj - Tag a black object (key/blob) with a tag object header. * * @info : keyblob_info structure, which contains - * the black key, obtained from CAAM, + * the black key/blob, obtained from CAAM, * that needs to be tagged - * @black_key_max_len : The maximum size of a black key + * @black_max_len : The maximum size of the black object (blob/key) + * @blob : Used to determine if it's a blob or key object * * Return : '0' on success, error code otherwise */ -static int tag_black_key(struct keyblob_info *info, size_t black_key_max_len) +static int tag_black_obj(struct keyblob_info *info, size_t black_max_len, + bool blob) { struct header_conf tag; u32 type; int ret; - u32 size_tagged = black_key_max_len; + u32 size_tagged = black_max_len; if (!info) return -EINVAL; type = info->type; - /* Prepare the tag */ - init_tag_object_header(&tag, 0, type, info->black_key_len); - - /* Set the tag */ - ret = set_tag_object_header_conf(&tag, info->black_key, - info->black_key_len, &size_tagged); + /* Prepare and set the tag */ + if (blob) { + init_tag_object_header(&tag, 0, type, info->key_len, + info->blob_len); + ret = set_tag_object_header_conf(&tag, info->blob, + info->blob_len, + &size_tagged); + } else { + init_tag_object_header(&tag, 0, type, info->key_len, + info->black_key_len); + ret = set_tag_object_header_conf(&tag, info->black_key, + info->black_key_len, + &size_tagged); + } if (ret) return ret; /* Update the size of the black key tagged */ - info->black_key_len = size_tagged; + if (blob) + info->blob_len = size_tagged; + else + info->black_key_len = size_tagged; return ret; } - /** * send_err_msg - Send the error message from kernel to user-space * @@ -132,6 +144,7 @@ static int validate_input(struct caam_keygen_cmd *key_crt, unsigned long arg, bool random = false; int ret = 0; u32 tmp_len = 0; + char null_ch = 0; /* * So far, we only support Black keys, encrypted with JDKEK, @@ -156,13 +169,25 @@ static int validate_input(struct caam_keygen_cmd *key_crt, unsigned long arg, * the Key Mode and Key Value */ if (create_key_op) { + /* + * Validate arguments received from user. + * These must be at least 1 since + * they have null terminator. + */ + if (key_crt->key_enc_len < 1 || key_crt->key_mode_len < 1 || + key_crt->key_value_len < 1) { + msg = "Invalid arguments.\n"; + send_err_msg(msg, u64_to_user_ptr(key_crt->blob), + key_crt->blob_len); + return -EFAULT; + } /* * Allocate memory for temporary buffer used to * get the user arguments from user-space */ tmp_size = max_t(size_t, key_crt->key_enc_len, max_t(size_t, key_crt->key_mode_len, - key_crt->key_value_len)); + key_crt->key_value_len)) + 1; tmp = kmalloc(tmp_size, GFP_KERNEL); if (!tmp) { msg = "Unable to allocate memory for temporary buffer.\n"; @@ -170,6 +195,8 @@ static int validate_input(struct caam_keygen_cmd *key_crt, unsigned long arg, key_crt->blob_len); return -ENOMEM; } + /* Add null terminator */ + tmp[tmp_size - 1] = null_ch; /* * Validate and set, in type, the Encrypted Key Type * given from user-space. @@ -326,16 +353,18 @@ static int keygen_create_keyblob(struct keyblob_info *info) } /* Tag the black key so it can be passed to CAAM Crypto API */ - ret = tag_black_key(info, sizeof(info->black_key)); + ret = tag_black_obj(info, sizeof(info->black_key), false); if (ret) { dev_err(jrdev, "Black key tagging failed: %d\n", ret); goto free_jr; } - /* Add the object type as a header to the blob */ - memcpy(info->blob, &info->type, BLOB_HEADER_SIZE); - /* Update blob length with the new added header */ - info->blob_len += BLOB_HEADER_SIZE; + /* Tag the black blob so it can be passed to CAAM Crypto API */ + ret = tag_black_obj(info, sizeof(info->blob), true); + if (ret) { + dev_err(jrdev, "Black blob tagging failed: %d\n", ret); + goto free_jr; + } free_jr: caam_jr_free(jrdev); @@ -355,6 +384,8 @@ static int keygen_import_key(struct keyblob_info *info) { int ret = 0; struct device *jrdev; + struct header_conf *header; + struct tagged_object *tag_obj; /* Allocate CAAM Job Ring for operation to be performed from CAAM */ jrdev = caam_jr_alloc(); @@ -371,11 +402,53 @@ static int keygen_import_key(struct keyblob_info *info) DUMP_PREFIX_ADDRESS, 16, 4, info->blob, info->blob_len, 1); - /* Get object type from blob header */ - memcpy(&info->type, info->blob, BLOB_HEADER_SIZE); + /* Check if one can retrieve the tag object header configuration */ + if (info->blob_len <= TAG_OVERHEAD_SIZE) { + dev_err(jrdev, "Invalid blob length\n"); + ret = -EINVAL; + goto free_jr; + } + + /* Retrieve the tag object */ + tag_obj = (struct tagged_object *)info->blob; + + /* + * Check tag object header configuration + * and retrieve the tag object header configuration + */ + if (is_valid_header_conf(&tag_obj->header)) { + header = &tag_obj->header; + } else { + dev_err(jrdev, + "Unable to get tag object header configuration for blob\n"); + ret = -EINVAL; + goto free_jr; + } + + info->key_len = header->red_key_len; + + /* Validate the red key size extracted from blob */ + if (info->key_len < MIN_KEY_SIZE || info->key_len > MAX_KEY_SIZE) { + dev_err(jrdev, + "Invalid red key length extracted from blob, expected values are between 16 and 64 bytes\n"); + ret = -EINVAL; + goto free_jr; + } + + info->type = header->type; /* Update blob length by removing the header size */ - info->blob_len -= BLOB_HEADER_SIZE; + info->blob_len -= TAG_OVERHEAD_SIZE; + + /* + * Check the received, from user, blob length + * with the one from tag header + */ + if (info->blob_len != header->obj_len) { + dev_err(jrdev, "Mismatch between received blob length and the one from tag header\n"); + ret = -EINVAL; + goto free_jr; + } /* * Decapsulate the blob into a black key, @@ -388,7 +461,7 @@ static int keygen_import_key(struct keyblob_info *info) } /* Tag the black key so it can be passed to CAAM Crypto API */ - ret = tag_black_key(info, sizeof(info->black_key)); + ret = tag_black_obj(info, sizeof(info->black_key), false); if (ret) dev_err(jrdev, "Black key tagging failed: %d\n", ret); diff --git a/drivers/crypto/caam/tag_object.c b/drivers/crypto/caam/tag_object.c index 25d32b9651f2..53f70129e630 100644 --- a/drivers/crypto/caam/tag_object.c +++ b/drivers/crypto/caam/tag_object.c @@ -68,53 +68,25 @@ bool is_valid_header_conf(const struct header_conf *header) { return (header->_magic_number == TAG_OBJECT_MAGIC); } - -/** - * get_tag_object_header_conf - Retrieve the address of tag object - * header configuration - * @buffer: Buffer containing the tag object - * @size: The size of buffer - * @header: Returned tag object header configuration - * - * Return: '0' on success, error code otherwise - */ -int get_tag_object_header_conf(const void *buffer, size_t size, - struct header_conf **header) -{ - bool valid; - - /* Retrieve the tag object */ - struct tagged_object *tag_obj = (struct tagged_object *)buffer; - - /* Check if one can retrieve the tag object header configuration */ - if (size < TAG_OVERHEAD_SIZE) - return -EINVAL; - - /* Check tag object header configuration */ - valid = is_valid_header_conf(&tag_obj->header); - - /* Retrieve the tag object header configuration address */ - *header = &tag_obj->header; - - return valid ? 0 : -EINVAL; -} -EXPORT_SYMBOL(get_tag_object_header_conf); +EXPORT_SYMBOL(is_valid_header_conf); /** * get_key_conf - Retrieve the key configuration, * meaning the length of the black key and * the KEY command parameters needed for CAAM * @header: The tag object header configuration - * @real_len: Key length + * @red_key_len: Red key length + * @obj_len: Black/Red key/blob length * @load_param: Load parameters for KEY command: * - indicator for encrypted keys: plaintext or black * - indicator for encryption mode: AES-ECB or AES-CCM * - indicator for encryption keys: JDKEK or TDKEK */ void get_key_conf(const struct header_conf *header, - u32 *real_len, u32 *load_param) + u32 *red_key_len, u32 *obj_len, u32 *load_param) { - *real_len = header->real_len; + *red_key_len = header->red_key_len; + *obj_len = header->obj_len; /* Based on the color of the key, set key encryption bit (ENC) */ *load_param = ((header->type >> TAG_OBJ_COLOR_OFFSET) & TAG_OBJ_COLOR_MASK) << KEY_ENC_OFFSET; @@ -129,36 +101,6 @@ void get_key_conf(const struct header_conf *header, } EXPORT_SYMBOL(get_key_conf); -/** - * get_tagged_data - Retrieve the address of the data and size - * of the tagged object - * @tagged_object: Pointer to tag object - * @tagged_object_size: The tagged object size - * @data: Returned the address of the data from - * the tagged object - * @data_size: Returned the size of the data from the - * tagged object - * - * Return: '0' on success, error code otherwise - */ -int get_tagged_data(const void *tagged_object, size_t tagged_object_size, - const void **data, u32 *data_size) -{ - /* Retrieve the tag object */ - struct tagged_object *tag_obj = (struct tagged_object *)tagged_object; - /* Check if one can retrieve the data from the tagged object */ - if (tagged_object_size < TAG_OVERHEAD_SIZE) - return -EINVAL; - - /* Retrieve the address of the data/object from the tagged object */ - *data = &tag_obj->object; - /* Retrieve the size of the data from the tagged object */ - *data_size = tagged_object_size - TAG_OVERHEAD_SIZE; - - return 0; -} -EXPORT_SYMBOL(get_tagged_data); - /** * init_tag_object_header - Initialize the tag object header by setting up * the TAG_OBJECT_MAGIC number, tag object version, @@ -166,15 +108,17 @@ EXPORT_SYMBOL(get_tagged_data); * @header: The header configuration to initialize * @version: The tag object version * @type: The tag object type - * @len: The object (actual data) length + * @red_key_len: The red key length + * @obj_len: The object (actual data) length */ void init_tag_object_header(struct header_conf *header, u32 version, - u32 type, size_t len) + u32 type, size_t red_key_len, size_t obj_len) { header->_magic_number = TAG_OBJECT_MAGIC; header->version = version; header->type = type; - header->real_len = len; + header->red_key_len = red_key_len; + header->obj_len = obj_len; } EXPORT_SYMBOL(init_tag_object_header); diff --git a/drivers/crypto/caam/tag_object.h b/drivers/crypto/caam/tag_object.h index fea460d151ef..6c840c30ce57 100644 --- a/drivers/crypto/caam/tag_object.h +++ b/drivers/crypto/caam/tag_object.h @@ -17,9 +17,9 @@ * 0x4f = 'O' */ #define TAG_OBJECT_MAGIC 0x5461674f -#define TAG_MIN_SIZE (2 * sizeof(struct header_conf)) #define TAG_OVERHEAD_SIZE sizeof(struct header_conf) - +#define MIN_KEY_SIZE 16 +#define TAG_MIN_SIZE (MIN_KEY_SIZE + TAG_OVERHEAD_SIZE) /* * Tag object type is a bitfield: * @@ -64,13 +64,17 @@ * @_magic_number : A magic number to identify the structure * @version : The version of the data contained (e.g. tag object) * @type : The type of data contained (e.g. black key, blob, etc.) - * @real_len : Length of the object to be loaded by CAAM + * @red_key_len : Length of the red key to be loaded by CAAM (for key + * generation or blob encapsulation) + * @obj_len : The total length of the (black/red) object (key/blob), + * after encryption/encapsulation */ struct header_conf { u32 _magic_number; u32 version; u32 type; - u32 real_len; + u32 red_key_len; + u32 obj_len; }; /** @@ -95,17 +99,11 @@ bool is_black_key(const struct header_conf * const header); bool is_valid_header_conf(const struct header_conf *header); -int get_tag_object_header_conf(const void *buffer, size_t buffer_size, - struct header_conf **header); - void get_key_conf(const struct header_conf *header, - u32 *real_len, u32 *load_param); - -int get_tagged_data(const void *buffer, size_t buffer_size, - const void **data, u32 *data_size); + u32 *red_key_len, u32 *obj_len, u32 *load_param); void init_tag_object_header(struct header_conf *header, u32 version, - u32 type, size_t len); + u32 type, size_t red_key_len, size_t obj_len); int set_tag_object_header_conf(const struct header_conf *header, void *buffer, size_t obj_size, u32 *to_size); diff --git a/drivers/crypto/mxs-dcp.c b/drivers/crypto/mxs-dcp.c index 871a8b028c49..21132ef37e4b 100644 --- a/drivers/crypto/mxs-dcp.c +++ b/drivers/crypto/mxs-dcp.c @@ -16,6 +16,10 @@ #include #include +#ifdef CONFIG_PM_SLEEP +#include +#endif + #include #include #include @@ -122,7 +126,10 @@ struct dcp_export_state { * design of Linux Crypto API. */ static struct dcp *global_sdcp; - +#ifdef CONFIG_PM_SLEEP +static uint32_t ctrl_bak; +static int dcp_vmi_irq_bak, dcp_irq_bak; +#endif /* DCP register layout. */ #define MXS_DCP_CTRL 0x00 #define MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES (1 << 23) @@ -399,9 +406,15 @@ static int dcp_chan_thread_aes(void *data) int ret; +#ifdef CONFIG_PM_SLEEP + set_freezable(); +#endif while (!kthread_should_stop()) { set_current_state(TASK_INTERRUPTIBLE); +#ifdef CONFIG_PM_SLEEP + try_to_freeze(); +#endif spin_lock(&sdcp->lock[chan]); backlog = crypto_get_backlog(&sdcp->queue[chan]); arq = crypto_dequeue_request(&sdcp->queue[chan]); @@ -438,6 +451,10 @@ static int mxs_dcp_block_fallback(struct ablkcipher_request *req, int enc) skcipher_request_set_crypt(subreq, req->src, req->dst, req->nbytes, req->info); +#ifdef CONFIG_PM_SLEEP + set_freezable(); + try_to_freeze(); +#endif if (enc) ret = crypto_skcipher_encrypt(subreq); else @@ -697,9 +714,15 @@ static int dcp_chan_thread_sha(void *data) struct crypto_async_request *arq; int ret; +#ifdef CONFIG_PM_SLEEP + set_freezable(); +#endif while (!kthread_should_stop()) { set_current_state(TASK_INTERRUPTIBLE); +#ifdef CONFIG_PM_SLEEP + try_to_freeze(); +#endif spin_lock(&sdcp->lock[chan]); backlog = crypto_get_backlog(&sdcp->queue[chan]); arq = crypto_dequeue_request(&sdcp->queue[chan]); @@ -982,6 +1005,49 @@ static irqreturn_t mxs_dcp_irq(int irq, void *context) return IRQ_HANDLED; } +#ifdef CONFIG_PM_SLEEP +static int mxs_dcp_resume(struct device *dev) +{ + struct dcp *sdcp = global_sdcp; + int ret; + + /* Restart the DCP block */ + ret = stmp_reset_block(sdcp->base); + if (ret) { + dev_err(dev, "Failed reset\n"); + clk_disable_unprepare(sdcp->dcp_clk); + return ret; + } + + /* Restore control register */ + writel(ctrl_bak, sdcp->base + MXS_DCP_CTRL); + /* Enable all DCP DMA channels */ + writel(MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK, + sdcp->base + MXS_DCP_CHANNELCTRL); + + /* Re-enable DCP interrupts */ + enable_irq(dcp_irq_bak); + enable_irq(dcp_vmi_irq_bak); + + return 0; +} + +static int mxs_dcp_suspend(struct device *dev) +{ + struct dcp *sdcp = global_sdcp; + + /* Backup control register */ + ctrl_bak = readl(sdcp->base + MXS_DCP_CTRL); + /* Temporarily disable DCP interrupts */ + disable_irq(dcp_irq_bak); + disable_irq(dcp_vmi_irq_bak); + + return 0; +} + +SIMPLE_DEV_PM_OPS(mxs_dcp_pm_ops, mxs_dcp_suspend, mxs_dcp_resume); +#endif + static int mxs_dcp_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1001,7 +1067,10 @@ static int mxs_dcp_probe(struct platform_device *pdev) dcp_irq = platform_get_irq(pdev, 1); if (dcp_irq < 0) return dcp_irq; - +#ifdef CONFIG_PM_SLEEP + dcp_vmi_irq_bak = dcp_vmi_irq; + dcp_irq_bak = dcp_irq; +#endif sdcp = devm_kzalloc(dev, sizeof(*sdcp), GFP_KERNEL); if (!sdcp) return -ENOMEM; @@ -1193,6 +1262,9 @@ static struct platform_driver mxs_dcp_driver = { .driver = { .name = "mxs-dcp", .of_match_table = mxs_dcp_dt_ids, +#ifdef CONFIG_PM_SLEEP + .pm = &mxs_dcp_pm_ops +#endif }, }; diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c index f902de72e538..26b53806a0c0 100644 --- a/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c +++ b/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c @@ -268,8 +268,8 @@ cdns_dp_bridge_mode_valid(struct drm_bridge *bridge, if (mode->clock > 594000) return MODE_CLOCK_HIGH; - /* 4096x2160 is not supported now */ - if (mode->hdisplay > 3840) + /* 5120 x 2160 is the maximum supported resulution */ + if (mode->hdisplay > 5120) return MODE_BAD_HVALUE; if (mode->vdisplay > 2160) diff --git a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c index c1cd5aaf46bf..c468885a594d 100644 --- a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c +++ b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c @@ -382,13 +382,16 @@ cdns_hdmi_bridge_mode_valid(struct drm_bridge *bridge, if (mode->clock > 594000) return MODE_CLOCK_HIGH; - /* 4096x2160 is not supported */ - if (mode->hdisplay > 3840 || mode->vdisplay > 2160) + /* 5120 x 2160 is the maximum supported resolution */ + if (mode->hdisplay > 5120 || mode->vdisplay > 2160) return MODE_BAD_HVALUE; - vic = drm_match_cea_mode(mode); - if (vic == 0) - return MODE_BAD; + /* imx8mq-hdmi does not support non CEA modes */ + if (!strncmp("imx8mq-hdmi", mhdp->plat_data->plat_name, 11)) { + vic = drm_match_cea_mode(mode); + if (vic == 0) + return MODE_BAD; + } mhdp->valid_mode = mode; ret = cdns_mhdp_plat_call(mhdp, phy_video_valid); diff --git a/drivers/gpu/drm/imx/dcss/dcss-crtc.c b/drivers/gpu/drm/imx/dcss/dcss-crtc.c index bb468a02ae03..d92143cb5565 100644 --- a/drivers/gpu/drm/imx/dcss/dcss-crtc.c +++ b/drivers/gpu/drm/imx/dcss/dcss-crtc.c @@ -155,11 +155,25 @@ static void dcss_crtc_atomic_disable(struct drm_crtc *crtc, pm_runtime_put_sync(dcss->dev); } +static enum drm_mode_status dcss_crtc_mode_valid(struct drm_crtc *crtc, + const struct drm_display_mode *mode) +{ + /* + * From DCSS perspective, dissallow any mode higher than + * 3840x2160 or 2160x3840. + */ + if (mode->hdisplay * mode->vdisplay > 3840 * 2160) + return MODE_BAD; + + return MODE_OK; +} + static const struct drm_crtc_helper_funcs dcss_helper_funcs = { .atomic_begin = dcss_crtc_atomic_begin, .atomic_flush = dcss_crtc_atomic_flush, .atomic_enable = dcss_crtc_atomic_enable, .atomic_disable = dcss_crtc_atomic_disable, + .mode_valid = dcss_crtc_mode_valid, }; static irqreturn_t dcss_crtc_irq_handler(int irq, void *dev_id) diff --git a/drivers/gpu/drm/imx/dpu/dpu-crtc.c b/drivers/gpu/drm/imx/dpu/dpu-crtc.c index 05ec22498f01..7b6b49e2e4fe 100644 --- a/drivers/gpu/drm/imx/dpu/dpu-crtc.c +++ b/drivers/gpu/drm/imx/dpu/dpu-crtc.c @@ -1378,6 +1378,9 @@ static int dpu_crtc_bind(struct device *dev, struct device *master, void *data) dpu_crtc->dev = dev; + drm->mode_config.max_width = 5120; + drm->mode_config.max_height = 4096; + ret = dpu_crtc_init(dpu_crtc, pdata, drm); if (ret) return ret; diff --git a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c index fce66fea4ee4..746bde884f8e 100644 --- a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c +++ b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c @@ -22,7 +22,7 @@ #define PLL_800MHZ (800000000) #define HDP_DUAL_MODE_MIN_PCLK_RATE 300000 /* KHz */ -#define HDP_SINGLE_MODE_MAX_WIDTH 1920 +#define HDP_SINGLE_MODE_MAX_WIDTH 2560 #define CSR_PIXEL_LINK_MUX_CTL 0x00 #define CSR_PIXEL_LINK_MUX_VCP_OFFSET 5 diff --git a/drivers/gpu/imx/dpu/dpu-common.c b/drivers/gpu/imx/dpu/dpu-common.c index 9fdf9fd06663..e7ce8363f7f4 100644 --- a/drivers/gpu/imx/dpu/dpu-common.c +++ b/drivers/gpu/imx/dpu/dpu-common.c @@ -305,7 +305,7 @@ static const struct dpu_data dpu_data_qm = { DPU_PLANE_SRC_FD0_ID | DPU_PLANE_SRC_FD1_ID, .has_dual_ldb = false, .syncmode_min_prate = 300000, - .singlemode_max_width = 1920, + .singlemode_max_width = 2560, .master_stream_id = 1, }; diff --git a/drivers/i2c/busses/i2c-imx-lpi2c.c b/drivers/i2c/busses/i2c-imx-lpi2c.c index e3a9454cf6a7..50e57a2298ac 100644 --- a/drivers/i2c/busses/i2c-imx-lpi2c.c +++ b/drivers/i2c/busses/i2c-imx-lpi2c.c @@ -73,23 +73,23 @@ #define MCFGR1_IGNACK BIT(9) #define MRDR_RXEMPTY BIT(14) -#define I2C_CLK_RATIO 2 +#define I2C_CLK_RATIO 24 / 59 #define CHUNK_DATA 256 -#define LPI2C_DEFAULT_RATE 100000 -#define STARDARD_MAX_BITRATE 400000 -#define FAST_MAX_BITRATE 1000000 -#define FAST_PLUS_MAX_BITRATE 3400000 -#define HIGHSPEED_MAX_BITRATE 5000000 +#define STARDARD_MAX_BITRATE 100000 +#define FAST_MAX_BITRATE 400000 +#define FAST_PLUS_MAX_BITRATE 1000000 +#define HIGHSPEED_MAX_BITRATE 3400000 +#define ULTRA_FAST_MAX_BITRATE 5000000 #define I2C_PM_TIMEOUT 1000 /* ms */ enum lpi2c_imx_mode { - STANDARD, /* 100+Kbps */ - FAST, /* 400+Kbps */ - FAST_PLUS, /* 1.0+Mbps */ - HS, /* 3.4+Mbps */ - ULTRA_FAST, /* 5.0+Mbps */ + STANDARD, /* <=100Kbps */ + FAST, /* <=400Kbps */ + FAST_PLUS, /* <=1.0Mbps */ + HS, /* <=3.4Mbps */ + ULTRA_FAST, /* <=5.0Mbps */ }; enum lpi2c_imx_pincfg { @@ -162,13 +162,13 @@ static void lpi2c_imx_set_mode(struct lpi2c_imx_struct *lpi2c_imx) unsigned int bitrate = lpi2c_imx->bitrate; enum lpi2c_imx_mode mode; - if (bitrate < STARDARD_MAX_BITRATE) + if (bitrate <= STARDARD_MAX_BITRATE) mode = STANDARD; - else if (bitrate < FAST_MAX_BITRATE) + else if (bitrate <= FAST_MAX_BITRATE) mode = FAST; - else if (bitrate < FAST_PLUS_MAX_BITRATE) + else if (bitrate <= FAST_PLUS_MAX_BITRATE) mode = FAST_PLUS; - else if (bitrate < HIGHSPEED_MAX_BITRATE) + else if (bitrate <= HIGHSPEED_MAX_BITRATE) mode = HS; else mode = ULTRA_FAST; @@ -215,11 +215,12 @@ static void lpi2c_imx_stop(struct lpi2c_imx_struct *lpi2c_imx) } while (1); } -/* CLKLO = I2C_CLK_RATIO * CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI/2 */ +/* CLKLO = (1 - I2C_CLK_RATIO) * clk_cycle, SETHOLD = CLKHI, DATAVD = CLKHI/2 + CLKHI = I2C_CLK_RATIO * clk_cycle */ static int lpi2c_imx_config(struct lpi2c_imx_struct *lpi2c_imx) { - u8 prescale, filt, sethold, clkhi, clklo, datavd; - unsigned int clk_rate, clk_cycle; + u8 prescale, filt, sethold, datavd; + unsigned int clk_rate, clk_cycle, clkhi, clklo; enum lpi2c_imx_pincfg pincfg; unsigned int temp; @@ -238,8 +239,8 @@ static int lpi2c_imx_config(struct lpi2c_imx_struct *lpi2c_imx) for (prescale = 0; prescale <= 7; prescale++) { clk_cycle = clk_rate / ((1 << prescale) * lpi2c_imx->bitrate) - - 3 - (filt >> 1); - clkhi = (clk_cycle + I2C_CLK_RATIO) / (I2C_CLK_RATIO + 1); + - (2 + filt) / (1 << prescale); + clkhi = clk_cycle * I2C_CLK_RATIO; clklo = clk_cycle - clkhi; if (clklo < 64) break; @@ -670,7 +671,7 @@ static int lpi2c_imx_probe(struct platform_device *pdev) ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency", &lpi2c_imx->bitrate); if (ret) - lpi2c_imx->bitrate = LPI2C_DEFAULT_RATE; + lpi2c_imx->bitrate = STARDARD_MAX_BITRATE; i2c_set_adapdata(&lpi2c_imx->adapter, lpi2c_imx); platform_set_drvdata(pdev, lpi2c_imx); diff --git a/drivers/input/touchscreen/synaptics_dsx/synaptics_dsx_i2c.c b/drivers/input/touchscreen/synaptics_dsx/synaptics_dsx_i2c.c index 00d0a6a544d9..2704b4f0f100 100644 --- a/drivers/input/touchscreen/synaptics_dsx/synaptics_dsx_i2c.c +++ b/drivers/input/touchscreen/synaptics_dsx/synaptics_dsx_i2c.c @@ -144,11 +144,11 @@ static struct synaptics_dsx_cap_button_map cap_button_map = { }; #ifdef CONFIG_OF_TOUCH -unsigned int touch_irq; +int touch_irq; #endif #ifdef CONFIG_OF_TOUCH -static irqreturn_t tpd_eint_handler(unsigned int irq, struct irq_desc *desc); +static irqreturn_t tpd_eint_handler(int irq, void *desc); #else static void tpd_eint_handler(void); #endif @@ -1567,7 +1567,7 @@ static void synaptics_rmi4_sensor_report(struct synaptics_rmi4_data *rmi4_data) * is detected. */ #ifdef CONFIG_OF_TOUCH -static irqreturn_t tpd_eint_handler(unsigned int irq, struct irq_desc *desc) +static irqreturn_t tpd_eint_handler(int irq, void *desc) { disable_irq_nosync(touch_irq); diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c index 64334ca0851d..d6bb8aad4654 100644 --- a/drivers/media/i2c/ov5640.c +++ b/drivers/media/i2c/ov5640.c @@ -2049,6 +2049,7 @@ static void ov5640_set_power_off(struct ov5640_dev *sensor) ov5640_power(sensor, false); regulator_bulk_disable(OV5640_NUM_SUPPLIES, sensor->supplies); clk_disable_unprepare(sensor->xclk); + sensor->streaming = false; } static int ov5640_set_power(struct ov5640_dev *sensor, bool on) diff --git a/drivers/media/v4l2-core/videobuf-core.c b/drivers/media/v4l2-core/videobuf-core.c index 939fc11cf080..8b6986e24ecf 100644 --- a/drivers/media/v4l2-core/videobuf-core.c +++ b/drivers/media/v4l2-core/videobuf-core.c @@ -590,6 +590,13 @@ int videobuf_qbuf(struct videobuf_queue *q, struct v4l2_buffer *b) buf->baddr != b->m.userptr) q->ops->buf_release(q, buf); buf->baddr = b->m.userptr; + if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT + || q->type == V4L2_BUF_TYPE_VBI_OUTPUT + || q->type == V4L2_BUF_TYPE_SLICED_VBI_OUTPUT + || q->type == V4L2_BUF_TYPE_SDR_OUTPUT) { + buf->field = b->field; + buf->ts = v4l2_timeval_to_ns(&b->timestamp); + } break; case V4L2_MEMORY_OVERLAY: buf->boff = b->m.offset; diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c index a5bc3b80f259..8d36f7bd780b 100644 --- a/drivers/mmc/core/sdio.c +++ b/drivers/mmc/core/sdio.c @@ -1011,7 +1011,7 @@ static int mmc_sdio_resume(struct mmc_host *host) if (!(host->caps2 & MMC_CAP2_SDIO_IRQ_NOTHREAD)) wake_up_process(host->sdio_irq_thread); else if (host->caps & MMC_CAP_SDIO_IRQ) - queue_delayed_work(system_wq, &host->sdio_irq_work, 0); + queue_delayed_work(system_wq, &host->sdio_irq_work, 1); } out: diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 4963e23278a5..b7443933df6c 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -967,10 +967,20 @@ static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) { u32 reg; + u8 sw_rst; + int ret; /* FIXME: delay a bit for card to be ready for next tuning due to errors */ mdelay(1); + /* IC suggest to reset USDHC before every tuning command */ + esdhc_clrset_le(host, 0xff, SDHCI_RESET_ALL, SDHCI_SOFTWARE_RESET); + ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst, + !(sw_rst & SDHCI_RESET_ALL), 10, 100); + if (ret == -ETIMEDOUT) + dev_warn(mmc_dev(host->mmc), + "warning! RESET_ALL never complete before sending tuning command\n"); + reg = readl(host->ioaddr + ESDHC_MIX_CTRL); reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | ESDHC_MIX_CTRL_FBCLK_SEL; diff --git a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.c b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.c index 5dd96492c016..dee60fa209d6 100644 --- a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.c +++ b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.c @@ -2044,20 +2044,11 @@ _SetVidMemMetadata( } else { -#ifdef gcdANDROID - if (nodeObj->metadata.ts_address == 0 && nodeObj->tsNode != NULL) - { - gctUINT32 PhysicalAddress = 0; - - /* Lock for GPU address. */ - gcmkONERROR(gckVIDMEM_NODE_Lock(Kernel, nodeObj->tsNode, &PhysicalAddress)); - - nodeObj->metadata.ts_address = ( - PhysicalAddress + Kernel->hardware->baseAddress); - - gcmkONERROR(gckVIDMEM_NODE_Unlock(Kernel, nodeObj->tsNode, ProcessID, gcvNULL)); + if ((nodeObj->metadata.ts_fd >= 0) && (nodeObj->metadata.ts_dma_buf != NULL) + && !(IS_ERR(nodeObj->metadata.ts_dma_buf))) { + dma_buf_put(nodeObj->metadata.ts_dma_buf); } -#else + nodeObj->metadata.ts_fd = Interface->u.SetVidMemMetadata.ts_fd; if (nodeObj->metadata.ts_fd >= 0) @@ -2068,14 +2059,11 @@ _SetVidMemMetadata( { gcmkONERROR(gcvSTATUS_NOT_FOUND); } - - dma_buf_put(nodeObj->metadata.ts_dma_buf); } else { nodeObj->metadata.ts_dma_buf = NULL; } -#endif nodeObj->metadata.fc_enabled = Interface->u.SetVidMemMetadata.fc_enabled; nodeObj->metadata.fc_value = Interface->u.SetVidMemMetadata.fc_value; diff --git a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_video_memory.c b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_video_memory.c index 2fa3afbf99ec..ee66dc1a498b 100644 --- a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_video_memory.c +++ b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_video_memory.c @@ -3034,9 +3034,6 @@ gckVIDMEM_NODE_Construct( node->metadata.magic = VIV_VIDMEM_METADATA_MAGIC; node->metadata.ts_fd = -1; -#ifdef gcdANDROID - node->metadata.ts_address = 0; -#endif node->node = VideoNode; node->kernel = Kernel; @@ -4098,6 +4095,12 @@ static void _dmabuf_release(struct dma_buf *dmabuf) { gckVIDMEM_NODE nodeObject = dmabuf->priv; + if (nodeObject->metadata.ts_dma_buf) + { + dma_buf_put(nodeObject->metadata.ts_dma_buf); + nodeObject->metadata.ts_dma_buf = NULL; + } + gcmkVERIFY_OK(gckVIDMEM_NODE_Dereference(nodeObject->kernel, nodeObject)); } diff --git a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_feature_database.h b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_feature_database.h index 179f0c001b29..ff04ec2097e9 100644 --- a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_feature_database.h +++ b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_feature_database.h @@ -53,7 +53,7 @@ *****************************************************************************/ -/*Auto created on 2020-07-29 19:14*/ +/*Auto created on 2020-08-19 10:25*/ #ifndef _gc_feature_database_h_ #define _gc_feature_database_h_ @@ -141,10 +141,11 @@ typedef struct gctUINT32 IMIMAGE_Y_STRIDE_BITS; gctUINT32 OUTIMAGE_X_SIZE_BITS; gctUINT32 OUTIMAGE_Y_SIZE_BITS; - gctUINT32 OUTIMAGE_SIZE_BITS; - gctUINT32 IMAGE_X_SIZE_BITS; + gctUINT32 OUTIMAGE_Z_SIZE_BITS; + gctUINT32 INIMAGE_X_SIZE_BITS; gctUINT32 INIMAGE_Y_SIZE_BITS; gctUINT32 MAX_TILE_X_SIZE; + gctUINT32 NN_CLUSTER_NUM_FOR_POWER_CONTROL; gctUINT32 REG_FastClear:1; gctUINT32 REG_SpecialAntiAliasing:1; gctUINT32 REG_Pipe3D:1; @@ -526,6 +527,7 @@ typedef struct gctUINT32 FORMAT_10BIT_CROSS_4K:1; gctUINT32 FORMAT_P010LSB_I010:1; gctUINT32 ENDIAN_CONTROL:1; + gctUINT32 G2D_RGB_PLANAR:1; gctUINT32 G2D_DEC400EX:1; gctUINT32 SH_VX2_FLOATING_MAD_FIX:1; gctUINT32 TS_FC_VULKAN_SUPPORT:1; @@ -637,6 +639,7 @@ typedef struct gctUINT32 TP_BFLOAT16:1; gctUINT32 TP_23BITS_POST_MULTIPLIER:1; gctUINT32 NN_TRANSPOSE:1; + gctUINT32 NN_ZDP_TRANSPOSE_CH9_ONLY:1; gctUINT32 USE_SINGLE_PORT_VIPSRAM:1; gctUINT32 NN_LEAKY_RELU:1; gctUINT32 NN_PRELU:1; @@ -667,6 +670,8 @@ typedef struct gctUINT32 TPLITE_SUPPORT_TP_DATA_TRANSPOSE:1; gctUINT32 NN_SUPPORT_CONV_1D:1; gctUINT32 USE_VIPSRAM_FOR_KERNEL_STREAMING:1; + gctUINT32 NN_SUPPORT_DUMMY_TILE:1; + gctUINT32 NN_SUPPORT_KERNEL_1BYTE_ALIGN:1; gctUINT32 NN_MP_INTER_CONNECT_RING:1; gctUINT32 NN_SUPPORT_BATCH:1; gctUINT32 NN_2D_AVERAGE_OUTPUT:1; @@ -698,6 +703,7 @@ typedef struct gctUINT32 OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX:1; gctUINT32 IMAGE_NOT_PACKED_IN_SRAM_FIX:1; gctUINT32 COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX:1; + gctUINT32 USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX:1; gctUINT32 LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX:1; gctUINT32 KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX:1; gctUINT32 USC_BOTTLENECK_FIX:1; @@ -725,7 +731,10 @@ typedef struct gctUINT32 TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX:1; gctUINT32 NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE:1; gctUINT32 NN_IN_TILE_DATA_IS_ALL_PAD_FIX:1; + gctUINT32 NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX:1; gctUINT32 TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX:1; + gctUINT32 NN_KERNEL_1x1_NO_PAD_FIX:1; + gctUINT32 NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX:1; gctUINT32 NN_INTERLEVE8:1; gctUINT32 NN_FP16_ALU:1; gctUINT32 NN_INT16_ALU:1; @@ -825,10 +834,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x0, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x0, /* gcFEATURE_BIT_REG_FastClear */ 0x1, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x0, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -1210,6 +1220,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -1321,6 +1332,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -1351,6 +1363,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -1382,6 +1396,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x0, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x0, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x0, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -1409,7 +1424,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x0, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x0, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x0, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x0, /* gcFEATURE_BIT_NN_INT16_ALU */ @@ -1507,10 +1525,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x0, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x0, /* gcFEATURE_BIT_REG_FastClear */ 0x1, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x0, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -1892,6 +1911,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -2003,6 +2023,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -2033,6 +2054,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -2064,6 +2087,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x0, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x0, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x0, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -2091,7 +2115,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x0, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x0, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x0, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x0, /* gcFEATURE_BIT_NN_INT16_ALU */ @@ -2189,10 +2216,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x0, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x0, /* gcFEATURE_BIT_REG_FastClear */ 0x1, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x0, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -2574,6 +2602,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -2685,6 +2714,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -2715,6 +2745,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -2746,6 +2778,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x0, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x0, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x0, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -2773,7 +2806,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x0, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x0, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x0, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x0, /* gcFEATURE_BIT_NN_INT16_ALU */ @@ -2871,10 +2907,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x0, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x0, /* gcFEATURE_BIT_REG_FastClear */ 0x0, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x0, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -3256,6 +3293,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -3367,6 +3405,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -3397,6 +3436,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -3428,6 +3469,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x0, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x0, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x0, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -3455,7 +3497,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x0, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x0, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x0, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x0, /* gcFEATURE_BIT_NN_INT16_ALU */ @@ -3553,10 +3598,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x0, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x1, /* gcFEATURE_BIT_REG_FastClear */ 0x0, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x1, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -3938,6 +3984,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -4049,6 +4096,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -4079,6 +4127,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -4110,6 +4160,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x0, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x0, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x0, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -4137,7 +4188,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x0, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x0, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x0, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x0, /* gcFEATURE_BIT_NN_INT16_ALU */ @@ -4235,10 +4289,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x0, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x0, /* gcFEATURE_BIT_REG_FastClear */ 0x1, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x0, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -4620,6 +4675,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -4731,6 +4787,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -4761,6 +4818,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -4792,6 +4851,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x0, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x0, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x0, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -4819,7 +4879,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x0, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x0, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x0, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x0, /* gcFEATURE_BIT_NN_INT16_ALU */ @@ -4917,10 +4980,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x0, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x0, /* gcFEATURE_BIT_REG_FastClear */ 0x1, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x0, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -5302,6 +5366,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -5413,6 +5478,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -5443,6 +5509,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -5474,6 +5542,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x0, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x0, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x0, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -5501,7 +5570,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x0, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x0, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x0, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x0, /* gcFEATURE_BIT_NN_INT16_ALU */ @@ -5599,10 +5671,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x0, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x0, /* gcFEATURE_BIT_REG_FastClear */ 0x1, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x0, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -5984,6 +6057,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -6095,6 +6169,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -6125,6 +6200,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -6156,6 +6233,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x0, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x0, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x0, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -6183,7 +6261,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x0, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x0, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x0, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x0, /* gcFEATURE_BIT_NN_INT16_ALU */ @@ -6281,10 +6362,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x0, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x1, /* gcFEATURE_BIT_REG_FastClear */ 0x0, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x1, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -6666,6 +6748,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -6777,6 +6860,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -6807,6 +6891,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -6838,6 +6924,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x0, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x0, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x0, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -6865,7 +6952,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x0, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x0, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x0, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x0, /* gcFEATURE_BIT_NN_INT16_ALU */ @@ -6963,10 +7053,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x0, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x1, /* gcFEATURE_BIT_REG_FastClear */ 0x0, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x1, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -7348,6 +7439,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -7459,6 +7551,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -7489,6 +7582,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -7520,6 +7615,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x0, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x0, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x0, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -7547,7 +7643,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x0, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x0, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x0, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x0, /* gcFEATURE_BIT_NN_INT16_ALU */ @@ -7645,10 +7744,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x0, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x1, /* gcFEATURE_BIT_REG_FastClear */ 0x0, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x1, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -8030,6 +8130,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -8141,6 +8242,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -8171,6 +8273,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -8202,6 +8306,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x0, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x0, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x0, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -8229,7 +8334,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x0, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x0, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x0, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x0, /* gcFEATURE_BIT_NN_INT16_ALU */ @@ -8327,10 +8435,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x0, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x1, /* gcFEATURE_BIT_REG_FastClear */ 0x0, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x1, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -8712,6 +8821,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -8823,6 +8933,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -8853,6 +8964,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -8884,6 +8997,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x0, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x0, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x0, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -8911,7 +9025,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x0, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x0, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x0, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x0, /* gcFEATURE_BIT_NN_INT16_ALU */ @@ -9009,10 +9126,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x0, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x1, /* gcFEATURE_BIT_REG_FastClear */ 0x0, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x1, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -9394,6 +9512,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -9505,6 +9624,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -9535,6 +9655,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -9566,6 +9688,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x0, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x0, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x0, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -9593,7 +9716,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x0, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x0, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x0, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x0, /* gcFEATURE_BIT_NN_INT16_ALU */ @@ -9691,10 +9817,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x0, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x1, /* gcFEATURE_BIT_REG_FastClear */ 0x0, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x1, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -10076,6 +10203,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -10187,6 +10315,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -10217,6 +10346,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -10248,6 +10379,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x0, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x0, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x0, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -10275,7 +10407,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x0, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x0, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x0, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x0, /* gcFEATURE_BIT_NN_INT16_ALU */ @@ -10373,10 +10508,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x0, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x1, /* gcFEATURE_BIT_REG_FastClear */ 0x0, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x1, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -10758,6 +10894,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -10869,6 +11006,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -10899,6 +11037,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -10930,6 +11070,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x0, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x0, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x0, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -10957,7 +11098,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x0, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x0, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x0, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x0, /* gcFEATURE_BIT_NN_INT16_ALU */ @@ -11055,10 +11199,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x0, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x1, /* gcFEATURE_BIT_REG_FastClear */ 0x0, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x1, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -11440,6 +11585,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -11551,6 +11697,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -11581,6 +11728,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -11612,6 +11761,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x0, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x0, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x0, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -11639,7 +11789,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x0, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x0, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x0, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x0, /* gcFEATURE_BIT_NN_INT16_ALU */ @@ -11737,10 +11890,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x0, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x1, /* gcFEATURE_BIT_REG_FastClear */ 0x0, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x1, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -12122,6 +12276,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -12233,6 +12388,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -12263,6 +12419,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -12294,6 +12452,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x0, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x0, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x0, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -12321,7 +12480,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x0, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x0, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x0, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x0, /* gcFEATURE_BIT_NN_INT16_ALU */ @@ -12419,10 +12581,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x0, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x1, /* gcFEATURE_BIT_REG_FastClear */ 0x0, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x1, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -12804,6 +12967,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -12915,6 +13079,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -12945,6 +13110,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -12976,6 +13143,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x0, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x0, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x0, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -13003,7 +13171,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x0, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x0, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x0, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x0, /* gcFEATURE_BIT_NN_INT16_ALU */ @@ -13101,10 +13272,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x0, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x1, /* gcFEATURE_BIT_REG_FastClear */ 0x0, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x1, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -13486,6 +13658,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -13597,6 +13770,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -13627,6 +13801,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -13658,6 +13834,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x0, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x0, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x0, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -13685,7 +13862,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x0, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x0, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x0, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x0, /* gcFEATURE_BIT_NN_INT16_ALU */ @@ -13783,10 +13963,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x0, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x1, /* gcFEATURE_BIT_REG_FastClear */ 0x0, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x1, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -14168,6 +14349,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -14279,6 +14461,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -14309,6 +14492,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -14340,6 +14525,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x0, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x0, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x0, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -14367,7 +14553,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x0, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x0, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x0, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x0, /* gcFEATURE_BIT_NN_INT16_ALU */ @@ -14465,10 +14654,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x0, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x1, /* gcFEATURE_BIT_REG_FastClear */ 0x0, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x1, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -14850,6 +15040,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -14961,6 +15152,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -14991,6 +15183,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -15022,6 +15216,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x0, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x0, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x0, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -15049,7 +15244,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x0, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x0, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x0, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x0, /* gcFEATURE_BIT_NN_INT16_ALU */ @@ -15147,10 +15345,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x0, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x1, /* gcFEATURE_BIT_REG_FastClear */ 0x0, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x1, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -15532,6 +15731,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -15643,6 +15843,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -15673,6 +15874,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -15704,6 +15907,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x0, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x0, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x0, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -15731,7 +15935,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x0, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x0, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x0, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x0, /* gcFEATURE_BIT_NN_INT16_ALU */ @@ -15829,10 +16036,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x0, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x1, /* gcFEATURE_BIT_REG_FastClear */ 0x0, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x1, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -16214,6 +16422,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -16325,6 +16534,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -16355,6 +16565,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -16386,6 +16598,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x0, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x0, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x0, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -16413,7 +16626,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x0, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x0, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x0, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x0, /* gcFEATURE_BIT_NN_INT16_ALU */ @@ -16511,10 +16727,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x0, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x1, /* gcFEATURE_BIT_REG_FastClear */ 0x0, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x1, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -16896,6 +17113,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -17007,6 +17225,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -17037,6 +17256,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -17068,6 +17289,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x0, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x0, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x0, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -17095,7 +17317,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x0, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x0, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x0, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x0, /* gcFEATURE_BIT_NN_INT16_ALU */ @@ -17193,10 +17418,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x0, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x1, /* gcFEATURE_BIT_REG_FastClear */ 0x0, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x1, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -17578,6 +17804,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -17689,6 +17916,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -17719,6 +17947,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -17750,6 +17980,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x0, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x0, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x0, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -17777,7 +18008,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x0, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x0, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x0, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x0, /* gcFEATURE_BIT_NN_INT16_ALU */ @@ -17875,10 +18109,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x0, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x1, /* gcFEATURE_BIT_REG_FastClear */ 0x0, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x1, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -18260,6 +18495,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -18371,6 +18607,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -18401,6 +18638,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -18432,6 +18671,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x0, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x0, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x0, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -18459,7 +18699,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x0, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x0, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x0, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x0, /* gcFEATURE_BIT_NN_INT16_ALU */ @@ -18557,10 +18800,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0x0, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0x0, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x0, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x0, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x1, /* gcFEATURE_BIT_REG_FastClear */ 0x0, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x1, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -18942,6 +19186,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -19053,6 +19298,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -19083,6 +19329,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -19114,6 +19362,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x0, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x0, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x0, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -19141,7 +19390,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x0, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x0, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x0, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x0, /* gcFEATURE_BIT_NN_INT16_ALU */ @@ -19239,10 +19491,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x10, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0xd, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0xd, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0xe, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0xd, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0xe, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0xd, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0xd, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x40, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x1, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x0, /* gcFEATURE_BIT_REG_FastClear */ 0x0, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x1, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -19624,6 +19877,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -19729,12 +19983,13 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x1, /* gcFEATURE_BIT_NN_XYDP0 */ 0x1, /* gcFEATURE_BIT_NN_WRITE_WITHOUT_USC */ 0x1, /* gcFEATURE_BIT_NN_HW_LIMITATION_NATIVE_KER_1x2_2x1 */ - 0x1, /* gcFEATURE_BIT_NN_SMALLBATCH_PHASE1 */ + 0x0, /* gcFEATURE_BIT_NN_SMALLBATCH_PHASE1 */ 0x0, /* gcFEATURE_BIT_NN_SLICE_PADDING_TO_64BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_DW_1x1_CONV_MERGE */ 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -19765,6 +20020,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -19796,6 +20053,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x1, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x1, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x1, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x1, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -19823,7 +20081,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x1, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x1, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x1, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x1, /* gcFEATURE_BIT_NN_INT16_ALU */ @@ -19921,10 +20182,11 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x10, /* gcFEATURE_VALUE_IMIMAGE_Y_STRIDE_BITS */ 0xd, /* gcFEATURE_VALUE_OUTIMAGE_X_SIZE_BITS */ 0xd, /* gcFEATURE_VALUE_OUTIMAGE_Y_SIZE_BITS */ - 0xe, /* gcFEATURE_VALUE_OUTIMAGE_SIZE_BITS */ - 0xd, /* gcFEATURE_VALUE_IMAGE_X_SIZE_BITS */ + 0xe, /* gcFEATURE_VALUE_OUTIMAGE_Z_SIZE_BITS */ + 0xd, /* gcFEATURE_VALUE_INIMAGE_X_SIZE_BITS */ 0xd, /* gcFEATURE_VALUE_INIMAGE_Y_SIZE_BITS */ 0x40, /* gcFEATURE_VALUE_MAX_TILE_X_SIZE */ + 0x1, /* gcFEATURE_VALUE_NN_CLUSTER_NUM_FOR_POWER_CONTROL */ 0x0, /* gcFEATURE_BIT_REG_FastClear */ 0x0, /* gcFEATURE_BIT_REG_SpecialAntiAliasing */ 0x1, /* gcFEATURE_BIT_REG_Pipe3D */ @@ -20306,6 +20568,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_FORMAT_10BIT_CROSS_4K */ 0x0, /* gcFEATURE_BIT_FORMAT_P010LSB_I010 */ 0x0, /* gcFEATURE_BIT_ENDIAN_CONTROL */ + 0x0, /* gcFEATURE_BIT_G2D_RGB_PLANAR */ 0x0, /* gcFEATURE_BIT_G2D_DEC400EX */ 0x0, /* gcFEATURE_BIT_SH_VX2_FLOATING_MAD_FIX */ 0x0, /* gcFEATURE_BIT_TS_FC_VULKAN_SUPPORT */ @@ -20411,12 +20674,13 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x1, /* gcFEATURE_BIT_NN_XYDP0 */ 0x1, /* gcFEATURE_BIT_NN_WRITE_WITHOUT_USC */ 0x1, /* gcFEATURE_BIT_NN_HW_LIMITATION_NATIVE_KER_1x2_2x1 */ - 0x1, /* gcFEATURE_BIT_NN_SMALLBATCH_PHASE1 */ + 0x0, /* gcFEATURE_BIT_NN_SMALLBATCH_PHASE1 */ 0x0, /* gcFEATURE_BIT_NN_SLICE_PADDING_TO_64BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_DW_1x1_CONV_MERGE */ 0x0, /* gcFEATURE_BIT_TP_BFLOAT16 */ 0x0, /* gcFEATURE_BIT_TP_23BITS_POST_MULTIPLIER */ 0x0, /* gcFEATURE_BIT_NN_TRANSPOSE */ + 0x0, /* gcFEATURE_BIT_NN_ZDP_TRANSPOSE_CH9_ONLY */ 0x0, /* gcFEATURE_BIT_USE_SINGLE_PORT_VIPSRAM */ 0x0, /* gcFEATURE_BIT_NN_LEAKY_RELU */ 0x0, /* gcFEATURE_BIT_NN_PRELU */ @@ -20447,6 +20711,8 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TPLITE_SUPPORT_TP_DATA_TRANSPOSE */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_CONV_1D */ 0x0, /* gcFEATURE_BIT_USE_VIPSRAM_FOR_KERNEL_STREAMING */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_DUMMY_TILE */ + 0x0, /* gcFEATURE_BIT_NN_SUPPORT_KERNEL_1BYTE_ALIGN */ 0x0, /* gcFEATURE_BIT_NN_MP_INTER_CONNECT_RING */ 0x0, /* gcFEATURE_BIT_NN_SUPPORT_BATCH */ 0x0, /* gcFEATURE_BIT_NN_2D_AVERAGE_OUTPUT */ @@ -20478,6 +20744,7 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x1, /* gcFEATURE_BIT_OUTPUT_CONVERT_UINT8_INT8_TO_UINT16_INT16_FIX */ 0x1, /* gcFEATURE_BIT_IMAGE_NOT_PACKED_IN_SRAM_FIX */ 0x1, /* gcFEATURE_BIT_COEF_DELTA_CORD_OVERFLOW_ZRL_8BIT_FIX */ + 0x0, /* gcFEATURE_BIT_USC_INDIVIDUAL_PORT_WRT_EARLY_EVICT_DATA_CORRUPT_FIX */ 0x0, /* gcFEATURE_BIT_LOW_EFFICIENCY_OF_ID_WRITE_IMGBUF_FIX */ 0x1, /* gcFEATURE_BIT_KERNEL_VIP_SRAM_READ_BW_LIMITATION_FIX */ 0x0, /* gcFEATURE_BIT_USC_BOTTLENECK_FIX */ @@ -20505,7 +20772,10 @@ static gcsFEATURE_DATABASE gChipInfo[] = { 0x0, /* gcFEATURE_BIT_TP_FC_FLOAT_LAST_PIXEL_NEGATIVE_0_FIX */ 0x1, /* gcFEATURE_BIT_NN_WASET_COEF_READ_WRITE_BANDWIDTH_128BYTE_VIPSRAM_IN_FULL_PATIAL_CACHE_MODE */ 0x1, /* gcFEATURE_BIT_NN_IN_TILE_DATA_IS_ALL_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_TP_INSTR_COMPLETE_IN_SAME_CYCLE_WITH_WAIT_EVENT_FIX */ 0x1, /* gcFEATURE_BIT_TP_FC_KERNEL_STREAM_MUST_LESS_THAN_OR_EQUAL_TO_64BYTE_WHEN_1BYTE_ALGINE_FIX */ + 0x0, /* gcFEATURE_BIT_NN_KERNEL_1x1_NO_PAD_FIX */ + 0x0, /* gcFEATURE_BIT_NN_DEPTHWISE_AFTER_16BIT_LAYER_LIMIT_FIX */ 0x0, /* gcFEATURE_BIT_NN_INTERLEVE8 */ 0x0, /* gcFEATURE_BIT_NN_FP16_ALU */ 0x1, /* gcFEATURE_BIT_NN_INT16_ALU */ diff --git a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h index 29e917c68665..e589de9d6e92 100644 --- a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h +++ b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h @@ -484,6 +484,13 @@ gcoHAL_GetProductName( OUT gctUINT *PID ); +gceSTATUS +gcoHAL_GetProductNameWithHardware( + IN gcoHARDWARE Hardware, + OUT gctSTRING *ProductName, + OUT gctUINT *PID + ); + gceSTATUS gcoHAL_SetFscaleValue( IN gcoHAL Hal, @@ -536,6 +543,12 @@ gcoHAL_IsFeatureAvailable( IN gceFEATURE Feature ); +gceSTATUS +gcoHAL_IsFeatureAvailableWithHardware( + IN gcoHARDWARE Hardware, + IN gceFEATURE Feature + ); + gceSTATUS gcoHAL_IsFeatureAvailable1( IN gcoHAL Hal, @@ -552,6 +565,12 @@ gcoHAL_QueryChipIdentity( OUT gctUINT32* ChipMinorFeatures ); +gceSTATUS gcoHAL_QueryChipIdentityWithHardware( + IN gcoHARDWARE Hardware, + OUT gceCHIPMODEL* ChipModel, + OUT gctUINT32* ChipRevision + ); + gceSTATUS gcoHAL_QueryChipIdentityEx( IN gcoHAL Hal, IN gctUINT32 SizeOfParam, diff --git a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_metadata.h b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_metadata.h index 8eaa20f60937..c3a567d356d6 100644 --- a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_metadata.h +++ b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_metadata.h @@ -73,9 +73,6 @@ typedef struct _VIV_VIDMEM_METADATA int32_t ts_fd; void * ts_dma_buf; -#ifdef gcdANDROID - dma_addr_t ts_address; -#endif uint32_t fc_enabled; uint32_t fc_value; diff --git a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_options.h b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_options.h index f01085718831..7284e658913b 100644 --- a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_options.h +++ b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_options.h @@ -1389,7 +1389,7 @@ This define enables the use of VM for gckCommand and fence buffers. When enabled, driver will ignore user and kernel driver version mismatch. */ #ifndef gcdIGNORE_DRIVER_VERSIONS_MISMATCH -# define gcdIGNORE_DRIVER_VERSIONS_MISMATCH 0 +# define gcdIGNORE_DRIVER_VERSIONS_MISMATCH 1 #endif /* diff --git a/drivers/mxc/gpu-viv/hal/os/linux/kernel/allocator/default/gc_hal_kernel_allocator_gfp.c b/drivers/mxc/gpu-viv/hal/os/linux/kernel/allocator/default/gc_hal_kernel_allocator_gfp.c index 2678b9033204..9c3dd859193d 100644 --- a/drivers/mxc/gpu-viv/hal/os/linux/kernel/allocator/default/gc_hal_kernel_allocator_gfp.c +++ b/drivers/mxc/gpu-viv/hal/os/linux/kernel/allocator/default/gc_hal_kernel_allocator_gfp.c @@ -479,6 +479,7 @@ _GFPAlloc( struct gfp_alloc *priv = (struct gfp_alloc *)Allocator->privateData; struct gfp_mdl_priv *mdlPriv = gcvNULL; + int result; int low = 0; int high = 0; @@ -565,6 +566,26 @@ _GFPAlloc( gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); } + mdlPriv->dma_addr = dma_map_page(galcore_device, + mdlPriv->contiguousPages, 0, NumPages * PAGE_SIZE, + DMA_FROM_DEVICE); + + if (dma_mapping_error(galcore_device, mdlPriv->dma_addr)) + { +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27) + if (mdlPriv->exact) + { + free_pages_exact(page_address(mdlPriv->contiguousPages), bytes); + } + else +#endif + { + __free_pages(mdlPriv->contiguousPages, get_order(bytes)); + } + + gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); + } + #if defined(CONFIG_X86) if (!PageHighMem(mdlPriv->contiguousPages)) { @@ -591,6 +612,56 @@ _GFPAlloc( } } +#if LINUX_VERSION_CODE >= KERNEL_VERSION (3,6,0) \ + && (defined(ARCH_HAS_SG_CHAIN) || defined(CONFIG_ARCH_HAS_SG_CHAIN)) + result = sg_alloc_table_from_pages(&mdlPriv->sgt, + mdlPriv->nonContiguousPages, NumPages, 0, + NumPages << PAGE_SHIFT, GFP_KERNEL); + +#else + result = alloc_sg_list_from_pages(&mdlPriv->sgt.sgl, + mdlPriv->nonContiguousPages, NumPages, 0, + NumPages << PAGE_SHIFT, &mdlPriv->sgt.nents); + + mdlPriv->sgt.orig_nents = mdlPriv->sgt.nents; +#endif + if (result < 0) + { + if (Mdl->pageUnit1M) + { + _NonContiguous1MPagesFree(mdlPriv, mdlPriv->numPages1M); + } + else + { + _NonContiguousFree(mdlPriv->nonContiguousPages, NumPages); + } + + gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); + } + + result = dma_map_sg(galcore_device, + mdlPriv->sgt.sgl, mdlPriv->sgt.nents, DMA_FROM_DEVICE); + + if (result != mdlPriv->sgt.nents) + { + if (Mdl->pageUnit1M) + { + _NonContiguous1MPagesFree(mdlPriv, mdlPriv->numPages1M); + } + else + { + _NonContiguousFree(mdlPriv->nonContiguousPages, NumPages); + } + +#if LINUX_VERSION_CODE >= KERNEL_VERSION (3,6,0) \ + && (defined (ARCH_HAS_SG_CHAIN) || defined (CONFIG_ARCH_HAS_SG_CHAIN)) + sg_free_table(&mdlPriv->sgt); +#else + kfree(mdlPriv->sgt.sgl); +#endif + gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); + } + #if defined(CONFIG_X86) if (set_pages_array_wc(mdlPriv->nonContiguousPages, NumPages)) { @@ -734,6 +805,24 @@ _GFPFree( int low = 0; int high = 0; + if (mdlPriv->contiguous) + { + dma_unmap_page(galcore_device, mdlPriv->dma_addr, + Mdl->numPages << PAGE_SHIFT, DMA_FROM_DEVICE); + } + else + { + dma_unmap_sg(galcore_device, mdlPriv->sgt.sgl, mdlPriv->sgt.nents, + DMA_FROM_DEVICE); + +#if LINUX_VERSION_CODE >= KERNEL_VERSION (3,6,0) \ + && (defined (ARCH_HAS_SG_CHAIN) || defined (CONFIG_ARCH_HAS_SG_CHAIN)) + sg_free_table(&mdlPriv->sgt); +#else + kfree(mdlPriv->sgt.sgl); +#endif + } + for (i = 0; i < Mdl->numPages; i++) { if (mdlPriv->contiguous) @@ -850,18 +939,7 @@ _GFPMmap( __FUNCTION__, __LINE__ ); - } - - if (Cacheable) - { - mdlPriv->dma_addr = dma_map_page(galcore_device, - mdlPriv->contiguousPages, 0, numPages * PAGE_SIZE, - DMA_BIDIRECTIONAL); - - if (dma_mapping_error(galcore_device, mdlPriv->dma_addr)) - { - gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); - } + gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); } } else @@ -890,43 +968,6 @@ _GFPMmap( start += PAGE_SIZE; } - - if (Cacheable) - { - int result; - -#if LINUX_VERSION_CODE >= KERNEL_VERSION (3,6,0) \ - && (defined(ARCH_HAS_SG_CHAIN) || defined(CONFIG_ARCH_HAS_SG_CHAIN)) - result = sg_alloc_table_from_pages(&mdlPriv->sgt, - mdlPriv->nonContiguousPages, numPages, 0, - numPages << PAGE_SHIFT, GFP_KERNEL); - -#else - result = alloc_sg_list_from_pages(&mdlPriv->sgt.sgl, - mdlPriv->nonContiguousPages, numPages, 0, - numPages << PAGE_SHIFT, &mdlPriv->sgt.nents); - - mdlPriv->sgt.orig_nents = mdlPriv->sgt.nents; -#endif - if (result < 0) - { - gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); - } - - result = dma_map_sg(galcore_device, - mdlPriv->sgt.sgl, mdlPriv->sgt.nents, DMA_BIDIRECTIONAL); - - if (result != mdlPriv->sgt.nents) - { -#if LINUX_VERSION_CODE >= KERNEL_VERSION (3,6,0) \ - && (defined (ARCH_HAS_SG_CHAIN) || defined (CONFIG_ARCH_HAS_SG_CHAIN)) - sg_free_table(&mdlPriv->sgt); -#else - kfree(mdlPriv->sgt.sgl); -#endif - gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); - } - } } OnError: @@ -942,8 +983,6 @@ _GFPUnmapUser( IN gctUINT32 Size ) { - struct gfp_mdl_priv *mdlPriv = Mdl->priv; - MdlMap->cacheable = gcvFALSE; if (unlikely(current->mm == gcvNULL)) @@ -952,27 +991,6 @@ _GFPUnmapUser( return; } - if (mdlPriv->contiguous) - { - if (mdlPriv->dma_addr) - { - dma_unmap_page(galcore_device, mdlPriv->dma_addr, - Mdl->numPages << PAGE_SHIFT, DMA_BIDIRECTIONAL); - } - } - else if (mdlPriv->sgt.sgl) - { - dma_unmap_sg(galcore_device, mdlPriv->sgt.sgl, mdlPriv->sgt.nents, - DMA_BIDIRECTIONAL); - -#if LINUX_VERSION_CODE >= KERNEL_VERSION (3,6,0) \ - && (defined (ARCH_HAS_SG_CHAIN) || defined (CONFIG_ARCH_HAS_SG_CHAIN)) - sg_free_table(&mdlPriv->sgt); -#else - kfree(mdlPriv->sgt.sgl); -#endif - } - #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0) if (vm_munmap((unsigned long)MdlMap->vmaAddr, Size) < 0) { diff --git a/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c b/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c index c441cf714de0..1e24c229f3cd 100644 --- a/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c +++ b/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c @@ -271,11 +271,16 @@ _AllocateIntegerId( { int result; gctINT next; + unsigned long flags = 0; #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) idr_preload(GFP_KERNEL | gcdNOWARN); - spin_lock(&Database->lock); + if(in_irq()){ + spin_lock(&Database->lock); + }else{ + spin_lock_irqsave(&Database->lock, flags); + } next = (Database->curr + 1 <= 0) ? 1 : Database->curr + 1; @@ -289,7 +294,11 @@ _AllocateIntegerId( Database->curr = *Id = result; } - spin_unlock(&Database->lock); + if(in_irq()){ + spin_unlock(&Database->lock); + }else{ + spin_unlock_irqrestore(&Database->lock, flags); + } idr_preload_end(); @@ -304,7 +313,11 @@ _AllocateIntegerId( return gcvSTATUS_OUT_OF_MEMORY; } - spin_lock(&Database->lock); + if(in_irq()){ + spin_lock(&Database->lock); + }else{ + spin_lock_irqsave(&Database->lock, flags); + } next = (Database->curr + 1 <= 0) ? 1 : Database->curr + 1; @@ -316,7 +329,11 @@ _AllocateIntegerId( Database->curr = *Id; } - spin_unlock(&Database->lock); + if(in_irq()){ + spin_unlock(&Database->lock); + }else{ + spin_unlock_irqrestore(&Database->lock, flags); + } if (result == -EAGAIN) { @@ -340,12 +357,21 @@ _QueryIntegerId( ) { gctPOINTER pointer; + unsigned long flags = 0; - spin_lock(&Database->lock); + if(in_irq()){ + spin_lock(&Database->lock); + }else{ + spin_lock_irqsave(&Database->lock, flags); + } pointer = idr_find(&Database->idr, Id); - spin_unlock(&Database->lock); + if(in_irq()){ + spin_unlock(&Database->lock); + }else{ + spin_unlock_irqrestore(&Database->lock, flags); + } if (pointer) { @@ -369,11 +395,21 @@ _DestroyIntegerId( IN gctUINT32 Id ) { - spin_lock(&Database->lock); + unsigned long flags = 0; + + if(in_irq()){ + spin_lock(&Database->lock); + }else{ + spin_lock_irqsave(&Database->lock, flags); + } idr_remove(&Database->idr, Id); - spin_unlock(&Database->lock); + if(in_irq()){ + spin_unlock(&Database->lock); + }else{ + spin_unlock_irqrestore(&Database->lock, flags); + } return gcvSTATUS_OK; } diff --git a/drivers/mxc/vpu_malone/vpu_b0.c b/drivers/mxc/vpu_malone/vpu_b0.c index 48b9cb409ba2..46397058e6d3 100644 --- a/drivers/mxc/vpu_malone/vpu_b0.c +++ b/drivers/mxc/vpu_malone/vpu_b0.c @@ -1745,6 +1745,7 @@ static int v4l2_ioctl_try_fmt(struct file *file, struct v4l2_format *f ) { + struct vpu_ctx *ctx = v4l2_fh_to_ctx(fh); unsigned int table_size; if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { @@ -1758,6 +1759,11 @@ static int v4l2_ioctl_try_fmt(struct file *file, } else return -EINVAL; + f->fmt.pix_mp.colorspace = ctx->colorspace; + f->fmt.pix_mp.xfer_func = ctx->xfer_func; + f->fmt.pix_mp.ycbcr_enc = ctx->ycbcr_enc; + f->fmt.pix_mp.quantization = ctx->quantization; + return 0; } diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_cmdevt.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_cmdevt.c index 8cf42e816e94..66c9c971080f 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_cmdevt.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_cmdevt.c @@ -2310,10 +2310,11 @@ mlan_status wlan_cancel_pending_scan_cmd(pmlan_adapter pmadapter, * @brief Cancel all pending cmd. * * @param pmadapter A pointer to mlan_adapter + * @param flag MTRUE/MFALSE * * @return N/A */ -t_void wlan_cancel_all_pending_cmd(pmlan_adapter pmadapter) +t_void wlan_cancel_all_pending_cmd(pmlan_adapter pmadapter, t_u8 flag) { cmd_ctrl_node *pcmd_node = MNULL; pmlan_callbacks pcb = &pmadapter->callbacks; @@ -2338,7 +2339,6 @@ t_void wlan_cancel_all_pending_cmd(pmlan_adapter pmadapter) #endif if (pmadapter->curr_cmd) { pcmd_node = pmadapter->curr_cmd; - pmadapter->curr_cmd = MNULL; if (pcmd_node->pioctl_buf) { pioctl_buf = (mlan_ioctl_req *)pcmd_node->pioctl_buf; pioctl_buf->status_code = MLAN_ERROR_CMD_CANCEL; @@ -2347,7 +2347,10 @@ t_void wlan_cancel_all_pending_cmd(pmlan_adapter pmadapter) MLAN_STATUS_FAILURE); pcmd_node->pioctl_buf = MNULL; } - wlan_insert_cmd_to_free_q(pmadapter, pcmd_node); + if (flag) { + pmadapter->curr_cmd = MNULL; + wlan_insert_cmd_to_free_q(pmadapter, pcmd_node); + } } /* Cancel all pending command */ diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_decl.h b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_decl.h index 1f2ef21d7548..63d61566e7cb 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_decl.h +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_decl.h @@ -24,7 +24,7 @@ #define _MLAN_DECL_H_ /** MLAN release version */ -#define MLAN_RELEASE_VERSION "186.p2" +#define MLAN_RELEASE_VERSION "186.p6" /** Re-define generic data types for MLAN/MOAL */ /** Signed char (1-byte) */ diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_init.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_init.c index 1831ac097bb6..e81299d690a4 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_init.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_init.c @@ -1584,7 +1584,7 @@ t_void wlan_free_adapter(pmlan_adapter pmadapter) return; } - wlan_cancel_all_pending_cmd(pmadapter); + wlan_cancel_all_pending_cmd(pmadapter, MTRUE); /* Free command buffer */ PRINTM(MINFO, "Free Command buffer\n"); wlan_free_cmd_buffer(pmadapter); @@ -1912,6 +1912,7 @@ mlan_status wlan_init_fw_complete(pmlan_adapter pmadapter) mlan_status status = MLAN_STATUS_SUCCESS; mlan_status ret = MLAN_STATUS_SUCCESS; pmlan_callbacks pcb = &pmadapter->callbacks; + mlan_private *pmpriv = MNULL; ENTER(); @@ -1921,10 +1922,12 @@ mlan_status wlan_init_fw_complete(pmlan_adapter pmadapter) /* Reconfigure wmm parameter*/ if (status == MLAN_STATUS_SUCCESS) { - status = wlan_prepare_cmd( - wlan_get_priv(pmadapter, MLAN_BSS_ROLE_STA), - HostCmd_CMD_WMM_PARAM_CONFIG, HostCmd_ACT_GEN_SET, 0, - MNULL, &pmadapter->ac_params); + pmpriv = wlan_get_priv(pmadapter, MLAN_BSS_ROLE_STA); + if (pmpriv) + status = wlan_prepare_cmd(pmpriv, + HostCmd_CMD_WMM_PARAM_CONFIG, + HostCmd_ACT_GEN_SET, 0, MNULL, + &pmadapter->ac_params); } /* Invoke callback */ ret = pcb->moal_init_fw_complete(pmadapter->pmoal_handle, status); diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_main.h b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_main.h index 8ff45747a6c8..a0035f27db4d 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_main.h +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_main.h @@ -2784,7 +2784,7 @@ mlan_status wlan_cancel_pending_scan_cmd(pmlan_adapter pmadapter, pmlan_ioctl_req pioctl_req); #endif /**Cancel pending command */ -t_void wlan_cancel_all_pending_cmd(pmlan_adapter pmadapter); +t_void wlan_cancel_all_pending_cmd(pmlan_adapter pmadapter, t_u8 flag); /**Cancel pending ioctl */ t_void wlan_cancel_pending_ioctl(pmlan_adapter pmadapter, pmlan_ioctl_req pioctl_req); diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_shim.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_shim.c index 4c4347938728..60472c8db461 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_shim.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_shim.c @@ -757,7 +757,7 @@ mlan_status mlan_shutdown_fw(t_void *pmlan_adapter) PRINTM(MINFO, "Shutdown MLAN...\n"); /* Cancel all pending commands and complete ioctls */ - wlan_cancel_all_pending_cmd(pmadapter); + wlan_cancel_all_pending_cmd(pmadapter, MTRUE); /* Clean up priv structures */ for (i = 0; i < pmadapter->priv_num; i++) { @@ -1342,7 +1342,7 @@ mlan_status mlan_ioctl(t_void *adapter, pmlan_ioctl_req pioctl_req) if (pioctl_req == MNULL) { PRINTM(MMSG, "Cancel all pending cmd!\n"); - wlan_cancel_all_pending_cmd(pmadapter); + wlan_cancel_all_pending_cmd(pmadapter, MFALSE); goto exit; } if (pioctl_req->action == MLAN_ACT_CANCEL) { diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_sta_ioctl.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_sta_ioctl.c index 0c98a7b61f83..159328d554a3 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_sta_ioctl.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlan/mlan_sta_ioctl.c @@ -3970,7 +3970,7 @@ mlan_status wlan_misc_ioctl_warm_reset(pmlan_adapter pmadapter, /* Cancel all pending commands and complete ioctls */ if (misc->param.fw_reload) - wlan_cancel_all_pending_cmd(pmadapter); + wlan_cancel_all_pending_cmd(pmadapter, MTRUE); /** Init all the head nodes and free all the locks here */ for (i = 0; i < pmadapter->priv_num; i++) diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/mlan_decl.h b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/mlan_decl.h index c931ef472040..63d61566e7cb 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/mlan_decl.h +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/mlan_decl.h @@ -24,7 +24,7 @@ #define _MLAN_DECL_H_ /** MLAN release version */ -#define MLAN_RELEASE_VERSION "186" +#define MLAN_RELEASE_VERSION "186.p6" /** Re-define generic data types for MLAN/MOAL */ /** Signed char (1-byte) */ @@ -556,6 +556,8 @@ typedef enum { #define MREG_D MBIT(9) +#define MLOG_D MBIT(10) + #define MMPA_D MBIT(15) #define MDAT_D MBIT(16) #define MCMD_D MBIT(17) diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_cfg80211.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_cfg80211.c index 5b3abded4ccd..63f1f2a35f79 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_cfg80211.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_cfg80211.c @@ -2621,14 +2621,11 @@ int woal_cfg80211_mgmt_tx(struct wiphy *wiphy, ->priv[priv->phandle->remain_bss_index]; /** cancel previous remain on channel */ if (priv->phandle->remain_on_channel && remain_priv) { - if ((priv->phandle->chan.center_freq != - chan->center_freq)) { - if (woal_cfg80211_remain_on_channel_cfg( - remain_priv, MOAL_IOCTL_WAIT, MTRUE, - &channel_status, NULL, 0, 0)) - PRINTM(MERROR, - "mgmt_tx:Fail to cancel remain on channel\n"); - } + if (woal_cfg80211_remain_on_channel_cfg( + remain_priv, MOAL_IOCTL_WAIT, MTRUE, + &channel_status, NULL, 0, 0)) + PRINTM(MERROR, + "mgmt_tx:Fail to cancel remain on channel\n"); if (priv->phandle->cookie) { cfg80211_remain_on_channel_expired( #if KERNEL_VERSION(3, 6, 0) > CFG80211_VERSION_CODE @@ -2782,7 +2779,8 @@ int woal_cfg80211_mgmt_tx(struct wiphy *wiphy, tx_info->tx_cookie = *cookie; tx_info->tx_skb = skb; tx_info->tx_seq_num = pmbuf->tx_seq_num; - if (priv->phandle->remain_on_channel && !wait) + if ((priv->bss_role == MLAN_BSS_ROLE_UAP) && + (priv->phandle->remain_on_channel && !wait)) tx_info->cancel_remain_on_channel = MTRUE; INIT_LIST_HEAD(&tx_info->link); diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_cfg80211_util.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_cfg80211_util.c index fbba87dd0dd2..61bc83c2ed2b 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_cfg80211_util.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_cfg80211_util.c @@ -2739,6 +2739,11 @@ static int woal_cfg80211_subcmd_link_statistic_get(struct wiphy *wiphy, t_u64 max_msec = (t_u64)24 * (t_u64)24 * (t_u64)3600 * (t_u64)1000; moal_handle *handle = priv->phandle; + /*Sending this command frequently causes TP to drop.*/ + /*ToDo : Check in vendor HAL if this callback is needed so frequently + * during normal run*/ + if (!(drvdbg & MLOG_D)) + return 0; /* Allocate an IOCTL request buffer */ req = woal_alloc_mlan_ioctl_req(sizeof(t_u32) + BUF_MAXLEN); if (req == NULL) { diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_ioctl.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_ioctl.c index 29c401f6f686..588a760ca931 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_ioctl.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_ioctl.c @@ -6834,7 +6834,9 @@ mlan_status woal_process_rf_test_mode_cmd(moal_handle *handle, t_u32 cmd, err = MTRUE; break; case MFG_CMD_RF_CHANNELBW: - if (val != 0 && val != 1 && val != 4) + if (val != 0 && val != 1 && + (val != 4 || + (val == 4 && handle->rf_data->band == BAND_2GHZ))) err = MTRUE; break; case MFG_CMD_RF_CHAN: @@ -6883,6 +6885,12 @@ mlan_status woal_process_rf_test_mode_cmd(moal_handle *handle, t_u32 cmd, break; case MFG_CMD_RF_BAND_AG: handle->rf_data->band = misc->param.mfg_generic_cfg.data1; + /* set fw default bw and channel config on band change */ + handle->rf_data->bandwidth = CHANNEL_BW_20MHZ; + if (handle->rf_data->band == BAND_2GHZ) + handle->rf_data->channel = 6; + else if (handle->rf_data->band == BAND_5GHZ) + handle->rf_data->channel = 36; break; case MFG_CMD_RF_CHANNELBW: handle->rf_data->bandwidth = misc->param.mfg_generic_cfg.data1; diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_main.h b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_main.h index d69a610cc5a4..41ecd642f202 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_main.h +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_main.h @@ -215,7 +215,7 @@ Change log: /** Define BOOLEAN */ typedef t_u8 BOOLEAN; -#define INTF_CARDTYPE "---------%s-MX" +#define INTF_CARDTYPE "---------%s-MXM" #define KERN_VERSION "4X" diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_proc.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_proc.c index 772c10892b65..e18f6e7993ce 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_proc.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_proc.c @@ -502,8 +502,8 @@ static ssize_t woal_config_write(struct file *f, const char __user *buf, config_data = (t_u32)woal_string_to_number(line); cmd = MFG_CMD_RF_BAND_AG; } - if (!strncmp(databuf, "bandwidth", strlen("bandwidth"))) { - line += strlen("bandwidth") + 1; + if (!strncmp(databuf, "bw", strlen("bw"))) { + line += strlen("bw") + 1; config_data = (t_u32)woal_string_to_number(line); cmd = MFG_CMD_RF_CHANNELBW; } @@ -567,7 +567,7 @@ static int woal_config_read(struct seq_file *sfp, void *data) seq_printf(sfp, "tx_antenna=%u\n", handle->rf_data->tx_antenna); seq_printf(sfp, "rx_antenna=%u\n", handle->rf_data->rx_antenna); seq_printf(sfp, "band=%u\n", handle->rf_data->band); - seq_printf(sfp, "bandwidth=%u\n", handle->rf_data->bandwidth); + seq_printf(sfp, "bw=%u\n", handle->rf_data->bandwidth); if (handle->rf_data->channel) seq_printf(sfp, "channel=%u\n", handle->rf_data->channel); diff --git a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_shim.c b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_shim.c index 0096b78210f1..c99e6e9332ad 100644 --- a/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_shim.c +++ b/drivers/net/wireless/nxp/mxm_wifiex/wlan_src/mlinux/moal_shim.c @@ -2635,6 +2635,7 @@ mlan_status moal_recv_event(t_void *pmoal_handle, pmlan_event pmevent) PRINTM(MEVENT, "HostMlme %s: Receive deauth/disassociate\n", priv->netdev->name); + priv->cfg_disconnect = MTRUE; woal_mgmt_frame_register( priv, IEEE80211_STYPE_DEAUTH, diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c index e6b9ace7bb73..62be4d67ac38 100644 --- a/drivers/nvmem/imx-ocotp.c +++ b/drivers/nvmem/imx-ocotp.c @@ -14,6 +14,7 @@ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc */ +#include #include #include #include @@ -319,6 +320,8 @@ static int imx_ocotp_write(void *context, unsigned int offset, void *val, return ret; } + request_bus_freq(BUS_FREQ_HIGH); + /* Setup the write timing values */ priv->params->set_timing(priv); @@ -458,6 +461,8 @@ static int imx_ocotp_write(void *context, unsigned int offset, void *val, } write_end: + release_bus_freq(BUS_FREQ_HIGH); + clk_disable_unprepare(priv->clk); mutex_unlock(&ocotp_mutex); if (ret < 0) diff --git a/drivers/phy/freescale/phy-fsl-imx8mq-usb.c b/drivers/phy/freescale/phy-fsl-imx8mq-usb.c index f07c7fda9589..1efb3722005a 100644 --- a/drivers/phy/freescale/phy-fsl-imx8mq-usb.c +++ b/drivers/phy/freescale/phy-fsl-imx8mq-usb.c @@ -8,20 +8,23 @@ #include #include #include +#include #define PHY_CTRL0 0x0 #define PHY_CTRL0_REF_CLKDIV2 BIT(1) #define PHY_CTRL0_REF_SSP_EN BIT(2) -#define PHY_CTRL0_FSEL_MASK GENMASK(5, 10) +#define PHY_CTRL0_FSEL_MASK GENMASK(10, 5) #define PHY_CTRL0_FSEL_24M 0x2a #define PHY_CTRL0_FSEL_100M 0x27 -#define PHY_CTRL0_SSC_RANGE_MASK GENMASK(21, 23) +#define PHY_CTRL0_SSC_RANGE_MASK GENMASK(23, 21) #define PHY_CTRL0_SSC_RANGE_4003PPM (0x2 << 21) #define PHY_CTRL1 0x4 #define PHY_CTRL1_RESET BIT(0) #define PHY_CTRL1_COMMONONN BIT(1) #define PHY_CTRL1_ATERESET BIT(3) +#define PHY_CTRL1_DCDENB BIT(17) +#define PHY_CTRL1_CHRGSEL BIT(18) #define PHY_CTRL1_VDATSRCENB0 BIT(19) #define PHY_CTRL1_VDATDETENB0 BIT(20) @@ -29,16 +32,31 @@ #define PHY_CTRL2_TXENABLEN0 BIT(8) #define PHY_CTRL2_OTG_DISABLE BIT(9) +#define PHY_CTRL5 0x14 +#define PHY_CTRL5_DMPWD_OVERRIDE_SEL BIT(23) +#define PHY_CTRL5_DMPWD_OVERRIDE BIT(22) +#define PHY_CTRL5_DPPWD_OVERRIDE_SEL BIT(21) +#define PHY_CTRL5_DPPWD_OVERRIDE BIT(20) + #define PHY_CTRL6 0x18 #define PHY_CTRL6_RXTERM_OVERRIDE_SEL BIT(29) #define PHY_CTRL6_ALT_CLK_EN BIT(1) #define PHY_CTRL6_ALT_CLK_SEL BIT(0) +#define PHY_STS0 0x40 +#define PHY_STS0_OTGSESSVLD BIT(7) +#define PHY_STS0_CHGDET BIT(4) +#define PHY_STS0_FSVPLUS BIT(3) +#define PHY_STS0_FSVMINUS BIT(2) + struct imx8mq_usb_phy { struct phy *phy; struct clk *clk; void __iomem *base; struct regulator *vbus; + struct notifier_block chg_det_nb; + struct power_supply *vbus_power_supply; + enum power_supply_usb_type chg_type; }; static int imx8mq_usb_phy_init(struct phy *phy) @@ -155,10 +173,245 @@ static int imx8mq_phy_power_off(struct phy *phy) return 0; } +static int imx8mq_chg_data_contact_det(struct imx8mq_usb_phy *imx_phy) +{ + int i, data_pin_contact_count = 0; + u32 val; + + /* Set DMPULLDOWN<#> = 1'b1 (to enable RDM_DWN) */ + val = readl(imx_phy->base + PHY_CTRL5); + val |= PHY_CTRL5_DMPWD_OVERRIDE_SEL | PHY_CTRL5_DMPWD_OVERRIDE; + writel(val, imx_phy->base + PHY_CTRL5); + + /* Set DPPULLDOWN<#> = 1'b0 */ + val = readl(imx_phy->base + PHY_CTRL5); + val |= PHY_CTRL5_DMPWD_OVERRIDE_SEL | PHY_CTRL5_DMPWD_OVERRIDE; + writel(val, imx_phy->base + PHY_CTRL5); + + /* Enable Data Contact Detect (DCD) per the USB BC 1.2 */ + val = readl(imx_phy->base + PHY_CTRL1); + writel(val | PHY_CTRL1_DCDENB, imx_phy->base + PHY_CTRL1); + + for (i = 0; i < 100; i = i + 1) { + val = readl(imx_phy->base + PHY_STS0); + /* DP is low */ + if (!(val & PHY_STS0_FSVPLUS)) { + if (data_pin_contact_count++ > 5) + /* Data pin makes contact */ + break; + usleep_range(5000, 10000); + } else { + data_pin_contact_count = 0; + usleep_range(5000, 6000); + } + } + + /* Disable DCD after finished data contact check */ + val = readl(imx_phy->base + PHY_CTRL1); + val &= ~PHY_CTRL1_DCDENB; + writel(val, imx_phy->base + PHY_CTRL1); + + if (i == 100) { + dev_err(&imx_phy->phy->dev, + "VBUS is coming from a dedicated power supply.\n"); + + /* disable override before finish */ + val = readl(imx_phy->base + PHY_CTRL5); + val &= ~(PHY_CTRL5_DMPWD_OVERRIDE | PHY_CTRL5_DPPWD_OVERRIDE); + writel(val, imx_phy->base + PHY_CTRL5); + + return -ENXIO; + } + + /* Set DMPULLDOWN<#> to 1'b0 when DCD is completed */ + val = readl(imx_phy->base + PHY_CTRL5); + val &= ~PHY_CTRL5_DMPWD_OVERRIDE_SEL; + val |= PHY_CTRL5_DMPWD_OVERRIDE; + writel(val, imx_phy->base + PHY_CTRL5); + + return 0; +} + +static int imx8mq_chg_primary_detect(struct imx8mq_usb_phy *imx_phy) +{ + u32 val; + + /* VDP_SRC is connected to D+ and IDM_SINK is connected to D- */ + val = readl(imx_phy->base + PHY_CTRL1); + val &= ~PHY_CTRL1_CHRGSEL; + val |= PHY_CTRL1_VDATSRCENB0 | PHY_CTRL1_VDATDETENB0; + writel(val, imx_phy->base + PHY_CTRL1); + + usleep_range(1000, 2000); + + /* Check if D- is less than VDAT_REF to determine an SDP per BC 1.2 */ + val = readl(imx_phy->base + PHY_STS0); + if (!(val & PHY_STS0_CHGDET)) { + dev_dbg(&imx_phy->phy->dev, "It is a SDP.\n"); + imx_phy->chg_type = POWER_SUPPLY_USB_TYPE_SDP; + } + + return 0; +} + +static int imx8mq_phy_chg_secondary_det(struct imx8mq_usb_phy *imx_phy) +{ + u32 val; + + /* VDM_SRC is connected to D- and IDP_SINK is connected to D+ */ + val = readl(imx_phy->base + PHY_CTRL1); + writel(val | PHY_CTRL1_VDATSRCENB0 | PHY_CTRL1_VDATDETENB0 | + PHY_CTRL1_CHRGSEL, imx_phy->base + PHY_CTRL1); + + usleep_range(1000, 2000); + + /* + * Per BC 1.2, check voltage of D+: + * DCP: if greater than VDAT_REF; + * CDP: if less than VDAT0_REF. + */ + val = readl(imx_phy->base + PHY_STS0); + if (val & PHY_STS0_CHGDET) { + dev_dbg(&imx_phy->phy->dev, "It is a DCP.\n"); + imx_phy->chg_type = POWER_SUPPLY_USB_TYPE_DCP; + } else { + dev_dbg(&imx_phy->phy->dev, "It is a CDP.\n"); + imx_phy->chg_type = POWER_SUPPLY_USB_TYPE_CDP; + } + + return 0; +} + +static void imx8mq_phy_disable_chg_det(struct imx8mq_usb_phy *imx_phy) +{ + u32 val; + + val = readl(imx_phy->base + PHY_CTRL5); + val &= ~(PHY_CTRL5_DMPWD_OVERRIDE | PHY_CTRL5_DPPWD_OVERRIDE); + writel(val, imx_phy->base + PHY_CTRL5); + + val = readl(imx_phy->base + PHY_CTRL1); + val &= ~(PHY_CTRL1_DCDENB | PHY_CTRL1_VDATSRCENB0 | + PHY_CTRL1_VDATDETENB0 | PHY_CTRL1_CHRGSEL); + writel(val, imx_phy->base + PHY_CTRL1); +} + +static int imx8mq_phy_charger_detect(struct imx8mq_usb_phy *imx_phy) +{ + struct device *dev = &imx_phy->phy->dev; + struct device_node *np = dev->parent->of_node; + union power_supply_propval propval; + u32 value; + int ret = 0; + + if (!np) + return 0; + + imx_phy->vbus_power_supply = power_supply_get_by_phandle(np, + "vbus-power-supply"); + if (IS_ERR_OR_NULL(imx_phy->vbus_power_supply)) + return 0; + + if (imx_phy->chg_type != POWER_SUPPLY_USB_TYPE_UNKNOWN) + goto put_psy; + + ret = power_supply_get_property(imx_phy->vbus_power_supply, + POWER_SUPPLY_PROP_ONLINE, + &propval); + if (ret || propval.intval == 0) { + dev_err(dev, "failed to get psy online infor\n"); + ret = -EINVAL; + goto put_psy; + } + + /* Check if vbus is valid */ + value = readl(imx_phy->base + PHY_STS0); + if (!(value & PHY_STS0_OTGSESSVLD)) { + dev_err(&imx_phy->phy->dev, "vbus is error\n"); + ret = -EINVAL; + goto put_psy; + } + + imx_phy->chg_type = POWER_SUPPLY_USB_TYPE_UNKNOWN; + + ret = imx8mq_chg_data_contact_det(imx_phy); + if (ret) + goto put_psy; + + ret = imx8mq_chg_primary_detect(imx_phy); + if (!ret && imx_phy->chg_type != POWER_SUPPLY_USB_TYPE_SDP) + ret = imx8mq_phy_chg_secondary_det(imx_phy); + + imx8mq_phy_disable_chg_det(imx_phy); + + if (!ret) { + propval.intval = imx_phy->chg_type; + power_supply_set_property(imx_phy->vbus_power_supply, + POWER_SUPPLY_PROP_USB_TYPE, + &propval); + } + +put_psy: + power_supply_put(imx_phy->vbus_power_supply); + + return ret; +} + +static int imx8mq_phy_usb_vbus_notify(struct notifier_block *nb, + unsigned long val, void *v) +{ + struct imx8mq_usb_phy *imx_phy = container_of(nb, struct imx8mq_usb_phy, + chg_det_nb); + struct device *dev = &imx_phy->phy->dev; + struct device_node *np = dev->parent->of_node; + union power_supply_propval propval; + struct power_supply *psy = v; + int ret; + + if (!np) + return NOTIFY_DONE; + + imx_phy->vbus_power_supply = power_supply_get_by_phandle(np, + "vbus-power-supply"); + if (IS_ERR_OR_NULL(imx_phy->vbus_power_supply)) { + dev_err(dev, "failed to get power supply\n"); + return NOTIFY_DONE; + } + + if (val == PSY_EVENT_PROP_CHANGED && psy == imx_phy->vbus_power_supply) { + ret = power_supply_get_property(imx_phy->vbus_power_supply, + POWER_SUPPLY_PROP_ONLINE, + &propval); + if (ret) { + power_supply_put(imx_phy->vbus_power_supply); + dev_err(dev, "failed to get psy online info\n"); + return NOTIFY_DONE; + } + + if (propval.intval == 0) + imx_phy->chg_type = POWER_SUPPLY_USB_TYPE_UNKNOWN; + } + power_supply_put(imx_phy->vbus_power_supply); + + return NOTIFY_OK; +} + +static int imx8mq_phy_set_mode(struct phy *phy, enum phy_mode mode, + int submode) +{ + struct imx8mq_usb_phy *imx_phy = phy_get_drvdata(phy); + + if (mode == PHY_MODE_USB_DEVICE) + return imx8mq_phy_charger_detect(imx_phy); + + return 0; +} + static struct phy_ops imx8mq_usb_phy_ops = { .init = imx8m_usb_phy_init, .power_on = imx8mq_phy_power_on, .power_off = imx8mq_phy_power_off, + .set_mode = imx8mq_phy_set_mode, .owner = THIS_MODULE, }; @@ -193,12 +446,28 @@ static int imx8mq_usb_phy_probe(struct platform_device *pdev) return PTR_ERR(imx_phy->vbus); phy_set_drvdata(imx_phy->phy, imx_phy); + platform_set_drvdata(pdev, imx_phy); + + if (device_property_present(dev, "vbus-power-supply")) { + imx_phy->chg_det_nb.notifier_call = imx8mq_phy_usb_vbus_notify; + power_supply_reg_notifier(&imx_phy->chg_det_nb); + } phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); return PTR_ERR_OR_ZERO(phy_provider); } +static int imx8mq_usb_phy_remove(struct platform_device *pdev) +{ + struct imx8mq_usb_phy *imx_phy = platform_get_drvdata(pdev); + + if (device_property_present(&pdev->dev, "vbus-power-supply")) + power_supply_unreg_notifier(&imx_phy->chg_det_nb); + + return 0; +} + static const struct of_device_id imx8mq_usb_phy_of_match[] = { {.compatible = "fsl,imx8mq-usb-phy",}, {.compatible = "fsl,imx8mp-usb-phy",}, @@ -208,6 +477,7 @@ MODULE_DEVICE_TABLE(of, imx8mq_usb_phy_of_match); static struct platform_driver imx8mq_usb_phy_driver = { .probe = imx8mq_usb_phy_probe, + .remove = imx8mq_usb_phy_remove, .driver = { .name = "imx8mq-usb-phy", .of_match_table = imx8mq_usb_phy_of_match, diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c index ae58853fcc2c..f608f89f45cd 100644 --- a/drivers/spi/spi-fsl-lpspi.c +++ b/drivers/spi/spi-fsl-lpspi.c @@ -973,6 +973,10 @@ static int fsl_lpspi_probe(struct platform_device *pdev) goto err_disable_runtime_pm; if (ret < 0) dev_err(&pdev->dev, "dma setup error %d, use pio\n", ret); + else + /* disable LPSPI module IRQ when enable DMA mode successfully, + * to prevent the unexpected LPSPI module IRQ events*/ + disable_irq(irq); ret = devm_spi_register_controller(&pdev->dev, controller); if (ret < 0) { diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index 91e32291c44e..0128e33eb5bc 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c @@ -1775,8 +1775,13 @@ static int spi_imx_probe(struct platform_device *pdev) /* Request GPIO CS lines, if any */ if (!spi_imx->slave_mode && master->cs_gpios) { for (i = 0; i < master->num_chipselect; i++) { - if (!gpio_is_valid(master->cs_gpios[i])) + if (!gpio_is_valid(master->cs_gpios[i])) { + if (master->cs_gpios[i] == -EPROBE_DEFER) { + ret = -EPROBE_DEFER; + goto out_spi_bitbang; + } continue; + } ret = devm_gpio_request(&pdev->dev, master->cs_gpios[i], diff --git a/drivers/staging/media/imx/imx8-isi-cap.c b/drivers/staging/media/imx/imx8-isi-cap.c index c50c1d21b6e4..52342029f3fc 100644 --- a/drivers/staging/media/imx/imx8-isi-cap.c +++ b/drivers/staging/media/imx/imx8-isi-cap.c @@ -617,9 +617,8 @@ void mxc_isi_ctrls_delete(struct mxc_isi_cap_dev *isi_cap) } static struct media_pad -*mxc_isi_get_remote_source_pad(struct mxc_isi_cap_dev *isi_cap) +*mxc_isi_get_remote_source_pad(struct v4l2_subdev *subdev) { - struct v4l2_subdev *subdev = &isi_cap->sd; struct media_pad *sink_pad, *source_pad; int i; @@ -644,30 +643,48 @@ static struct media_pad return NULL; } -static struct v4l2_subdev *mxc_get_remote_subdev(struct mxc_isi_cap_dev *isi_cap, +static struct v4l2_subdev *mxc_get_remote_subdev(struct v4l2_subdev *subdev, const char * const label) { struct media_pad *source_pad; struct v4l2_subdev *sen_sd; /* Get remote source pad */ - source_pad = mxc_isi_get_remote_source_pad(isi_cap); + source_pad = mxc_isi_get_remote_source_pad(subdev); if (!source_pad) { - v4l2_err(&isi_cap->sd, - "%s, No remote pad found!\n", label); + v4l2_err(subdev, "%s, No remote pad found!\n", label); return NULL; } /* Get remote source pad subdev */ sen_sd = media_entity_to_v4l2_subdev(source_pad->entity); if (!sen_sd) { - v4l2_err(&isi_cap->sd, "%s, No remote subdev found!\n", label); + v4l2_err(subdev, "%s, No remote subdev found!\n", label); return NULL; } return sen_sd; } +static bool is_entity_link_setup(struct mxc_isi_cap_dev *isi_cap) +{ + struct video_device *vdev = &isi_cap->vdev; + struct v4l2_subdev *csi_sd, *sen_sd; + + if (!vdev->entity.num_links || !isi_cap->sd.entity.num_links) + return false; + + csi_sd = mxc_get_remote_subdev(&isi_cap->sd, __func__); + if (!csi_sd || !csi_sd->entity.num_links) + return false; + + sen_sd = mxc_get_remote_subdev(csi_sd, __func__); + if (!sen_sd || !sen_sd->entity.num_links) + return false; + + return true; +} + static int mxc_isi_capture_open(struct file *file) { struct mxc_isi_cap_dev *isi_cap = video_drvdata(file); @@ -676,12 +693,20 @@ static int mxc_isi_capture_open(struct file *file) struct v4l2_subdev *sd; int ret = -EBUSY; + mutex_lock(&isi_cap->lock); + isi_cap->is_link_setup = is_entity_link_setup(isi_cap); + if (!isi_cap->is_link_setup) { + mutex_unlock(&isi_cap->lock); + return 0; + } + mutex_unlock(&isi_cap->lock); + if (mxc_isi->m2m_enabled) { dev_err(dev, "ISI channel[%d] is busy\n", isi_cap->id); return ret; } - sd = mxc_get_remote_subdev(isi_cap, __func__); + sd = mxc_get_remote_subdev(&isi_cap->sd, __func__); if (!sd) return -ENODEV; @@ -719,7 +744,10 @@ static int mxc_isi_capture_release(struct file *file) struct v4l2_subdev *sd; int ret = -1; - sd = mxc_get_remote_subdev(isi_cap, __func__); + if (!isi_cap->is_link_setup) + return 0; + + sd = mxc_get_remote_subdev(&isi_cap->sd, __func__); if (!sd) goto label; @@ -862,14 +890,14 @@ static int mxc_isi_source_fmt_init(struct mxc_isi_cap_dev *isi_cap) struct v4l2_subdev *src_sd; int ret; - source_pad = mxc_isi_get_remote_source_pad(isi_cap); + source_pad = mxc_isi_get_remote_source_pad(&isi_cap->sd); if (!source_pad) { v4l2_err(&isi_cap->sd, "%s, No remote pad found!\n", __func__); return -EINVAL; } - src_sd = mxc_get_remote_subdev(isi_cap, __func__); + src_sd = mxc_get_remote_subdev(&isi_cap->sd, __func__); if (!src_sd) return -EINVAL; @@ -1010,7 +1038,7 @@ static int mxc_isi_cap_g_parm(struct file *file, void *fh, struct mxc_isi_cap_dev *isi_cap = video_drvdata(file); struct v4l2_subdev *sd; - sd = mxc_get_remote_subdev(isi_cap, __func__); + sd = mxc_get_remote_subdev(&isi_cap->sd, __func__); if (!sd) return -ENODEV; @@ -1023,7 +1051,7 @@ static int mxc_isi_cap_s_parm(struct file *file, void *fh, struct mxc_isi_cap_dev *isi_cap = video_drvdata(file); struct v4l2_subdev *sd; - sd = mxc_get_remote_subdev(isi_cap, __func__); + sd = mxc_get_remote_subdev(&isi_cap->sd, __func__); if (!sd) return -ENODEV; @@ -1179,7 +1207,7 @@ static int mxc_isi_cap_enum_framesizes(struct file *file, void *priv, return -EINVAL; fse.code = fmt->mbus_code; - sd = mxc_get_remote_subdev(isi_cap, __func__); + sd = mxc_get_remote_subdev(&isi_cap->sd, __func__); if (!sd) { v4l2_err(&isi_cap->sd, "Can't find subdev\n"); return -ENODEV; @@ -1233,7 +1261,7 @@ static int mxc_isi_cap_enum_frameintervals(struct file *file, void *fh, return -EINVAL; fie.code = fmt->mbus_code; - sd = mxc_get_remote_subdev(isi_cap, __func__); + sd = mxc_get_remote_subdev(&isi_cap->sd, __func__); if (!sd) return -EINVAL; diff --git a/drivers/staging/media/imx/imx8-isi-core.h b/drivers/staging/media/imx/imx8-isi-core.h index 35f8cbba0ecb..dbf9242873c2 100644 --- a/drivers/staging/media/imx/imx8-isi-core.h +++ b/drivers/staging/media/imx/imx8-isi-core.h @@ -310,6 +310,7 @@ struct mxc_isi_cap_dev { u32 frame_count; u32 id; + bool is_link_setup; struct mutex lock; spinlock_t slock; diff --git a/drivers/staging/media/imx/imx8-media-dev.c b/drivers/staging/media/imx/imx8-media-dev.c index f50a53e5abdb..4962ffcb7e45 100644 --- a/drivers/staging/media/imx/imx8-media-dev.c +++ b/drivers/staging/media/imx/imx8-media-dev.c @@ -177,6 +177,9 @@ static int mxc_md_do_clean(struct mxc_md *mxc_md, struct media_pad *pad) struct media_pad *remote_pad; struct v4l2_subdev *subdev; + if (!pad->entity->num_links) + return 0; + remote_pad = media_entity_remote_pad(pad); if (remote_pad == NULL) { dev_err(dev, "%s get remote pad fail\n", __func__); diff --git a/drivers/staging/media/imx/imx8-mipi-csi2-sam.c b/drivers/staging/media/imx/imx8-mipi-csi2-sam.c index 8d87b2c64970..f7d44dad95a0 100644 --- a/drivers/staging/media/imx/imx8-mipi-csi2-sam.c +++ b/drivers/staging/media/imx/imx8-mipi-csi2-sam.c @@ -657,7 +657,8 @@ static void mipi_csis_phy_reset_mx8mn(struct csi_state *state) usleep_range(10, 20); /* temporary place */ - regmap_write(state->mix_gpr, 0x138, 0x8d8360); + if (state->mix_gpr) + regmap_write(state->mix_gpr, 0x138, 0x8d8360); } static void mipi_csis_system_enable(struct csi_state *state, int on) @@ -1333,6 +1334,7 @@ static long csis_priv_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg_ break; default: v4l2_err(&state->sd, "unsupported csi-sam command %d.", cmd); + ret = -EINVAL; break; } pm_runtime_put(state->dev); @@ -1578,11 +1580,10 @@ static int mipi_csis_probe(struct platform_device *pdev) state->mix_gpr = syscon_regmap_lookup_by_phandle(dev->of_node, "gpr"); if (IS_ERR(state->mix_gpr)) { - dev_err(dev, "failed to get mix gpr\n"); - return PTR_ERR(state->mix_gpr); + dev_warn(dev, "failed to get mix gpr\n"); + state->mix_gpr = NULL; } - mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); state->regs = devm_ioremap_resource(dev, mem_res); if (IS_ERR(state->regs)) diff --git a/drivers/usb/cdns3/core.c b/drivers/usb/cdns3/core.c index 335bc2685d27..2065c2cb1b1d 100644 --- a/drivers/usb/cdns3/core.c +++ b/drivers/usb/cdns3/core.c @@ -458,6 +458,11 @@ static int cdns3_do_role_switch(struct cdns3 *cdns, enum cdns3_roles role) return 0; } + /* + * WORKAROUND: Mass storage gadget calls .ep_disable after + * disconnect with host, wait some time for .ep_disable completion. + */ + msleep(20); cdns_set_role(cdns, role); ret = cdns3_role_start(cdns, role); if (ret) { diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c index 529128086b1a..579e65ababbd 100644 --- a/drivers/usb/chipidea/core.c +++ b/drivers/usb/chipidea/core.c @@ -541,6 +541,13 @@ static irqreturn_t ci_irq(int irq, void *data) u32 otgsc = 0; if (ci->in_lpm) { + /* + * If we already have a wakeup irq pending there, + * let's just return to wait resume finished firstly. + */ + if (ci->wakeup_int) + return IRQ_HANDLED; + disable_irq_nosync(irq); ci->wakeup_int = true; pm_runtime_get(ci->dev); diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index c7beed06336d..cffa801ea1b2 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -103,10 +103,12 @@ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) { u32 reg; - reg = dwc3_readl(dwc->regs, DWC3_GCTL); - reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); - reg |= DWC3_GCTL_PRTCAPDIR(mode); - dwc3_writel(dwc->regs, DWC3_GCTL, reg); + if (mode != DWC3_GCTL_PRTCAP_NONE) { + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); + reg |= DWC3_GCTL_PRTCAPDIR(mode); + dwc3_writel(dwc->regs, DWC3_GCTL, reg); + } dwc->current_dr_role = mode; } @@ -114,20 +116,15 @@ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) static void __dwc3_set_mode(struct work_struct *work) { struct dwc3 *dwc = work_to_dwc(work); + struct dwc3_platform_data *dwc3_pdata; unsigned long flags; int ret; - if (dwc->dr_mode != USB_DR_MODE_OTG) - return; - pm_runtime_get_sync(dwc->dev); if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) dwc3_otg_update(dwc, 0); - if (!dwc->desired_dr_role) - goto out; - if (dwc->desired_dr_role == dwc->current_dr_role) goto out; @@ -191,8 +188,9 @@ static void __dwc3_set_mode(struct work_struct *work) break; } - if (dwc->priv_data && dwc->priv_data->set_role_post) - dwc->priv_data->set_role_post(dwc, dwc->desired_dr_role); + dwc3_pdata = (struct dwc3_platform_data *)dev_get_platdata(dwc->dev); + if (dwc3_pdata && dwc3_pdata->set_role_post) + dwc3_pdata->set_role_post(dwc, dwc->desired_dr_role); out: pm_runtime_mark_last_busy(dwc->dev); @@ -203,6 +201,9 @@ void dwc3_set_mode(struct dwc3 *dwc, u32 mode) { unsigned long flags; + if (dwc->dr_mode != USB_DR_MODE_OTG) + return; + spin_lock_irqsave(&dwc->lock, flags); dwc->desired_dr_role = mode; spin_unlock_irqrestore(&dwc->lock, flags); @@ -302,25 +303,32 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc) */ static void dwc3_frame_length_adjustment(struct dwc3 *dwc) { + struct dwc3_platform_data *dwc3_pdata; u32 reg; u32 dft; - /* - * if GCTL.SOFITPSYNC is set to '1': - * FLADJ_REF_CLK_FLADJ= - * ((125000/ref_clk_period_integer)-(125000/ref_clk_period)) * - * ref_clk_period - * where - * - the ref_clk_period_integer is the integer value of - * the ref_clk period got by truncating the decimal (fractional) - * value that is programmed in the GUCTL.REF_CLK_PERIOD field. - * - the ref_clk_period is the ref_clk period including the fractional - * value. - */ - if (dwc->soft_itp_sync_quirk) { + dwc3_pdata = (struct dwc3_platform_data *)dev_get_platdata(dwc->dev); + if (dwc3_pdata && dwc3_pdata->quirks & DWC3_SOFT_ITP_SYNC) { u32 ref_clk_hz, ref_clk_period_integer; u64 temp; + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + reg |= DWC3_GCTL_SOFITPSYNC; + dwc3_writel(dwc->regs, DWC3_GCTL, reg); + + /* + * if GCTL.SOFITPSYNC is set to '1': + * FLADJ_REF_CLK_FLADJ= + * ((125000/ref_clk_period_integer)-(125000/ref_clk_period)) * + * ref_clk_period + * where + * - the ref_clk_period_integer is the integer value of + * the ref_clk period got by truncating the decimal + * (fractional) value that is programmed in the + * GUCTL.REF_CLK_PERIOD field. + * - the ref_clk_period is the ref_clk period including + * the fractional value. + */ reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); ref_clk_hz = clk_get_rate(dwc->clks[0].clk); if (ref_clk_hz == 0) { @@ -837,9 +845,6 @@ static void dwc3_core_setup_global_control(struct dwc3 *dwc) if (dwc->revision < DWC3_REVISION_190A) reg |= DWC3_GCTL_U2RSTECN; - if (dwc->soft_itp_sync_quirk) - reg |= DWC3_GCTL_SOFITPSYNC; - dwc3_writel(dwc->regs, DWC3_GCTL, reg); } @@ -1281,6 +1286,7 @@ static int dwc3_core_get_phy(struct dwc3 *dwc) static int dwc3_core_init_mode(struct dwc3 *dwc) { struct device *dev = dwc->dev; + struct dwc3_platform_data *dwc3_pdata; int ret; switch (dwc->dr_mode) { @@ -1328,6 +1334,10 @@ static int dwc3_core_init_mode(struct dwc3 *dwc) return -EINVAL; } + dwc3_pdata = (struct dwc3_platform_data *)dev_get_platdata(dwc->dev); + if (dwc3_pdata && dwc3_pdata->set_role_post) + dwc3_pdata->set_role_post(dwc, dwc->current_dr_role); + return 0; } @@ -1472,9 +1482,6 @@ static void dwc3_get_properties(struct dwc3 *dwc) dwc->host_vbus_glitches = device_property_read_bool(dev, "snps,host-vbus-glitches"); - dwc->soft_itp_sync_quirk = device_property_read_bool(dev, - "snps,soft-itp-sync"); - dwc->lpm_nyet_threshold = lpm_nyet_threshold; dwc->tx_de_emphasis = tx_de_emphasis; @@ -1709,9 +1716,9 @@ static int dwc3_remove(struct platform_device *pdev) dwc3_core_exit(dwc); dwc3_ulpi_exit(dwc); - pm_runtime_put_sync(&pdev->dev); - pm_runtime_allow(&pdev->dev); pm_runtime_disable(&pdev->dev); + pm_runtime_put_noidle(&pdev->dev); + pm_runtime_set_suspended(&pdev->dev); dwc3_free_event_buffers(dwc); dwc3_free_scratch_buffers(dwc); @@ -1752,6 +1759,11 @@ static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) u32 reg; switch (dwc->current_dr_role) { + case DWC3_GCTL_PRTCAP_NONE: + if (pm_runtime_suspended(dwc->dev)) + break; + dwc3_core_exit(dwc); + break; case DWC3_GCTL_PRTCAP_DEVICE: if (pm_runtime_suspended(dwc->dev)) break; @@ -1812,6 +1824,14 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) u32 reg; switch (dwc->current_dr_role) { + case DWC3_GCTL_PRTCAP_NONE: + if (dwc->core_inited) + break; + + ret = dwc3_core_init_for_resume(dwc); + if (ret) + return ret; + break; case DWC3_GCTL_PRTCAP_DEVICE: /* * system resume may come after runtime resume diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index f59651460414..530c885a33c9 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -29,6 +29,7 @@ #include #include +#include "../host/xhci-plat.h" #define DWC3_MSG_MAX 500 @@ -249,6 +250,7 @@ #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) +#define DWC3_GCTL_PRTCAP_NONE 0 #define DWC3_GCTL_PRTCAP_HOST 1 #define DWC3_GCTL_PRTCAP_DEVICE 2 #define DWC3_GCTL_PRTCAP_OTG 3 @@ -937,8 +939,11 @@ struct dwc3_scratchpad_array { __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; }; -struct dwc3_priv_data { +struct dwc3_platform_data { + struct xhci_plat_priv *xhci_priv; void (*set_role_post)(struct dwc3 *dwc, u32 role); + unsigned long long quirks; +#define DWC3_SOFT_ITP_SYNC BIT(0) }; /** @@ -1268,7 +1273,6 @@ struct dwc3 { unsigned dis_metastability_quirk:1; unsigned host_vbus_glitches:1; - unsigned soft_itp_sync_quirk:1; u16 imod_interval; }; diff --git a/drivers/usb/dwc3/drd.c b/drivers/usb/dwc3/drd.c index 8e26fbbdc6ff..9b522396746b 100644 --- a/drivers/usb/dwc3/drd.c +++ b/drivers/usb/dwc3/drd.c @@ -488,7 +488,7 @@ static int dwc3_usb_role_switch_set(struct device *dev, enum usb_role role) mode = DWC3_GCTL_PRTCAP_DEVICE; break; default: - mode = DWC3_GCTL_PRTCAP_DEVICE; + mode = DWC3_GCTL_PRTCAP_NONE; break; }; diff --git a/drivers/usb/dwc3/dwc3-imx8mp.c b/drivers/usb/dwc3/dwc3-imx8mp.c index 0ef3dfc2a5da..0235ea22abbd 100644 --- a/drivers/usb/dwc3/dwc3-imx8mp.c +++ b/drivers/usb/dwc3/dwc3-imx8mp.c @@ -43,6 +43,7 @@ struct dwc3_imx8mp { struct platform_device *dwc3; void __iomem *glue_base; struct clk *hsio_clk; + struct clk *suspend_clk; int irq; bool pm_suspended; bool wakeup_pending; @@ -53,6 +54,9 @@ static void dwc_imx8mp_wakeup_enable(struct dwc3_imx8mp *dwc_imx) struct dwc3 *dwc = platform_get_drvdata(dwc_imx->dwc3); u32 val; + if (!dwc) + return; + val = readl(dwc_imx->glue_base + USB_WAKEUP_CTRL); if ((dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) && dwc->xhci) @@ -63,6 +67,7 @@ static void dwc_imx8mp_wakeup_enable(struct dwc3_imx8mp *dwc_imx) USB_WAKEUP_VBUS_SRC_SESS_VAL; writel(val, dwc_imx->glue_base + USB_WAKEUP_CTRL); + } static void dwc_imx8mp_wakeup_disable(struct dwc3_imx8mp *dwc_imx) @@ -96,6 +101,12 @@ static irqreturn_t dwc3_imx8mp_interrupt(int irq, void *_dwc_imx) disable_irq_nosync(dwc_imx->irq); dwc_imx->wakeup_pending = true; + + if (!dwc) { + pm_runtime_resume(dwc_imx->dev); + return IRQ_HANDLED; + } + /* * runtime resume xhci or gadget, dwc3_imx8mp itself * as parent device will be resumed firstly by pm core @@ -129,12 +140,31 @@ static void dwc3_imx8mp_set_role_post(struct dwc3 *dwc, u32 role) } } +static struct xhci_plat_priv dwc3_imx8mp_xhci_priv = { + .quirks = XHCI_NO_64BIT_SUPPORT | + XHCI_MISSING_CAS | + XHCI_SKIP_PHY_INIT, +}; + +static struct dwc3_platform_data dwc3_imx8mp_pdata = { + .xhci_priv = &dwc3_imx8mp_xhci_priv, + .set_role_post = dwc3_imx8mp_set_role_post, + .quirks = DWC3_SOFT_ITP_SYNC, +}; + +static struct of_dev_auxdata dwc3_imx8mp_auxdata[] = { + { + .compatible = "snps,dwc3", + .platform_data = &dwc3_imx8mp_pdata, + }, + {}, +}; + static int dwc3_imx8mp_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct device_node *dwc3_np, *node = dev->of_node; struct dwc3_imx8mp *dwc_imx; - struct dwc3 *dwc; int error, irq; if (!node) { @@ -169,6 +199,19 @@ static int dwc3_imx8mp_probe(struct platform_device *pdev) goto rel_high_bus; } + dwc_imx->suspend_clk = devm_clk_get(dev, "suspend"); + if (IS_ERR(dwc_imx->suspend_clk)) { + error = PTR_ERR(dwc_imx->suspend_clk); + dev_err(dev, "Failed to get suspend clk, err=%d\n", error); + goto disable_hsio_clk; + } + + error = clk_prepare_enable(dwc_imx->suspend_clk); + if (error) { + dev_err(dev, "Failed to enable suspend clk, err=%d\n", error); + goto disable_hsio_clk; + } + irq = platform_get_irq(pdev, 0); if (irq < 0) { error = irq; @@ -190,7 +233,7 @@ static int dwc3_imx8mp_probe(struct platform_device *pdev) goto disable_clks; } - error = of_platform_populate(node, NULL, NULL, dev); + error = of_platform_populate(node, NULL, dwc3_imx8mp_auxdata, dev); if (error) { dev_err(&pdev->dev, "failed to create dwc3 core\n"); goto disable_clks; @@ -202,25 +245,7 @@ static int dwc3_imx8mp_probe(struct platform_device *pdev) error = -ENODEV; goto depopulate; } - - dwc = platform_get_drvdata(dwc_imx->dwc3); - if (!dwc) { - error = -EPROBE_DEFER; - goto depopulate; - } - - dwc->priv_data = devm_kzalloc(dev, sizeof(struct dwc3_priv_data), - GFP_KERNEL); - if (!dwc->priv_data) { - error = -ENOMEM; - goto depopulate; - } - dwc->priv_data->set_role_post = dwc3_imx8mp_set_role_post; - - if (dwc->dr_mode == USB_DR_MODE_HOST) - dwc->priv_data->set_role_post(dwc, DWC3_GCTL_PRTCAP_HOST); - else if (dwc->dr_mode == USB_DR_MODE_PERIPHERAL) - dwc->priv_data->set_role_post(dwc, DWC3_GCTL_PRTCAP_DEVICE); + of_node_put(dwc3_np); device_set_wakeup_capable(dev, true); pm_runtime_set_active(dev); @@ -231,6 +256,8 @@ static int dwc3_imx8mp_probe(struct platform_device *pdev) depopulate: of_platform_depopulate(dev); disable_clks: + clk_disable_unprepare(dwc_imx->suspend_clk); +disable_hsio_clk: clk_disable_unprepare(dwc_imx->hsio_clk); rel_high_bus: release_bus_freq(BUS_FREQ_HIGH); @@ -287,7 +314,7 @@ static int dwc3_imx8mp_resume(struct dwc3_imx8mp *dwc_imx, pm_message_t msg) if (dwc_imx->wakeup_pending) { dwc_imx->wakeup_pending = false; - if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_DEVICE) { + if (dwc && dwc->current_dr_role == DWC3_GCTL_PRTCAP_DEVICE) { pm_runtime_mark_last_busy(dwc->dev); pm_runtime_put_autosuspend(dwc->dev); } @@ -304,10 +331,12 @@ static int __maybe_unused dwc3_imx8mp_pm_suspend(struct device *dev) ret = dwc3_imx8mp_suspend(dwc_imx, PMSG_SUSPEND); - if (device_may_wakeup(dwc_imx->dev)) + if (device_may_wakeup(dwc_imx->dev)) { enable_irq_wake(dwc_imx->irq); - else + } else { dwc_imx8mp_wakeup_disable_u3(dwc_imx); + clk_disable_unprepare(dwc_imx->suspend_clk); + } clk_disable_unprepare(dwc_imx->hsio_clk); @@ -319,8 +348,13 @@ static int __maybe_unused dwc3_imx8mp_pm_resume(struct device *dev) struct dwc3_imx8mp *dwc_imx = dev_get_drvdata(dev); int ret; - if (device_may_wakeup(dwc_imx->dev)) + if (device_may_wakeup(dwc_imx->dev)) { disable_irq_wake(dwc_imx->irq); + } else { + ret = clk_prepare_enable(dwc_imx->suspend_clk); + if (ret) + return ret; + } ret = clk_prepare_enable(dwc_imx->hsio_clk); if (ret) diff --git a/drivers/usb/dwc3/host.c b/drivers/usb/dwc3/host.c index 05047911a884..b71c5b828b71 100644 --- a/drivers/usb/dwc3/host.c +++ b/drivers/usb/dwc3/host.c @@ -89,6 +89,7 @@ int dwc3_host_init(struct dwc3 *dwc) int ret, irq; struct resource *res; struct platform_device *dwc3_pdev = to_platform_device(dwc->dev); + struct dwc3_platform_data *dwc3_pdata; int prop_idx = 0; /* @@ -161,6 +162,14 @@ int dwc3_host_init(struct dwc3 *dwc) } } + dwc3_pdata = (struct dwc3_platform_data *)dev_get_platdata(dwc->dev); + if (dwc3_pdata && dwc3_pdata->xhci_priv) { + ret = platform_device_add_data(xhci, dwc3_pdata->xhci_priv, + sizeof(struct xhci_plat_priv)); + if (ret) + goto err; + } + ret = platform_device_add(xhci); if (ret) { dev_err(dwc->dev, "failed to register xHCI device\n"); diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c index cd1c92f24a26..fa7f313f23d0 100644 --- a/drivers/usb/host/xhci-plat.c +++ b/drivers/usb/host/xhci-plat.c @@ -163,6 +163,8 @@ static int xhci_plat_probe(struct platform_device *pdev) struct usb_hcd *hcd; int ret; int irq; + struct xhci_plat_priv *priv = NULL; + if (usb_disabled()) return -ENODEV; @@ -255,13 +257,15 @@ static int xhci_plat_probe(struct platform_device *pdev) if (ret) goto disable_reg_clk; - priv_match = of_device_get_match_data(&pdev->dev); - if (priv_match) { - struct xhci_plat_priv *priv = hcd_to_xhci_priv(hcd); + if (pdev->dev.of_node) + priv_match = of_device_get_match_data(&pdev->dev); + else + priv_match = dev_get_platdata(&pdev->dev); + if (priv_match) { + priv = hcd_to_xhci_priv(hcd); /* Just copy data for now */ - if (priv_match) - *priv = *priv_match; + *priv = *priv_match; } device_wakeup_enable(hcd->self.controller); @@ -315,6 +319,9 @@ static int xhci_plat_probe(struct platform_device *pdev) hcd->tpl_support = of_usb_host_tpl_support(sysdev->of_node); xhci->shared_hcd->tpl_support = hcd->tpl_support; + if (priv && (priv->quirks & XHCI_SKIP_PHY_INIT)) + hcd->skip_phy_initialization = 1; + ret = usb_add_hcd(hcd, irq, IRQF_SHARED); if (ret) goto disable_usb_phy; diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index 5af41ae9ac16..a7955a94556b 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -1874,6 +1874,7 @@ struct xhci_hcd { #define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34) #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35) #define XHCI_CDNS_HOST BIT_ULL(36) +#define XHCI_SKIP_PHY_INIT BIT_ULL(37) unsigned int num_active_eps; unsigned int limit_active_eps; diff --git a/drivers/usb/phy/phy-mxs-usb.c b/drivers/usb/phy/phy-mxs-usb.c index e692e88a6374..4ac3746f769c 100644 --- a/drivers/usb/phy/phy-mxs-usb.c +++ b/drivers/usb/phy/phy-mxs-usb.c @@ -20,6 +20,7 @@ #include #include #include +#include #define DRIVER_NAME "mxs_phy" @@ -606,7 +607,9 @@ static int mxs_phy_suspend(struct usb_phy *x, int suspend) if (!(mxs_phy->port_id == 1 && mxs_phy->hardware_control_phy2_clk)) clk_disable_unprepare(mxs_phy->clk); + pm_runtime_put(x->dev); } else { + pm_runtime_get_sync(x->dev); mxs_phy_clock_switch_delay(); if (!(mxs_phy->port_id == 1 && mxs_phy->hardware_control_phy2_clk)) { @@ -1124,6 +1127,10 @@ static int mxs_phy_probe(struct platform_device *pdev) device_set_wakeup_capable(&pdev->dev, true); + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + pm_runtime_get_noresume(&pdev->dev); + return usb_add_phy_dev(&mxs_phy->phy); } @@ -1132,10 +1139,15 @@ static int mxs_phy_remove(struct platform_device *pdev) struct mxs_phy *mxs_phy = platform_get_drvdata(pdev); usb_remove_phy(&mxs_phy->phy); + pm_runtime_get_sync(&pdev->dev); + pm_runtime_disable(&pdev->dev); + pm_runtime_put_noidle(&pdev->dev); return 0; } +#ifdef CONFIG_PM + #ifdef CONFIG_PM_SLEEP static void mxs_phy_wakeup_enable(struct mxs_phy *mxs_phy, bool on) { @@ -1202,12 +1214,29 @@ static int mxs_phy_system_resume(struct device *dev) mxs_phy_wakeup_enable(mxs_phy, false); } + pm_runtime_disable(dev); + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + return 0; } #endif /* CONFIG_PM_SLEEP */ -static SIMPLE_DEV_PM_OPS(mxs_phy_pm, mxs_phy_system_suspend, - mxs_phy_system_resume); +static int mxs_phy_runtime_resume(struct device *dev) +{ + return 0; +} + +static int mxs_phy_runtime_suspend(struct device *dev) +{ + return 0; +} +#endif /* CONFIG_PM */ + +static const struct dev_pm_ops mxs_phy_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(mxs_phy_system_suspend, mxs_phy_system_resume) + SET_RUNTIME_PM_OPS(mxs_phy_runtime_suspend, mxs_phy_runtime_resume, NULL) +}; static struct platform_driver mxs_phy_driver = { .probe = mxs_phy_probe, @@ -1215,7 +1244,7 @@ static struct platform_driver mxs_phy_driver = { .driver = { .name = DRIVER_NAME, .of_match_table = mxs_phy_dt_ids, - .pm = &mxs_phy_pm, + .pm = &mxs_phy_pm_ops, }, }; diff --git a/drivers/usb/typec/tcpm/tcpm.c b/drivers/usb/typec/tcpm/tcpm.c index e8f428d718a2..2b9cad16a8e3 100644 --- a/drivers/usb/typec/tcpm/tcpm.c +++ b/drivers/usb/typec/tcpm/tcpm.c @@ -4586,7 +4586,7 @@ static enum power_supply_property tcpm_psy_props[] = { static int tcpm_psy_get_online(struct tcpm_port *port, union power_supply_propval *val) { - if (port->vbus_charge) { + if (port->vbus_present && tcpm_port_is_sink(port)) { if (port->pps_data.active) val->intval = TCPM_PSY_PROG_ONLINE; else @@ -4728,6 +4728,9 @@ static int tcpm_psy_set_prop(struct power_supply *psy, else ret = tcpm_pps_set_op_curr(port, val->intval / 1000); break; + case POWER_SUPPLY_PROP_USB_TYPE: + port->usb_type = val->intval; + break; default: ret = -EINVAL; break; @@ -4750,6 +4753,10 @@ static int tcpm_psy_prop_writeable(struct power_supply *psy, } static enum power_supply_usb_type tcpm_psy_usb_types[] = { + POWER_SUPPLY_USB_TYPE_SDP, + POWER_SUPPLY_USB_TYPE_DCP, + POWER_SUPPLY_USB_TYPE_CDP, + POWER_SUPPLY_USB_TYPE_ACA, POWER_SUPPLY_USB_TYPE_C, POWER_SUPPLY_USB_TYPE_PD, POWER_SUPPLY_USB_TYPE_PD_PPS, diff --git a/drivers/watchdog/imx7ulp_wdt.c b/drivers/watchdog/imx7ulp_wdt.c index 6fecc59d7daa..014f497ea0dc 100644 --- a/drivers/watchdog/imx7ulp_wdt.c +++ b/drivers/watchdog/imx7ulp_wdt.c @@ -4,8 +4,8 @@ */ #include -#include #include +#include #include #include #include @@ -17,8 +17,13 @@ #define WDOG_CS_CMD32EN BIT(13) #define WDOG_CS_ULK BIT(11) #define WDOG_CS_RCS BIT(10) +#define LPO_CLK 0x1 +#define LPO_CLK_SHIFT 8 +#define WDOG_CS_CLK (LPO_CLK << LPO_CLK_SHIFT) #define WDOG_CS_EN BIT(7) #define WDOG_CS_UPDATE BIT(5) +#define WDOG_CS_WAIT BIT(1) +#define WDOG_CS_STOP BIT(0) #define WDOG_CNT 0x4 #define WDOG_TOVAL 0x8 @@ -34,6 +39,7 @@ #define DEFAULT_TIMEOUT 60 #define MAX_TIMEOUT 128 #define WDOG_CLOCK_RATE 1000 +#define WDOG_WAIT_TIMEOUT 20 static bool nowayout = WATCHDOG_NOWAYOUT; module_param(nowayout, bool, 0000); @@ -41,24 +47,48 @@ MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); struct imx7ulp_wdt_device { - struct notifier_block restart_handler; struct watchdog_device wdd; void __iomem *base; struct clk *clk; }; -static inline void imx7ulp_wdt_enable(void __iomem *base, bool enable) +static int imx7ulp_wdt_wait(void __iomem *base, u32 mask) { u32 val = readl(base + WDOG_CS); - writel(UNLOCK, base + WDOG_CNT); + if (!(val & mask) && readl_poll_timeout_atomic(base + WDOG_CS, val, + val & mask, 0, + WDOG_WAIT_TIMEOUT)) + return -ETIMEDOUT; + + return 0; +} + +static int imx7ulp_wdt_enable(struct watchdog_device *wdog, bool enable) +{ + struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog); + + u32 val = readl(wdt->base + WDOG_CS); + int ret; + + local_irq_disable(); + writel(UNLOCK, wdt->base + WDOG_CNT); + ret = imx7ulp_wdt_wait(wdt->base, WDOG_CS_ULK); + if (ret) + goto enable_out; if (enable) - writel(val | WDOG_CS_EN, base + WDOG_CS); + writel(val | WDOG_CS_EN, wdt->base + WDOG_CS); else - writel(val & ~WDOG_CS_EN, base + WDOG_CS); + writel(val & ~WDOG_CS_EN, wdt->base + WDOG_CS); + imx7ulp_wdt_wait(wdt->base, WDOG_CS_RCS); + +enable_out: + local_irq_enable(); + + return ret; } -static inline bool imx7ulp_wdt_is_enabled(void __iomem *base) +static bool imx7ulp_wdt_is_enabled(void __iomem *base) { u32 val = readl(base + WDOG_CS); @@ -76,20 +106,12 @@ static int imx7ulp_wdt_ping(struct watchdog_device *wdog) static int imx7ulp_wdt_start(struct watchdog_device *wdog) { - struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog); - - imx7ulp_wdt_enable(wdt->base, true); - - return 0; + return imx7ulp_wdt_enable(wdog, true); } static int imx7ulp_wdt_stop(struct watchdog_device *wdog) { - struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog); - - imx7ulp_wdt_enable(wdt->base, false); - - return 0; + return imx7ulp_wdt_enable(wdog, false); } static int imx7ulp_wdt_set_timeout(struct watchdog_device *wdog, @@ -97,22 +119,37 @@ static int imx7ulp_wdt_set_timeout(struct watchdog_device *wdog, { struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog); u32 val = WDOG_CLOCK_RATE * timeout; + int ret; + local_irq_disable(); writel(UNLOCK, wdt->base + WDOG_CNT); + ret = imx7ulp_wdt_wait(wdt->base, WDOG_CS_ULK); + if (ret) + goto timeout_out; writel(val, wdt->base + WDOG_TOVAL); + imx7ulp_wdt_wait(wdt->base, WDOG_CS_RCS); wdog->timeout = timeout; - return 0; +timeout_out: + local_irq_enable(); + + return ret; } static int imx7ulp_wdt_restart(struct watchdog_device *wdog, unsigned long action, void *data) { struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog); + int ret; - imx7ulp_wdt_enable(wdt->base, true); - imx7ulp_wdt_set_timeout(&wdt->wdd, 1); + ret = imx7ulp_wdt_enable(wdog, true); + if (ret) + return ret; + + ret = imx7ulp_wdt_set_timeout(&wdt->wdd, 1); + if (ret) + return ret; /* wait for wdog to fire */ while (true) @@ -136,19 +173,31 @@ static const struct watchdog_info imx7ulp_wdt_info = { WDIOF_MAGICCLOSE, }; -static inline void imx7ulp_wdt_init(void __iomem *base, unsigned int timeout) +static int imx7ulp_wdt_init(void __iomem *base, unsigned int timeout) { u32 val; + int ret; + local_irq_disable(); /* unlock the wdog for reconfiguration */ writel_relaxed(UNLOCK_SEQ0, base + WDOG_CNT); writel_relaxed(UNLOCK_SEQ1, base + WDOG_CNT); + ret = imx7ulp_wdt_wait(base, WDOG_CS_ULK); + if (ret) + goto init_out; /* set an initial timeout value in TOVAL */ writel(timeout, base + WDOG_TOVAL); /* enable 32bit command sequence and reconfigure */ - val = BIT(13) | BIT(8) | BIT(5) | BIT(1) | BIT(0); + val = WDOG_CS_CMD32EN | WDOG_CS_CLK | WDOG_CS_UPDATE | + WDOG_CS_WAIT | WDOG_CS_STOP; writel(val, base + WDOG_CS); + imx7ulp_wdt_wait(base, WDOG_CS_RCS); + +init_out: + local_irq_enable(); + + return ret; } static void imx7ulp_wdt_action(void *data) @@ -199,12 +248,14 @@ static int imx7ulp_wdt_probe(struct platform_device *pdev) watchdog_stop_on_reboot(wdog); watchdog_stop_on_unregister(wdog); watchdog_set_drvdata(wdog, imx7ulp_wdt); - imx7ulp_wdt_init(imx7ulp_wdt->base, wdog->timeout * WDOG_CLOCK_RATE); + ret = imx7ulp_wdt_init(imx7ulp_wdt->base, wdog->timeout * WDOG_CLOCK_RATE); + if (ret) + return ret; return devm_watchdog_register_device(dev, wdog); } -static int __maybe_unused imx7ulp_wdt_suspend(struct device *dev) +static int __maybe_unused imx7ulp_wdt_suspend_noirq(struct device *dev) { struct imx7ulp_wdt_device *imx7ulp_wdt = dev_get_drvdata(dev); @@ -216,7 +267,7 @@ static int __maybe_unused imx7ulp_wdt_suspend(struct device *dev) return 0; } -static int __maybe_unused imx7ulp_wdt_resume(struct device *dev) +static int __maybe_unused imx7ulp_wdt_resume_noirq(struct device *dev) { struct imx7ulp_wdt_device *imx7ulp_wdt = dev_get_drvdata(dev); u32 timeout = imx7ulp_wdt->wdd.timeout * WDOG_CLOCK_RATE; @@ -235,8 +286,10 @@ static int __maybe_unused imx7ulp_wdt_resume(struct device *dev) return 0; } -static SIMPLE_DEV_PM_OPS(imx7ulp_wdt_pm_ops, imx7ulp_wdt_suspend, - imx7ulp_wdt_resume); +static const struct dev_pm_ops imx7ulp_wdt_pm_ops = { + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx7ulp_wdt_suspend_noirq, + imx7ulp_wdt_resume_noirq) +}; static const struct of_device_id imx7ulp_wdt_dt_ids[] = { { .compatible = "fsl,imx7ulp-wdt", }, diff --git a/include/sound/sof/topology.h b/include/sound/sof/topology.h index c47b36240920..534c3e160e0d 100644 --- a/include/sound/sof/topology.h +++ b/include/sound/sof/topology.h @@ -36,6 +36,10 @@ enum sof_comp_type { SOF_COMP_KPB, /* A key phrase buffer component */ SOF_COMP_SELECTOR, /**< channel selector component */ SOF_COMP_DEMUX, + SOF_COMP_ASRC, + SOF_COMP_DCBLOCK, + SOF_COMP_PP, + /* keep FILEREAD/FILEWRITE as the last ones */ SOF_COMP_FILEREAD = 10000, /**< host test based file IO */ SOF_COMP_FILEWRITE = 10001, /**< host test based file IO */ @@ -178,6 +182,8 @@ enum sof_ipc_process_type { SOF_PROCESS_CHAN_SELECTOR, /**< Channel Selector */ SOF_PROCESS_MUX, SOF_PROCESS_DEMUX, + SOF_PROCESS_DCBLOCK, + SOF_PROCESS_PP, /** < Post process */ }; /* generic "effect", "codec" or proprietary processing component */ diff --git a/sound/soc/sof/imx/imx8.c b/sound/soc/sof/imx/imx8.c index f6d934f8358e..28d5981e3aa9 100644 --- a/sound/soc/sof/imx/imx8.c +++ b/sound/soc/sof/imx/imx8.c @@ -523,8 +523,8 @@ struct snd_sof_dsp_ops sof_imx8x_ops = { /* PM */ .suspend = imx8_dsp_suspend, .resume = imx8_dsp_resume, - .runtime_suspend = imx8_dsp_suspend, - .runtime_resume = imx8_dsp_resume, + .runtime_suspend = imx8_dsp_runtime_suspend, + .runtime_resume = imx8_dsp_runtime_resume, /* ALSA HW info flags */ .hw_info = SNDRV_PCM_INFO_MMAP | diff --git a/sound/soc/sof/topology.c b/sound/soc/sof/topology.c index 5e86072e057a..bbe9069e8464 100644 --- a/sound/soc/sof/topology.c +++ b/sound/soc/sof/topology.c @@ -406,6 +406,7 @@ static const struct sof_process_types sof_process[] = { {"CHAN_SELECTOR", SOF_PROCESS_CHAN_SELECTOR, SOF_COMP_SELECTOR}, {"MUX", SOF_PROCESS_MUX, SOF_COMP_MUX}, {"DEMUX", SOF_PROCESS_DEMUX, SOF_COMP_DEMUX}, + {"POST_PROCESS", SOF_PROCESS_PP, SOF_COMP_PP}, }; static enum sof_ipc_process_type find_process(const char *name) diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/imx8qxp-ddr-uncore.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/imx8qxp-ddr-uncore.json index f3f57a3d48b4..9a399b52c178 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/imx8qxp-ddr-uncore.json +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/imx8qxp-ddr-uncore.json @@ -1,4 +1,13 @@ [ + { + "PublicDescription": "lpddr4 mek board bandwidth usage", + "BriefDescription": "imx8qxp: percentage of bandwidth usage for ddr0", + "MetricName": "imx8qxp-ddr0-bandwidth-usage", + "MetricExpr": "(( imx8_ddr0\\/read\\-cycles\\/ + imx8_ddr0\\/write\\-cycles\\/ ) * 4 * 4 / duration_time) / (600 * 1000000 * 4 * 4)", + "MetricGroup": "i.MX8QXP_DDR_MON", + "ScaleUnit": "1e2%", + "SocName": "i.MX8QXP" + }, { "PublicDescription": "Calculate bytes all masters read from DDR based on read-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 4 bytes of each beat if DDR burst width is 32 bit.", "BriefDescription": "imx8qxp: bytes of all masters read from ddr0", diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/imx8mm-ddr-uncore.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/imx8mm-ddr-uncore.json index 673275162406..db64fa9f66b5 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/imx8mm-ddr-uncore.json +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/imx8mm-ddr-uncore.json @@ -1,4 +1,23 @@ [ + { + "PublicDescription": "lpddr4 evk board bandwidth usage", + "BriefDescription": "imx8mm: percentage of bandwidth usage for ddr0", + "MetricName": "imx8mm-ddr0-bandwidth-usage-lpddr4", + "MetricExpr": "(( imx8_ddr0\\/read\\-cycles\\/ + imx8_ddr0\\/write\\-cycles\\/) * 4 * 4 / duration_time) / (750 * 1000000 * 4 * 4)", + "MetricGroup": "i.MX8MM_DDR_MON", + "ScaleUnit": "1e2%", + "SocName": "i.MX8MM" + }, + { + "PublicDescription": "ddr4 evk board bandwidth usage", + "BriefDescription": "imx8mm: percentage of bandwidth usage for ddr0", + "MetricName": "imx8mm-ddr0-bandwidth-usage-ddr4", + "MetricExpr": "(( imx8_ddr0\\/read\\-cycles\\/ + imx8_ddr0\\/write\\-cycles\\/) * 4 * 4 / duration_time) / (600 * 1000000 * 4 * 4)", + "MetricGroup": "i.MX8MM_DDR_MON", + "ScaleUnit": "1e2%", + "SocName": "i.MX8MM" + }, + { "PublicDescription": "Calculate bytes all masters read from DDR based on read-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 4 bytes of each beat if DDR burst width is 32 bit.", "BriefDescription": "imx8mm: bytes of all masters read from ddr0", diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/imx8mn-ddr-uncore.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/imx8mn-ddr-uncore.json new file mode 100644 index 000000000000..27d64e1cb76b --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/imx8mn-ddr-uncore.json @@ -0,0 +1,37 @@ +[ + { + "PublicDescription": "lpddr4 evk board bandwidth usage", + "BriefDescription": "imx8mn: percentage of bandwidth usage for ddr0", + "MetricName": "imx8mn-ddr0-bandwidth-usage-lpddr4", + "MetricExpr": "(( imx8_ddr0\\/read\\-cycles\\/ + imx8_ddr0\\/write\\-cycles\\/) * 4 * 4 / duration_time) / (800 * 1000000 * 4 * 4)", + "MetricGroup": "i.MX8MN_DDR_MON", + "ScaleUnit": "1e2%", + "SocName": "i.MX8MN" + }, + { + "PublicDescription": "ddr4 evk board bandwidth usage", + "BriefDescription": "imx8mn: percentage of bandwidth usage for ddr0", + "MetricName": "imx8mn-ddr0-bandwidth-usage-ddr4", + "MetricExpr": "(( imx8_ddr0\\/read\\-cycles\\/ + imx8_ddr0\\/write\\-cycles\\/) * 4 * 4 / duration_time) / (600 * 1000000 * 4 * 4)", + "MetricGroup": "i.MX8MN_DDR_MON", + "ScaleUnit": "1e2%", + "SocName": "i.MX8MN" + }, + + { + "PublicDescription": "Calculate bytes all masters read from DDR based on read-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 4 bytes of each beat if DDR burst width is 32 bit.", + "BriefDescription": "imx8mn: bytes of all masters read from ddr0", + "MetricName": "imx8mn-ddr0-all-r", + "MetricExpr": "imx8_ddr0\\/read\\-cycles\\/ * 4 * 4", + "MetricGroup": "i.MX8MN_DDR_MON", + "SocName": "i.MX8MN" + }, + { + "PublicDescription": "Calculate bytes all masters write to DDR based on write-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 4 bytes of each beat if DDR burst width is 32 bit.", + "BriefDescription": "imx8mn: bytes of all masters write to ddr0", + "MetricName": "imx8mn-ddr0-all-w", + "MetricExpr": "imx8_ddr0\\/write\\-cycles\\/ * 4 * 4", + "MetricGroup": "i.MX8MN_DDR_MON", + "SocName": "i.MX8MN" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/imx8mq-ddr-uncore.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/imx8mq-ddr-uncore.json new file mode 100644 index 000000000000..ae4fcd0f8ff7 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/imx8mq-ddr-uncore.json @@ -0,0 +1,28 @@ +[ + { + "PublicDescription": "lpddr4 evk board bandwidth usage", + "BriefDescription": "imx8mq: percentage of bandwidth usage for ddr0", + "MetricName": "imx8mq-ddr0-bandwidth-usage", + "MetricExpr": "(( imx8_ddr0\\/read\\-cycles\\/ + imx8_ddr0\\/write\\-cycles\\/) * 4 * 4 / duration_time) / (800 * 1000000 * 4 * 4)", + "MetricGroup": "i.MX8MQ_DDR_MON", + "ScaleUnit": "1e2%", + "SocName": "i.MX8MQ" + }, + + { + "PublicDescription": "Calculate bytes all masters read from DDR based on read-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 4 bytes of each beat if DDR burst width is 32 bit.", + "BriefDescription": "imx8mq: bytes of all masters read from ddr0", + "MetricName": "imx8mq-ddr0-all-r", + "MetricExpr": "imx8_ddr0\\/read\\-cycles\\/ * 4 * 4", + "MetricGroup": "i.MX8MQ_DDR_MON", + "SocName": "i.MX8MQ" + }, + { + "PublicDescription": "Calculate bytes all masters write to DDR based on write-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 4 bytes of each beat if DDR burst width is 32 bit.", + "BriefDescription": "imx8mq: bytes of all masters write to ddr0", + "MetricName": "imx8mq-ddr0-all-w", + "MetricExpr": "imx8_ddr0\\/write\\-cycles\\/ * 4 * 4", + "MetricGroup": "i.MX8MQ_DDR_MON", + "SocName": "i.MX8MQ" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/imx8qm-ddr-uncore.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/imx8qm-ddr-uncore.json index 6a204cb20014..33825d161da1 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/imx8qm-ddr-uncore.json +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/imx8qm-ddr-uncore.json @@ -1,4 +1,13 @@ [ + { + "PublicDescription": "lpddr4 mek board bandwidth usage", + "BriefDescription": "imx8qm: percentage of bandwidth usage for ddr0", + "MetricName": "imx8qm-ddr0-bandwidth-usage", + "MetricExpr": "(( imx8_ddr0\\/read\\-cycles\\/ + imx8_ddr0\\/write\\-cycles\\/) * 4 * 4 / duration_time) / (800 * 1000000 * 4 * 4)", + "MetricGroup": "i.MX8QM_DDR_MON", + "ScaleUnit": "1e2%", + "SocName": "i.MX8QM" + }, { "PublicDescription": "Calculate bytes all masters read from DDR based on read-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 4 bytes of each beat if DDR burst width is 32 bit.", "BriefDescription": "imx8qm: bytes of all masters read from ddr0", @@ -15,6 +24,15 @@ "MetricGroup": "i.MX8QM_DDR_MON", "SocName": "i.MX8QM" }, + { + "PublicDescription": "lpddr4 mek board bandwidth usage", + "BriefDescription": "imx8qm: percentage of bandwidth usage for ddr1", + "MetricName": "imx8qm-ddr1-bandwidth-usage", + "MetricExpr": "(( imx8_ddr1\\/read\\-cycles\\/ + imx8_ddr1\\/write\\-cycles\\/) * 4 * 4 / duration_time) / (800 * 1000000 * 4 * 4)", + "MetricGroup": "i.MX8QM_DDR_MON", + "ScaleUnit": "1e2%", + "SocName": "i.MX8QM" + }, { "PublicDescription": "Calculate bytes all masters read from DDR based on read-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 4 bytes of each beat if DDR burst width is 32 bit.", "BriefDescription": "imx8qm: bytes of all masters read from ddr1",