Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

In the firmware/fpgas/aes/icestorm path, a problem about "make" #497

Open
HoulaiZhang opened this issue Aug 6, 2024 · 0 comments
Open

Comments

@HoulaiZhang
Copy link

I have configured the nextpnr environment, and can generate bin file when TOP=ss_ice40_aes_top, but when TOP=ss2_ice40_aes_top, the logical unit is insufficient. How can I solve this problem? All the files I used were Chipwhisperer-supplied, and I only changed the TOP. The following is the information in the pnr.log.

Info: constrained 'clk' to bel 'X12/Y31/io1'
Info: constrained 'IO3' to bel 'X4/Y31/io0'
Info: constrained 'IO4' to bel 'X19/Y31/io1'
Info: constrained 'TxD' to bel 'X5/Y0/io0'
Info: constrained 'RxD' to bel 'X6/Y0/io0'
Info: constrained 'clock_alive' to bel 'X13/Y0/io0'

Info: Packing constants..
Info: Packing IOs..
Info: Packing LUT-FFs..
Info: 3852 LCs used as LUT4 only
Info: 1215 LCs used as LUT4 and DFF
Info: Packing non-LUT FFs..
Info: 349 LCs used as DFF only
Info: Packing carries..
Info: 67 LCs used as CARRY only
Info: Packing indirect carry+LUT pairs...
Info: 50 LUTs merged into carry LCs
Info: Packing RAMs..
Info: Placing PLLs..
Info: Packing special functions..
Info: Packing PLLs..
Info: Promoting globals..
Info: promoting clk$SB_IO_IN (fanout 1566)
Info: promoting U_cw305_dut.aes_load [reset] (fanout 269)
Info: promoting ss2_reset [reset] (fanout 112)
Info: promoting U_cw305_dut.aes_core.ks_en_SB_DFF_Q_D_SB_LUT4_I2_O [cen] (fanout 136)
Info: promoting U_cw305_dut.aes_core.busy_o_SB_LUT4_I1_O [cen] (fanout 132)
Info: promoting U_cw305_dut.U_reg_aes.done_pulse [cen] (fanout 128)
Info: promoting U_cw305_dut.U_usb_reg_fe.usb_wrn_r_SB_LUT4_I2_1_O [cen] (fanout 128)
Info: Constraining chains...
Info: 36 LCs used to legalise carry chains.
Info: Checksum: 0xa9c8f6cb

Info: Annotating ports with timing budgets for target frequency 20.00 MHz
Info: Checksum: 0x349efbfa

Info: Device utilisation:
Info: ICESTORM_LC: 5471/ 5280 103%
Info: ICESTORM_RAM: 1/ 30 3%
Info: SB_IO: 6/ 96 6%
Info: SB_GB: 7/ 8 87%
Info: ICESTORM_PLL: 0/ 1 0%
Info: SB_WARMBOOT: 0/ 1 0%
Info: ICESTORM_DSP: 0/ 8 0%
Info: ICESTORM_HFOSC: 0/ 1 0%
Info: ICESTORM_LFOSC: 0/ 1 0%
Info: SB_I2C: 0/ 2 0%
Info: SB_SPI: 0/ 2 0%
Info: IO_I3C: 0/ 2 0%
Info: SB_LEDDA_IP: 0/ 1 0%
Info: SB_RGBA_DRV: 0/ 1 0%
Info: ICESTORM_SPRAM: 0/ 4 0%

Info: Placed 6 cells based on constraints.
Info: Creating initial analytic placement for 5205 cells, random placement wirelen = 142138.
Info: at initial placer iter 0, wirelen = 228
Info: at initial placer iter 1, wirelen = 219
Info: at initial placer iter 2, wirelen = 233
Info: at initial placer iter 3, wirelen = 204
Info: Running main analytical placer, max placement attempts per cell = 3760653.
ERROR: Failed to expand region (0, 0) |_> (25, 31) of 5471 ICESTORM_LCs
0 warnings, 1 error

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

No branches or pull requests

1 participant