From 077c08cdd3def71bddce4d2a450fa159197fa826 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 8 Sep 2023 12:27:33 +0100 Subject: [PATCH 01/44] Add target structure Adjust mcuconf Adjust cmakepresets --- .github/workflows/build-chibios-targets.yml | 147 ++ .../ST_STM32F767ZI_NUCLEO/CMakeLists.txt | 51 + .../ST_STM32F767ZI_NUCLEO/CMakePresets.json | 58 + .../ChibiOS/ST_STM32F767ZI_NUCLEO/README.md | 32 + targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.c | 266 +++ targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.h | 1768 +++++++++++++++++ .../common/CMakeLists.txt | 13 + .../common/Device_BlockStorage-DEBUG.c | 106 + .../common/Device_BlockStorage.c | 102 + .../ST_STM32F767ZI_NUCLEO/common/serialcfg.h | 15 + .../common/targetHAL_ConfigurationManager.cpp | 38 + .../ChibiOS/ST_STM32F767ZI_NUCLEO/ffconf.h | 273 +++ .../ChibiOS/ST_STM32F767ZI_NUCLEO/launch.json | 107 + .../managed_helpers/README.md | 5 + .../STM32F769I_DISCOVERY.Adc.cs | 53 + .../managed_helpers/package.nuspec | 26 + .../ST_STM32F767ZI_NUCLEO/mbedtls_config.h | 53 + .../nanoBooter/CMakeLists.txt | 10 + .../nanoBooter/STM32F76xx_booter-DEBUG.ld | 137 ++ .../nanoBooter/STM32F76xx_booter.ld | 137 ++ .../ST_STM32F767ZI_NUCLEO/nanoBooter/chconf.h | 819 ++++++++ .../nanoBooter/halconf.h | 547 +++++ .../nanoBooter/halconf_nf.h | 23 + .../ST_STM32F767ZI_NUCLEO/nanoBooter/main.c | 103 + .../nanoBooter/mcuconf.h | 437 ++++ .../nanoBooter/mcuconf_nf.h | 9 + .../nanoBooter/target_board.h.in | 18 + .../nanoCLR/CMakeLists.txt | 11 + .../nanoCLR/STM32F76xx_CLR-DEBUG.ld | 156 ++ .../nanoCLR/STM32F76xx_CLR.ld | 156 ++ .../ST_STM32F767ZI_NUCLEO/nanoCLR/chconf.h | 819 ++++++++ .../ST_STM32F767ZI_NUCLEO/nanoCLR/halconf.h | 568 ++++++ .../nanoCLR/halconf_nf.h | 35 + .../ST_STM32F767ZI_NUCLEO/nanoCLR/main.c | 107 + .../ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h | 437 ++++ .../nanoCLR/mcuconf_nf.h | 22 + .../ST_STM32F767ZI_NUCLEO/nanoCLR/nanoHAL.cpp | 8 + .../nanoCLR/target_board.h.in | 18 + .../ST_STM32F767ZI_NUCLEO/spiffs_config.h | 370 ++++ .../stm32f7xx_hal_conf.h | 56 + .../target_BlockStorage.c | 15 + .../target_BlockStorage.h | 12 + .../ST_STM32F767ZI_NUCLEO/target_common.c | 27 + .../ST_STM32F767ZI_NUCLEO/target_common.h.in | 47 + .../target_external_memory.c | 111 ++ .../target_lwip_sntp_opts.h | 8 + .../ST_STM32F767ZI_NUCLEO/target_lwipopts.h | 8 + .../target_nf_dev_onewire_config.cpp | 29 + .../target_nf_dev_onewire_config.h | 17 + .../target_nf_device_can_config.cpp | 46 + .../target_nf_device_can_config.h | 24 + .../ST_STM32F767ZI_NUCLEO/target_spiffs.c | 864 ++++++++ .../ST_STM32F767ZI_NUCLEO/target_spiffs.h | 138 ++ .../target_system_device_adc_config.cpp | 25 + .../target_system_device_dac_config.cpp | 14 + .../target_system_device_i2c_config.cpp | 18 + .../target_system_device_pwm_config.cpp | 9 + .../target_system_device_spi_config.cpp | 31 + .../target_system_io_ports_config.cpp | 153 ++ .../target_system_io_ports_config.h | 60 + .../target_windows_storage_config.h | 10 + 61 files changed, 9782 insertions(+) create mode 100644 .github/workflows/build-chibios-targets.yml create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakeLists.txt create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/README.md create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.c create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.h create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/CMakeLists.txt create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/Device_BlockStorage-DEBUG.c create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/Device_BlockStorage.c create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/serialcfg.h create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/targetHAL_ConfigurationManager.cpp create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/ffconf.h create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/launch.json create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/README.md create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/STM32F769I_DISCOVERY.Adc.cs create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/package.nuspec create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/mbedtls_config.h create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/CMakeLists.txt create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/STM32F76xx_booter-DEBUG.ld create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/STM32F76xx_booter.ld create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/chconf.h create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/halconf.h create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/halconf_nf.h create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/main.c create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/mcuconf.h create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/mcuconf_nf.h create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/target_board.h.in create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/CMakeLists.txt create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/STM32F76xx_CLR-DEBUG.ld create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/STM32F76xx_CLR.ld create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/chconf.h create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/halconf.h create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/halconf_nf.h create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/main.c create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf_nf.h create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/nanoHAL.cpp create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/target_board.h.in create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/spiffs_config.h create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/stm32f7xx_hal_conf.h create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_BlockStorage.c create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_BlockStorage.h create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_common.c create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_common.h.in create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_external_memory.c create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_lwip_sntp_opts.h create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_lwipopts.h create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_dev_onewire_config.cpp create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_dev_onewire_config.h create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.cpp create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.h create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_spiffs.c create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_spiffs.h create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_adc_config.cpp create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_dac_config.cpp create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_i2c_config.cpp create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_pwm_config.cpp create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_spi_config.cpp create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.cpp create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.h create mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_windows_storage_config.h diff --git a/.github/workflows/build-chibios-targets.yml b/.github/workflows/build-chibios-targets.yml new file mode 100644 index 0000000000..5dfbb4aa6b --- /dev/null +++ b/.github/workflows/build-chibios-targets.yml @@ -0,0 +1,147 @@ +name: Devcontainer build for ChibiOS targets +# run-name: ${{ github.actor }}-test + +on: + push: + pull_request: + release: + types: + - created + workflow_dispatch: + +jobs: + build-target: + strategy: + fail-fast: false # Continues to build other targets in the matrix, even if one fails. + + matrix: # Add the target and build type you wish to generate firmware for: + include: [ + { target: ST_STM32F767ZI_NUCLEO, build-type: MinSizeRel }, + { target: ST_STM32F767ZI_NUCLEO, build-type: Debug }, + + # { target: ST_STM32F769I_DISCOVERY, build-type: MinSizeRel }, + # { target: ST_STM32F769I_DISCOVERY, build-type: Debug }, + + # { target: ORGPAL_PALTHREE, build-type: MinSizeRel }, + # { target: ORGPAL_PALTHREE, build-type: Debug }, + + # { target: ST_STM32F429I_DISCOVERY, build-type: MinSizeRel }, + # { target: ST_STM32F429I_DISCOVERY, build-type: Debug }, + + # { target: ST_NUCLEO64_F091RC, build-type: MinSizeRel }, + # Note: The F091RC debug build is currently broken, so is expected to fail. + # { target: ST_NUCLEO64_F091RC, build-type: Debug }, + + + # Community targets: + + # { target: ST_NUCLEO64_F411RE_NF, build-type: MinSizeRel }, + # { target: ST_NUCLEO64_F411RE_NF, build-type: Debug }, + + # { target: ST_STM32F411_DISCOVERY, build-type: MinSizeRel }, + # { target: ST_STM32F411_DISCOVERY, build-type: Debug }, + + # { target: BrainPad2, build-type: MinSizeRel }, + # { target: BrainPad2, build-type: Debug }, + + # { target: GHI_FEZ_CERB40_NF, build-type: MinSizeRel }, + # { target: GHI_FEZ_CERB40_NF, build-type: Debug }, + + # { target: I2M_ELECTRON_NF, build-type: MinSizeRel }, + # { target: I2M_ELECTRON_NF, build-type: Debug }, + + # { target: I2M_OXYGEN_NF, build-type: MinSizeRel }, + # { target: I2M_OXYGEN_NF, build-type: Debug }, + + # { target: MBN_QUAIL, build-type: MinSizeRel }, + # { target: MBN_QUAIL, build-type: Debug }, + + # { target: NESHTEC_NESHNODE_V1, build-type: MinSizeRel }, + # { target: NESHTEC_NESHNODE_V1, build-type: Debug }, + + # { target: NETDUINO3_WIFI, build-type: MinSizeRel }, + # { target: NETDUINO3_WIFI, build-type: Debug }, + + # { target: PybStick2x, build-type: MinSizeRel }, + # { target: PybStick2x, build-type: Debug }, + + # { target: ST_NUCLEO144_F412ZG_NF, build-type: MinSizeRel }, + # { target: ST_NUCLEO144_F412ZG_NF, build-type: Debug }, + + # { target: ST_NUCLEO144_F439ZI, build-type: MinSizeRel }, + # { target: ST_NUCLEO144_F439ZI, build-type: Debug }, + + # { target: ST_NUCLEO144_F746ZG, build-type: MinSizeRel }, + # { target: ST_NUCLEO144_F746ZG, build-type: Debug }, + + # { target: ST_NUCLEO64_F401RE_NF, build-type: MinSizeRel }, + # { target: ST_NUCLEO64_F401RE_NF, build-type: Debug }, + + # { target: ST_STM32F4_DISCOVERY, build-type: MinSizeRel }, + # { target: ST_STM32F4_DISCOVERY, build-type: Debug }, + + # { target: WEACT_F411CE, build-type: MinSizeRel }, + # { target: WEACT_F411CE, build-type: Debug }, + ] + + runs-on: ubuntu-latest + + steps: + - uses: actions/checkout@v3 + with: + submodules: recursive + + - name: Adjust config templates for devcontainer + run: | + # Move into the config directory + pushd config + # Rename the templates + mv user-prefs.TEMPLATE.json user-prefs.json + mv user-tools-repos.TEMPLATE.json user-tools-repos.json + # Adjust the file content for a devcontainer + sed -i -- 's|"name": "user-tools-repos-container"|"name": "user-tools-repos"|g' user-tools-repos.json + # Move out of the config directory + popd + + - name: Adjust devcontainer.json (ChibiOS source) + run: | + # required fixes for current devcontainer + # Move into the .devcontainer directory + pushd .devcontainer + # We could target the chibios container for a quicker build + # sed -i -- 's|"dockerFile": "Dockerfile.All"|"dockerFile": "Dockerfile.ChibiOS"|g' devcontainer.json + # But we actually require a change to the available devcontainer image, so we target the source instead (which takes a little longer to build). + sed -i -- 's|"dockerFile": "Dockerfile.All"|"dockerFile": "sources/Dockerfile.ChibiOS"|g' devcontainer.json + # For the CI, we need to remove the unsupported (azure cli) mount directive. + sed -i -- 's|"source=${env:HOME}${env:USERPROFILE}/.azure,target=/home/vscode/.azure,type=bind"|//"source=${env:HOME}${env:USERPROFILE}/.azure,target=/home/vscode/.azure,type=bind",|g' devcontainer.json + # Move out of the .devcontainer directory + popd + + - name: Login to GitHub Container Registry + uses: docker/login-action@v2 + with: + registry: ghcr.io + username: ${{ github.repository_owner }} + password: ${{ secrets.GITHUB_TOKEN }} + + - name: Build ${{ matrix.target }} ${{ matrix.build-type }} Firmware + uses: devcontainers/ci@v0.3 + with: + # The ChibiOS container + cacheFrom: ghcr.io/nanoframework/dev-container-chibios + push: never + runCmd: | + # Build target: + cmake --preset=${{ matrix.target }} -DCMAKE_BUILD_TYPE=${{ matrix.build-type }} + cmake --build build + + - name: Upload Artifact + uses: actions/upload-artifact@v3 + with: + name: Firmware ${{ matrix.target }}-${{ matrix.build-type }} + path: | + ./build/*.map + ./build/*.elf + ./build/*.hex + ./build/*.bin + ./build/*.dfu diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakeLists.txt b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakeLists.txt new file mode 100644 index 0000000000..f18cb0015d --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakeLists.txt @@ -0,0 +1,51 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +include(binutils.common) +include(binutils.ChibiOS) + +nf_setup_target_build( + HAS_NANOBOOTER + + BOOTER_LINKER_FILE + STM32F76xx_booter + + CLR_LINKER_FILE + STM32F76xx_CLR + + CLR_EXTRA_SOURCE_FILES + # the next one is required is the target implements and it's using external memory + ${CMAKE_CURRENT_SOURCE_DIR}/target_external_memory.c + + BOOTER_EXTRA_LINKMAP_PROPERTIES + ",--library-path=${CMAKE_SOURCE_DIR}/targets/ChibiOS/_common,--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x2000" + + CLR_EXTRA_LINKMAP_PROPERTIES + ",--library-path=${CMAKE_SOURCE_DIR}/targets/ChibiOS/_common,--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x3B000" +) + +# generate bin file for deployment +if(SRECORD_TOOL_AVAILABLE) + + ############################################################################################################ + ## when changing the linker file make sure to update the addresses below with the offset of the CLR image ## + ## DO NOT use the leading 0x notation, just the address in plain hexadecimal formating ## + ############################################################################################################ + + if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + nf_generate_bin_package( + ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin + ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin + 10000 + ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) + else() + nf_generate_bin_package( + ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin + ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin + 10000 + ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) + endif() + +endif() diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json new file mode 100644 index 0000000000..cd9fdabebf --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json @@ -0,0 +1,58 @@ +{ + "version": 4, + "include": [ + "../../../CMake/arm-gcc.json", + "../../../config/user-tools-repos.json", + "../../../config/user-prefs.json" + ], + "configurePresets": [ + { + "name": "ST_STM32F767ZI_NUCLEO", + "inherits": [ + "arm-gcc-cortex-preset", + "user-tools-repos", + "user-prefs" + ], + "hidden": false, + "cacheVariables": { + "TARGET_BOARD": "${presetName}", + "RTOS": "ChibiOS", + "TARGET_SERIES": "STM32F7xx", + "CHIBIOS_CONTRIB_REQUIRED": "OFF", + "STM32_CUBE_PACKAGE_REQUIRED": "OFF", + "SUPPORT_ANY_BASE_CONVERSION": "ON", + "NF_FEATURE_DEBUGGER": "ON", + "NF_FEATURE_RTC": "ON", + "NF_FEATURE_HAS_SDCARD": "OFF", + "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", + "SWO_OUTPUT": "OFF", + "NF_BUILD_RTM": "OFF", + "API_System.Math": "ON", + "API_Hardware.Stm32": "ON", + "API_System.Device.Gpio": "ON", + "API_System.Device.Spi": "ON", + "API_System.Device.I2c": "ON", + "API_System.Device.Pwm": "ON", + "API_System.IO.Ports": "ON", + "API_System.Device.Adc": "ON", + "API_System.Device.Dac": "ON", + "API_System.Net": "ON", + "API_nanoFramework.Device.OneWire": "OFF", + "API_nanoFramework.Device.Can": "ON", + "API_nanoFramework.ResourceManager": "ON", + "API_nanoFramework.System.Collections": "ON", + "API_nanoFramework.System.Text": "ON", + "API_Windows.Storage": "OFF", + "API_nanoFramework.Graphics": "OFF" + } + } + ], + "buildPresets": [ + { + "inherits": "base-user", + "name": "ST_STM32F769I_DISCOVERY", + "displayName": "ST_STM32F769I_DISCOVERY", + "configurePreset": "ST_STM32F769I_DISCOVERY" + } + ] +} diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/README.md b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/README.md new file mode 100644 index 0000000000..5e6f15e70d --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/README.md @@ -0,0 +1,32 @@ +## Configuration of ChibiOS, HAL and MCU + +For a successful build the following changes are required: + +For memory maps, uuid etc. the reference document used was: http://www.st.com/content/ccc/resource/technical/document/reference_manual/group0/96/8b/0d/ec/16/22/43/71/DM00224583/files/DM00224583.pdf/jcr:content/translations/en.DM00224583.pdf + +In _halconf.g_ (in both nanoBooter and nanoCLR folders), when compared with a default file available from (https://github.com/ChibiOS/ChibiOS/tree/master/demos/STM32/RT-STM32F769I-DISCOVERY): +- HAL_USE_SERIAL to TRUE +- SERIAL_DEFAULT_BITRATE to 921600 + +In _mcuconf.h_ (in both nanoBooter and nanoCLR folders), when compared with a default file available from (https://github.com/ChibiOS/ChibiOS/tree/master/demos/STM32/RT-STM32F769I-DISCOVERY): +- STM32_SERIAL_USE_USART1 to TRUE + +NOTE: this configuration was successfully tested in an ST_STM32F769I_DISCOVERY board using the Serial port through the onboard ST Link USB connection. + +## ADC configurations + +The following ADC channels (and respective GPIO pins) are available to the managed API, in the respective index: +- PA6, ADC1 IN6 +- PA4 ADC1 IN4 +- PC2 ADC1 IN12 +- PF10 ADC1 IN8 +- PF8 ADC3 IN6 +- PB8 ADC3 IN7 +- Temp Sensor ADC1 +- VrefInt ADC1 +- Vbatt ADC1 + +## Floating point + +The current build is set to add support for single-precision floating point. +Meaning that `System.Math` API supports only the `float` overloads. The `double` ones will throw a `NotImplementedException`. diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.c b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.c new file mode 100644 index 0000000000..d08d420349 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.c @@ -0,0 +1,266 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" +#include "stm32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of STM32 GPIO port setup. + */ +typedef struct { + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t odr; + uint32_t afrl; + uint32_t afrh; +} gpio_setup_t; + +/** + * @brief Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + gpio_setup_t PEData; +#endif +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) + gpio_setup_t PFData; +#endif +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) + gpio_setup_t PGData; +#endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) + gpio_setup_t PHData; +#endif +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) + gpio_setup_t PIData; +#endif +#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) + gpio_setup_t PJData; +#endif +#if STM32_HAS_GPIOK || defined(__DOXYGEN__) + gpio_setup_t PKData; +#endif +} gpio_config_t; + +/** + * @brief STM32 GPIO static initialization data. + */ +static const gpio_config_t gpio_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, +#endif +#if STM32_HAS_GPIOJ + {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, + VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, +#endif +#if STM32_HAS_GPIOK + {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, + VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} +#endif +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { + + gpiop->OTYPER = config->otyper; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->ODR = config->odr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; + gpiop->MODER = config->moder; +} + +static void stm32_gpio_init(void) { + + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + rccResetAHB1(STM32_GPIO_EN_MASK); + rccEnableAHB1(STM32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); +#endif +#if STM32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE + gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +#if STM32_HAS_GPIOF + gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +#if STM32_HAS_GPIOG + gpio_init(GPIOG, &gpio_default_config.PGData); +#endif +#if STM32_HAS_GPIOH + gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +#if STM32_HAS_GPIOI + gpio_init(GPIOI, &gpio_default_config.PIData); +#endif +#if STM32_HAS_GPIOJ + gpio_init(GPIOJ, &gpio_default_config.PJData); +#endif +#if STM32_HAS_GPIOK + gpio_init(GPIOK, &gpio_default_config.PKData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Early initialization code. + * @details GPIO ports and system clocks are initialized before everything + * else. + */ +void __early_init(void) { + + stm32_gpio_init(); + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + + return !palReadLine(LINE_SD_DETECT); +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { + +} diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.h new file mode 100644 index 0000000000..5a0b99cc14 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.h @@ -0,0 +1,1768 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#ifndef BOARD_H +#define BOARD_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/* + * Setup for STMicroelectronics STM32F769I-Discovery board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_STM32F769I_DISCOVERY +#define BOARD_NAME "STMicroelectronics STM32F769I-Discovery" + +/* + * Ethernet PHY type. + */ +#define BOARD_PHY_ID MII_LAN8742A_ID +#define BOARD_PHY_RMII + +/* + * The board has an ULPI USB PHY. + */ +#define BOARD_OTG2_USES_ULPI + +/* + * Board oscillators-related settings. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768U +#endif + +#define STM32_LSEDRV (3U << 3U) + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 25000000U +#endif + +#define STM32_HSE_BYPASS + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300U + +/* + * MCU type as defined in the ST header. + */ +#define STM32F769xx + +/* + * IO pins assignments. + */ +#define GPIOA_BUTTON_USER 0U +#define GPIOA_RMII_REF_CLK 1U +#define GPIOA_RMII_MDIO 2U +#define GPIOA_ULPI_D0 3U +#define GPIOA_ARD_A1 4U +#define GPIOA_ULPI_CK 5U +#define GPIOA_ARD_A0 6U +#define GPIOA_RMII_CRS_DV 7U +#define GPIOA_CEC_CLK 8U +#define GPIOA_VCP_TX 9U +#define GPIOA_VCP_RX 10U +#define GPIOA_ARD_D10 11U +#define GPIOA_ARD_D13 12U +#define GPIOA_SWDIO 13U +#define GPIOA_SWCLK 14U +#define GPIOA_CEC 15U + +#define GPIOB_ULPI_D1 0U +#define GPIOB_ULPI_D2 1U +#define GPIOB_QSPI_CLK 2U +#define GPIOB_SD_D2 3U +#define GPIOB_SD_D3 4U +#define GPIOB_ULPI_D7 5U +#define GPIOB_QUADSPI_BK1_NCS 6U +#define GPIOB_AUDIO_SDA 7U +#define GPIOB_LCD_SDA 7U +#define GPIOB_ARD_D15 8U +#define GPIOB_ARD_D14 9U +#define GPIOB_ULPI_D3 10U +#define GPIOB_ULPI_D4 11U +#define GPIOB_ULPI_D5 12U +#define GPIOB_ULPI_D6 13U +#define GPIOB_ARD_D12 14U +#define GPIOB_ARD_D11 15U + +#define GPIOC_ULPI_STP 0U +#define GPIOC_RMII_MDC 1U +#define GPIOC_ARD_A2 2U +#define GPIOC_DFSDM_DATIN1 3U +#define GPIOC_RMII_RXD0 4U +#define GPIOC_RMII_RXD1 5U +#define GPIOC_ARD_D1 6U +#define GPIOC_ARD_D0 7U +#define GPIOC_ARD_D5 8U +#define GPIOB_I2C1_SCL 8U +#define GPIOC_QSPI_D0 9U +#define GPIOB_I2C1_SDA 9U +#define GPIOC_QSPI_D1 10U +#define GPIOC_DFSDM_DATIN5 11U +#define GPIOC_WIFI_RX 12U +#define GPIOC_PIN13 13U +#define GPIOC_OSC32_IN 14U +#define GPIOC_OSC32_OUT 15U + +#define GPIOD_FMC_D2 0U +#define GPIOD_FMC_D3 1U +#define GPIOD_WIFI_TX 2U +#define GPIOD_DFSDM_CKOUT 3U +#define GPIOD_OTG_HS_OVER_CURRENT 4U +#define GPIOD_RMII_RXER 5U +#define GPIOD_SD_CLK 6U +#define GPIOD_SD_CMD 7U +#define GPIOD_FMC_D13 8U +#define GPIOD_FMC_D14 9U +#define GPIOD_FMC_D15 10U +#define GPIOD_SPDIF_I2S 11U +#define GPIOD_AUDIO_SCL 12U +#define GPIOD_LCD_SCL 12U +#define GPIOD_QSPI_D3 13U +#define GPIOD_FMC_D0 14U +#define GPIOD_FMC_D1 15U + +#define GPIOE_FMC_NBL0 0U +#define GPIOE_FMC_NBL1 1U +#define GPIOE_QSPI_D2 2U +#define GPIOE_SAI1_SDB 3U +#define GPIOE_SAI1_FSA 4U +#define GPIOE_SAI1_SCKA 5U +#define GPIOE_SAI1_SDA 6U +#define GPIOE_FMC_D4 7U +#define GPIOE_FMC_D5 8U +#define GPIOE_FMC_D6 9U +#define GPIOE_FMC_D7 10U +#define GPIOE_FMC_D8 11U +#define GPIOE_FMC_D9 12U +#define GPIOE_FMC_D10 13U +#define GPIOE_FMC_11 14U +#define GPIOE_FMC_D12 15U + +#define GPIOF_FMC_A0 0U +#define GPIOF_FMC_A1 1U +#define GPIOF_FMC_A2 2U +#define GPIOF_FMC_A3 3U +#define GPIOF_FMC_A4 4U +#define GPIOF_FMC_A5 5U +#define GPIOF_ARD_D3 6U +#define GPIOF_ARD_D6 7U +#define GPIOF_ARD_A4 8U +#define GPIOF_ARD_A5 9U +#define GPIOF_ARD_A3 10U +#define GPIOF_FMC_SDNRAS 11U +#define GPIOF_FMC_A6 12U +#define GPIOF_FMC_A7 13U +#define GPIOF_FMC_A8 14U +#define GPIOF_FMC_A9 15U + +#define GPIOG_FMC_A10 0U +#define GPIOG_FMC_A11 1U +#define GPIOG_FMC_A12 2U +#define GPIOG_EXT_SCL 3U +#define GPIOG_FMC_BA0 4U +#define GPIOG_FMC_BA1 5U +#define GPIOG_EXT_SDA 6U +#define GPIOG_SAI1_MCLKA 7U +#define GPIOG_FMC_SDCLK 8U +#define GPIOG_SD_D0 9U +#define GPIOG_SD_D1 10U +#define GPIOG_RMII_TX_EN 11U +#define GPIOG_SPDIF_RX 12U +#define GPIOG_RMII_TXD0 13U +#define GPIOG_RMII_TXD1 14U +#define GPIOG_FMC_SDNCAS 15U + +#define GPIOH_OSC_IN 0U +#define GPIOH_OSC_OUT 1U +#define GPIOH_FMC_SDCKE0 2U +#define GPIOH_FMC_SDNE0 3U +#define GPIOH_ULPI_NXT 4U +#define GPIOH_FMC_SDNWE 5U +#define GPIOH_ARD_D9 6U +#define GPIOH_EXT_RST 7U +#define GPIOH_FMC_D16 8U +#define GPIOH_FMC_D17 9U +#define GPIOH_FMC_D18 10U +#define GPIOH_FMC_D19 11U +#define GPIOH_FMC_D20 12U +#define GPIOH_FMC_D21 13U +#define GPIOH_FMC_D22 14U +#define GPIOH_FMC_D23 15U + +#define GPIOI_FMC_D24 0U +#define GPIOI_FMC_D25 1U +#define GPIOI_FMC_D26 2U +#define GPIOI_FMC_D27 3U +#define GPIOI_FMC_NBL2 4U +#define GPIOI_FMC_NBL3 5U +#define GPIOI_FMC_D28 6U +#define GPIOI_FMC_D29 7U +#define GPIOI_PIN8 8U +#define GPIOI_FMC_D30 9U +#define GPIOI_FMC_D31 10U +#define GPIOI_ULPI_DIR 11U +#define GPIOI_PIN12 12U +#define GPIOI_LCD_INT 13U +#define GPIOI_LCD_BL_CTRL 14U +#define GPIOI_SD_DETECT 15U + +#define GPIOJ_ARD_D4 0U +#define GPIOJ_ARD_D2 1U +#define GPIOJ_DSI_TE 2U +#define GPIOJ_ARD_D7 3U +#define GPIOJ_ARD_D8 4U +#define GPIOJ_LED2_GREEN 5U +#define GPIOJ_PIN6 6U +#define GPIOJ_PIN7 7U +#define GPIOJ_PIN8 8U +#define GPIOJ_PIN9 9U +#define GPIOJ_PIN10 10U +#define GPIOJ_PIN11 11U +#define GPIOJ_AUDIO_INT 12U +#define GPIOJ_LED1_RED 13U +#define GPIOJ_WIFI_RST 14U +#define GPIOJ_DSI_RESET 15U + +#define GPIOK_PIN0 0U +#define GPIOK_PIN1 1U +#define GPIOK_PIN2 2U +#define GPIOK_PIN3 3U +#define GPIOK_PIN4 4U +#define GPIOK_PIN5 5U +#define GPIOK_PIN6 6U +#define GPIOK_PIN7 7U +#define GPIOK_PIN8 8U +#define GPIOK_PIN9 9U +#define GPIOK_PIN10 10U +#define GPIOK_PIN11 11U +#define GPIOK_PIN12 12U +#define GPIOK_PIN13 13U +#define GPIOK_PIN14 14U +#define GPIOK_PIN15 15U + +/* + * IO lines assignments. + */ +#define LINE_BUTTON_USER PAL_LINE(GPIOA, 0U) +#define LINE_RMII_REF_CLK PAL_LINE(GPIOA, 1U) +#define LINE_RMII_MDIO PAL_LINE(GPIOA, 2U) +#define LINE_ULPI_D0 PAL_LINE(GPIOA, 3U) +#define LINE_ARD_A1 PAL_LINE(GPIOA, 4U) +#define LINE_ULPI_CK PAL_LINE(GPIOA, 5U) +#define LINE_ARD_A0 PAL_LINE(GPIOA, 6U) +#define LINE_RMII_CRS_DV PAL_LINE(GPIOA, 7U) +#define LINE_CEC_CLK PAL_LINE(GPIOA, 8U) +#define LINE_VCP_TX PAL_LINE(GPIOA, 9U) +#define LINE_VCP_RX PAL_LINE(GPIOA, 10U) +#define LINE_ARD_D10 PAL_LINE(GPIOA, 11U) +#define LINE_ARD_D13 PAL_LINE(GPIOA, 12U) +#define LINE_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) +#define LINE_CEC PAL_LINE(GPIOA, 15U) +#define LINE_ULPI_D1 PAL_LINE(GPIOB, 0U) +#define LINE_ULPI_D2 PAL_LINE(GPIOB, 1U) +#define LINE_QSPI_CLK PAL_LINE(GPIOB, 2U) +#define LINE_SD_D2 PAL_LINE(GPIOB, 3U) +#define LINE_SD_D3 PAL_LINE(GPIOB, 4U) +#define LINE_ULPI_D7 PAL_LINE(GPIOB, 5U) +#define LINE_QUADSPI_BK1_NCS PAL_LINE(GPIOB, 6U) +#define LINE_AUDIO_SDA PAL_LINE(GPIOB, 7U) +#define LINE_LCD_SDA PAL_LINE(GPIOB, 7U) +#define LINE_ARD_D15 PAL_LINE(GPIOB, 8U) +#define LINE_I2C1_SCL PAL_LINE(GPIOB, 8U) +#define LINE_ARD_D14 PAL_LINE(GPIOB, 9U) +#define LINE_I2C1_SDA PAL_LINE(GPIOB, 9U) +#define LINE_ULPI_D3 PAL_LINE(GPIOB, 10U) +#define LINE_ULPI_D4 PAL_LINE(GPIOB, 11U) +#define LINE_ULPI_D5 PAL_LINE(GPIOB, 12U) +#define LINE_ULPI_D6 PAL_LINE(GPIOB, 13U) +#define LINE_ARD_D12 PAL_LINE(GPIOB, 14U) +#define LINE_ARD_D11 PAL_LINE(GPIOB, 15U) +#define LINE_ULPI_STP PAL_LINE(GPIOC, 0U) +#define LINE_RMII_MDC PAL_LINE(GPIOC, 1U) +#define LINE_ARD_A2 PAL_LINE(GPIOC, 2U) +#define LINE_DFSDM_DATIN1 PAL_LINE(GPIOC, 3U) +#define LINE_RMII_RXD0 PAL_LINE(GPIOC, 4U) +#define LINE_RMII_RXD1 PAL_LINE(GPIOC, 5U) +#define LINE_ARD_D1 PAL_LINE(GPIOC, 6U) +#define LINE_ARD_D0 PAL_LINE(GPIOC, 7U) +#define LINE_ARD_D5 PAL_LINE(GPIOC, 8U) +#define LINE_QSPI_D0 PAL_LINE(GPIOC, 9U) +#define LINE_QSPI_D1 PAL_LINE(GPIOC, 10U) +#define LINE_DFSDM_DATIN5 PAL_LINE(GPIOC, 11U) +#define LINE_WIFI_RX PAL_LINE(GPIOC, 12U) +#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) +#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) +#define LINE_FMC_D2 PAL_LINE(GPIOD, 0U) +#define LINE_FMC_D3 PAL_LINE(GPIOD, 1U) +#define LINE_WIFI_TX PAL_LINE(GPIOD, 2U) +#define LINE_DFSDM_CKOUT PAL_LINE(GPIOD, 3U) +#define LINE_OTG_HS_OVER_CURRENT PAL_LINE(GPIOD, 4U) +#define LINE_RMII_RXER PAL_LINE(GPIOD, 5U) +#define LINE_SD_CLK PAL_LINE(GPIOD, 6U) +#define LINE_SD_CMD PAL_LINE(GPIOD, 7U) +#define LINE_FMC_D13 PAL_LINE(GPIOD, 8U) +#define LINE_FMC_D14 PAL_LINE(GPIOD, 9U) +#define LINE_FMC_D15 PAL_LINE(GPIOD, 10U) +#define LINE_SPDIF_I2S PAL_LINE(GPIOD, 11U) +#define LINE_AUDIO_SCL PAL_LINE(GPIOD, 12U) +#define LINE_LCD_SCL PAL_LINE(GPIOD, 12U) +#define LINE_QSPI_D3 PAL_LINE(GPIOD, 13U) +#define LINE_FMC_D0 PAL_LINE(GPIOD, 14U) +#define LINE_FMC_D1 PAL_LINE(GPIOD, 15U) +#define LINE_FMC_NBL0 PAL_LINE(GPIOE, 0U) +#define LINE_FMC_NBL1 PAL_LINE(GPIOE, 1U) +#define LINE_QSPI_D2 PAL_LINE(GPIOE, 2U) +#define LINE_SAI1_SDB PAL_LINE(GPIOE, 3U) +#define LINE_SAI1_FSA PAL_LINE(GPIOE, 4U) +#define LINE_SAI1_SCKA PAL_LINE(GPIOE, 5U) +#define LINE_SAI1_SDA PAL_LINE(GPIOE, 6U) +#define LINE_FMC_D4 PAL_LINE(GPIOE, 7U) +#define LINE_FMC_D5 PAL_LINE(GPIOE, 8U) +#define LINE_FMC_D6 PAL_LINE(GPIOE, 9U) +#define LINE_FMC_D7 PAL_LINE(GPIOE, 10U) +#define LINE_FMC_D8 PAL_LINE(GPIOE, 11U) +#define LINE_FMC_D9 PAL_LINE(GPIOE, 12U) +#define LINE_FMC_D10 PAL_LINE(GPIOE, 13U) +#define LINE_FMC_11 PAL_LINE(GPIOE, 14U) +#define LINE_FMC_D12 PAL_LINE(GPIOE, 15U) +#define LINE_FMC_A0 PAL_LINE(GPIOF, 0U) +#define LINE_FMC_A1 PAL_LINE(GPIOF, 1U) +#define LINE_FMC_A2 PAL_LINE(GPIOF, 2U) +#define LINE_FMC_A3 PAL_LINE(GPIOF, 3U) +#define LINE_FMC_A4 PAL_LINE(GPIOF, 4U) +#define LINE_FMC_A5 PAL_LINE(GPIOF, 5U) +#define LINE_ARD_D3 PAL_LINE(GPIOF, 6U) +#define LINE_ARD_D6 PAL_LINE(GPIOF, 7U) +#define LINE_ARD_A4 PAL_LINE(GPIOF, 8U) +#define LINE_ARD_A5 PAL_LINE(GPIOF, 9U) +#define LINE_ARD_A3 PAL_LINE(GPIOF, 10U) +#define LINE_FMC_SDNRAS PAL_LINE(GPIOF, 11U) +#define LINE_FMC_A6 PAL_LINE(GPIOF, 12U) +#define LINE_FMC_A7 PAL_LINE(GPIOF, 13U) +#define LINE_FMC_A8 PAL_LINE(GPIOF, 14U) +#define LINE_FMC_A9 PAL_LINE(GPIOF, 15U) +#define LINE_FMC_A10 PAL_LINE(GPIOG, 0U) +#define LINE_FMC_A11 PAL_LINE(GPIOG, 1U) +#define LINE_FMC_A12 PAL_LINE(GPIOG, 2U) +#define LINE_EXT_SCL PAL_LINE(GPIOG, 3U) +#define LINE_FMC_BA0 PAL_LINE(GPIOG, 4U) +#define LINE_FMC_BA1 PAL_LINE(GPIOG, 5U) +#define LINE_EXT_SDA PAL_LINE(GPIOG, 6U) +#define LINE_SAI1_MCLKA PAL_LINE(GPIOG, 7U) +#define LINE_FMC_SDCLK PAL_LINE(GPIOG, 8U) +#define LINE_SD_D0 PAL_LINE(GPIOG, 9U) +#define LINE_SD_D1 PAL_LINE(GPIOG, 10U) +#define LINE_RMII_TX_EN PAL_LINE(GPIOG, 11U) +#define LINE_SPDIF_RX PAL_LINE(GPIOG, 12U) +#define LINE_RMII_TXD0 PAL_LINE(GPIOG, 13U) +#define LINE_RMII_TXD1 PAL_LINE(GPIOG, 14U) +#define LINE_FMC_SDNCAS PAL_LINE(GPIOG, 15U) +#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) +#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) +#define LINE_FMC_SDCKE0 PAL_LINE(GPIOH, 2U) +#define LINE_FMC_SDNE0 PAL_LINE(GPIOH, 3U) +#define LINE_ULPI_NXT PAL_LINE(GPIOH, 4U) +#define LINE_FMC_SDNWE PAL_LINE(GPIOH, 5U) +#define LINE_ARD_D9 PAL_LINE(GPIOH, 6U) +#define LINE_EXT_RST PAL_LINE(GPIOH, 7U) +#define LINE_FMC_D16 PAL_LINE(GPIOH, 8U) +#define LINE_FMC_D17 PAL_LINE(GPIOH, 9U) +#define LINE_FMC_D18 PAL_LINE(GPIOH, 10U) +#define LINE_FMC_D19 PAL_LINE(GPIOH, 11U) +#define LINE_FMC_D20 PAL_LINE(GPIOH, 12U) +#define LINE_FMC_D21 PAL_LINE(GPIOH, 13U) +#define LINE_FMC_D22 PAL_LINE(GPIOH, 14U) +#define LINE_FMC_D23 PAL_LINE(GPIOH, 15U) +#define LINE_FMC_D24 PAL_LINE(GPIOI, 0U) +#define LINE_FMC_D25 PAL_LINE(GPIOI, 1U) +#define LINE_FMC_D26 PAL_LINE(GPIOI, 2U) +#define LINE_FMC_D27 PAL_LINE(GPIOI, 3U) +#define LINE_FMC_NBL2 PAL_LINE(GPIOI, 4U) +#define LINE_FMC_NBL3 PAL_LINE(GPIOI, 5U) +#define LINE_FMC_D28 PAL_LINE(GPIOI, 6U) +#define LINE_FMC_D29 PAL_LINE(GPIOI, 7U) +#define LINE_FMC_D30 PAL_LINE(GPIOI, 9U) +#define LINE_FMC_D31 PAL_LINE(GPIOI, 10U) +#define LINE_ULPI_DIR PAL_LINE(GPIOI, 11U) +#define LINE_LCD_INT PAL_LINE(GPIOI, 13U) +#define LINE_LCD_BL_CTRL PAL_LINE(GPIOI, 14U) +#define LINE_SD_DETECT PAL_LINE(GPIOI, 15U) +#define LINE_ARD_D4 PAL_LINE(GPIOJ, 0U) +#define LINE_ARD_D2 PAL_LINE(GPIOJ, 1U) +#define LINE_DSI_TE PAL_LINE(GPIOJ, 2U) +#define LINE_ARD_D7 PAL_LINE(GPIOJ, 3U) +#define LINE_ARD_D8 PAL_LINE(GPIOJ, 4U) +#define LINE_LED2_GREEN PAL_LINE(GPIOJ, 5U) +#define LINE_AUDIO_INT PAL_LINE(GPIOJ, 12U) +#define LINE_LED1_RED PAL_LINE(GPIOJ, 13U) +#define LINE_WIFI_RST PAL_LINE(GPIOJ, 14U) +#define LINE_DSI_RESET PAL_LINE(GPIOJ, 15U) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * GPIOA setup: + * + * PA0 - BUTTON_USER (input floating). + * PA1 - RMII_REF_CLK (alternate 11). + * PA2 - RMII_MDIO (alternate 11). + * PA3 - ULPI_D0 (alternate 10). + * PA4 - ARD_A1 (input pullup). + * PA5 - ULPI_CK (alternate 10). + * PA6 - ARD_A0 (input pullup). + * PA7 - RMII_CRS_DV (alternate 11). + * PA8 - CEC_CLK (alternate 0). + * PA9 - VCP_TX (alternate 7). + * PA10 - VCP_RX (alternate 7). + * PA11 - ARD_D10 (input pullup). + * PA12 - ARD_D13 (input pullup). + * PA13 - SWDIO (alternate 0). + * PA14 - SWCLK (alternate 0). + * PA15 - CEC (alternate 3). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON_USER) | \ + PIN_MODE_ALTERNATE(GPIOA_RMII_REF_CLK) |\ + PIN_MODE_ALTERNATE(GPIOA_RMII_MDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_ULPI_D0) | \ + PIN_MODE_INPUT(GPIOA_ARD_A1) | \ + PIN_MODE_ALTERNATE(GPIOA_ULPI_CK) | \ + PIN_MODE_INPUT(GPIOA_ARD_A0) | \ + PIN_MODE_ALTERNATE(GPIOA_RMII_CRS_DV) |\ + PIN_MODE_ALTERNATE(GPIOA_CEC_CLK) | \ + PIN_MODE_ALTERNATE(GPIOA_VCP_TX) | \ + PIN_MODE_ALTERNATE(GPIOA_VCP_RX) | \ + PIN_MODE_INPUT(GPIOA_ARD_D10) | \ + PIN_MODE_INPUT(GPIOA_ARD_D13) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_ALTERNATE(GPIOA_CEC)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON_USER) |\ + PIN_OTYPE_PUSHPULL(GPIOA_RMII_REF_CLK) |\ + PIN_OTYPE_PUSHPULL(GPIOA_RMII_MDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ULPI_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_A1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ULPI_CK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_RMII_CRS_DV) |\ + PIN_OTYPE_PUSHPULL(GPIOA_CEC_CLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_VCP_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOA_VCP_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D10) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D13) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_CEC)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_BUTTON_USER) | \ + PIN_OSPEED_HIGH(GPIOA_RMII_REF_CLK) | \ + PIN_OSPEED_HIGH(GPIOA_RMII_MDIO) | \ + PIN_OSPEED_HIGH(GPIOA_ULPI_D0) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_A1) | \ + PIN_OSPEED_HIGH(GPIOA_ULPI_CK) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_A0) | \ + PIN_OSPEED_VERYLOW(GPIOA_RMII_CRS_DV) |\ + PIN_OSPEED_HIGH(GPIOA_CEC_CLK) | \ + PIN_OSPEED_HIGH(GPIOA_VCP_TX) | \ + PIN_OSPEED_HIGH(GPIOA_VCP_RX) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D10) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D13) | \ + PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ + PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ + PIN_OSPEED_HIGH(GPIOA_CEC)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON_USER) |\ + PIN_PUPDR_FLOATING(GPIOA_RMII_REF_CLK) |\ + PIN_PUPDR_PULLUP(GPIOA_RMII_MDIO) | \ + PIN_PUPDR_FLOATING(GPIOA_ULPI_D0) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_A1) | \ + PIN_PUPDR_FLOATING(GPIOA_ULPI_CK) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_A0) | \ + PIN_PUPDR_FLOATING(GPIOA_RMII_CRS_DV) |\ + PIN_PUPDR_FLOATING(GPIOA_CEC_CLK) | \ + PIN_PUPDR_FLOATING(GPIOA_VCP_TX) | \ + PIN_PUPDR_FLOATING(GPIOA_VCP_RX) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_D10) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_D13) | \ + PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \ + PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \ + PIN_PUPDR_FLOATING(GPIOA_CEC)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON_USER) | \ + PIN_ODR_HIGH(GPIOA_RMII_REF_CLK) | \ + PIN_ODR_HIGH(GPIOA_RMII_MDIO) | \ + PIN_ODR_HIGH(GPIOA_ULPI_D0) | \ + PIN_ODR_HIGH(GPIOA_ARD_A1) | \ + PIN_ODR_HIGH(GPIOA_ULPI_CK) | \ + PIN_ODR_HIGH(GPIOA_ARD_A0) | \ + PIN_ODR_HIGH(GPIOA_RMII_CRS_DV) | \ + PIN_ODR_HIGH(GPIOA_CEC_CLK) | \ + PIN_ODR_HIGH(GPIOA_VCP_TX) | \ + PIN_ODR_HIGH(GPIOA_VCP_RX) | \ + PIN_ODR_HIGH(GPIOA_ARD_D10) | \ + PIN_ODR_HIGH(GPIOA_ARD_D13) | \ + PIN_ODR_HIGH(GPIOA_SWDIO) | \ + PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_CEC)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON_USER, 0U) | \ + PIN_AFIO_AF(GPIOA_RMII_REF_CLK, 11U) | \ + PIN_AFIO_AF(GPIOA_RMII_MDIO, 11U) | \ + PIN_AFIO_AF(GPIOA_ULPI_D0, 10U) | \ + PIN_AFIO_AF(GPIOA_ARD_A1, 0U) | \ + PIN_AFIO_AF(GPIOA_ULPI_CK, 10U) | \ + PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \ + PIN_AFIO_AF(GPIOA_RMII_CRS_DV, 11U)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_CEC_CLK, 0U) | \ + PIN_AFIO_AF(GPIOA_VCP_TX, 7U) | \ + PIN_AFIO_AF(GPIOA_VCP_RX, 7U) | \ + PIN_AFIO_AF(GPIOA_ARD_D10, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D13, 0U) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ + PIN_AFIO_AF(GPIOA_CEC, 3U)) + +/* + * GPIOB setup: + * + * PB0 - ULPI_D1 (alternate 10). + * PB1 - ULPI_D2 (alternate 10). + * PB2 - QSPI_CLK (alternate 9). + * PB3 - SD_D2 (alternate 10). + * PB4 - SD_D3 (alternate 10). + * PB5 - ULPI_D7 (alternate 10). + * PB6 - QUADSPI_BK1_NCS (alternate 10). + * PB7 - AUDIO_SDA LCD_SDA (alternate 11). + * PB8 - ARD_D15 (input pullup). + * PB9 - ARD_D14 (input pullup). + * PB10 - ULPI_D3 (alternate 10). + * PB11 - ULPI_D4 (alternate 10). + * PB12 - ULPI_D5 (alternate 10). + * PB13 - ULPI_D6 (alternate 10). + * PB14 - ARD_D12 (input pullup). + * PB15 - ARD_D11 (input pullup). + */ +#define VAL_GPIOB_MODER (PIN_MODE_ALTERNATE(GPIOB_ULPI_D1) | \ + PIN_MODE_ALTERNATE(GPIOB_ULPI_D2) | \ + PIN_MODE_ALTERNATE(GPIOB_QSPI_CLK) | \ + PIN_MODE_ALTERNATE(GPIOB_SD_D2) | \ + PIN_MODE_ALTERNATE(GPIOB_SD_D3) | \ + PIN_MODE_ALTERNATE(GPIOB_ULPI_D7) | \ + PIN_MODE_ALTERNATE(GPIOB_QUADSPI_BK1_NCS) | \ + PIN_MODE_ALTERNATE(GPIOB_AUDIO_SDA) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ + PIN_MODE_ALTERNATE(GPIOB_ULPI_D3) | \ + PIN_MODE_ALTERNATE(GPIOB_ULPI_D4) | \ + PIN_MODE_ALTERNATE(GPIOB_ULPI_D5) | \ + PIN_MODE_ALTERNATE(GPIOB_ULPI_D6) | \ + PIN_MODE_INPUT(GPIOB_ARD_D12) | \ + PIN_MODE_INPUT(GPIOB_ARD_D11)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_ULPI_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ULPI_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOB_QSPI_CLK) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SD_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SD_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ULPI_D7) | \ + PIN_OTYPE_PUSHPULL(GPIOB_QUADSPI_BK1_NCS) | \ + PIN_OTYPE_PUSHPULL(GPIOB_AUDIO_SDA) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ULPI_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ULPI_D4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ULPI_D5) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ULPI_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D12) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D11)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_ULPI_D1) | \ + PIN_OSPEED_HIGH(GPIOB_ULPI_D2) | \ + PIN_OSPEED_HIGH(GPIOB_QSPI_CLK) | \ + PIN_OSPEED_HIGH(GPIOB_SD_D2) | \ + PIN_OSPEED_HIGH(GPIOB_SD_D3) | \ + PIN_OSPEED_HIGH(GPIOB_ULPI_D7) | \ + PIN_OSPEED_HIGH(GPIOB_QUADSPI_BK1_NCS) | \ + PIN_OSPEED_HIGH(GPIOB_AUDIO_SDA) | \ + PIN_OSPEED_HIGH(GPIOB_I2C1_SCL) | \ + PIN_OSPEED_HIGH(GPIOB_I2C1_SDA) | \ + PIN_OSPEED_HIGH(GPIOB_ULPI_D3) | \ + PIN_OSPEED_HIGH(GPIOB_ULPI_D4) | \ + PIN_OSPEED_HIGH(GPIOB_ULPI_D5) | \ + PIN_OSPEED_HIGH(GPIOB_ULPI_D6) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D12) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D11)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_ULPI_D1) | \ + PIN_PUPDR_FLOATING(GPIOB_ULPI_D2) | \ + PIN_PUPDR_FLOATING(GPIOB_QSPI_CLK) | \ + PIN_PUPDR_FLOATING(GPIOB_SD_D2) | \ + PIN_PUPDR_FLOATING(GPIOB_SD_D3) | \ + PIN_PUPDR_PULLUP(GPIOB_ULPI_D7) | \ + PIN_PUPDR_FLOATING(GPIOB_QUADSPI_BK1_NCS) | \ + PIN_PUPDR_FLOATING(GPIOB_AUDIO_SDA) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \ + PIN_PUPDR_FLOATING(GPIOB_ULPI_D3) | \ + PIN_PUPDR_FLOATING(GPIOB_ULPI_D4) | \ + PIN_PUPDR_FLOATING(GPIOB_ULPI_D5) | \ + PIN_PUPDR_FLOATING(GPIOB_ULPI_D6) | \ + PIN_PUPDR_PULLUP(GPIOB_ARD_D12) | \ + PIN_PUPDR_PULLUP(GPIOB_ARD_D11)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_ULPI_D1) | \ + PIN_ODR_HIGH(GPIOB_ULPI_D2) | \ + PIN_ODR_HIGH(GPIOB_QSPI_CLK) | \ + PIN_ODR_HIGH(GPIOB_SD_D2) | \ + PIN_ODR_HIGH(GPIOB_SD_D3) | \ + PIN_ODR_HIGH(GPIOB_ULPI_D7) | \ + PIN_ODR_HIGH(GPIOB_QUADSPI_BK1_NCS) | \ + PIN_ODR_HIGH(GPIOB_AUDIO_SDA) | \ + PIN_ODR_LOW(GPIOB_I2C1_SCL) | \ + PIN_ODR_LOW(GPIOB_I2C1_SDA) | \ + PIN_ODR_HIGH(GPIOB_ULPI_D3) | \ + PIN_ODR_HIGH(GPIOB_ULPI_D4) | \ + PIN_ODR_HIGH(GPIOB_ULPI_D5) | \ + PIN_ODR_HIGH(GPIOB_ULPI_D6) | \ + PIN_ODR_HIGH(GPIOB_ARD_D12) | \ + PIN_ODR_HIGH(GPIOB_ARD_D11)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ULPI_D1, 10U) | \ + PIN_AFIO_AF(GPIOB_ULPI_D2, 10U) | \ + PIN_AFIO_AF(GPIOB_QSPI_CLK, 9U) | \ + PIN_AFIO_AF(GPIOB_SD_D2, 10U) | \ + PIN_AFIO_AF(GPIOB_SD_D3, 10U) | \ + PIN_AFIO_AF(GPIOB_ULPI_D7, 10U) | \ + PIN_AFIO_AF(GPIOB_QUADSPI_BK1_NCS, 10U) | \ + PIN_AFIO_AF(GPIOB_AUDIO_SDA, 11U)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4U) | \ + PIN_AFIO_AF(GPIOB_I2C1_SDA, 4U) | \ + PIN_AFIO_AF(GPIOB_ULPI_D3, 10U) | \ + PIN_AFIO_AF(GPIOB_ULPI_D4, 10U) | \ + PIN_AFIO_AF(GPIOB_ULPI_D5, 10U) | \ + PIN_AFIO_AF(GPIOB_ULPI_D6, 10U) | \ + PIN_AFIO_AF(GPIOB_ARD_D12, 0U) | \ + PIN_AFIO_AF(GPIOB_ARD_D11, 0U)) + +/* + * GPIOC setup: + * + * PC0 - ULPI_STP (alternate 10). + * PC1 - RMII_MDC (alternate 11). + * PC2 - ARD_A2 (input pullup). + * PC3 - DFSDM_DATIN1 (alternate 3). + * PC4 - RMII_RXD0 (alternate 11). + * PC5 - RMII_RXD1 (alternate 11). + * PC6 - ARD_D1 (input pullup). + * PC7 - ARD_D0 (input floating). + * PC8 - ARD_D5 (input floating). + * PC9 - QSPI_D0 (alternate 9). + * PC10 - QSPI_D1 (alternate 9). + * PC11 - DFSDM_DATIN5 (alternate 3). + * PC12 - WIFI_RX (alternate 8). + * PC13 - PIN13 (input pullup). + * PC14 - OSC32_IN (input floating). + * PC15 - OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_ALTERNATE(GPIOC_ULPI_STP) | \ + PIN_MODE_ALTERNATE(GPIOC_RMII_MDC) | \ + PIN_MODE_INPUT(GPIOC_ARD_A2) | \ + PIN_MODE_ALTERNATE(GPIOC_DFSDM_DATIN1) |\ + PIN_MODE_ALTERNATE(GPIOC_RMII_RXD0) | \ + PIN_MODE_ALTERNATE(GPIOC_RMII_RXD1) | \ + PIN_MODE_INPUT(GPIOC_ARD_D1) | \ + PIN_MODE_INPUT(GPIOC_ARD_D0) | \ + PIN_MODE_INPUT(GPIOC_ARD_D5) | \ + PIN_MODE_ALTERNATE(GPIOC_QSPI_D0) | \ + PIN_MODE_ALTERNATE(GPIOC_QSPI_D1) | \ + PIN_MODE_ALTERNATE(GPIOC_DFSDM_DATIN5) |\ + PIN_MODE_ALTERNATE(GPIOC_WIFI_RX) | \ + PIN_MODE_INPUT(GPIOC_PIN13) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ULPI_STP) | \ + PIN_OTYPE_PUSHPULL(GPIOC_RMII_MDC) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_A2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_DFSDM_DATIN1) |\ + PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_D5) | \ + PIN_OTYPE_PUSHPULL(GPIOC_QSPI_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_QSPI_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_DFSDM_DATIN5) |\ + PIN_OTYPE_PUSHPULL(GPIOC_WIFI_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_ULPI_STP) | \ + PIN_OSPEED_HIGH(GPIOC_RMII_MDC) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_A2) | \ + PIN_OSPEED_HIGH(GPIOC_DFSDM_DATIN1) | \ + PIN_OSPEED_HIGH(GPIOC_RMII_RXD0) | \ + PIN_OSPEED_HIGH(GPIOC_RMII_RXD1) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_D1) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_D0) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_D5) | \ + PIN_OSPEED_HIGH(GPIOC_QSPI_D0) | \ + PIN_OSPEED_HIGH(GPIOC_QSPI_D1) | \ + PIN_OSPEED_HIGH(GPIOC_DFSDM_DATIN5) | \ + PIN_OSPEED_HIGH(GPIOC_WIFI_RX) | \ + PIN_OSPEED_HIGH(GPIOC_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOC_OSC32_IN) | \ + PIN_OSPEED_VERYLOW(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_ULPI_STP) | \ + PIN_PUPDR_FLOATING(GPIOC_RMII_MDC) | \ + PIN_PUPDR_PULLUP(GPIOC_ARD_A2) | \ + PIN_PUPDR_FLOATING(GPIOC_DFSDM_DATIN1) |\ + PIN_PUPDR_FLOATING(GPIOC_RMII_RXD0) | \ + PIN_PUPDR_FLOATING(GPIOC_RMII_RXD1) | \ + PIN_PUPDR_PULLUP(GPIOC_ARD_D1) | \ + PIN_PUPDR_FLOATING(GPIOC_ARD_D0) | \ + PIN_PUPDR_FLOATING(GPIOC_ARD_D5) | \ + PIN_PUPDR_FLOATING(GPIOC_QSPI_D0) | \ + PIN_PUPDR_FLOATING(GPIOC_QSPI_D1) | \ + PIN_PUPDR_FLOATING(GPIOC_DFSDM_DATIN5) |\ + PIN_PUPDR_FLOATING(GPIOC_WIFI_RX) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_ULPI_STP) | \ + PIN_ODR_HIGH(GPIOC_RMII_MDC) | \ + PIN_ODR_HIGH(GPIOC_ARD_A2) | \ + PIN_ODR_HIGH(GPIOC_DFSDM_DATIN1) | \ + PIN_ODR_HIGH(GPIOC_RMII_RXD0) | \ + PIN_ODR_HIGH(GPIOC_RMII_RXD1) | \ + PIN_ODR_HIGH(GPIOC_ARD_D1) | \ + PIN_ODR_HIGH(GPIOC_ARD_D0) | \ + PIN_ODR_HIGH(GPIOC_ARD_D5) | \ + PIN_ODR_HIGH(GPIOC_QSPI_D0) | \ + PIN_ODR_HIGH(GPIOC_QSPI_D1) | \ + PIN_ODR_HIGH(GPIOC_DFSDM_DATIN5) | \ + PIN_ODR_HIGH(GPIOC_WIFI_RX) | \ + PIN_ODR_HIGH(GPIOC_PIN13) | \ + PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ + PIN_ODR_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ULPI_STP, 10U) | \ + PIN_AFIO_AF(GPIOC_RMII_MDC, 11U) | \ + PIN_AFIO_AF(GPIOC_ARD_A2, 0U) | \ + PIN_AFIO_AF(GPIOC_DFSDM_DATIN1, 3U) | \ + PIN_AFIO_AF(GPIOC_RMII_RXD0, 11U) | \ + PIN_AFIO_AF(GPIOC_RMII_RXD1, 11U) | \ + PIN_AFIO_AF(GPIOC_ARD_D1, 0U) | \ + PIN_AFIO_AF(GPIOC_ARD_D0, 0U)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_ARD_D5, 0U) | \ + PIN_AFIO_AF(GPIOC_QSPI_D0, 9U) | \ + PIN_AFIO_AF(GPIOC_QSPI_D1, 9U) | \ + PIN_AFIO_AF(GPIOC_DFSDM_DATIN5, 3U) | \ + PIN_AFIO_AF(GPIOC_WIFI_RX, 8U) | \ + PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) + +/* + * GPIOD setup: + * + * PD0 - FMC_D2 (alternate 12). + * PD1 - FMC_D3 (alternate 12). + * PD2 - WIFI_TX (alternate 8). + * PD3 - DFSDM_CKOUT (alternate 3). + * PD4 - OTG_HS_OVER_CURRENT (input floating). + * PD5 - RMII_RXER (alternate 11). + * PD6 - SD_CLK (alternate 11). + * PD7 - SD_CMD (alternate 11). + * PD8 - FMC_D13 (alternate 12). + * PD9 - FMC_D14 (alternate 12). + * PD10 - FMC_D15 (alternate 12). + * PD11 - SPDIF_I2S (alternate 10). + * PD12 - AUDIO_SCL LCD_SCL (alternate 4). + * PD13 - QSPI_D3 (alternate 9). + * PD14 - FMC_D0 (alternate 12). + * PD15 - FMC_D1 (alternate 12). + */ +#define VAL_GPIOD_MODER (PIN_MODE_ALTERNATE(GPIOD_FMC_D2) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D3) | \ + PIN_MODE_ALTERNATE(GPIOD_WIFI_TX) | \ + PIN_MODE_ALTERNATE(GPIOD_DFSDM_CKOUT) |\ + PIN_MODE_INPUT(GPIOD_OTG_HS_OVER_CURRENT) |\ + PIN_MODE_ALTERNATE(GPIOD_RMII_RXER) | \ + PIN_MODE_ALTERNATE(GPIOD_SD_CLK) | \ + PIN_MODE_ALTERNATE(GPIOD_SD_CMD) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D13) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D14) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D15) | \ + PIN_MODE_ALTERNATE(GPIOD_SPDIF_I2S) | \ + PIN_MODE_ALTERNATE(GPIOD_AUDIO_SCL) | \ + PIN_MODE_ALTERNATE(GPIOD_QSPI_D3) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D0) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D1)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_FMC_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_WIFI_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_DFSDM_CKOUT) |\ + PIN_OTYPE_PUSHPULL(GPIOD_OTG_HS_OVER_CURRENT) |\ + PIN_OTYPE_PUSHPULL(GPIOD_RMII_RXER) | \ + PIN_OTYPE_PUSHPULL(GPIOD_SD_CLK) | \ + PIN_OTYPE_PUSHPULL(GPIOD_SD_CMD) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D13) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D14) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D15) | \ + PIN_OTYPE_PUSHPULL(GPIOD_SPDIF_I2S) | \ + PIN_OTYPE_PUSHPULL(GPIOD_AUDIO_SCL) | \ + PIN_OTYPE_PUSHPULL(GPIOD_QSPI_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D1)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_FMC_D2) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D3) | \ + PIN_OSPEED_HIGH(GPIOD_WIFI_TX) | \ + PIN_OSPEED_HIGH(GPIOD_DFSDM_CKOUT) | \ + PIN_OSPEED_HIGH(GPIOD_OTG_HS_OVER_CURRENT) |\ + PIN_OSPEED_HIGH(GPIOD_RMII_RXER) | \ + PIN_OSPEED_HIGH(GPIOD_SD_CLK) | \ + PIN_OSPEED_HIGH(GPIOD_SD_CMD) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D13) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D14) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D15) | \ + PIN_OSPEED_HIGH(GPIOD_SPDIF_I2S) | \ + PIN_OSPEED_HIGH(GPIOD_AUDIO_SCL) | \ + PIN_OSPEED_HIGH(GPIOD_QSPI_D3) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D0) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D1)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_FMC_D2) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D3) | \ + PIN_PUPDR_FLOATING(GPIOD_WIFI_TX) | \ + PIN_PUPDR_FLOATING(GPIOD_DFSDM_CKOUT) |\ + PIN_PUPDR_FLOATING(GPIOD_OTG_HS_OVER_CURRENT) |\ + PIN_PUPDR_FLOATING(GPIOD_RMII_RXER) | \ + PIN_PUPDR_FLOATING(GPIOD_SD_CLK) | \ + PIN_PUPDR_FLOATING(GPIOD_SD_CMD) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D13) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D14) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D15) | \ + PIN_PUPDR_FLOATING(GPIOD_SPDIF_I2S) | \ + PIN_PUPDR_FLOATING(GPIOD_AUDIO_SCL) | \ + PIN_PUPDR_FLOATING(GPIOD_QSPI_D3) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D0) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D1)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_FMC_D2) | \ + PIN_ODR_HIGH(GPIOD_FMC_D3) | \ + PIN_ODR_HIGH(GPIOD_WIFI_TX) | \ + PIN_ODR_HIGH(GPIOD_DFSDM_CKOUT) | \ + PIN_ODR_HIGH(GPIOD_OTG_HS_OVER_CURRENT) |\ + PIN_ODR_HIGH(GPIOD_RMII_RXER) | \ + PIN_ODR_HIGH(GPIOD_SD_CLK) | \ + PIN_ODR_HIGH(GPIOD_SD_CMD) | \ + PIN_ODR_HIGH(GPIOD_FMC_D13) | \ + PIN_ODR_HIGH(GPIOD_FMC_D14) | \ + PIN_ODR_HIGH(GPIOD_FMC_D15) | \ + PIN_ODR_HIGH(GPIOD_SPDIF_I2S) | \ + PIN_ODR_HIGH(GPIOD_AUDIO_SCL) | \ + PIN_ODR_HIGH(GPIOD_QSPI_D3) | \ + PIN_ODR_LOW(GPIOD_FMC_D0) | \ + PIN_ODR_LOW(GPIOD_FMC_D1)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_FMC_D2, 12U) | \ + PIN_AFIO_AF(GPIOD_FMC_D3, 12U) | \ + PIN_AFIO_AF(GPIOD_WIFI_TX, 8U) | \ + PIN_AFIO_AF(GPIOD_DFSDM_CKOUT, 3U) | \ + PIN_AFIO_AF(GPIOD_OTG_HS_OVER_CURRENT, 0U) |\ + PIN_AFIO_AF(GPIOD_RMII_RXER, 11U) | \ + PIN_AFIO_AF(GPIOD_SD_CLK, 11U) | \ + PIN_AFIO_AF(GPIOD_SD_CMD, 11U)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_FMC_D13, 12U) | \ + PIN_AFIO_AF(GPIOD_FMC_D14, 12U) | \ + PIN_AFIO_AF(GPIOD_FMC_D15, 12U) | \ + PIN_AFIO_AF(GPIOD_SPDIF_I2S, 10U) | \ + PIN_AFIO_AF(GPIOD_AUDIO_SCL, 4U) | \ + PIN_AFIO_AF(GPIOD_QSPI_D3, 9U) | \ + PIN_AFIO_AF(GPIOD_FMC_D0, 12U) | \ + PIN_AFIO_AF(GPIOD_FMC_D1, 12U)) + +/* + * GPIOE setup: + * + * PE0 - FMC_NBL0 (alternate 12). + * PE1 - FMC_NBL1 (alternate 12). + * PE2 - QSPI_D2 (alternate 9). + * PE3 - SAI1_SDB (alternate 6). + * PE4 - SAI1_FSA (alternate 6). + * PE5 - SAI1_SCKA (alternate 6). + * PE6 - SAI1_SDA (alternate 6). + * PE7 - FMC_D4 (alternate 12). + * PE8 - FMC_D5 (alternate 12). + * PE9 - FMC_D6 (alternate 12). + * PE10 - FMC_D7 (alternate 12). + * PE11 - FMC_D8 (alternate 12). + * PE12 - FMC_D9 (alternate 12). + * PE13 - FMC_D10 (alternate 12). + * PE14 - FMC_11 (alternate 12). + * PE15 - FMC_D12 (alternate 12). + */ +#define VAL_GPIOE_MODER (PIN_MODE_ALTERNATE(GPIOE_FMC_NBL0) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_NBL1) | \ + PIN_MODE_ALTERNATE(GPIOE_QSPI_D2) | \ + PIN_MODE_ALTERNATE(GPIOE_SAI1_SDB) | \ + PIN_MODE_ALTERNATE(GPIOE_SAI1_FSA) | \ + PIN_MODE_ALTERNATE(GPIOE_SAI1_SCKA) | \ + PIN_MODE_ALTERNATE(GPIOE_SAI1_SDA) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D4) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D5) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D6) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D7) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D8) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D9) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D10) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_11) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D12)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_FMC_NBL0) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_NBL1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_QSPI_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SAI1_SDB) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SAI1_FSA) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SAI1_SCKA) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SAI1_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D8) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D12)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_FMC_NBL0) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_NBL1) | \ + PIN_OSPEED_HIGH(GPIOE_QSPI_D2) | \ + PIN_OSPEED_HIGH(GPIOE_SAI1_SDB) | \ + PIN_OSPEED_HIGH(GPIOE_SAI1_FSA) | \ + PIN_OSPEED_HIGH(GPIOE_SAI1_SCKA) | \ + PIN_OSPEED_HIGH(GPIOE_SAI1_SDA) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D4) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D5) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D6) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D7) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D8) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D9) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D10) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_11) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D12)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_FMC_NBL0) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_NBL1) | \ + PIN_PUPDR_FLOATING(GPIOE_QSPI_D2) | \ + PIN_PUPDR_FLOATING(GPIOE_SAI1_SDB) | \ + PIN_PUPDR_FLOATING(GPIOE_SAI1_FSA) | \ + PIN_PUPDR_FLOATING(GPIOE_SAI1_SCKA) | \ + PIN_PUPDR_FLOATING(GPIOE_SAI1_SDA) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D4) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D5) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D6) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D7) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D8) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D9) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D10) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_11) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D12)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_FMC_NBL0) | \ + PIN_ODR_HIGH(GPIOE_FMC_NBL1) | \ + PIN_ODR_HIGH(GPIOE_QSPI_D2) | \ + PIN_ODR_HIGH(GPIOE_SAI1_SDB) | \ + PIN_ODR_HIGH(GPIOE_SAI1_FSA) | \ + PIN_ODR_HIGH(GPIOE_SAI1_SCKA) | \ + PIN_ODR_HIGH(GPIOE_SAI1_SDA) | \ + PIN_ODR_HIGH(GPIOE_FMC_D4) | \ + PIN_ODR_HIGH(GPIOE_FMC_D5) | \ + PIN_ODR_HIGH(GPIOE_FMC_D6) | \ + PIN_ODR_HIGH(GPIOE_FMC_D7) | \ + PIN_ODR_HIGH(GPIOE_FMC_D8) | \ + PIN_ODR_HIGH(GPIOE_FMC_D9) | \ + PIN_ODR_HIGH(GPIOE_FMC_D10) | \ + PIN_ODR_HIGH(GPIOE_FMC_11) | \ + PIN_ODR_HIGH(GPIOE_FMC_D12)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_FMC_NBL0, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_NBL1, 12U) | \ + PIN_AFIO_AF(GPIOE_QSPI_D2, 9U) | \ + PIN_AFIO_AF(GPIOE_SAI1_SDB, 6U) | \ + PIN_AFIO_AF(GPIOE_SAI1_FSA, 6U) | \ + PIN_AFIO_AF(GPIOE_SAI1_SCKA, 6U) | \ + PIN_AFIO_AF(GPIOE_SAI1_SDA, 6U) | \ + PIN_AFIO_AF(GPIOE_FMC_D4, 12U)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_FMC_D5, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_D6, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_D7, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_D8, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_D9, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_D10, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_11, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_D12, 12U)) + +/* + * GPIOF setup: + * + * PF0 - FMC_A0 (alternate 12). + * PF1 - FMC_A1 (alternate 12). + * PF2 - FMC_A2 (alternate 12). + * PF3 - FMC_A3 (alternate 12). + * PF4 - FMC_A4 (alternate 12). + * PF5 - FMC_A5 (alternate 12). + * PF6 - ARD_D3 (input pullup). + * PF7 - ARD_D6 (input pullup). + * PF8 - ARD_A4 (input pullup). + * PF9 - ARD_A5 (input pullup). + * PF10 - ARD_A3 (input pullup). + * PF11 - FMC_SDNRAS (alternate 12). + * PF12 - FMC_A6 (alternate 12). + * PF13 - FMC_A7 (alternate 12). + * PF14 - FMC_A8 (alternate 12). + * PF15 - FMC_A9 (alternate 12). + */ +#define VAL_GPIOF_MODER (PIN_MODE_ALTERNATE(GPIOF_FMC_A0) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A1) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A2) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A3) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A4) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A5) | \ + PIN_MODE_INPUT(GPIOF_ARD_D3) | \ + PIN_MODE_INPUT(GPIOF_ARD_D6) | \ + PIN_MODE_INPUT(GPIOF_ARD_A4) | \ + PIN_MODE_INPUT(GPIOF_ARD_A5) | \ + PIN_MODE_INPUT(GPIOF_ARD_A3) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_SDNRAS) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A6) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A7) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A8) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A9)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_FMC_A0) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A1) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_A4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_A5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_A3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_SDNRAS) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A9)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_FMC_A0) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A1) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A2) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A3) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A4) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A5) | \ + PIN_OSPEED_HIGH(GPIOF_ARD_D3) | \ + PIN_OSPEED_HIGH(GPIOF_ARD_D6) | \ + PIN_OSPEED_HIGH(GPIOF_ARD_A4) | \ + PIN_OSPEED_HIGH(GPIOF_ARD_A5) | \ + PIN_OSPEED_HIGH(GPIOF_ARD_A3) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_SDNRAS) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A6) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A7) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A8) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A9)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_FMC_A0) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A1) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A2) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A3) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A4) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A5) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_D3) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_D6) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_A4) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_A5) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_A3) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_SDNRAS) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A6) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A7) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A8) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A9)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_FMC_A0) | \ + PIN_ODR_HIGH(GPIOF_FMC_A1) | \ + PIN_ODR_HIGH(GPIOF_FMC_A2) | \ + PIN_ODR_HIGH(GPIOF_FMC_A3) | \ + PIN_ODR_HIGH(GPIOF_FMC_A4) | \ + PIN_ODR_HIGH(GPIOF_FMC_A5) | \ + PIN_ODR_HIGH(GPIOF_ARD_D3) | \ + PIN_ODR_HIGH(GPIOF_ARD_D6) | \ + PIN_ODR_HIGH(GPIOF_ARD_A4) | \ + PIN_ODR_HIGH(GPIOF_ARD_A5) | \ + PIN_ODR_HIGH(GPIOF_ARD_A3) | \ + PIN_ODR_HIGH(GPIOF_FMC_SDNRAS) | \ + PIN_ODR_HIGH(GPIOF_FMC_A6) | \ + PIN_ODR_HIGH(GPIOF_FMC_A7) | \ + PIN_ODR_HIGH(GPIOF_FMC_A8) | \ + PIN_ODR_HIGH(GPIOF_FMC_A9)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_FMC_A0, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A1, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A2, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A3, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A4, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A5, 12U) | \ + PIN_AFIO_AF(GPIOF_ARD_D3, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_D6, 0U)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_ARD_A4, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_A5, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_A3, 0U) | \ + PIN_AFIO_AF(GPIOF_FMC_SDNRAS, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A6, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A7, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A8, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A9, 12U)) + +/* + * GPIOG setup: + * + * PG0 - FMC_A10 (alternate 12). + * PG1 - FMC_A11 (alternate 12). + * PG2 - FMC_A12 (alternate 12). + * PG3 - EXT_SCL (input pullup). + * PG4 - FMC_BA0 (alternate 12). + * PG5 - FMC_BA1 (alternate 12). + * PG6 - EXT_SDA (input pullup). + * PG7 - SAI1_MCLKA (alternate 6). + * PG8 - FMC_SDCLK (alternate 12). + * PG9 - SD_D0 (alternate 11). + * PG10 - SD_D1 (alternate 11). + * PG11 - RMII_TX_EN (alternate 11). + * PG12 - SPDIF_RX (alternate 7). + * PG13 - RMII_TXD0 (alternate 11). + * PG14 - RMII_TXD1 (alternate 11). + * PG15 - FMC_SDNCAS (alternate 12). + */ +#define VAL_GPIOG_MODER (PIN_MODE_ALTERNATE(GPIOG_FMC_A10) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_A11) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_A12) | \ + PIN_MODE_INPUT(GPIOG_EXT_SCL) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_BA0) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_BA1) | \ + PIN_MODE_INPUT(GPIOG_EXT_SDA) | \ + PIN_MODE_ALTERNATE(GPIOG_SAI1_MCLKA) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_SDCLK) | \ + PIN_MODE_ALTERNATE(GPIOG_SD_D0) | \ + PIN_MODE_ALTERNATE(GPIOG_SD_D1) | \ + PIN_MODE_ALTERNATE(GPIOG_RMII_TX_EN) | \ + PIN_MODE_ALTERNATE(GPIOG_SPDIF_RX) | \ + PIN_MODE_ALTERNATE(GPIOG_RMII_TXD0) | \ + PIN_MODE_ALTERNATE(GPIOG_RMII_TXD1) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_FMC_A10) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_A11) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_A12) | \ + PIN_OTYPE_PUSHPULL(GPIOG_EXT_SCL) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_BA0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_BA1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_EXT_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOG_SAI1_MCLKA) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_SDCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOG_SD_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_SD_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_RMII_TX_EN) | \ + PIN_OTYPE_PUSHPULL(GPIOG_SPDIF_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOG_RMII_TXD0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_RMII_TXD1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_FMC_A10) | \ + PIN_OSPEED_HIGH(GPIOG_FMC_A11) | \ + PIN_OSPEED_HIGH(GPIOG_FMC_A12) | \ + PIN_OSPEED_HIGH(GPIOG_EXT_SCL) | \ + PIN_OSPEED_HIGH(GPIOG_FMC_BA0) | \ + PIN_OSPEED_HIGH(GPIOG_FMC_BA1) | \ + PIN_OSPEED_HIGH(GPIOG_EXT_SDA) | \ + PIN_OSPEED_HIGH(GPIOG_SAI1_MCLKA) | \ + PIN_OSPEED_HIGH(GPIOG_FMC_SDCLK) | \ + PIN_OSPEED_HIGH(GPIOG_SD_D0) | \ + PIN_OSPEED_HIGH(GPIOG_SD_D1) | \ + PIN_OSPEED_HIGH(GPIOG_RMII_TX_EN) | \ + PIN_OSPEED_HIGH(GPIOG_SPDIF_RX) | \ + PIN_OSPEED_HIGH(GPIOG_RMII_TXD0) | \ + PIN_OSPEED_HIGH(GPIOG_RMII_TXD1) | \ + PIN_OSPEED_HIGH(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_FMC_A10) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_A11) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_A12) | \ + PIN_PUPDR_PULLUP(GPIOG_EXT_SCL) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_BA0) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_BA1) | \ + PIN_PUPDR_PULLUP(GPIOG_EXT_SDA) | \ + PIN_PUPDR_PULLUP(GPIOG_SAI1_MCLKA) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_SDCLK) | \ + PIN_PUPDR_FLOATING(GPIOG_SD_D0) | \ + PIN_PUPDR_FLOATING(GPIOG_SD_D1) | \ + PIN_PUPDR_FLOATING(GPIOG_RMII_TX_EN) | \ + PIN_PUPDR_FLOATING(GPIOG_SPDIF_RX) | \ + PIN_PUPDR_FLOATING(GPIOG_RMII_TXD0) | \ + PIN_PUPDR_FLOATING(GPIOG_RMII_TXD1) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_FMC_A10) | \ + PIN_ODR_HIGH(GPIOG_FMC_A11) | \ + PIN_ODR_HIGH(GPIOG_FMC_A12) | \ + PIN_ODR_HIGH(GPIOG_EXT_SCL) | \ + PIN_ODR_HIGH(GPIOG_FMC_BA0) | \ + PIN_ODR_HIGH(GPIOG_FMC_BA1) | \ + PIN_ODR_HIGH(GPIOG_EXT_SDA) | \ + PIN_ODR_HIGH(GPIOG_SAI1_MCLKA) | \ + PIN_ODR_HIGH(GPIOG_FMC_SDCLK) | \ + PIN_ODR_HIGH(GPIOG_SD_D0) | \ + PIN_ODR_HIGH(GPIOG_SD_D1) | \ + PIN_ODR_HIGH(GPIOG_RMII_TX_EN) | \ + PIN_ODR_HIGH(GPIOG_SPDIF_RX) | \ + PIN_ODR_HIGH(GPIOG_RMII_TXD0) | \ + PIN_ODR_HIGH(GPIOG_RMII_TXD1) | \ + PIN_ODR_HIGH(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_FMC_A10, 12U) | \ + PIN_AFIO_AF(GPIOG_FMC_A11, 12U) | \ + PIN_AFIO_AF(GPIOG_FMC_A12, 12U) | \ + PIN_AFIO_AF(GPIOG_EXT_SCL, 0U) | \ + PIN_AFIO_AF(GPIOG_FMC_BA0, 12U) | \ + PIN_AFIO_AF(GPIOG_FMC_BA1, 12U) | \ + PIN_AFIO_AF(GPIOG_EXT_SDA, 0U) | \ + PIN_AFIO_AF(GPIOG_SAI1_MCLKA, 6U)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_FMC_SDCLK, 12U) | \ + PIN_AFIO_AF(GPIOG_SD_D0, 11U) | \ + PIN_AFIO_AF(GPIOG_SD_D1, 11U) | \ + PIN_AFIO_AF(GPIOG_RMII_TX_EN, 11U) | \ + PIN_AFIO_AF(GPIOG_SPDIF_RX, 7U) | \ + PIN_AFIO_AF(GPIOG_RMII_TXD0, 11U) | \ + PIN_AFIO_AF(GPIOG_RMII_TXD1, 11U) | \ + PIN_AFIO_AF(GPIOG_FMC_SDNCAS, 12U)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - FMC_SDCKE0 (alternate 12). + * PH3 - FMC_SDNE0 (alternate 12). + * PH4 - ULPI_NXT (alternate 10). + * PH5 - FMC_SDNWE (alternate 12). + * PH6 - ARD_D9 (input pullup). + * PH7 - EXT_RST (input floating). + * PH8 - FMC_D16 (alternate 12). + * PH9 - FMC_D17 (alternate 12). + * PH10 - FMC_D18 (alternate 12). + * PH11 - FMC_D19 (alternate 12). + * PH12 - FMC_D20 (alternate 12). + * PH13 - FMC_D21 (alternate 12). + * PH14 - FMC_D22 (alternate 12). + * PH15 - FMC_D23 (alternate 12). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_SDCKE0) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_SDNE0) | \ + PIN_MODE_ALTERNATE(GPIOH_ULPI_NXT) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_SDNWE) | \ + PIN_MODE_INPUT(GPIOH_ARD_D9) | \ + PIN_MODE_INPUT(GPIOH_EXT_RST) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_D16) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_D17) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_D18) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_D19) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_D20) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_D21) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_D22) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_D23)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_SDCKE0) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_SDNE0) | \ + PIN_OTYPE_PUSHPULL(GPIOH_ULPI_NXT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_SDNWE) | \ + PIN_OTYPE_PUSHPULL(GPIOH_ARD_D9) | \ + PIN_OTYPE_OPENDRAIN(GPIOH_EXT_RST) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_D16) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_D17) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_D18) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_D19) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_D20) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_D21) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_D22) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_D23)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ + PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_SDCKE0) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_SDNE0) | \ + PIN_OSPEED_HIGH(GPIOH_ULPI_NXT) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_SDNWE) | \ + PIN_OSPEED_HIGH(GPIOH_ARD_D9) | \ + PIN_OSPEED_HIGH(GPIOH_EXT_RST) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_D16) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_D17) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_D18) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_D19) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_D20) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_D21) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_D22) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_D23)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_SDCKE0) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_SDNE0) | \ + PIN_PUPDR_FLOATING(GPIOH_ULPI_NXT) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_SDNWE) | \ + PIN_PUPDR_PULLUP(GPIOH_ARD_D9) | \ + PIN_PUPDR_FLOATING(GPIOH_EXT_RST) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_D16) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_D17) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_D18) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_D19) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_D20) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_D21) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_D22) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_D23)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_FMC_SDCKE0) | \ + PIN_ODR_HIGH(GPIOH_FMC_SDNE0) | \ + PIN_ODR_HIGH(GPIOH_ULPI_NXT) | \ + PIN_ODR_HIGH(GPIOH_FMC_SDNWE) | \ + PIN_ODR_HIGH(GPIOH_ARD_D9) | \ + PIN_ODR_HIGH(GPIOH_EXT_RST) | \ + PIN_ODR_HIGH(GPIOH_FMC_D16) | \ + PIN_ODR_HIGH(GPIOH_FMC_D17) | \ + PIN_ODR_HIGH(GPIOH_FMC_D18) | \ + PIN_ODR_HIGH(GPIOH_FMC_D19) | \ + PIN_ODR_HIGH(GPIOH_FMC_D20) | \ + PIN_ODR_HIGH(GPIOH_FMC_D21) | \ + PIN_ODR_HIGH(GPIOH_FMC_D22) | \ + PIN_ODR_HIGH(GPIOH_FMC_D23)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ + PIN_AFIO_AF(GPIOH_FMC_SDCKE0, 12U) | \ + PIN_AFIO_AF(GPIOH_FMC_SDNE0, 12U) | \ + PIN_AFIO_AF(GPIOH_ULPI_NXT, 10U) | \ + PIN_AFIO_AF(GPIOH_FMC_SDNWE, 12U) | \ + PIN_AFIO_AF(GPIOH_ARD_D9, 0U) | \ + PIN_AFIO_AF(GPIOH_EXT_RST, 0U)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_FMC_D16, 12U) | \ + PIN_AFIO_AF(GPIOH_FMC_D17, 12U) | \ + PIN_AFIO_AF(GPIOH_FMC_D18, 12U) | \ + PIN_AFIO_AF(GPIOH_FMC_D19, 12U) | \ + PIN_AFIO_AF(GPIOH_FMC_D20, 12U) | \ + PIN_AFIO_AF(GPIOH_FMC_D21, 12U) | \ + PIN_AFIO_AF(GPIOH_FMC_D22, 12U) | \ + PIN_AFIO_AF(GPIOH_FMC_D23, 12U)) + +/* + * GPIOI setup: + * + * PI0 - FMC_D24 (alternate 12). + * PI1 - FMC_D25 (alternate 12). + * PI2 - FMC_D26 (alternate 12). + * PI3 - FMC_D27 (alternate 12). + * PI4 - FMC_NBL2 (alternate 12). + * PI5 - FMC_NBL3 (alternate 12). + * PI6 - FMC_D28 (alternate 12). + * PI7 - FMC_D29 (alternate 12). + * PI8 - PIN8 (input pullup). + * PI9 - FMC_D30 (alternate 12). + * PI10 - FMC_D31 (alternate 12). + * PI11 - ULPI_DIR (alternate 10). + * PI12 - PIN12 (input pullup). + * PI13 - LCD_INT (alternate 14). + * PI14 - LCD_BL_CTRL (alternate 14). + * PI15 - SD_DETECT (input pullup). + */ +#define VAL_GPIOI_MODER (PIN_MODE_ALTERNATE(GPIOI_FMC_D24) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_D25) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_D26) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_D27) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_NBL2) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_NBL3) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_D28) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_D29) | \ + PIN_MODE_INPUT(GPIOI_PIN8) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_D30) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_D31) | \ + PIN_MODE_ALTERNATE(GPIOI_ULPI_DIR) | \ + PIN_MODE_INPUT(GPIOI_PIN12) | \ + PIN_MODE_ALTERNATE(GPIOI_LCD_INT) | \ + PIN_MODE_ALTERNATE(GPIOI_LCD_BL_CTRL) |\ + PIN_MODE_INPUT(GPIOI_SD_DETECT)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_FMC_D24) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_D25) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_D26) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_D27) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_NBL2) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_NBL3) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_D28) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_D29) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_D30) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_D31) | \ + PIN_OTYPE_PUSHPULL(GPIOI_ULPI_DIR) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOI_LCD_INT) | \ + PIN_OTYPE_PUSHPULL(GPIOI_LCD_BL_CTRL) |\ + PIN_OTYPE_PUSHPULL(GPIOI_SD_DETECT)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_HIGH(GPIOI_FMC_D24) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_D25) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_D26) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_D27) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_NBL2) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_NBL3) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_D28) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_D29) | \ + PIN_OSPEED_HIGH(GPIOI_PIN8) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_D30) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_D31) | \ + PIN_OSPEED_HIGH(GPIOI_ULPI_DIR) | \ + PIN_OSPEED_HIGH(GPIOI_PIN12) | \ + PIN_OSPEED_HIGH(GPIOI_LCD_INT) | \ + PIN_OSPEED_HIGH(GPIOI_LCD_BL_CTRL) | \ + PIN_OSPEED_HIGH(GPIOI_SD_DETECT)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(GPIOI_FMC_D24) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_D25) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_D26) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_D27) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_NBL2) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_NBL3) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_D28) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_D29) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_D30) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_D31) | \ + PIN_PUPDR_FLOATING(GPIOI_ULPI_DIR) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOI_LCD_INT) | \ + PIN_PUPDR_FLOATING(GPIOI_LCD_BL_CTRL) |\ + PIN_PUPDR_PULLUP(GPIOI_SD_DETECT)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_FMC_D24) | \ + PIN_ODR_HIGH(GPIOI_FMC_D25) | \ + PIN_ODR_HIGH(GPIOI_FMC_D26) | \ + PIN_ODR_HIGH(GPIOI_FMC_D27) | \ + PIN_ODR_HIGH(GPIOI_FMC_NBL2) | \ + PIN_ODR_HIGH(GPIOI_FMC_NBL3) | \ + PIN_ODR_HIGH(GPIOI_FMC_D28) | \ + PIN_ODR_HIGH(GPIOI_FMC_D29) | \ + PIN_ODR_HIGH(GPIOI_PIN8) | \ + PIN_ODR_HIGH(GPIOI_FMC_D30) | \ + PIN_ODR_HIGH(GPIOI_FMC_D31) | \ + PIN_ODR_HIGH(GPIOI_ULPI_DIR) | \ + PIN_ODR_HIGH(GPIOI_PIN12) | \ + PIN_ODR_HIGH(GPIOI_LCD_INT) | \ + PIN_ODR_HIGH(GPIOI_LCD_BL_CTRL) | \ + PIN_ODR_HIGH(GPIOI_SD_DETECT)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_FMC_D24, 12U) | \ + PIN_AFIO_AF(GPIOI_FMC_D25, 12U) | \ + PIN_AFIO_AF(GPIOI_FMC_D26, 12U) | \ + PIN_AFIO_AF(GPIOI_FMC_D27, 12U) | \ + PIN_AFIO_AF(GPIOI_FMC_NBL2, 12U) | \ + PIN_AFIO_AF(GPIOI_FMC_NBL3, 12U) | \ + PIN_AFIO_AF(GPIOI_FMC_D28, 12U) | \ + PIN_AFIO_AF(GPIOI_FMC_D29, 12U)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOI_FMC_D30, 12U) | \ + PIN_AFIO_AF(GPIOI_FMC_D31, 12U) | \ + PIN_AFIO_AF(GPIOI_ULPI_DIR, 10U) | \ + PIN_AFIO_AF(GPIOI_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOI_LCD_INT, 14U) | \ + PIN_AFIO_AF(GPIOI_LCD_BL_CTRL, 14U) | \ + PIN_AFIO_AF(GPIOI_SD_DETECT, 0U)) + +/* + * GPIOJ setup: + * + * PJ0 - ARD_D4 (input floating). + * PJ1 - ARD_D2 (input floating). + * PJ2 - DSI_TE (alternate 13). + * PJ3 - ARD_D7 (input floating). + * PJ4 - ARD_D8 (input floating). + * PJ5 - LED2_GREEN (output pushpull maximum). + * PJ6 - PIN6 (input floating). + * PJ7 - PIN7 (input floating). + * PJ8 - PIN8 (input floating). + * PJ9 - PIN9 (input floating). + * PJ10 - PIN10 (input floating). + * PJ11 - PIN11 (input floating). + * PJ12 - AUDIO_INT (input floating). + * PJ13 - LED1_RED (output pushpull maximum). + * PJ14 - WIFI_RST (input floating). + * PJ15 - DSI_RESET (input floating). + */ +#define VAL_GPIOJ_MODER (PIN_MODE_INPUT(GPIOJ_ARD_D4) | \ + PIN_MODE_INPUT(GPIOJ_ARD_D2) | \ + PIN_MODE_ALTERNATE(GPIOJ_DSI_TE) | \ + PIN_MODE_INPUT(GPIOJ_ARD_D7) | \ + PIN_MODE_INPUT(GPIOJ_ARD_D8) | \ + PIN_MODE_OUTPUT(GPIOJ_LED2_GREEN) | \ + PIN_MODE_INPUT(GPIOJ_PIN6) | \ + PIN_MODE_INPUT(GPIOJ_PIN7) | \ + PIN_MODE_INPUT(GPIOJ_PIN8) | \ + PIN_MODE_INPUT(GPIOJ_PIN9) | \ + PIN_MODE_INPUT(GPIOJ_PIN10) | \ + PIN_MODE_INPUT(GPIOJ_PIN11) | \ + PIN_MODE_INPUT(GPIOJ_AUDIO_INT) | \ + PIN_MODE_OUTPUT(GPIOJ_LED1_RED) | \ + PIN_MODE_INPUT(GPIOJ_WIFI_RST) | \ + PIN_MODE_OUTPUT(GPIOJ_DSI_RESET)) // LCD/TFT +#define VAL_GPIOJ_OTYPER (PIN_OTYPE_PUSHPULL(GPIOJ_ARD_D4) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_ARD_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_DSI_TE) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_ARD_D7) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_ARD_D8) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_LED2_GREEN) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_AUDIO_INT) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_LED1_RED) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_WIFI_RST) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_DSI_RESET)) +#define VAL_GPIOJ_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOJ_ARD_D4) | \ + PIN_OSPEED_VERYLOW(GPIOJ_ARD_D2) | \ + PIN_OSPEED_VERYLOW(GPIOJ_DSI_TE) | \ + PIN_OSPEED_VERYLOW(GPIOJ_ARD_D7) | \ + PIN_OSPEED_VERYLOW(GPIOJ_ARD_D8) | \ + PIN_OSPEED_HIGH(GPIOJ_LED2_GREEN) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOJ_AUDIO_INT) | \ + PIN_OSPEED_HIGH(GPIOJ_LED1_RED) | \ + PIN_OSPEED_VERYLOW(GPIOJ_WIFI_RST) | \ + PIN_OSPEED_HIGH(GPIOJ_DSI_RESET)) +#define VAL_GPIOJ_PUPDR (PIN_PUPDR_FLOATING(GPIOJ_ARD_D4) | \ + PIN_PUPDR_FLOATING(GPIOJ_ARD_D2) | \ + PIN_PUPDR_FLOATING(GPIOJ_DSI_TE) | \ + PIN_PUPDR_FLOATING(GPIOJ_ARD_D7) | \ + PIN_PUPDR_FLOATING(GPIOJ_ARD_D8) | \ + PIN_PUPDR_FLOATING(GPIOJ_LED2_GREEN) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOJ_AUDIO_INT) | \ + PIN_PUPDR_FLOATING(GPIOJ_LED1_RED) | \ + PIN_PUPDR_FLOATING(GPIOJ_WIFI_RST) | \ + PIN_PUPDR_PULLUP(GPIOJ_DSI_RESET)) +#define VAL_GPIOJ_ODR (PIN_ODR_HIGH(GPIOJ_ARD_D4) | \ + PIN_ODR_HIGH(GPIOJ_ARD_D2) | \ + PIN_ODR_HIGH(GPIOJ_DSI_TE) | \ + PIN_ODR_HIGH(GPIOJ_ARD_D7) | \ + PIN_ODR_HIGH(GPIOJ_ARD_D8) | \ + PIN_ODR_LOW(GPIOJ_LED2_GREEN) | \ + PIN_ODR_HIGH(GPIOJ_PIN6) | \ + PIN_ODR_HIGH(GPIOJ_PIN7) | \ + PIN_ODR_HIGH(GPIOJ_PIN8) | \ + PIN_ODR_HIGH(GPIOJ_PIN9) | \ + PIN_ODR_HIGH(GPIOJ_PIN10) | \ + PIN_ODR_HIGH(GPIOJ_PIN11) | \ + PIN_ODR_HIGH(GPIOJ_AUDIO_INT) | \ + PIN_ODR_LOW(GPIOJ_LED1_RED) | \ + PIN_ODR_HIGH(GPIOJ_WIFI_RST) | \ + PIN_ODR_HIGH(GPIOJ_DSI_RESET)) +#define VAL_GPIOJ_AFRL (PIN_AFIO_AF(GPIOJ_ARD_D4, 0U) | \ + PIN_AFIO_AF(GPIOJ_ARD_D2, 0U) | \ + PIN_AFIO_AF(GPIOJ_DSI_TE, 13U) | \ + PIN_AFIO_AF(GPIOJ_ARD_D7, 0U) | \ + PIN_AFIO_AF(GPIOJ_ARD_D8, 0U) | \ + PIN_AFIO_AF(GPIOJ_LED2_GREEN, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN7, 0U)) +#define VAL_GPIOJ_AFRH (PIN_AFIO_AF(GPIOJ_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOJ_AUDIO_INT, 0U) | \ + PIN_AFIO_AF(GPIOJ_LED1_RED, 0U) | \ + PIN_AFIO_AF(GPIOJ_WIFI_RST, 0U) | \ + PIN_AFIO_AF(GPIOJ_DSI_RESET, 0U)) + +/* + * GPIOK setup: + * + * PK0 - PIN0 (input floating). + * PK1 - PIN1 (input floating). + * PK2 - PIN2 (input floating). + * PK3 - PIN3 (input floating). + * PK4 - PIN4 (input floating). + * PK5 - PIN5 (input floating). + * PK6 - PIN6 (input floating). + * PK7 - PIN7 (input floating). + * PK8 - PIN8 (input floating). + * PK9 - PIN9 (input floating). + * PK10 - PIN10 (input floating). + * PK11 - PIN11 (input floating). + * PK12 - PIN12 (input floating). + * PK13 - PIN13 (input floating). + * PK14 - PIN14 (input floating). + * PK15 - PIN15 (input floating). + */ +#define VAL_GPIOK_MODER (PIN_MODE_INPUT(GPIOK_PIN0) | \ + PIN_MODE_INPUT(GPIOK_PIN1) | \ + PIN_MODE_INPUT(GPIOK_PIN2) | \ + PIN_MODE_INPUT(GPIOK_PIN3) | \ + PIN_MODE_INPUT(GPIOK_PIN4) | \ + PIN_MODE_INPUT(GPIOK_PIN5) | \ + PIN_MODE_INPUT(GPIOK_PIN6) | \ + PIN_MODE_INPUT(GPIOK_PIN7) | \ + PIN_MODE_INPUT(GPIOK_PIN8) | \ + PIN_MODE_INPUT(GPIOK_PIN9) | \ + PIN_MODE_INPUT(GPIOK_PIN10) | \ + PIN_MODE_INPUT(GPIOK_PIN11) | \ + PIN_MODE_INPUT(GPIOK_PIN12) | \ + PIN_MODE_INPUT(GPIOK_PIN13) | \ + PIN_MODE_INPUT(GPIOK_PIN14) | \ + PIN_MODE_INPUT(GPIOK_PIN15)) +#define VAL_GPIOK_OTYPER (PIN_OTYPE_PUSHPULL(GPIOK_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN15)) +#define VAL_GPIOK_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOK_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN15)) +#define VAL_GPIOK_PUPDR (PIN_PUPDR_FLOATING(GPIOK_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN15)) +#define VAL_GPIOK_ODR (PIN_ODR_HIGH(GPIOK_PIN0) | \ + PIN_ODR_HIGH(GPIOK_PIN1) | \ + PIN_ODR_HIGH(GPIOK_PIN2) | \ + PIN_ODR_HIGH(GPIOK_PIN3) | \ + PIN_ODR_HIGH(GPIOK_PIN4) | \ + PIN_ODR_HIGH(GPIOK_PIN5) | \ + PIN_ODR_HIGH(GPIOK_PIN6) | \ + PIN_ODR_HIGH(GPIOK_PIN7) | \ + PIN_ODR_HIGH(GPIOK_PIN8) | \ + PIN_ODR_HIGH(GPIOK_PIN9) | \ + PIN_ODR_HIGH(GPIOK_PIN10) | \ + PIN_ODR_HIGH(GPIOK_PIN11) | \ + PIN_ODR_HIGH(GPIOK_PIN12) | \ + PIN_ODR_HIGH(GPIOK_PIN13) | \ + PIN_ODR_HIGH(GPIOK_PIN14) | \ + PIN_ODR_HIGH(GPIOK_PIN15)) +#define VAL_GPIOK_AFRL (PIN_AFIO_AF(GPIOK_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN7, 0U)) +#define VAL_GPIOK_AFRH (PIN_AFIO_AF(GPIOK_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN15, 0U)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* BOARD_H */ diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/CMakeLists.txt b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/CMakeLists.txt new file mode 100644 index 0000000000..190dc7f5fd --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/CMakeLists.txt @@ -0,0 +1,13 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c") +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_ConfigurationManager.cpp") + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") + +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/Device_BlockStorage-DEBUG.c b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 0000000000..05c8653805 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,106 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 32kB blocks +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 0 }, // 08000000 nanoBooter + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + { BlockRange_BLOCKTYPE_CONFIG , 1, 1 }, // 08008000 configuration block + /////////////////////////////////////////////////////////////////////////////////////// + + { BlockRange_BLOCKTYPE_CODE , 2, 3 } // 08010000 nanoCLR +}; + +//128kB block +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 08020000 nanoCLR +}; + +// 256kB blocks +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 2 }, // 08040000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 3, 6 } // 08100000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x8000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + (0), // no attributes for this region + 0x08020000, // start address for block region + 1, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + (0), // no attributes for this region + 0x08040000, // start address for block region + 7, // total number of blocks in this region + 0x40000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), // STM32 flash memory is XIP + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00200000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/Device_BlockStorage.c b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/Device_BlockStorage.c new file mode 100644 index 0000000000..717f0fc94e --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/Device_BlockStorage.c @@ -0,0 +1,102 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 32kB blocks +const BlockRange BlockRange1[] = { + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 0}, // 0x08000000 nanoBooter + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + {BlockRange_BLOCKTYPE_CONFIG, 1, 1}, // 0x08008000 configuration block + /////////////////////////////////////////////////////////////////////////////////////// + + {BlockRange_BLOCKTYPE_CODE, 2, 3} // 0x08010000 nanoCLR +}; + +// 128kB block +const BlockRange BlockRange2[] = { + {BlockRange_BLOCKTYPE_CODE, 0, 0} // 0x08020000 nanoCLR +}; + +// 256kB blocks +const BlockRange BlockRange3[] = { + {BlockRange_BLOCKTYPE_CODE, 0, 1}, // 08040000 nanoCLR + {BlockRange_BLOCKTYPE_DEPLOYMENT, 2, 6} // 080C0000 deployment +}; + +const BlockRegionInfo BlockRegions[] = { + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x8000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + (0), // no attributes for this region + 0x08020000, // start address for block region + 1, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + (0), // no attributes for this region + 0x08040000, // start address for block region + 7, // total number of blocks in this region + 0x40000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = { + (MediaAttribute_SupportsXIP), // STM32 flash memory is XIP + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo *)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo *)&Device_BlockInfo, // BlockDeviceinfo + }, + + { + // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00200000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/serialcfg.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/serialcfg.h new file mode 100644 index 0000000000..b356b1736a --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/serialcfg.h @@ -0,0 +1,15 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef SERIALCFG_H +#define SERIALCFG_H + +// define which serial driver the Wire Protocol will be using +#define SERIAL_DRIVER SD1 + +#endif /* SERIALCFG_H */ + +/** @} */ + diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/targetHAL_ConfigurationManager.cpp b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/targetHAL_ConfigurationManager.cpp new file mode 100644 index 0000000000..06dc9238e2 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/targetHAL_ConfigurationManager.cpp @@ -0,0 +1,38 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include + +// Default initialisation for Network interface config blocks +// strong implementation replacing ChibiOS 'weak' one +bool InitialiseNetworkDefaultConfig(HAL_Configuration_NetworkInterface *pconfig, uint32_t configurationIndex) +{ + (void)configurationIndex; + + // zero memory + memset(pconfig, 0, sizeof(HAL_Configuration_NetworkInterface)); + + // make sure the config block marker is set + memcpy(pconfig->Marker, c_MARKER_CONFIGURATION_NETWORK_V1, sizeof(c_MARKER_CONFIGURATION_NETWORK_V1)); + + pconfig->InterfaceType = NetworkInterfaceType_Ethernet; + pconfig->StartupAddressMode = AddressMode_DHCP; + pconfig->AutomaticDNS = 1; + pconfig->SpecificConfigId = UINT32_MAX; + + // set MAC address with ST provided MAC for development boards + // 00:80:E1:01:35:D1 + pconfig->MacAddress[0] = 0x00; + pconfig->MacAddress[1] = 0x80; + pconfig->MacAddress[2] = 0xE1; + pconfig->MacAddress[3] = 0x01; + pconfig->MacAddress[4] = 0x35; + pconfig->MacAddress[5] = 0xD1; + + return true; +} diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/ffconf.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/ffconf.h new file mode 100644 index 0000000000..5890370a95 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/ffconf.h @@ -0,0 +1,273 @@ +/* CHIBIOS FIX */ +#include "ch.h" + +/*---------------------------------------------------------------------------/ +/ FatFs Functional Configurations +/---------------------------------------------------------------------------*/ + +#define FFCONF_DEF 86631 /* Revision ID */ + +/*---------------------------------------------------------------------------/ +/ Function Configurations +/---------------------------------------------------------------------------*/ + +#define FF_FS_READONLY 0 +/* This option switches read-only configuration. (0:Read/Write or 1:Read-only) +/ Read-only configuration removes writing API functions, f_write(), f_sync(), +/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree() +/ and optional writing functions as well. */ + +#define FF_FS_MINIMIZE 0 +/* This option defines minimization level to remove some basic API functions. +/ +/ 0: Basic functions are fully enabled. +/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename() +/ are removed. +/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1. +/ 3: f_lseek() function is removed in addition to 2. */ + +#define FF_USE_FIND 1 +/* This option switches filtered directory read functions, f_findfirst() and +/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */ + +#define FF_USE_MKFS 0 +/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */ + +#define FF_USE_FASTSEEK 0 +/* This option switches fast seek function. (0:Disable or 1:Enable) */ + +#define FF_USE_EXPAND 0 +/* This option switches f_expand function. (0:Disable or 1:Enable) */ + +#define FF_USE_CHMOD 1 +/* This option switches attribute manipulation functions, f_chmod() and f_utime(). +/ (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */ + +#define FF_USE_LABEL 1 +/* This option switches volume label functions, f_getlabel() and f_setlabel(). +/ (0:Disable or 1:Enable) */ + +#define FF_USE_FORWARD 0 +/* This option switches f_forward() function. (0:Disable or 1:Enable) */ + +#define FF_USE_STRFUNC 1 +#define FF_PRINT_LLI 0 +#define FF_PRINT_FLOAT 0 +#define FF_STRF_ENCODE 3 +/* FF_USE_STRFUNC switches string functions, f_gets(), f_putc(), f_puts() and +/ f_printf(). +/ +/ 0: Disable. FF_PRINT_LLI, FF_PRINT_FLOAT and FF_STRF_ENCODE have no effect. +/ 1: Enable without LF-CRLF conversion. +/ 2: Enable with LF-CRLF conversion. +/ +/ FF_PRINT_LLI = 1 makes f_printf() support long long argument and FF_PRINT_FLOAT = 1/2 + makes f_printf() support floating point argument. These features want C99 or later. +/ When FF_LFN_UNICODE >= 1 with LFN enabled, string functions convert the character +/ encoding in it. FF_STRF_ENCODE selects assumption of character encoding ON THE FILE +/ to be read/written via those functions. +/ +/ 0: ANSI/OEM in current CP +/ 1: Unicode in UTF-16LE +/ 2: Unicode in UTF-16BE +/ 3: Unicode in UTF-8 +*/ + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/---------------------------------------------------------------------------*/ + +#define FF_CODE_PAGE 850 +/* This option specifies the OEM code page to be used on the target system. +/ Incorrect code page setting can cause a file open failure. +/ +/ 437 - U.S. +/ 720 - Arabic +/ 737 - Greek +/ 771 - KBL +/ 775 - Baltic +/ 850 - Latin 1 +/ 852 - Latin 2 +/ 855 - Cyrillic +/ 857 - Turkish +/ 860 - Portuguese +/ 861 - Icelandic +/ 862 - Hebrew +/ 863 - Canadian French +/ 864 - Arabic +/ 865 - Nordic +/ 866 - Russian +/ 869 - Greek 2 +/ 932 - Japanese (DBCS) +/ 936 - Simplified Chinese (DBCS) +/ 949 - Korean (DBCS) +/ 950 - Traditional Chinese (DBCS) +/ 0 - Include all code pages above and configured by f_setcp() +*/ + +#define FF_USE_LFN 3 +#define FF_MAX_LFN 255 +/* The FF_USE_LFN switches the support for LFN (long file name). +/ +/ 0: Disable LFN. FF_MAX_LFN has no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ To enable the LFN, ffunicode.c needs to be added to the project. The LFN function +/ requiers certain internal working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and +/ additional (FF_MAX_LFN + 44) / 15 * 32 bytes when exFAT is enabled. +/ The FF_MAX_LFN defines size of the working buffer in UTF-16 code unit and it can +/ be in range of 12 to 255. It is recommended to be set it 255 to fully support LFN +/ specification. +/ When use stack for the working buffer, take care on stack overflow. When use heap +/ memory for the working buffer, memory management functions, ff_memalloc() and +/ ff_memfree() exemplified in ffsystem.c, need to be added to the project. */ + +#define FF_LFN_UNICODE 0 +/* This option switches the character encoding on the API when LFN is enabled. +/ +/ 0: ANSI/OEM in current CP (TCHAR = char) +/ 1: Unicode in UTF-16 (TCHAR = WCHAR) +/ 2: Unicode in UTF-8 (TCHAR = char) +/ 3: Unicode in UTF-32 (TCHAR = DWORD) +/ +/ Also behavior of string I/O functions will be affected by this option. +/ When LFN is not enabled, this option has no effect. */ + +#define FF_LFN_BUF 255 +#define FF_SFN_BUF 12 +/* This set of options defines size of file name members in the FILINFO structure +/ which is used to read out directory items. These values should be suffcient for +/ the file names to read. The maximum possible length of the read file name depends +/ on character encoding. When LFN is not enabled, these options have no effect. */ + +#define FF_FS_RPATH 2 +/* This option configures support for relative path. +/ +/ 0: Disable relative path and remove related functions. +/ 1: Enable relative path. f_chdir() and f_chdrive() are available. +/ 2: f_getcwd() function is available in addition to 1. +*/ + +/*---------------------------------------------------------------------------/ +/ Drive/Volume Configurations +/---------------------------------------------------------------------------*/ + +#define FF_VOLUMES 3 +/* Number of volumes (logical drives) to be used. (1-10) */ + +#define FF_STR_VOLUME_ID 1 +#define FF_VOLUME_STRS "D", "E", "F" +/* FF_STR_VOLUME_ID switches support for volume ID in arbitrary strings. +/ When FF_STR_VOLUME_ID is set to 1 or 2, arbitrary strings can be used as drive +/ number in the path name. FF_VOLUME_STRS defines the volume ID strings for each +/ logical drives. Number of items must not be less than FF_VOLUMES. Valid +/ characters for the volume ID strings are A-Z, a-z and 0-9, however, they are +/ compared in case-insensitive. If FF_STR_VOLUME_ID >= 1 and FF_VOLUME_STRS is +/ not defined, a user defined volume string table needs to be defined as: +/ +/ const char* VolumeStr[FF_VOLUMES] = {"ram","flash","sd","usb",... +*/ + +#define FF_MULTI_PARTITION 0 +/* This option switches support for multiple volumes on the physical drive. +/ By default (0), each logical drive number is bound to the same physical drive +/ number and only an FAT volume found on the physical drive will be mounted. +/ When this function is enabled (1), each logical drive number can be bound to +/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk() +/ funciton will be available. */ + +#define FF_MIN_SS 512 +#define FF_MAX_SS 512 +/* This set of options configures the range of sector size to be supported. (512, +/ 1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and +/ harddisk, but a larger value may be required for on-board flash memory and some +/ type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured +/ for variable sector size mode and disk_ioctl() function needs to implement +/ GET_SECTOR_SIZE command. */ + +#define FF_LBA64 0 +/* This option switches support for 64-bit LBA. (0:Disable or 1:Enable) +/ To enable the 64-bit LBA, also exFAT needs to be enabled. (FF_FS_EXFAT == 1) */ + +#define FF_MIN_GPT 0x100000000 +/* Minimum number of sectors to switch GPT as partitioning format in f_mkfs and +/ f_fdisk function. 0x100000000 max. This option has no effect when FF_LBA64 == 0. */ + +#define FF_USE_TRIM 0 +/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable) +/ To enable Trim function, also CTRL_TRIM command should be implemented to the +/ disk_ioctl() function. */ + +/*---------------------------------------------------------------------------/ +/ System Configurations +/---------------------------------------------------------------------------*/ + +#define FF_FS_TINY 0 +/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny) +/ At the tiny configuration, size of file object (FIL) is shrinked FF_MAX_SS bytes. +/ Instead of private sector buffer eliminated from the file object, common sector +/ buffer in the filesystem object (FATFS) is used for the file data transfer. */ + +#define FF_FS_EXFAT 0 +/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable) +/ To enable exFAT, also LFN needs to be enabled. (FF_USE_LFN >= 1) +/ Note that enabling exFAT discards ANSI C (C89) compatibility. */ + +#define FF_FS_NORTC 1 +#define FF_NORTC_MON 1 +#define FF_NORTC_MDAY 1 +#define FF_NORTC_YEAR 2020 +/* The option FF_FS_NORTC switches timestamp functiton. If the system does not have +/ any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable +/ the timestamp function. Every object modified by FatFs will have a fixed timestamp +/ defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time. +/ To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be +/ added to the project to read current time form real-time clock. FF_NORTC_MON, +/ FF_NORTC_MDAY and FF_NORTC_YEAR have no effect. +/ These options have no effect in read-only configuration (FF_FS_READONLY = 1). */ + +#define FF_FS_NOFSINFO 0 +/* If you need to know correct free space on the FAT32 volume, set bit 0 of this +/ option, and f_getfree() function at first time after volume mount will force +/ a full FAT scan. Bit 1 controls the use of last allocated cluster number. +/ +/ bit0=0: Use free cluster count in the FSINFO if available. +/ bit0=1: Do not trust free cluster count in the FSINFO. +/ bit1=0: Use last allocated cluster number in the FSINFO if available. +/ bit1=1: Do not trust last allocated cluster number in the FSINFO. +*/ + +#define FF_FS_LOCK 0 +/* The option FF_FS_LOCK switches file lock function to control duplicated file open +/ and illegal operation to open objects. This option must be 0 when FF_FS_READONLY +/ is 1. +/ +/ 0: Disable file lock function. To avoid volume corruption, application program +/ should avoid illegal open, remove and rename to the open objects. +/ >0: Enable file lock function. The value defines how many files/sub-directories +/ can be opened simultaneously under file lock control. Note that the file +/ lock control is independent of re-entrancy. */ + +#define FF_FS_REENTRANT 1 +#define FF_FS_TIMEOUT TIME_MS2I(1000) +#define FF_SYNC_t semaphore_t * +/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs +/ module itself. Note that regardless of this option, file access to different +/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs() +/ and f_fdisk() function, are always not re-entrant. Only file/directory access +/ to the same volume is under control of this function. +/ +/ 0: Disable re-entrancy. FF_FS_TIMEOUT and FF_SYNC_t have no effect. +/ 1: Enable re-entrancy. Also user provided synchronization handlers, +/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj() +/ function, must be added to the project. Samples are available in +/ option/syscall.c. +/ +/ The FF_FS_TIMEOUT defines timeout period in unit of time tick. +/ The FF_SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*, +/ SemaphoreHandle_t and etc. A header file for O/S definitions needs to be +/ included somewhere in the scope of ff.h. */ + +/*--- End of configuration options ---*/ diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/launch.json b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/launch.json new file mode 100644 index 0000000000..1088b16113 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/launch.json @@ -0,0 +1,107 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "ST_STM32F769I_DISCOVERY nanoBooter", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", + "MIMode": "gdb", + "miDebuggerArgs": "", + "program": "${workspaceRoot}/build/nanoBooter.elf", + "setupCommands": [ + { + "text": "target extended-remote localhost:3333" + }, + { + "text": "monitor reset_config none separate" + }, + { + "text": "monitor reset halt" + }, + { + "text": "monitor flash write_image erase \"/build/nanoBooter.hex\" " + }, + { + "text": "file /build/nanoBooter.elf" + }, + { + "text": "set output-radix 16", + "description": "set the default numeric base to 16", + "ignoreFailures": true + } + ], + "logging": { + "moduleLoad": false, + "trace": false, + "engineLogging": false, + "programOutput": true, + "exceptions": true + }, + "launchCompleteCommand": "exec-continue", + "debugServerPath": "/bin/openocd.exe", + "debugServerArgs": "-s \"/scripts/\" -f board/stm32f769i-disco.cfg", + "serverStarted": "Listening on port .* for gdb connections", + "filterStderr": true, + "stopAtConnect": false, + "stopAtEntry": false, + "externalConsole": false, + "cwd": "${cwd}", + "hardwareBreakpoints": { + "require": true, + "limit": 6 + } + }, + { + "name": "ST_STM32F769I_DISCOVERY nanoCLR", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", + "MIMode": "gdb", + "miDebuggerArgs": "", + "program": "${workspaceRoot}/build/nanoCLR.elf", + "setupCommands": [ + { + "text": "target extended-remote localhost:3333" + }, + { + "text": "monitor reset_config none separate" + }, + { + "text": "monitor reset halt" + }, + { + "text": "monitor flash write_image erase \"/build/nanoCLR.hex\" " + }, + { + "text": "file /build/nanoCLR.elf" + }, + { + "text": "set output-radix 16", + "description": "set the default numeric base to 16", + "ignoreFailures": true + } + ], + "logging": { + "moduleLoad": false, + "trace": false, + "engineLogging": false, + "programOutput": true, + "exceptions": true + }, + "launchCompleteCommand": "exec-continue", + "debugServerPath": "/bin/openocd.exe", + "debugServerArgs": "-s \"/scripts/\" -f board/stm32f769i-disco.cfg", + "serverStarted": "Listening on port .* for gdb connections", + "filterStderr": true, + "stopAtConnect": false, + "stopAtEntry": false, + "externalConsole": false, + "cwd": "${cwd}", + "hardwareBreakpoints": { + "require": true, + "limit": 6 + } + } + ] +} diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/README.md b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/README.md new file mode 100644 index 0000000000..ac46ddc7fd --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/README.md @@ -0,0 +1,5 @@ +## Managed code helpers + +This folder contains helper classes to make developers life easier when coding for this target board. + +* [Adc](STM32F769I_DISCOVERY.Adc.cs) diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/STM32F769I_DISCOVERY.Adc.cs b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/STM32F769I_DISCOVERY.Adc.cs new file mode 100644 index 0000000000..b5cde5b8eb --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/STM32F769I_DISCOVERY.Adc.cs @@ -0,0 +1,53 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +namespace nanoFramework.Targets.STM32F767ZI_NUCLEO +{ + /// + /// Enumeration of ADC channels available in STM32F769I_DISCOVERY + /// + public static class AdcChannels + { + /// + /// Channel 0, exposed on A0, connected to PA6 (ADC1 - IN6) + /// + public const int Channel_0 = 0; + + /// + /// Channel 1, exposed on A1, connected to PA4 (ADC1 - IN4) + /// + public const int Channel_1 = 1; + + /// + /// Channel 2, exposed on A2, connected to PC2 (ADC1 - IN12) + /// + public const int Channel_2 = 2; + + /// + /// Channel 3, exposed on A3, connected to PF10 (ADC3 - IN8) + /// + public const int Channel_3 = 3; + + /// + /// Channel 4, exposed on A4, connected to PF8 (ADC3 - IN6) + /// + public const int Channel_4 = 4; + + /// + /// Channel 5, internal temperature sensor, connected to ADC1 + /// + public const int Channel_TemperatureSensor = 5; + + /// + /// Channel 6, internal voltage reference, connected to ADC1 + /// + public const int Channel_VrefIn = 6; + + /// + /// Channel 7, connected to VBatt pin, ADC1 + /// + public const int Channel_Vbatt = 7; + } +} diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/package.nuspec b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/package.nuspec new file mode 100644 index 0000000000..25e7cfd184 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/package.nuspec @@ -0,0 +1,26 @@ + + + + nanoFramework.Targets.ST_STM32F769I_DISCOVERY + nanoFramework.Targets.ST_STM32F769I_DISCOVERY + 1.0.0 + nanoframework + false + + Helper classes to use ST_STM32F769I_DISCOVERY target in C# applications. + + + + https://github.com/nanoframework + images\nf-logo.png + LICENSE.md + Copyright (c) .NET Foundation and Contributors + + nanoFramework, nano Framework, NETNF, NETMF, Micro Framework, STM32, .net, STM32F769I + + + + + + + diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/mbedtls_config.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/mbedtls_config.h new file mode 100644 index 0000000000..f70dd41e40 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/mbedtls_config.h @@ -0,0 +1,53 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) 2006-2015, ARM Limited, All Rights Reserved +// See LICENSE file in the project root for full license information. +// + +#ifndef MBEDTLS_CONFIG_H +#define MBEDTLS_CONFIG_H + +/* For test certificates */ +// #define MBEDTLS_CERTS_C +// #define MBEDTLS_PEM_PARSE_C + +// #define SSL_DEBUG_BUF MBEDTLS_SSL_DEBUG_BUF +// #define SSL_DEBUG_CRT MBEDTLS_SSL_DEBUG_CRT +// #define SSL_DEBUG_ECP MBEDTLS_SSL_DEBUG_ECP +// #define SSL_DEBUG_MPI MBEDTLS_SSL_DEBUG_MPI +// #define SSL_DEBUG_MSG MBEDTLS_SSL_DEBUG_MSG +// #define SSL_DEBUG_RET MBEDTLS_SSL_DEBUG_RET + +// #define MBEDTLS_SSL_ALL_ALERT_MESSAGES +// #define MBEDTLS_VERSION_FEATURES +// #define MBEDTLS_CERTS_C +// #define MBEDTLS_ERROR_C +// #define MBEDTLS_VERSION_C + +// uncomment the defines below to enable static memory allocation feature +#if 0 +#define MBEDTLS_MEMORY_BUFFER_ALLOC_C +#define MBEDTLS_PLATFORM_MEMORY +#endif + +#ifdef USE_LCD +#include "lcd_log.h" +#define MBEDTLS_PLATFORM_PRINTF_MACRO LCD_UsrLog +#endif + +// uncomment the defines bellow to generate debug output +// set below the threshold level for debug messages +// check Mbed TLS mbedtls/debug.h header for details. +// Debug levels: +// 0 No debug +// 1 Error +// 2 State change +// 3 Informational +// 4 Verbose + +// #define MBEDTLS_DEBUG_C +// #define MBEDTLS_SSL_DEBUG_ALL +// #define MBEDTLS_SSL_ALL_ALERT_MESSAGES +// #define MBEDTLS_DEBUG_THRESHOLD 2 + +#endif // MBEDTLS_CONFIG_H diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/CMakeLists.txt b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/CMakeLists.txt new file mode 100644 index 0000000000..73b5927c6b --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# # append nanoBooter source files +list(APPEND NANOBOOTER_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") + +# make var global +set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/STM32F76xx_booter-DEBUG.ld b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/STM32F76xx_booter-DEBUG.ld new file mode 100644 index 0000000000..5b9a6050cd --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/STM32F76xx_booter-DEBUG.ld @@ -0,0 +1,137 @@ +/* +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F76xx generic setup. + * + * RAM0 - Data, Heap. + * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH. + * + * Notes: + * BSS is placed in DTCM RAM in order to simplify DMA buffers management. + */ +MEMORY +{ + flash0 (rx) : org = 0x08000000, len = 32k /* space reserved for nanoBooter (1st sector 0x08000000 to 0x08008000)*/ + flash1 (rx) : org = 0x00200000, len = 32k + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + config (rw) : org = 0x08008000, len = 32k /* space reserved for configuration block */ + deployment (rx) : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt (wx) : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 (wx) : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */ + ram1 (wx) : org = 0x20020000, len = 368k /* SRAM1 */ + ram2 (wx) : org = 0x2007C000, len = 16k /* SRAM2 */ + ram3 (wx) : org = 0x20000030, len = 128k-48 /* DTCM-RAM */ + ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */ + ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 + bootclpbrd (wx) : org = 0x20000000, len = 48 /* boot clipboard area */ +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash1); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash1); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash1); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash1); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram3); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram3); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram3); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* rules inclusion.*/ +INCLUDE rules_stacks.ld + +/*===========================================================================*/ +/* Custom sections for STM32F7xx. */ +/*===========================================================================*/ + +/* RAM region to be used for nocache segment.*/ +REGION_ALIAS("NOCACHE_RAM", ram3); + +/* RAM region to be used for eth segment.*/ +REGION_ALIAS("ETH_RAM", ram3); + +SECTIONS +{ + /* Special section for non cache-able areas.*/ + .nocache (NOLOAD) : ALIGN(4) + { + __nocache_base__ = .; + *(.nocache) + *(.nocache.*) + *(.bss.__nocache_*) + . = ALIGN(4); + __nocache_end__ = .; + } > NOCACHE_RAM + + /* Special section for Ethernet DMA non cache-able areas.*/ + .eth (NOLOAD) : ALIGN(4) + { + __eth_base__ = .; + *(.eth) + *(.eth.*) + *(.bss.__eth_*) + . = ALIGN(4); + __eth_end__ = .; + } > ETH_RAM +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld + +/* Memory rules inclusion.*/ +INCLUDE rules_memory.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/STM32F76xx_booter.ld b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/STM32F76xx_booter.ld new file mode 100644 index 0000000000..5b9a6050cd --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/STM32F76xx_booter.ld @@ -0,0 +1,137 @@ +/* +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F76xx generic setup. + * + * RAM0 - Data, Heap. + * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH. + * + * Notes: + * BSS is placed in DTCM RAM in order to simplify DMA buffers management. + */ +MEMORY +{ + flash0 (rx) : org = 0x08000000, len = 32k /* space reserved for nanoBooter (1st sector 0x08000000 to 0x08008000)*/ + flash1 (rx) : org = 0x00200000, len = 32k + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + config (rw) : org = 0x08008000, len = 32k /* space reserved for configuration block */ + deployment (rx) : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt (wx) : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 (wx) : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */ + ram1 (wx) : org = 0x20020000, len = 368k /* SRAM1 */ + ram2 (wx) : org = 0x2007C000, len = 16k /* SRAM2 */ + ram3 (wx) : org = 0x20000030, len = 128k-48 /* DTCM-RAM */ + ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */ + ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 + bootclpbrd (wx) : org = 0x20000000, len = 48 /* boot clipboard area */ +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash1); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash1); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash1); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash1); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram3); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram3); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram3); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* rules inclusion.*/ +INCLUDE rules_stacks.ld + +/*===========================================================================*/ +/* Custom sections for STM32F7xx. */ +/*===========================================================================*/ + +/* RAM region to be used for nocache segment.*/ +REGION_ALIAS("NOCACHE_RAM", ram3); + +/* RAM region to be used for eth segment.*/ +REGION_ALIAS("ETH_RAM", ram3); + +SECTIONS +{ + /* Special section for non cache-able areas.*/ + .nocache (NOLOAD) : ALIGN(4) + { + __nocache_base__ = .; + *(.nocache) + *(.nocache.*) + *(.bss.__nocache_*) + . = ALIGN(4); + __nocache_end__ = .; + } > NOCACHE_RAM + + /* Special section for Ethernet DMA non cache-able areas.*/ + .eth (NOLOAD) : ALIGN(4) + { + __eth_base__ = .; + *(.eth) + *(.eth.*) + *(.bss.__eth_*) + . = ALIGN(4); + __eth_end__ = .; + } > ETH_RAM +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld + +/* Memory rules inclusion.*/ +INCLUDE rules_memory.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/chconf.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/chconf.h new file mode 100644 index 0000000000..d24abc78a9 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/chconf.h @@ -0,0 +1,819 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM FALSE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time time stamps APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES FALSE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS FALSE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT FALSE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES FALSE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES FALSE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES FALSE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY FALSE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() \ + { \ + /* Add system initialization code here.*/ \ + } + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) \ + { \ + /* Add OS instance initialization code here.*/ \ + } + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) \ + { \ + /* Add threads initialization code here.*/ \ + } + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) \ + { \ + /* Add threads finalization code here.*/ \ + } + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) \ + { \ + /* Context switch code here.*/ \ + } + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() \ + { \ + /* IRQ prologue code here.*/ \ + } + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() \ + { \ + /* IRQ epilogue code here.*/ \ + } + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() \ + { \ + /* Idle-enter code here.*/ \ + } + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() \ + { \ + /* Idle-leave code here.*/ \ + } + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() \ + { \ + /* Idle loop code here.*/ \ + } + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() \ + { \ + /* System tick event code here.*/ \ + } + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) \ + { \ + /* System halt code here.*/ \ + } + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) \ + { \ + /* Trace code here.*/ \ + } + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) \ + { \ + /* Faults handling code here.*/ \ + } + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/halconf.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/halconf.h new file mode 100644 index 0000000000..22b723bec1 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/halconf.h @@ -0,0 +1,547 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +// clang-format off + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 64 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_NONE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" +#endif /* HALCONF_H */ + +/** @} */ + +// clang-format on diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/halconf_nf.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/halconf_nf.h new file mode 100644 index 0000000000..d320122ed1 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/halconf_nf.h @@ -0,0 +1,23 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef HALCONF_NF_H +#define HALCONF_NF_H + +// enables STM32 Flash driver +#if !defined(HAL_NF_USE_STM32_FLASH) +#define HAL_NF_USE_STM32_FLASH TRUE +#endif + +// // Enable graphics low level hardware on STM32F769 + +// #if !defined(HAL_DSI_MODULE_ENABLED) +// #define HAL_DSI_MODULE_ENABLED TRUE +// #endif + +// enable USB MSD (from ChibiOS Contrib) +#define HAL_USBH_USE_MSD FALSE + +#endif // HALCONF_NF_H diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/main.c b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/main.c new file mode 100644 index 0000000000..c147f7feeb --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/main.c @@ -0,0 +1,103 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); + +// Application entry point. +int main(void) +{ + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init boot clipboard + InitBootClipboard(); + +// init SWO as soon as possible to make it available to output ASAP +#if (SWO_OUTPUT == TRUE) + SwoInit(); +#endif + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + osDelay(20); // Let init stabilize + + // the following IF is not mandatory, it's just providing a way for a user to 'force' + // the board to remain in nanoBooter and not launching nanoCLR + + // check if there is a request to remain on nanoBooter + if (!IsToRemainInBooter()) + { + // if the USER button (blue one) is pressed, skip the check for a valid CLR image and remain in booter + // the user button in this board has a pull-up resistor so the check has to be inverted + if (!palReadLine(LINE_BUTTON_USER)) + { + // check for valid CLR image + // we are checking for a valid image right after the configuration block + if (CheckValidCLRImage((uint32_t)&__nanoConfig_end__)) + { + // there seems to be a valid CLR image + // launch nanoCLR + LaunchCLR((uint32_t)&__nanoConfig_end__); + } + } + } + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + +#if (HAL_NF_USE_STM32_CRC == TRUE) + // startup crc + crcStart(NULL); +#endif + + // starts the serial driver + sdStart(&SERIAL_DRIVER, NULL); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); + + // initialize configuration manager + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it here to have access to network configuration blocks + ConfigurationManager_Initialize(); + + // report successfull nanoBooter execution + ReportSuccessfullNanoBooter(); + + // Normal main() thread + while (true) + { + palSetLine(LINE_LED2_GREEN); + osDelay(500); + palClearLine(LINE_LED2_GREEN); + osDelay(500); + } +} diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/mcuconf.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/mcuconf.h new file mode 100644 index 0000000000..aad75fe0bc --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/mcuconf.h @@ -0,0 +1,437 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +// clang-format off + +/* + * STM32F7xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F7xx_MCUCONF +#define STM32F767_MCUCONF + +/* + * General settings. + */ +#define STM32_NO_INIT FALSE + +/* + * Memory attributes settings. + */ +#define STM32_NOCACHE_ENABLE FALSE +#define STM32_NOCACHE_MPU_REGION MPU_REGION_6 +#define STM32_NOCACHE_RBAR 0x2004C000U +#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K + +/* + * HAL driver system settings. + */ +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 432 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 25 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_TIMPRE_ENABLE FALSE +#define STM32_I2SSRC STM32_I2SSRC_OFF +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SP_VALUE 4 +#define STM32_PLLI2SQ_VALUE 4 +#define STM32_PLLI2SR_VALUE 4 +#define STM32_PLLI2SDIVQ_VALUE 2 +#define STM32_PLLSAIN_VALUE 192 +#define STM32_PLLSAIP_VALUE 4 +#define STM32_PLLSAIQ_VALUE 4 +#define STM32_PLLSAIR_VALUE 4 +#define STM32_PLLSAIDIVQ_VALUE 2 +#define STM32_PLLSAIDIVR_VALUE 2 +#define STM32_SAI1SEL STM32_SAI1SEL_OFF +#define STM32_SAI2SEL STM32_SAI2SEL_OFF +#define STM32_LCDTFT_REQUIRED FALSE +#define STM32_USART1SEL STM32_USART1SEL_PCLK2 +#define STM32_USART2SEL STM32_USART2SEL_PCLK1 +#define STM32_USART3SEL STM32_USART3SEL_PCLK1 +#define STM32_UART4SEL STM32_UART4SEL_PCLK1 +#define STM32_UART5SEL STM32_UART5SEL_PCLK1 +#define STM32_USART6SEL STM32_USART6SEL_PCLK2 +#define STM32_UART7SEL STM32_UART7SEL_PCLK1 +#define STM32_UART8SEL STM32_UART8SEL_PCLK1 +#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1 +#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1 +#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1 +#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1 +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 +#define STM32_CECSEL STM32_CECSEL_LSE +#define STM32_CK48MSEL STM32_CK48MSEL_PLL +#define STM32_SDMMC1SEL STM32_SDMMC1SEL_PLL48CLK +#define STM32_SDMMC2SEL STM32_SDMMC2SEL_PLL48CLK + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 6 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 6 +#define STM32_IRQ_EXTI22_PRIORITY 6 +#define STM32_IRQ_EXTI23_PRIORITY 6 + +#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7 +#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7 +#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7 +#define STM32_IRQ_TIM1_CC_PRIORITY 7 +#define STM32_IRQ_TIM2_PRIORITY 7 +#define STM32_IRQ_TIM3_PRIORITY 7 +#define STM32_IRQ_TIM4_PRIORITY 7 +#define STM32_IRQ_TIM5_PRIORITY 7 +#define STM32_IRQ_TIM6_PRIORITY 7 +#define STM32_IRQ_TIM7_PRIORITY 7 +#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7 +#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7 +#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7 +#define STM32_IRQ_TIM8_CC_PRIORITY 7 + +#define STM32_IRQ_USART1_PRIORITY 12 +#define STM32_IRQ_USART2_PRIORITY 12 +#define STM32_IRQ_USART3_PRIORITY 12 +#define STM32_IRQ_UART4_PRIORITY 12 +#define STM32_IRQ_UART5_PRIORITY 12 +#define STM32_IRQ_USART6_PRIORITY 12 +#define STM32_IRQ_UART7_PRIORITY 12 +#define STM32_IRQ_UART8_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_USE_CAN3 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 +#define STM32_CAN_CAN3_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM10 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM13 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_USE_TIM15 FALSE +#define STM32_GPT_USE_TIM16 FALSE +#define STM32_GPT_USE_TIM17 FALSE + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_USE_I2C4 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C4_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C4_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_USE_TIM10 FALSE +#define STM32_ICU_USE_TIM11 FALSE +#define STM32_ICU_USE_TIM12 FALSE +#define STM32_ICU_USE_TIM13 FALSE +#define STM32_ICU_USE_TIM14 FALSE +#define STM32_ICU_USE_TIM15 FALSE +#define STM32_ICU_USE_TIM16 FALSE +#define STM32_ICU_USE_TIM17 FALSE + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_USE_TIM10 FALSE +#define STM32_PWM_USE_TIM11 FALSE +#define STM32_PWM_USE_TIM12 FALSE +#define STM32_PWM_USE_TIM13 FALSE +#define STM32_PWM_USE_TIM14 FALSE +#define STM32_PWM_USE_TIM15 FALSE +#define STM32_PWM_USE_TIM16 FALSE +#define STM32_PWM_USE_TIM17 FALSE + +/* + * RTC driver system settings. + */ +#define STM32_RTC_PRESA_VALUE 32 +#define STM32_RTC_PRESS_VALUE 1024 +#define STM32_RTC_CR_INIT 0 +#define STM32_RTC_TAMPCR_INIT 0 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_USE_SDMMC1 FALSE +#define STM32_SDC_USE_SDMMC2 FALSE +#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDMMC_WRITE_TIMEOUT 10000 +#define STM32_SDC_SDMMC_READ_TIMEOUT 10000 +#define STM32_SDC_SDMMC_CLOCK_DELAY 10 +#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SDC_SDMMC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC2_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 +#define STM32_SDC_SDMMC2_IRQ_PRIORITY 9 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 TRUE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_UART7 FALSE +#define STM32_SERIAL_USE_UART8 FALSE + +/* + * SIO driver system settings. + */ +#define STM32_SIO_USE_USART1 FALSE +#define STM32_SIO_USE_USART2 FALSE +#define STM32_SIO_USE_USART3 FALSE +#define STM32_SIO_USE_UART4 FALSE +#define STM32_SIO_USE_UART5 FALSE +#define STM32_SIO_USE_USART6 FALSE +#define STM32_SIO_USE_UART7 FALSE +#define STM32_SIO_USE_UART8 FALSE + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI4 FALSE +#define STM32_SPI_USE_SPI5 FALSE +#define STM32_SPI_USE_SPI6 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI5_DMA_PRIORITY 1 +#define STM32_SPI_SPI6_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_SPI5_IRQ_PRIORITY 10 +#define STM32_SPI_SPI6_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * TRNG driver system settings. + */ +#define STM32_TRNG_USE_RNG1 FALSE + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USE_UART7 FALSE +#define STM32_UART_USE_UART8 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_UART7_DMA_PRIORITY 0 +#define STM32_UART_UART8_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +/* + * WSPI driver system settings. + */ +#define STM32_WSPI_USE_QUADSPI1 FALSE +#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1 + +// clang-format on + +#endif /* MCUCONF_H */ diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/mcuconf_nf.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/mcuconf_nf.h new file mode 100644 index 0000000000..35e74e10aa --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/mcuconf_nf.h @@ -0,0 +1,9 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_NF_H +#define MCUCONF_NF_H + +#endif // MCUCONF_NF_H diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/target_board.h.in b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/target_board.h.in new file mode 100644 index 0000000000..ac85c850b9 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef TARGET_BOARD_NANOBOOTER_H +#define TARGET_BOARD_NANOBOOTER_H + +#include + +#define OEMSYSTEMINFOSTRING "nanoBooter running @ @TARGET_NAME@" + +#endif // TARGET_BOARD_NANOBOOTER_H diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/CMakeLists.txt b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/CMakeLists.txt new file mode 100644 index 0000000000..f5fab75926 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp") + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/STM32F76xx_CLR-DEBUG.ld b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/STM32F76xx_CLR-DEBUG.ld new file mode 100644 index 0000000000..81a1ad82e7 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/STM32F76xx_CLR-DEBUG.ld @@ -0,0 +1,156 @@ +/* +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F76xxI generic setup. + * + * RAM0 - Data, Heap. + * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH. + * + * Notes: + * BSS is placed in DTCM RAM in order to simplify DMA buffers management. + * When updating the flash0 address below make sure to update the address in nf_generate_bin_package + */ +MEMORY +{ + flash0 (rx) : org = 0x08010000, len = 2M - 32k - 32k - 1024k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + flash1 (rx) : org = 0x00210000, len = 2M - 32k - 32k - 1024k + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + config (rw) : org = 0x08008000, len = 32k /* space reserved for configuration block */ + deployment (rx) : org = 0x08100000, len = 1024k /* space reserved for application deployment */ + ramvt (wx) : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 (wx) : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */ + ram1 (wx) : org = 0x20020000, len = 368k /* SRAM1 */ + ram2 (wx) : org = 0x2007C000, len = 16k /* SRAM2 */ + ram3 (wx) : org = 0x20000030, len = 128k-48 /* DTCM-RAM */ + ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */ + ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 + ext_ram (wx) : org = 0xC0000000, len = 13631488 /* external SDRAM */ + graphics_ram (wx) : org = 0xC0D00000, len = 2377728 /* external graphics ram for frame buffer and bitmaps*/ + graphics_vfb (wx) : org = 0xC0F44800, len = 768000 /* Frame buffer for video output mode 800*480*2 bytes ( 16 bits RGB565 )*/ + bootclpbrd (wx) : org = 0x20000000, len = 48 /* boot clipboard area */ +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash1); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash1); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash1); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash1); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram3); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram3); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram3); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ext_ram); + +/* RAM region to be used for the nanoFramework graphics heap.*/ +REGION_ALIAS("GRAPHICS_HEAP_RAM", graphics_ram); + +/* RAM region to be used for the nanoFramework graphics heap.*/ +REGION_ALIAS("GRAPHICS_VIDEO_FRAME_BUFFER", graphics_vfb); + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* rules inclusion.*/ +INCLUDE rules_stacks.ld + +/*===========================================================================*/ +/* Custom sections for STM32F7xx. */ +/*===========================================================================*/ + +/* RAM region to be used for nocache segment.*/ +REGION_ALIAS("NOCACHE_RAM", ram3); + +/* RAM region to be used for eth segment.*/ +REGION_ALIAS("ETH_RAM", ram3); + +SECTIONS +{ + /* Special section for non cache-able areas.*/ + .nocache (NOLOAD) : ALIGN(4) + { + __nocache_base__ = .; + *(.nocache) + *(.nocache.*) + *(.bss.__nocache_*) + . = ALIGN(4); + __nocache_end__ = .; + } > NOCACHE_RAM + + /* Special section for Ethernet DMA non cache-able areas.*/ + .eth (NOLOAD) : ALIGN(4) + { + __eth_base__ = .; + *(.eth) + *(.eth.*) + *(.bss.__eth_*) + . = ALIGN(4); + __eth_end__ = .; + } > ETH_RAM +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld + +/* Memory rules inclusion.*/ +INCLUDE rules_memory.ld + +/* nanoCLR rules inclusion.*/ +INCLUDE rules_clr.ld + +/* Graphics rules inclusion.*/ +INCLUDE rules_graphics.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/STM32F76xx_CLR.ld b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/STM32F76xx_CLR.ld new file mode 100644 index 0000000000..b067340e01 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/STM32F76xx_CLR.ld @@ -0,0 +1,156 @@ +/* +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F76xxI generic setup. + * + * RAM0 - Data, Heap. + * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH. + * + * Notes: + * BSS is placed in DTCM RAM in order to simplify DMA buffers management. + * When updating the flash0 address below make sure to update the address in nf_generate_bin_package + */ +MEMORY +{ + flash0 (rx) : org = 0x08010000, len = 2M - 32k - 32k - 1280k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + flash1 (rx) : org = 0x00210000, len = 2M - 32k - 32k - 1280k + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + config (rw) : org = 0x08008000, len = 32k /* space reserved for configuration block */ + deployment (rx) : org = 0x080C0000, len = 1280k /* space reserved for application deployment */ + ramvt (wx) : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 (wx) : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */ + ram1 (wx) : org = 0x20020000, len = 368k /* SRAM1 */ + ram2 (wx) : org = 0x2007C000, len = 16k /* SRAM2 */ + ram3 (wx) : org = 0x20000030, len = 128k-48 /* DTCM-RAM */ + ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */ + ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 + ext_ram (wx) : org = 0xC0000000, len = 13631488 /* external SDRAM */ + graphics_ram (wx) : org = 0xC0D00000, len = 2377728 /* external graphics ram for frame buffer and bitmaps*/ + graphics_vfb (wx) : org = 0xC0F44800, len = 768000 /* Frame buffer for video output mode 800*480*2 bytes ( 16 bits RGB565 )*/ + bootclpbrd (wx) : org = 0x20000000, len = 48 /* boot clipboard area */ +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash1); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash1); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash1); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash1); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram3); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram3); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram3); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ext_ram); + +/* RAM region to be used for the nanoFramework graphics heap.*/ +REGION_ALIAS("GRAPHICS_HEAP_RAM", graphics_ram); + +/* RAM region to be used for the nanoFramework graphics heap.*/ +REGION_ALIAS("GRAPHICS_VIDEO_FRAME_BUFFER", graphics_vfb); + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* rules inclusion.*/ +INCLUDE rules_stacks.ld + +/*===========================================================================*/ +/* Custom sections for STM32F7xx. */ +/*===========================================================================*/ + +/* RAM region to be used for nocache segment.*/ +REGION_ALIAS("NOCACHE_RAM", ram3); + +/* RAM region to be used for eth segment.*/ +REGION_ALIAS("ETH_RAM", ram3); + +SECTIONS +{ + /* Special section for non cache-able areas.*/ + .nocache (NOLOAD) : ALIGN(4) + { + __nocache_base__ = .; + *(.nocache) + *(.nocache.*) + *(.bss.__nocache_*) + . = ALIGN(4); + __nocache_end__ = .; + } > NOCACHE_RAM + + /* Special section for Ethernet DMA non cache-able areas.*/ + .eth (NOLOAD) : ALIGN(4) + { + __eth_base__ = .; + *(.eth) + *(.eth.*) + *(.bss.__eth_*) + . = ALIGN(4); + __eth_end__ = .; + } > ETH_RAM +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld + +/* Memory rules inclusion.*/ +INCLUDE rules_memory.ld + +/* nanoCLR rules inclusion.*/ +INCLUDE rules_clr.ld + +/* Graphics rules inclusion.*/ +INCLUDE rules_graphics.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/chconf.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/chconf.h new file mode 100644 index 0000000000..2cbe763aa7 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/chconf.h @@ -0,0 +1,819 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM FALSE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time time stamps APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES FALSE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES FALSE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY FALSE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() \ + { \ + /* Add system initialization code here.*/ \ + } + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) \ + { \ + /* Add OS instance initialization code here.*/ \ + } + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) \ + { \ + /* Add threads initialization code here.*/ \ + } + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) \ + { \ + /* Add threads finalization code here.*/ \ + } + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) \ + { \ + /* Context switch code here.*/ \ + } + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() \ + { \ + /* IRQ prologue code here.*/ \ + } + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() \ + { \ + /* IRQ epilogue code here.*/ \ + } + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() \ + { \ + /* Idle-enter code here.*/ \ + } + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() \ + { \ + /* Idle-leave code here.*/ \ + } + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() \ + { \ + /* Idle loop code here.*/ \ + } + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() \ + { \ + /* System tick event code here.*/ \ + } + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) \ + { \ + /* System halt code here.*/ \ + } + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) \ + { \ + /* Trace code here.*/ \ + } + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) \ + { \ + /* Faults handling code here.*/ \ + } + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/halconf.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/halconf.h new file mode 100644 index 0000000000..5df08fc9ba --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/halconf.h @@ -0,0 +1,568 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +// clang-format off + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +//Not in default template, added manually +#if !defined(FATFS_HAL_DEVICE) || defined(__DOXYGEN__) +//this board requires SDCD2 not SDCD1 +#define FATFS_HAL_DEVICE SDCD2 +#endif +//////// + +//#define STM32_SDC_SDMMC_50MHZ TRUE + +/** + * @brief Enables the ADC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +// #define HAL_USE_ADC FALSE +// #endif + +/** + * @brief Enables the CAN subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +// #define HAL_USE_CAN FALSE +// #endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +// #define HAL_USE_DAC FALSE +// #endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +// #define HAL_USE_I2C FALSE +// #endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +// #define HAL_USE_MAC FALSE +// #endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +// #define HAL_USE_PWM FALSE +// #endif + +/** + * @brief Enables the RTC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +// #define HAL_USE_RTC FALSE +// #endif + +/** + * @brief Enables the SDC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +// #define HAL_USE_SDC FALSE +// #endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +// #define HAL_USE_SPI FALSE +// #endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +// #define HAL_USE_UART FALSE +// #endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +// #define HAL_USE_WDG FALSE +// #endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS TRUE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 64 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_NONE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" +#endif /* HALCONF_H */ + +/** @} */ + +// clang-format on diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/halconf_nf.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/halconf_nf.h new file mode 100644 index 0000000000..59eeb3c570 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/halconf_nf.h @@ -0,0 +1,35 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef HALCONF_NF_H +#define HALCONF_NF_H + +// enables STM32 Flash driver +#if !defined(HAL_NF_USE_STM32_FLASH) +#define HAL_NF_USE_STM32_FLASH TRUE +#endif + +// Enables the FSMC subsystem. +#if !defined(HAL_NF_USE_FSMC) +#define HAL_NF_USE_FSMC TRUE +#endif + +// enables STM32 QSPI driver +#if !defined(HAL_NF_USE_STM32_QSPI) +#define HAL_NF_USE_STM32_QSPI FALSE +#endif + +// enable STM32 graphics +#if !defined(HAL_DSI_MODULE_ENABLED) +#define HAL_DSI_MODULE_ENABLED TRUE +#endif + +#if !defined(HAL_LTDC_MODULE_ENABLED) +#define HAL_LTDC_MODULE_ENABLED TRUE +#endif + + + +#endif // HALCONF_NF_H diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/main.c b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/main.c new file mode 100644 index 0000000000..f4b3d4ea75 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/main.c @@ -0,0 +1,107 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern uint8_t hal_spiffs_config(); + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); +// declare CLRStartup thread here +osThreadDef(CLRStartupThread, osPriorityNormal, 4096, "CLRStartupThread"); + +#if HAL_USE_SDC +// declare SD Card working thread here +osThreadDef(SdCardWorkingThread, osPriorityNormal, 1024, "SDCWT"); +#endif +#if HAL_USBH_USE_MSD +// declare USB MSD thread here +osThreadDef(UsbMsdWorkingThread, osPriorityNormal, 1024, "USBMSDWT"); +#endif + +// Application entry point. +int main(void) +{ + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init boot clipboard + InitBootClipboard(); + +// init SWO as soon as possible to make it available to output ASAP +#if (SWO_OUTPUT == TRUE) + SwoInit(); +#endif + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + + // start watchdog + Watchdog_Init(); + +#if (HAL_NF_USE_STM32_CRC == TRUE) + // startup crc + crcStart(NULL); +#endif + + // config and init external memory + // this has to be called after osKernelInitialize, otherwise an hard fault will occur + Target_ExternalMemoryInit(); + +#if (NF_FEATURE_USE_SPIFFS == TRUE) + // config and init SPIFFS + hal_spiffs_config(); +#endif + + // starts the serial driver + sdStart(&SERIAL_DRIVER, NULL); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // CLR settings to launch CLR thread + CLR_SETTINGS clrSettings; + (void)memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.EnterDebuggerLoopAfterExit = true; + + // create the CLR Startup thread + osThreadCreate(osThread(CLRStartupThread), &clrSettings); + +#if HAL_USE_SDC + // creates the SD card working thread + osThreadCreate(osThread(SdCardWorkingThread), NULL); +#endif + +#if HAL_USBH_USE_MSD + // create the USB MSD working thread + osThreadCreate(osThread(UsbMsdWorkingThread), &MSBLKD[0]); +#endif + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + while (true) + { + osDelay(100); + } +} \ No newline at end of file diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h new file mode 100644 index 0000000000..aad75fe0bc --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h @@ -0,0 +1,437 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +// clang-format off + +/* + * STM32F7xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F7xx_MCUCONF +#define STM32F767_MCUCONF + +/* + * General settings. + */ +#define STM32_NO_INIT FALSE + +/* + * Memory attributes settings. + */ +#define STM32_NOCACHE_ENABLE FALSE +#define STM32_NOCACHE_MPU_REGION MPU_REGION_6 +#define STM32_NOCACHE_RBAR 0x2004C000U +#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K + +/* + * HAL driver system settings. + */ +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 432 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 25 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_TIMPRE_ENABLE FALSE +#define STM32_I2SSRC STM32_I2SSRC_OFF +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SP_VALUE 4 +#define STM32_PLLI2SQ_VALUE 4 +#define STM32_PLLI2SR_VALUE 4 +#define STM32_PLLI2SDIVQ_VALUE 2 +#define STM32_PLLSAIN_VALUE 192 +#define STM32_PLLSAIP_VALUE 4 +#define STM32_PLLSAIQ_VALUE 4 +#define STM32_PLLSAIR_VALUE 4 +#define STM32_PLLSAIDIVQ_VALUE 2 +#define STM32_PLLSAIDIVR_VALUE 2 +#define STM32_SAI1SEL STM32_SAI1SEL_OFF +#define STM32_SAI2SEL STM32_SAI2SEL_OFF +#define STM32_LCDTFT_REQUIRED FALSE +#define STM32_USART1SEL STM32_USART1SEL_PCLK2 +#define STM32_USART2SEL STM32_USART2SEL_PCLK1 +#define STM32_USART3SEL STM32_USART3SEL_PCLK1 +#define STM32_UART4SEL STM32_UART4SEL_PCLK1 +#define STM32_UART5SEL STM32_UART5SEL_PCLK1 +#define STM32_USART6SEL STM32_USART6SEL_PCLK2 +#define STM32_UART7SEL STM32_UART7SEL_PCLK1 +#define STM32_UART8SEL STM32_UART8SEL_PCLK1 +#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1 +#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1 +#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1 +#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1 +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 +#define STM32_CECSEL STM32_CECSEL_LSE +#define STM32_CK48MSEL STM32_CK48MSEL_PLL +#define STM32_SDMMC1SEL STM32_SDMMC1SEL_PLL48CLK +#define STM32_SDMMC2SEL STM32_SDMMC2SEL_PLL48CLK + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 6 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 6 +#define STM32_IRQ_EXTI22_PRIORITY 6 +#define STM32_IRQ_EXTI23_PRIORITY 6 + +#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7 +#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7 +#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7 +#define STM32_IRQ_TIM1_CC_PRIORITY 7 +#define STM32_IRQ_TIM2_PRIORITY 7 +#define STM32_IRQ_TIM3_PRIORITY 7 +#define STM32_IRQ_TIM4_PRIORITY 7 +#define STM32_IRQ_TIM5_PRIORITY 7 +#define STM32_IRQ_TIM6_PRIORITY 7 +#define STM32_IRQ_TIM7_PRIORITY 7 +#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7 +#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7 +#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7 +#define STM32_IRQ_TIM8_CC_PRIORITY 7 + +#define STM32_IRQ_USART1_PRIORITY 12 +#define STM32_IRQ_USART2_PRIORITY 12 +#define STM32_IRQ_USART3_PRIORITY 12 +#define STM32_IRQ_UART4_PRIORITY 12 +#define STM32_IRQ_UART5_PRIORITY 12 +#define STM32_IRQ_USART6_PRIORITY 12 +#define STM32_IRQ_UART7_PRIORITY 12 +#define STM32_IRQ_UART8_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_USE_CAN3 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 +#define STM32_CAN_CAN3_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM10 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM13 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_USE_TIM15 FALSE +#define STM32_GPT_USE_TIM16 FALSE +#define STM32_GPT_USE_TIM17 FALSE + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_USE_I2C4 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C4_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C4_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_USE_TIM10 FALSE +#define STM32_ICU_USE_TIM11 FALSE +#define STM32_ICU_USE_TIM12 FALSE +#define STM32_ICU_USE_TIM13 FALSE +#define STM32_ICU_USE_TIM14 FALSE +#define STM32_ICU_USE_TIM15 FALSE +#define STM32_ICU_USE_TIM16 FALSE +#define STM32_ICU_USE_TIM17 FALSE + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_USE_TIM10 FALSE +#define STM32_PWM_USE_TIM11 FALSE +#define STM32_PWM_USE_TIM12 FALSE +#define STM32_PWM_USE_TIM13 FALSE +#define STM32_PWM_USE_TIM14 FALSE +#define STM32_PWM_USE_TIM15 FALSE +#define STM32_PWM_USE_TIM16 FALSE +#define STM32_PWM_USE_TIM17 FALSE + +/* + * RTC driver system settings. + */ +#define STM32_RTC_PRESA_VALUE 32 +#define STM32_RTC_PRESS_VALUE 1024 +#define STM32_RTC_CR_INIT 0 +#define STM32_RTC_TAMPCR_INIT 0 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_USE_SDMMC1 FALSE +#define STM32_SDC_USE_SDMMC2 FALSE +#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDMMC_WRITE_TIMEOUT 10000 +#define STM32_SDC_SDMMC_READ_TIMEOUT 10000 +#define STM32_SDC_SDMMC_CLOCK_DELAY 10 +#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SDC_SDMMC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC2_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 +#define STM32_SDC_SDMMC2_IRQ_PRIORITY 9 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 TRUE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_UART7 FALSE +#define STM32_SERIAL_USE_UART8 FALSE + +/* + * SIO driver system settings. + */ +#define STM32_SIO_USE_USART1 FALSE +#define STM32_SIO_USE_USART2 FALSE +#define STM32_SIO_USE_USART3 FALSE +#define STM32_SIO_USE_UART4 FALSE +#define STM32_SIO_USE_UART5 FALSE +#define STM32_SIO_USE_USART6 FALSE +#define STM32_SIO_USE_UART7 FALSE +#define STM32_SIO_USE_UART8 FALSE + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI4 FALSE +#define STM32_SPI_USE_SPI5 FALSE +#define STM32_SPI_USE_SPI6 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI5_DMA_PRIORITY 1 +#define STM32_SPI_SPI6_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_SPI5_IRQ_PRIORITY 10 +#define STM32_SPI_SPI6_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * TRNG driver system settings. + */ +#define STM32_TRNG_USE_RNG1 FALSE + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USE_UART7 FALSE +#define STM32_UART_USE_UART8 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_UART7_DMA_PRIORITY 0 +#define STM32_UART_UART8_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +/* + * WSPI driver system settings. + */ +#define STM32_WSPI_USE_QUADSPI1 FALSE +#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1 + +// clang-format on + +#endif /* MCUCONF_H */ diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf_nf.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf_nf.h new file mode 100644 index 0000000000..bae0152d36 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf_nf.h @@ -0,0 +1,22 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_NF_H +#define MCUCONF_NF_H +/* + * FSMC driver system settings. + */ +#define STM32_FSMC_USE_FSMC1 TRUE +#define STM32_FSMC_FSMC1_IRQ_PRIORITY 10 +#define STM32_FSMC_DMA_CHN 0x03010201 + +/* + * FSMC SDRAM driver system settings. + */ +#define STM32_USE_FSMC_SDRAM TRUE +#define STM32_SDRAM_USE_FSMC_SDRAM1 TRUE +#define STM32_SDRAM_USE_FSMC_SDRAM2 FALSE + +#endif // MCUCONF_NF_H diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/nanoHAL.cpp b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/nanoHAL.cpp new file mode 100644 index 0000000000..e754dd5f80 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/nanoHAL.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/target_board.h.in b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/target_board.h.in new file mode 100644 index 0000000000..53a87fce3d --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef TARGET_BOARD_NANOCLR_H +#define TARGET_BOARD_NANOCLR_H + +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @TARGET_NAME@" + +#endif // TARGET_BOARD_NANOCLR_H diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/spiffs_config.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/spiffs_config.h new file mode 100644 index 0000000000..87356939c5 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/spiffs_config.h @@ -0,0 +1,370 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) 2013, petera, All Rights Reserved +// See LICENSE file in the project root for full license information. +// + +///////////////////////////////////////////////////////////////////////////// +// the configurations below are tunned for the MX25L51245G (from MACRONIX) +// that's fitted in the STM32F769I-DISCO board +///////////////////////////////////////////////////////////////////////////// + +#ifndef SPIFFS_CONFIG_H +#define SPIFFS_CONFIG_H + +#include + +///////////////////////////////////// +// need to map these types +typedef int32_t s32_t; +typedef uint32_t u32_t; +typedef int16_t s16_t; +typedef uint16_t u16_t; +typedef int8_t s8_t; +typedef uint8_t u8_t; + +// compile time switches + +// Set generic spiffs debug output call. +#ifndef SPIFFS_DBG +#define SPIFFS_DBG(_f, ...) // printf(_f, ## __VA_ARGS__) +#endif +// Set spiffs debug output call for garbage collecting. +#ifndef SPIFFS_GC_DBG +#define SPIFFS_GC_DBG(_f, ...) // printf(_f, ## __VA_ARGS__) +#endif +// Set spiffs debug output call for caching. +#ifndef SPIFFS_CACHE_DBG +#define SPIFFS_CACHE_DBG(_f, ...) // printf(_f, ## __VA_ARGS__) +#endif +// Set spiffs debug output call for system consistency checks. +#ifndef SPIFFS_CHECK_DBG +#define SPIFFS_CHECK_DBG(_f, ...) // printf(_f, ## __VA_ARGS__) +#endif +// Set spiffs debug output call for all api invocations. +#ifndef SPIFFS_API_DBG +#define SPIFFS_API_DBG(_f, ...) // printf(_f, ## __VA_ARGS__) +#endif + +// Defines spiffs debug print formatters +// some general signed number +#ifndef _SPIPRIi +#define _SPIPRIi "%d" +#endif +// address +#ifndef _SPIPRIad +#define _SPIPRIad "%08x" +#endif +// block +#ifndef _SPIPRIbl +#define _SPIPRIbl "%04x" +#endif +// page +#ifndef _SPIPRIpg +#define _SPIPRIpg "%04x" +#endif +// span index +#ifndef _SPIPRIsp +#define _SPIPRIsp "%04x" +#endif +// file descriptor +#ifndef _SPIPRIfd +#define _SPIPRIfd "%d" +#endif +// file object id +#ifndef _SPIPRIid +#define _SPIPRIid "%04x" +#endif +// file flags +#ifndef _SPIPRIfl +#define _SPIPRIfl "%02x" +#endif + +// Enable/disable API functions to determine exact number of bytes +// for filedescriptor and cache buffers. Once decided for a configuration, +// this can be disabled to reduce flash. +#ifndef SPIFFS_BUFFER_HELP +#define SPIFFS_BUFFER_HELP 0 +#endif + +// Enables/disable memory read caching of nucleus file system operations. +// If enabled, memory area must be provided for cache in SPIFFS_mount. +#ifndef SPIFFS_CACHE +#define SPIFFS_CACHE 1 +#endif +#if SPIFFS_CACHE +// Enables memory write caching for file descriptors in hydrogen +#ifndef SPIFFS_CACHE_WR +#define SPIFFS_CACHE_WR 1 +#endif + +// Enable/disable statistics on caching. Debug/test purpose only. +#ifndef SPIFFS_CACHE_STATS +#define SPIFFS_CACHE_STATS 1 +#endif +#endif + +// Always check header of each accessed page to ensure consistent state. +// If enabled it will increase number of reads, will increase flash. +#ifndef SPIFFS_PAGE_CHECK +#define SPIFFS_PAGE_CHECK 1 +#endif + +// Define maximum number of gc runs to perform to reach desired free pages. +#ifndef SPIFFS_GC_MAX_RUNS +#define SPIFFS_GC_MAX_RUNS 5 +#endif + +// Enable/disable statistics on gc. Debug/test purpose only. +#ifndef SPIFFS_GC_STATS +#define SPIFFS_GC_STATS 1 +#endif + +// Garbage collecting examines all pages in a block which and sums up +// to a block score. Deleted pages normally gives positive score and +// used pages normally gives a negative score (as these must be moved). +// To have a fair wear-leveling, the erase age is also included in score, +// whose factor normally is the most positive. +// The larger the score, the more likely it is that the block will +// picked for garbage collection. + +// Garbage collecting heuristics - weight used for deleted pages. +#ifndef SPIFFS_GC_HEUR_W_DELET +#define SPIFFS_GC_HEUR_W_DELET (5) +#endif +// Garbage collecting heuristics - weight used for used pages. +#ifndef SPIFFS_GC_HEUR_W_USED +#define SPIFFS_GC_HEUR_W_USED (-1) +#endif +// Garbage collecting heuristics - weight used for time between +// last erased and erase of this block. +#ifndef SPIFFS_GC_HEUR_W_ERASE_AGE +#define SPIFFS_GC_HEUR_W_ERASE_AGE (50) +#endif + +// Object name maximum length. Note that this length include the +// zero-termination character, meaning maximum string of characters +// can at most be SPIFFS_OBJ_NAME_LEN - 1. +#ifndef SPIFFS_OBJ_NAME_LEN +#define SPIFFS_OBJ_NAME_LEN (256) +#endif + +// Maximum length of the metadata associated with an object. +// Setting to non-zero value enables metadata-related API but also +// changes the on-disk format, so the change is not backward-compatible. +// +// Do note: the meta length must never exceed +// logical_page_size - (SPIFFS_OBJ_NAME_LEN + 64) +// +// This is derived from following: +// logical_page_size - (SPIFFS_OBJ_NAME_LEN + sizeof(spiffs_page_header) + +// spiffs_object_ix_header fields + at least some LUT entries) +#ifndef SPIFFS_OBJ_META_LEN +#define SPIFFS_OBJ_META_LEN (0) +#endif + +// Size of buffer allocated on stack used when copying data. +// Lower value generates more read/writes. No meaning having it bigger +// than logical page size. +#ifndef SPIFFS_COPY_BUFFER_STACK +#define SPIFFS_COPY_BUFFER_STACK (64) +#endif + +// Enable this to have an identifiable spiffs filesystem. This will look for +// a magic in all sectors to determine if this is a valid spiffs system or +// not on mount point. If not, SPIFFS_format must be called prior to mounting +// again. +#ifndef SPIFFS_USE_MAGIC +#define SPIFFS_USE_MAGIC (0) +#endif + +#if SPIFFS_USE_MAGIC +// Only valid when SPIFFS_USE_MAGIC is enabled. If SPIFFS_USE_MAGIC_LENGTH is +// enabled, the magic will also be dependent on the length of the filesystem. +// For example, a filesystem configured and formatted for 4 megabytes will not +// be accepted for mounting with a configuration defining the filesystem as 2 +// megabytes. +#ifndef SPIFFS_USE_MAGIC_LENGTH +#define SPIFFS_USE_MAGIC_LENGTH (0) +#endif +#endif + +// SPIFFS_LOCK and SPIFFS_UNLOCK protects spiffs from reentrancy on api level +// These should be defined on a multithreaded system + +// define this to enter a mutex if you're running on a multithreaded system +#ifndef SPIFFS_LOCK +extern void hal_spiffs_lock(); +#define SPIFFS_LOCK(fs) hal_spiffs_lock(fs); +#endif +// define this to exit a mutex if you're running on a multithreaded system +#ifndef SPIFFS_UNLOCK +extern void hal_spiffs_unlock(); +#define SPIFFS_UNLOCK(fs) hal_spiffs_unlock(fs); +#endif + +// Enable if only one spiffs instance with constant configuration will exist +// on the target. This will reduce calculations, flash and memory accesses. +// Parts of configuration must be defined below instead of at time of mount. +#ifndef SPIFFS_SINGLETON +#define SPIFFS_SINGLETON 0 +#endif + +#if SPIFFS_SINGLETON +// Instead of giving parameters in config struct, singleton build must +// give parameters in defines below. +#ifndef SPIFFS_CFG_PHYS_SZ +#define SPIFFS_CFG_PHYS_SZ(ignore) (1024 * 1024 * 2) +#endif +#ifndef SPIFFS_CFG_PHYS_ERASE_SZ +#define SPIFFS_CFG_PHYS_ERASE_SZ(ignore) (65536) +#endif +#ifndef SPIFFS_CFG_PHYS_ADDR +#define SPIFFS_CFG_PHYS_ADDR(ignore) (0) +#endif +#ifndef SPIFFS_CFG_LOG_PAGE_SZ +#define SPIFFS_CFG_LOG_PAGE_SZ(ignore) (256) +#endif +#ifndef SPIFFS_CFG_LOG_BLOCK_SZ +#define SPIFFS_CFG_LOG_BLOCK_SZ(ignore) (65536) +#endif +#endif + +// Enable this if your target needs aligned data for index tables +#ifndef SPIFFS_ALIGNED_OBJECT_INDEX_TABLES +#define SPIFFS_ALIGNED_OBJECT_INDEX_TABLES 0 +#endif + +// Enable this if you want the HAL callbacks to be called with the spiffs struct +#ifndef SPIFFS_HAL_CALLBACK_EXTRA +#define SPIFFS_HAL_CALLBACK_EXTRA 0 +#endif + +// Enable this if you want to add an integer offset to all file handles +// (spiffs_file). This is useful if running multiple instances of spiffs on +// same target, in order to recognise to what spiffs instance a file handle +// belongs. +// NB: This adds config field fh_ix_offset in the configuration struct when +// mounting, which must be defined. +#ifndef SPIFFS_FILEHDL_OFFSET +#define SPIFFS_FILEHDL_OFFSET 0 +#endif + +// Enable this to compile a read only version of spiffs. +// This will reduce binary size of spiffs. All code comprising modification +// of the file system will not be compiled. Some config will be ignored. +// HAL functions for erasing and writing to spi-flash may be null. Cache +// can be disabled for even further binary size reduction (and ram savings). +// Functions modifying the fs will return SPIFFS_ERR_RO_NOT_IMPL. +// If the file system cannot be mounted due to aborted erase operation and +// SPIFFS_USE_MAGIC is enabled, SPIFFS_ERR_RO_ABORTED_OPERATION will be +// returned. +// Might be useful for e.g. bootloaders and such. +#ifndef SPIFFS_READ_ONLY +#define SPIFFS_READ_ONLY 0 +#endif + +// Enable this to add a temporal file cache using the fd buffer. +// The effects of the cache is that SPIFFS_open will find the file faster in +// certain cases. It will make it a lot easier for spiffs to find files +// opened frequently, reducing number of readings from the spi flash for +// finding those files. +// This will grow each fd by 6 bytes. If your files are opened in patterns +// with a degree of temporal locality, the system is optimized. +// Examples can be letting spiffs serve web content, where one file is the css. +// The css is accessed for each html file that is opened, meaning it is +// accessed almost every second time a file is opened. Another example could be +// a log file that is often opened, written, and closed. +// The size of the cache is number of given file descriptors, as it piggybacks +// on the fd update mechanism. The cache lives in the closed file descriptors. +// When closed, the fd know the whereabouts of the file. Instead of forgetting +// this, the temporal cache will keep handling updates to that file even if the +// fd is closed. If the file is opened again, the location of the file is found +// directly. If all available descriptors become opened, all cache memory is +// lost. +#ifndef SPIFFS_TEMPORAL_FD_CACHE +#define SPIFFS_TEMPORAL_FD_CACHE 1 +#endif + +// Temporal file cache hit score. Each time a file is opened, all cached files +// will lose one point. If the opened file is found in cache, that entry will +// gain SPIFFS_TEMPORAL_CACHE_HIT_SCORE points. One can experiment with this +// value for the specific access patterns of the application. However, it must +// be between 1 (no gain for hitting a cached entry often) and 255. +#ifndef SPIFFS_TEMPORAL_CACHE_HIT_SCORE +#define SPIFFS_TEMPORAL_CACHE_HIT_SCORE 4 +#endif + +// Enable to be able to map object indices to memory. +// This allows for faster and more deterministic reading if cases of reading +// large files and when changing file offset by seeking around a lot. +// When mapping a file's index, the file system will be scanned for index pages +// and the info will be put in memory provided by user. When reading, the +// memory map can be looked up instead of searching for index pages on the +// medium. This way, user can trade memory against performance. +// Whole, parts of, or future parts not being written yet can be mapped. The +// memory array will be owned by spiffs and updated accordingly during garbage +// collecting or when modifying the indices. The latter is invoked by when the +// file is modified in some way. The index buffer is tied to the file +// descriptor. +#ifndef SPIFFS_IX_MAP +#define SPIFFS_IX_MAP 1 +#endif + +// By default SPIFFS in some cases relies on the property of NOR flash that bits +// cannot be set from 0 to 1 by writing and that controllers will ignore such +// bit changes. This results in fewer reads as SPIFFS can in some cases perform +// blind writes, with all bits set to 1 and only those it needs reset set to 0. +// Most of the chips and controllers allow this behavior, so the default is to +// use this technique. If your controller is one of the rare ones that don't, +// turn this option on and SPIFFS will perform a read-modify-write instead. +#ifndef SPIFFS_NO_BLIND_WRITES +#define SPIFFS_NO_BLIND_WRITES 0 +#endif + +// SPIFFS_vis disabled +#define SPIFFS_TEST_VISUALISATION 0 + +#if SPIFFS_TEST_VISUALISATION +#ifndef spiffs_printf +#define spiffs_printf(...) printf(__VA_ARGS__) +#endif +// spiffs_printf argument for a free page +#ifndef SPIFFS_TEST_VIS_FREE_STR +#define SPIFFS_TEST_VIS_FREE_STR "_" +#endif +// spiffs_printf argument for a deleted page +#ifndef SPIFFS_TEST_VIS_DELE_STR +#define SPIFFS_TEST_VIS_DELE_STR "/" +#endif +// spiffs_printf argument for an index page for given object id +#ifndef SPIFFS_TEST_VIS_INDX_STR +#define SPIFFS_TEST_VIS_INDX_STR(id) "i" +#endif +// spiffs_printf argument for a data page for given object id +#ifndef SPIFFS_TEST_VIS_DATA_STR +#define SPIFFS_TEST_VIS_DATA_STR(id) "d" +#endif +#endif + +// Types depending on configuration such as the amount of flash bytes +// given to spiffs file system in total (spiffs_file_system_size), +// the logical block size (log_block_size), and the logical page size +// (log_page_size) + +// Block index type. Make sure the size of this type can hold +// the highest number of all blocks - i.e. spiffs_file_system_size / log_block_size +typedef u16_t spiffs_block_ix; +// Page index type. Make sure the size of this type can hold +// the highest page number of all pages - i.e. spiffs_file_system_size / log_page_size +typedef u16_t spiffs_page_ix; +// Object id type - most significant bit is reserved for index flag. Make sure the +// size of this type can hold the highest object id on a full system, +// i.e. 2 + (spiffs_file_system_size / (2*log_page_size))*2 +typedef u16_t spiffs_obj_id; +// Object span index type. Make sure the size of this type can +// hold the largest possible span index on the system - +// i.e. (spiffs_file_system_size / log_page_size) - 1 +typedef u16_t spiffs_span_ix; + +#endif // SPIFFS_CONFIG_H diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/stm32f7xx_hal_conf.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/stm32f7xx_hal_conf.h new file mode 100644 index 0000000000..7f681bc7ce --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/stm32f7xx_hal_conf.h @@ -0,0 +1,56 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) 2016 STMicroelectronics. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef STM32F7xx_HAL_CONF_H +#define STM32F7xx_HAL_CONF_H + +#define STM32F769xx + +#ifdef __cplusplus + extern "C" { +#endif + +#define HAL_DMA_MODULE_ENABLED +#define HAL_QSPI_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED + +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f7xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f7xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f7xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + + +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + + +#ifdef __cplusplus +} +#endif + +#endif // __STM32F7xx_HAL_CONF_H diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_BlockStorage.c b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_BlockStorage.c new file mode 100644 index 0000000000..db45d1a411 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_BlockStorage.c @@ -0,0 +1,15 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice STM32Flash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( (BlockStorageDevice*)&Device_BlockStorage, &STM32Flash_BlockStorageInterface, &Device_BlockStorageConfig, false); +} diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_BlockStorage.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_BlockStorage.h new file mode 100644 index 0000000000..eac9e104e5 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef TARGETPAL_BLOCKSTORAGE_H +#define TARGETPAL_BLOCKSTORAGE_H + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //TARGETPAL_BLOCKSTORAGE_H diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_common.c b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_common.c new file mode 100644 index 0000000000..413b264ba6 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_common.c @@ -0,0 +1,27 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include "target_common.h" +#include + +HAL_SYSTEM_CONFIG HalSystemConfig = { + {true}, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, // ConvertCOM_DebugHandle(1), + 0, // ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + {RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size}, + {FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size}}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; + +// this target can use JTAG for updates +inline GET_TARGET_CAPABILITIES(TargetCapabilities_JtagUpdate); +inline TARGET_HAS_PROPRIETARY_BOOTER(false); diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_common.h.in b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_common.h.in new file mode 100644 index 0000000000..bbc95e8294 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_common.h.in @@ -0,0 +1,47 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef TARGET_COMMON_H +#define TARGET_COMMON_H + +// #include +#include +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0xC0000000) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x01000000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x08000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00200000) + +///////////////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////// +#define TARGETNAMESTRING "@TARGET_NAME@" +#define PLATFORMNAMESTRING "STM32F7" +////////////////////////////////////////////// + +///////////////////////////////////// +#define PLATFORM_HAS_RNG TRUE +///////////////////////////////////// + +///////////////////////////////////// +//#define EVENTS_HEART_BEAT palToggleLine(LINE_LED2_GREEN) +///////////////////////////////////// + +#endif // TARGET_COMMON_H diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_external_memory.c b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_external_memory.c new file mode 100644 index 0000000000..ac5a917b4c --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_external_memory.c @@ -0,0 +1,111 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "hal.h" +#include "fsmc_sdram_lld.h" + + +// SDRAM Mode definition register defines +#define FMC_SDCMR_MRD_BURST_LENGTH_1 ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_BURST_LENGTH_2 ((uint16_t)0x0001) +#define FMC_SDCMR_MRD_BURST_LENGTH_4 ((uint16_t)0x0002) +#define FMC_SDCMR_MRD_BURST_LENGTH_8 ((uint16_t)0x0004) +#define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) +#define FMC_SDCMR_MRD_CAS_LATENCY_2 ((uint16_t)0x0020) +#define FMC_SDCMR_MRD_CAS_LATENCY_3 ((uint16_t)0x0030) +#define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) + +// FMC_ReadPipe_Delay +#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000) +#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000) +#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000) +#define FMC_ReadPipe_Delay_Mask ((uint32_t)0x00006000) + +// FMC_Read_Burst +#define FMC_Read_Burst_Disable ((uint32_t)0x00000000) +#define FMC_Read_Burst_Enable ((uint32_t)0x00001000) +#define FMC_Read_Burst_Mask ((uint32_t)0x00001000) + +// FMC_SDClock_Period +#define FMC_SDClock_Disable ((uint32_t)0x00000000) +#define FMC_SDClock_Period_2 ((uint32_t)0x00000800) +#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00) +#define FMC_SDClock_Period_Mask ((uint32_t)0x00000C00) + +// FMC_ColumnBits_Number +#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000) +#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001) +#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002) +#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003) + +// FMC_RowBits_Number +#define FMC_RowBits_Number_11b ((uint32_t)0x00000000) +#define FMC_RowBits_Number_12b ((uint32_t)0x00000004) +#define FMC_RowBits_Number_13b ((uint32_t)0x00000008) + +// FMC_SDMemory_Data_Width +#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000) +#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010) +#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020) + +// FMC_InternalBank_Number +#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000) +#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040) + +// FMC_CAS_Latency +#define FMC_CAS_Latency_1 ((uint32_t)0x00000080) +#define FMC_CAS_Latency_2 ((uint32_t)0x00000100) +#define FMC_CAS_Latency_3 ((uint32_t)0x00000180) + +// FMC_Write_Protection +#define FMC_Write_Protection_Disable ((uint32_t)0x00000000) +#define FMC_Write_Protection_Enable ((uint32_t)0x00000200) + +#define SDRAM_SIZE (16 * 1024 * 1024) +#define SDRAM_START ((void *)FSMC_Bank5_MAP_BASE) + + +// SDRAM driver configuration structure. +static const SDRAMConfig sdram_cfg = { + .sdcr = (uint32_t) FMC_ColumnBits_Number_8b | + FMC_RowBits_Number_12b | + FMC_SDMemory_Width_32b | + FMC_InternalBank_Number_4 | + FMC_CAS_Latency_3 | + FMC_Write_Protection_Disable | + FMC_SDClock_Period_2 | + FMC_Read_Burst_Enable | + FMC_ReadPipe_Delay_0, + .sdtr = (uint32_t) (2 - 1) | // FMC_LoadToActiveDelay = 2 (TMRD: 2 Clock cycles) + (7 << 4) | // FMC_ExitSelfRefreshDelay = 7 (TXSR: min=70ns (7x11.11ns)) + (4 << 8) | // FMC_SelfRefreshTime = 4 (TRAS: min=42ns (4x11.11ns) max=120k (ns)) + (7 << 12) | // FMC_RowCycleDelay = 7 (TRC: min=70 (7x11.11ns)) + (3 << 16) | // FMC_WriteRecoveryTime = 2 (TWR: min=1+ 7ns (1+1x11.11ns)) + (2 << 20) | // FMC_RPDelay = 2 (TRP: 20ns => 2x11.11ns) + (2 << 24), // FMC_RCDDelay = 2 (TRCD: 20ns => 2x11.11ns) + // NRFS = 4-1 + .sdcmr = (3 << 5) | (FMC_SDCMR_MRD_BURST_LENGTH_2 | + FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL | + FMC_SDCMR_MRD_CAS_LATENCY_3 | + FMC_SDCMR_MRD_OPERATING_MODE_STANDARD | + FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE) << 9, + + .sdrtr = (uint32_t)(683 << 1), +}; + +void Target_ExternalMemoryInit() +{ + fsmcSdramInit(); + + // FIXME + // this swaps SDRAM address to 0x60000000 and makes it L1 cacheable + //SYSCFG->MEMRMP |= SYSCFG_MEMRMP_SWP_FMC_0; + + fsmcSdramStart(&SDRAMD, &sdram_cfg); +} diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_lwip_sntp_opts.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_lwip_sntp_opts.h new file mode 100644 index 0000000000..c4d09f1f1a --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_lwip_sntp_opts.h @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T OVERRIDE ANY lwIP SNTP OPTIONS // +////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_lwipopts.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_lwipopts.h new file mode 100644 index 0000000000..ca1a0b4465 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_lwipopts.h @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +///////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T OVERRIDE ANY lwIP OPTIONS // +///////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_dev_onewire_config.cpp b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_dev_onewire_config.cpp new file mode 100644 index 0000000000..d2fe09ebc0 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_dev_onewire_config.cpp @@ -0,0 +1,29 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include "target_nf_dev_onewire_config.h" +#include + +/////////// +// UART4 // +/////////// + +// pin configuration for UART4 +// port for TX pin is: GPIOC +// TX pin: is GPIOC_10 +// GPIO alternate pin function is 8 +UART_CONFIG_PINS(4, GPIOC, 10, 8) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned(32))) +#endif +uint8_t Uart4_TxBuffer[UART4_TX_SIZE]; +#if defined(__GNUC__) +__attribute__((aligned(32))) +#endif +uint8_t Uart4_RxBuffer[UART4_RX_SIZE]; diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_dev_onewire_config.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_dev_onewire_config.h new file mode 100644 index 0000000000..b4c3aba457 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_dev_onewire_config.h @@ -0,0 +1,17 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////// +// UART4 // +/////////// + +// enable USART4 +#define NF_ONEWIRE_STM32_UART_USE_USART4 TRUE + +// buffers size +// tx buffer size: 32 bytes +#define UART4_TX_SIZE 32 +// rx buffer size: 32 bytes +#define UART4_RX_SIZE 32 \ No newline at end of file diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.cpp b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.cpp new file mode 100644 index 0000000000..4c83d9afa5 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.cpp @@ -0,0 +1,46 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_nf_device_can_config.h" +#include + +/////////// +// CAN1 // +/////////// + +// pin configuration for CAN1 +// port for TX pin is: GPIOB +// TX pin: is GPIOB_09 +// port for RX pin is: GPIOB +// RX pin: is GPIOB_08 +// GPIO alternate pin function is 9 (see "Table 9. STM32F405xx and STM32F407xx alternate function mapping" in +// STM32F405xx/STM32F407xx datasheet) +CAN_CONFIG_PINS(1, GPIOB, GPIOB, 9, 8, 9) + +// buffer +CANRxFrame Can1_MsgBuffer[CAN1_RX_BUFFER_SIZE]; + +// initialization for CAN1 +CAN_INIT(1, CAN1_RX_BUFFER_SIZE) + +/////////// +// CAN2 // +/////////// + +// pin configuration for CAN2 +// port for TX pin is: GPIOB +// TX pin: is GPIOB_06 +// port for RX pin is: GPIOB +// RX pin: is GPIOB_05 +// GPIO alternate pin function is 9 (see "Table 9. STM32F405xx and STM32F407xx alternate function mapping" in +// STM32F405xx/STM32F407xx datasheet) +CAN_CONFIG_PINS(2, GPIOB, GPIOB, 6, 5, 9) + +// buffer +CANRxFrame Can2_MsgBuffer[CAN2_RX_BUFFER_SIZE]; + +// initialization for CAN1 +CAN_INIT(2, CAN2_RX_BUFFER_SIZE) diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.h new file mode 100644 index 0000000000..77cbceded5 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.h @@ -0,0 +1,24 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////// +// CAN1 // +////////// + +// enable CAN1 +#define NF_CAN_STM32_CAN_USE_CAN1 TRUE + +// buffers size +#define CAN1_RX_BUFFER_SIZE 16 + +////////// +// CAN2 // +////////// + +// enable CAN2 +#define NF_CAN_STM32_CAN_USE_CAN2 TRUE + +// buffers size +#define CAN2_RX_BUFFER_SIZE 16 diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_spiffs.c b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_spiffs.c new file mode 100644 index 0000000000..78fd0575f6 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_spiffs.c @@ -0,0 +1,864 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) 2016 STMicroelectronics. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#ifdef __cplusplus +extern "C" +{ + void HAL_Delay(uint32_t delay); + +#endif + + static uint8_t QSPI_ResetMemory(QSPI_HandleTypeDef *hqspi); + static uint8_t QSPI_EnterFourBytesAddress(QSPI_HandleTypeDef *hqspi); + static uint8_t QSPI_DummyCyclesCfg(QSPI_HandleTypeDef *hqspi); + static uint8_t QSPI_EnterMemory_QPI(QSPI_HandleTypeDef *hqspi); + // static uint8_t QSPI_ExitMemory_QPI(QSPI_HandleTypeDef *hqspi); + static uint8_t QSPI_OutDrvStrengthCfg(QSPI_HandleTypeDef *hqspi); + static uint8_t QSPI_WriteEnable(QSPI_HandleTypeDef *hqspi); + static uint8_t QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi, uint32_t Timeout); + static uint8_t QSPI_ReadChipID(QSPI_HandleTypeDef *hqspi, uint8_t *buffer); + + uint8_t QSPI_Read(uint8_t *pData, uint32_t readAddr, uint32_t size); + uint8_t QSPI_Write(uint8_t *pData, uint32_t writeAddr, uint32_t size); + uint8_t QSPI_Erase_Block(uint32_t blockAddress); + + // initialization of everything required for SPIFFS + // for this target is the QSPI driver + uint8_t target_spiffs_init() + { + uint8_t device_id[3] = {0, 0, 0}; + + /* QSPI initialization */ + /* QSPI freq = SYSCLK /(1 + ClockPrescaler) = 216 MHz/(1+1) = 108 Mhz */ + QSPID1.Init.ClockPrescaler = 1; /* QSPI freq = 216 MHz/(1+1) = 108 Mhz */ + QSPID1.Init.FifoThreshold = 16; + QSPID1.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE; + QSPID1.Init.FlashSize = POSITION_VAL(MX25L512_FLASH_SIZE) - 1; + QSPID1.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE; /* Min 30ns for nonRead */ + QSPID1.Init.ClockMode = QSPI_CLOCK_MODE_0; + QSPID1.Init.FlashID = QSPI_FLASH_ID_1; + QSPID1.Init.DualFlash = QSPI_DUALFLASH_DISABLE; + + // init driver + qspiStart(&QSPID1); + + if (HAL_QSPI_Init(&QSPID1) != HAL_OK) + { + return QSPI_ERROR; + } + + /* QSPI memory reset */ + if (QSPI_ResetMemory(&QSPID1) != QSPI_OK) + { + return QSPI_NOT_SUPPORTED; + } + + /* Put QSPI memory in QPI mode */ + if (QSPI_EnterMemory_QPI(&QSPID1) != QSPI_OK) + { + return QSPI_NOT_SUPPORTED; + } + + /* Set the QSPI memory in 4-bytes address mode */ + if (QSPI_EnterFourBytesAddress(&QSPID1) != QSPI_OK) + { + return QSPI_NOT_SUPPORTED; + } + + /* Configuration of the dummy cycles on QSPI memory side */ + if (QSPI_DummyCyclesCfg(&QSPID1) != QSPI_OK) + { + return QSPI_NOT_SUPPORTED; + } + + /* Configuration of the Output driver strength on memory side */ + if (QSPI_OutDrvStrengthCfg(&QSPID1) != QSPI_OK) + { + return QSPI_NOT_SUPPORTED; + } + + HAL_Delay(10); + + // sanity check: read device ID and unique ID + if (QSPI_ReadChipID(&QSPID1, device_id) != QSPI_OK) + { + return QSPI_ERROR; + } + + // // invalidate cache over read buffer to ensure that content from DMA is read + // // (only required for Cortex-M7) + // cacheBufferInvalidate(device_id, 3); + + // constants from ID Definitions table in MX25L51245G datasheet + ASSERT(device_id[0] == MX25L512_MANUFACTURER_ID); + ASSERT(device_id[1] == MX25L512_DEVICE_ID_MEM_TYPE); + ASSERT(device_id[2] == MX25L512_DEVICE_ID_MEM_CAPACITY); + + return QSPI_OK; + } + + // target specific implementation of hal_spiffs_erase + s32_t hal_spiffs_erase_0(u32_t addr, u32_t size) + { + uint32_t i = 0; + + // how many sectors need to be erased? + uint32_t erase_count = (size + SPIFFS0_ERASE_BLOCK_SIZE - 1) / SPIFFS0_ERASE_BLOCK_SIZE; + + for (i = 0; i < erase_count; i++) + { + if (QSPI_Erase_Block(addr) != QSPI_OK) + { + return SPIFFS_ERROR; + } + + // adjust sector address + addr += i * SPIFFS0_ERASE_BLOCK_SIZE; + } + + return SPIFFS_SUCCESS; + } + + // target specific implementation of hal_spiffs_read + s32_t hal_spiffs_read_0(u32_t addr, u32_t size, u8_t *dst) + { + if (QSPI_Read(dst, addr, size) != QSPI_OK) + { + return SPIFFS_ERROR; + } + + return SPIFFS_SUCCESS; + } + + // target specific implementation of hal_spiffs_write + s32_t hal_spiffs_write_0(u32_t addr, u32_t size, u8_t *src) + { + if (QSPI_Write(src, addr, size) != QSPI_OK) + { + return SPIFFS_ERROR; + } + + return SPIFFS_SUCCESS; + } + + static uint8_t QSPI_ResetMemory(QSPI_HandleTypeDef *hqspi) + { + QSPI_CommandTypeDef s_command; + QSPI_AutoPollingTypeDef s_config; + uint8_t reg; + + /* Send command RESET command in QPI mode (QUAD I/Os) */ + /* Initialize the reset enable command */ + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = RESET_ENABLE_CMD; + s_command.AddressMode = QSPI_ADDRESS_NONE; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_NONE; + s_command.DummyCycles = 0; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + /* Send the command */ + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Send the reset memory command */ + s_command.Instruction = RESET_MEMORY_CMD; + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Send command RESET command in SPI mode */ + /* Initialize the reset enable command */ + s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE; + s_command.Instruction = RESET_ENABLE_CMD; + /* Send the command */ + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + /* Send the reset memory command */ + s_command.Instruction = RESET_MEMORY_CMD; + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* After reset CMD, 1000ms requested if QSPI memory SWReset occured during full chip erase operation */ + HAL_Delay(1000); + + /* Configure automatic polling mode to wait the WIP bit=0 */ + s_config.Match = 0; + s_config.Mask = MX25L512_SR_WIP; + s_config.MatchMode = QSPI_MATCH_MODE_AND; + s_config.StatusBytesSize = 1; + s_config.Interval = 0x10; + s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; + + s_command.Instruction = READ_STATUS_REG_CMD; + s_command.DataMode = QSPI_DATA_1_LINE; + + if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Initialize the reading of status register */ + s_command.Instruction = READ_STATUS_REG_CMD; + s_command.NbData = 1; + + /* Configure the command */ + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Reception of the data */ + if (HAL_QSPI_Receive(hqspi, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Enable write operations, command in 1 bit */ + /* Enable write operations */ + s_command.Instruction = WRITE_ENABLE_CMD; + s_command.DataMode = QSPI_DATA_NONE; + s_command.DummyCycles = 0; + s_command.NbData = 0; + + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Configure automatic polling mode to wait for write enabling */ + s_config.Match = MX25L512_SR_WREN; + s_config.Mask = MX25L512_SR_WREN; + s_config.MatchMode = QSPI_MATCH_MODE_AND; + s_config.StatusBytesSize = 1; + s_config.Interval = 0x10; + s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; + + s_command.Instruction = READ_STATUS_REG_CMD; + s_command.DataMode = QSPI_DATA_1_LINE; + s_command.NbData = 0; + + if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Update the configuration register with new dummy cycles */ + s_command.Instruction = WRITE_STATUS_CFG_REG_CMD; + s_command.DataMode = QSPI_DATA_1_LINE; + s_command.NbData = 1; + + /* Enable the Quad IO on the QSPI memory (Non-volatile bit) */ + reg |= MX25L512_SR_QUADEN; + + /* Configure the command */ + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Transmission of the data */ + if (HAL_QSPI_Transmit(hqspi, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* 40ms Write Status/Configuration Register Cycle Time */ + HAL_Delay(40); + + // read back register to check MX25L512_SR_QUADEN + s_command.Instruction = READ_STATUS_REG_CMD; + s_command.DataMode = QSPI_DATA_1_LINE; + s_command.DummyCycles = 0; + s_command.NbData = 1; + + /* Configure the command */ + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Reception of the data */ + if (HAL_QSPI_Receive(hqspi, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + if (reg & MX25L512_SR_QUADEN) + { + return QSPI_OK; + } + else + { + return QSPI_ERROR; + } + } + + static uint8_t QSPI_DummyCyclesCfg(QSPI_HandleTypeDef *hqspi) + { + QSPI_CommandTypeDef s_command; + uint8_t reg[2]; + + /* Initialize the reading of status register */ + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = READ_STATUS_REG_CMD; + s_command.AddressMode = QSPI_ADDRESS_NONE; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_4_LINES; + s_command.DummyCycles = 0; + s_command.NbData = 1; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + /* Configure the command */ + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Reception of the data */ + if (HAL_QSPI_Receive(hqspi, &(reg[0]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Initialize the reading of configuration register */ + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = READ_CFG_REG_CMD; + s_command.AddressMode = QSPI_ADDRESS_NONE; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_4_LINES; + s_command.DummyCycles = 0; + s_command.NbData = 1; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + /* Configure the command */ + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Reception of the data */ + if (HAL_QSPI_Receive(hqspi, &(reg[1]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Enable write operations */ + if (QSPI_WriteEnable(hqspi) != QSPI_OK) + { + return QSPI_ERROR; + } + + /* Update the configuration register with new dummy cycles */ + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = WRITE_STATUS_CFG_REG_CMD; + s_command.AddressMode = QSPI_ADDRESS_NONE; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_4_LINES; + s_command.DummyCycles = 0; + s_command.NbData = 2; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + /* MX25L512_DUMMY_CYCLES_READ_QUAD = 3 for 10 cycles in QPI mode */ + MODIFY_REG( + reg[1], + MX25L512_CR_NB_DUMMY, + (MX25L512_DUMMY_CYCLES_READ_QUAD << POSITION_VAL(MX25L512_CR_NB_DUMMY))); + + /* Configure the write volatile configuration register command */ + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Transmission of the data */ + if (HAL_QSPI_Transmit(hqspi, &(reg[0]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* 40ms Write Status/Configuration Register Cycle Time */ + HAL_Delay(40); + + return QSPI_OK; + } + + static uint8_t QSPI_EnterMemory_QPI(QSPI_HandleTypeDef *hqspi) + { + QSPI_CommandTypeDef s_command; + QSPI_AutoPollingTypeDef s_config; + + /* Initialize the QPI enable command */ + /* QSPI memory is supported to be in SPI mode, so CMD on 1 LINE */ + s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE; + s_command.Instruction = ENTER_QUAD_CMD; + s_command.AddressMode = QSPI_ADDRESS_NONE; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_NONE; + s_command.DummyCycles = 0; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + /* Send the command */ + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Configure automatic polling mode to wait the QUADEN bit=1 and WIP bit=0 */ + s_config.Match = MX25L512_SR_QUADEN; + s_config.Mask = MX25L512_SR_QUADEN | MX25L512_SR_WIP; + s_config.MatchMode = QSPI_MATCH_MODE_AND; + s_config.StatusBytesSize = 1; + s_config.Interval = 0x10; + s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; + + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = READ_STATUS_REG_CMD; + s_command.DataMode = QSPI_DATA_4_LINES; + + if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + return QSPI_OK; + } + + // static uint8_t QSPI_ExitMemory_QPI( QSPI_HandleTypeDef *hqspi) + // { + // QSPI_CommandTypeDef s_command; + + // /* Initialize the QPI enable command */ + // /* QSPI memory is supported to be in QPI mode, so CMD on 4 LINES */ + // s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + // s_command.Instruction = EXIT_QUAD_CMD; + // s_command.AddressMode = QSPI_ADDRESS_NONE; + // s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + // s_command.DataMode = QSPI_DATA_NONE; + // s_command.DummyCycles = 0; + // s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + // s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + // s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + // /* Send the command */ + // if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + // { + // return QSPI_ERROR; + // } + + // return QSPI_OK; + // } + + static uint8_t QSPI_EnterFourBytesAddress(QSPI_HandleTypeDef *hqspi) + { + QSPI_CommandTypeDef s_command; + + /* Initialize the command */ + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = ENTER_4_BYTE_ADDR_MODE_CMD; + s_command.AddressMode = QSPI_ADDRESS_NONE; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_NONE; + s_command.DummyCycles = 0; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + /* Enable write operations */ + if (QSPI_WriteEnable(hqspi) != QSPI_OK) + { + return QSPI_ERROR; + } + + /* Send the command */ + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Configure automatic polling mode to wait the memory is ready */ + if (QSPI_AutoPollingMemReady(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK) + { + return QSPI_ERROR; + } + + return QSPI_OK; + } + + static uint8_t QSPI_WriteEnable(QSPI_HandleTypeDef *hqspi) + { + + // HAL_QSPI_Abort(&QSPID1); + + QSPI_CommandTypeDef s_command; + QSPI_AutoPollingTypeDef s_config; + + /* Enable write operations */ + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = WRITE_ENABLE_CMD; + s_command.AddressMode = QSPI_ADDRESS_NONE; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_NONE; + s_command.DummyCycles = 0; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Configure automatic polling mode to wait for write enabling */ + s_config.Match = MX25L512_SR_WREN; + s_config.Mask = MX25L512_SR_WREN; + s_config.MatchMode = QSPI_MATCH_MODE_AND; + s_config.StatusBytesSize = 1; + s_config.Interval = 0x10; + s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; + + s_command.Instruction = READ_STATUS_REG_CMD; + s_command.DataMode = QSPI_DATA_4_LINES; + + if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + return QSPI_OK; + } + + static uint8_t QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) + { + QSPI_CommandTypeDef s_command; + QSPI_AutoPollingTypeDef s_config; + + /* Configure automatic polling mode to wait for memory ready */ + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = READ_STATUS_REG_CMD; + s_command.AddressMode = QSPI_ADDRESS_NONE; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_4_LINES; + s_command.DummyCycles = 0; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + s_config.Match = 0; + s_config.Mask = MX25L512_SR_WIP; + s_config.MatchMode = QSPI_MATCH_MODE_AND; + s_config.StatusBytesSize = 1; + s_config.Interval = 0x10; + s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; + + if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, Timeout) != HAL_OK) + { + return QSPI_ERROR; + } + + return QSPI_OK; + } + + static uint8_t QSPI_OutDrvStrengthCfg(QSPI_HandleTypeDef *hqspi) + { + QSPI_CommandTypeDef s_command; + uint8_t reg[2]; + + /* Initialize the reading of status register */ + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = READ_STATUS_REG_CMD; + s_command.AddressMode = QSPI_ADDRESS_NONE; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_4_LINES; + s_command.DummyCycles = 0; + s_command.NbData = 1; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + /* Configure the command */ + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Reception of the data */ + if (HAL_QSPI_Receive(hqspi, &(reg[0]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Initialize the reading of configuration register */ + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = READ_CFG_REG_CMD; + s_command.AddressMode = QSPI_ADDRESS_NONE; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_4_LINES; + s_command.DummyCycles = 0; + s_command.NbData = 1; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + /* Configure the command */ + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Reception of the data */ + if (HAL_QSPI_Receive(hqspi, &(reg[1]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Enable write operations */ + if (QSPI_WriteEnable(&QSPID1) != QSPI_OK) + { + return QSPI_ERROR; + } + + /* Update the configuration register with new output driver strength */ + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = WRITE_STATUS_CFG_REG_CMD; + s_command.AddressMode = QSPI_ADDRESS_NONE; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_4_LINES; + s_command.DummyCycles = 0; + s_command.NbData = 2; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + /* Set Output Strength of the QSPI memory 15 ohms */ + MODIFY_REG(reg[1], MX25L512_CR_ODS, (MX25L512_CR_ODS_15 << POSITION_VAL(MX25L512_CR_ODS))); + + /* Configure the write volatile configuration register command */ + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Transmission of the data */ + if (HAL_QSPI_Transmit(hqspi, &(reg[0]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + return QSPI_OK; + } + + static uint8_t QSPI_ReadChipID(QSPI_HandleTypeDef *hqspi, uint8_t *buffer) + { + QSPI_CommandTypeDef s_command; + + /* Initialize the reading of status register */ + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = MULTIPLE_IO_READ_ID_CMD; + s_command.AddressMode = QSPI_ADDRESS_NONE; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_4_LINES; + s_command.DummyCycles = 0; + s_command.NbData = 3; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + /* Configure the command */ + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Reception of the data */ + if (HAL_QSPI_Receive(hqspi, buffer, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + return QSPI_OK; + } + + uint8_t QSPI_Read(uint8_t *pData, uint32_t readAddr, uint32_t size) + { + QSPI_CommandTypeDef s_command; + + /* Initialize the read command */ + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = QSPI_READ_4_BYTE_ADDR_CMD; + s_command.AddressMode = QSPI_ADDRESS_4_LINES; + s_command.AddressSize = QSPI_ADDRESS_32_BITS; + s_command.Address = readAddr; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_4_LINES; + s_command.DummyCycles = MX25L512_DUMMY_CYCLES_READ_QUAD_IO; + s_command.NbData = size; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + /* Configure the command */ + if (HAL_QSPI_Command(&QSPID1, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Set S# timing for Read command */ + MODIFY_REG(QSPID1.Instance->DCR, QUADSPI_DCR_CSHT, QSPI_CS_HIGH_TIME_1_CYCLE); + + /* Reception of the data */ + if (HAL_QSPI_Receive(&QSPID1, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + // // invalidate cache over read buffer to ensure that content from DMA is read + // // (only required for Cortex-M7) + // cacheBufferInvalidate(pData, size); + + /* Restore S# timing for nonRead commands */ + MODIFY_REG(QSPID1.Instance->DCR, QUADSPI_DCR_CSHT, QSPI_CS_HIGH_TIME_4_CYCLE); + + SET_BIT(QSPID1.Instance->CR, QUADSPI_CR_ABORT); + + return QSPI_OK; + } + + uint8_t QSPI_Write(uint8_t *pData, uint32_t writeAddr, uint32_t size) + { + QSPI_CommandTypeDef s_command; + uint32_t end_addr, current_size, current_addr; + + /* Calculation of the size between the write address and the end of the page */ + current_size = MX25L512_PAGE_SIZE - (writeAddr % MX25L512_PAGE_SIZE); + + /* Check if the size of the data is less than the remaining place in the page */ + if (current_size > size) + { + current_size = size; + } + + /* Initialize the address variables */ + current_addr = writeAddr; + end_addr = writeAddr + size; + + /* Initialize the program command */ + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = PAGE_PROG_CMD; + s_command.AddressMode = QSPI_ADDRESS_4_LINES; + s_command.AddressSize = QSPI_ADDRESS_32_BITS; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_4_LINES; + s_command.DummyCycles = 0; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + /* Perform the write page by page */ + do + { + s_command.Address = current_addr; + s_command.NbData = current_size; + + /* Enable write operations */ + if (QSPI_WriteEnable(&QSPID1) != QSPI_OK) + { + return QSPI_ERROR; + } + + /* Configure the command */ + if (HAL_QSPI_Command(&QSPID1, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + // // flush DMA buffer to ensure cache coherency + // // (only required for Cortex-M7) + // cacheBufferFlush(pData, current_size); + + /* Transmission of the data */ + if (HAL_QSPI_Transmit(&QSPID1, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Configure automatic polling mode to wait for end of program */ + if (QSPI_AutoPollingMemReady(&QSPID1, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK) + { + return QSPI_ERROR; + } + + /* Update the address and size variables for next page programming */ + current_addr += current_size; + pData += current_size; + current_size = + ((current_addr + MX25L512_PAGE_SIZE) > end_addr) ? (end_addr - current_addr) : MX25L512_PAGE_SIZE; + + } while (current_addr < end_addr); + + return QSPI_OK; + } + + uint8_t QSPI_Erase_Block(uint32_t blockAddress) + { + QSPI_CommandTypeDef s_command; + + /* Initialize the erase command */ + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = SECTOR_ERASE_4_BYTE_ADDR_CMD; + s_command.AddressMode = QSPI_ADDRESS_4_LINES; + s_command.AddressSize = QSPI_ADDRESS_32_BITS; + s_command.Address = blockAddress; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_NONE; + s_command.DummyCycles = 0; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + /* Enable write operations */ + if (QSPI_WriteEnable(&QSPID1) != QSPI_OK) + { + return QSPI_ERROR; + } + + /* Send the command */ + if (HAL_QSPI_Command(&QSPID1, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Configure automatic polling mode to wait for end of erase */ + if (QSPI_AutoPollingMemReady(&QSPID1, MX25L512_SECTOR_ERASE_MAX_TIME) != QSPI_OK) + { + return QSPI_ERROR; + } + + return QSPI_OK; + } + +#ifdef __cplusplus +} +#endif diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_spiffs.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_spiffs.h new file mode 100644 index 0000000000..6e83b339bb --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_spiffs.h @@ -0,0 +1,138 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef TARGET_SPIFFS_H +#define TARGET_SPIFFS_H + +#include +#include +#include +#include + +#define SPIFFS_DRIVER_QSPI (1) + +// MX25L512 Configuration +#define MX25L512_FLASH_SIZE 0x4000000 /* 512 MBits => 64MBytes */ +#define MX25L512_SECTOR_SIZE 0x10000 /* 1024 sectors of 64KBytes */ +#define MX25L512_SUBSECTOR_SIZE 0x1000 /* 16384 subsectors of 4kBytes */ +#define MX25L512_PAGE_SIZE 0x100 /* 262144 pages of 256 bytes */ +#define MX25L512_DUMMY_CYCLES_READ_QUAD 3 +#define MX25L512_DUMMY_CYCLES_READ 8 +#define MX25L512_DUMMY_CYCLES_READ_QUAD_IO 10 +#define MX25L512_DUMMY_CYCLES_READ_DTR 6 +#define MX25L512_DUMMY_CYCLES_READ_QUAD_DTR 8 +#define MX25L512_BULK_ERASE_MAX_TIME 600000 +#define MX25L512_SECTOR_ERASE_MAX_TIME 2000 +#define MX25L512_SUBSECTOR_ERASE_MAX_TIME 800 + +// MX25L512 Commands +/* Reset Operations */ +#define RESET_ENABLE_CMD 0x66 +#define RESET_MEMORY_CMD 0x99 + +/* Identification Operations */ +#define READ_ID_CMD 0x9F +#define MULTIPLE_IO_READ_ID_CMD 0xAF +#define READ_SERIAL_FLASH_DISCO_PARAM_CMD 0x5A + +/* Read Operations */ +#define READ_CMD 0x03 +#define READ_4_BYTE_ADDR_CMD 0x13 +#define FAST_READ_CMD 0x0B +#define FAST_READ_DTR_CMD 0x0D +#define FAST_READ_4_BYTE_ADDR_CMD 0x0C +#define DUAL_OUT_FAST_READ_CMD 0x3B +#define DUAL_OUT_FAST_READ_4_BYTE_ADDR_CMD 0x3C +#define DUAL_INOUT_FAST_READ_CMD 0xBB +#define DUAL_INOUT_FAST_READ_DTR_CMD 0xBD +#define DUAL_INOUT_FAST_READ_4_BYTE_ADDR_CMD 0xBC +#define QUAD_OUT_FAST_READ_CMD 0x6B +#define QUAD_OUT_FAST_READ_4_BYTE_ADDR_CMD 0x6C +#define QUAD_INOUT_FAST_READ_CMD 0xEB +#define QUAD_INOUT_FAST_READ_DTR_CMD 0xED +#define QSPI_READ_4_BYTE_ADDR_CMD 0xEC + +/* Write Operations */ +#define WRITE_ENABLE_CMD 0x06 +#define WRITE_DISABLE_CMD 0x04 + +/* Register Operations */ +#define READ_STATUS_REG_CMD 0x05 +#define READ_CFG_REG_CMD 0x15 +#define WRITE_STATUS_CFG_REG_CMD 0x01 +#define READ_LOCK_REG_CMD 0x2D +#define WRITE_LOCK_REG_CMD 0x2C +#define READ_EXT_ADDR_REG_CMD 0xC8 +#define WRITE_EXT_ADDR_REG_CMD 0xC5 + +/* Program Operations */ +#define PAGE_PROG_CMD 0x02 +#define QSPI_PAGE_PROG_4_BYTE_ADDR_CMD 0x12 +#define QUAD_IN_FAST_PROG_CMD 0x38 +#define EXT_QUAD_IN_FAST_PROG_CMD 0x38 +#define QUAD_IN_FAST_PROG_4_BYTE_ADDR_CMD 0x3E + +/* Erase Operations */ +#define SUBSECTOR_ERASE_CMD 0x20 +#define SUBSECTOR_ERASE_4_BYTE_ADDR_CMD 0x21 +#define SECTOR_ERASE_CMD 0xD8 +#define SECTOR_ERASE_4_BYTE_ADDR_CMD 0xDC +#define BULK_ERASE_CMD 0xC7 +#define PROG_ERASE_RESUME_CMD 0x30 +#define PROG_ERASE_SUSPEND_CMD 0xB0 + +/* 4-byte Address Mode Operations */ +#define ENTER_4_BYTE_ADDR_MODE_CMD 0xB7 +#define EXIT_4_BYTE_ADDR_MODE_CMD 0xE9 + +/* Quad Operations */ +#define ENTER_QUAD_CMD 0x35 +#define EXIT_QUAD_CMD 0xF5 + +/* Added for compatibility */ +#define QPI_READ_4_BYTE_ADDR_CMD QSPI_READ_4_BYTE_ADDR_CMD +#define QPI_PAGE_PROG_4_BYTE_ADDR_CMD QSPI_PAGE_PROG_4_BYTE_ADDR_CMD + +// MX25L512 Registers +/* Status Register */ +#define MX25L512_SR_WIP ((uint8_t)0x01) /*!< Write in progress */ +#define MX25L512_SR_WREN ((uint8_t)0x02) /*!< Write enable latch */ +#define MX25L512_SR_BLOCKPR ((uint8_t)0x5C) /*!< Block protected against program and erase operations */ +#define MX25L512_SR_PRBOTTOM \ + ((uint8_t)0x20) /*!< Protected memory area defined by BLOCKPR starts from top or bottom \ + */ +#define MX25L512_SR_QUADEN ((uint8_t)0x40) /*!< Quad IO mode enabled if =1 */ +#define MX25L512_SR_SRWREN ((uint8_t)0x80) /*!< Status register write enable/disable */ + +/* Configuration Register */ +#define MX25L512_CR_ODS ((uint8_t)0x07) /*!< Output driver strength */ +#define MX25L512_CR_ODS_30 ((uint8_t)0x07) /*!< Output driver strength 30 ohms (default)*/ +#define MX25L512_CR_ODS_15 ((uint8_t)0x06) /*!< Output driver strength 15 ohms */ +#define MX25L512_CR_ODS_20 ((uint8_t)0x05) /*!< Output driver strength 20 ohms */ +#define MX25L512_CR_ODS_45 ((uint8_t)0x03) /*!< Output driver strength 45 ohms */ +#define MX25L512_CR_ODS_60 ((uint8_t)0x02) /*!< Output driver strength 60 ohms */ +#define MX25L512_CR_ODS_90 ((uint8_t)0x01) /*!< Output driver strength 90 ohms */ +#define MX25L512_CR_TB ((uint8_t)0x08) /*!< Top/Bottom bit used to configure the block protect area */ +#define MX25L512_CR_PBE ((uint8_t)0x10) /*!< Preamble Bit Enable */ +#define MX25L512_CR_4BYTE ((uint8_t)0x20) /*!< 3-bytes or 4-bytes addressing */ +#define MX25L512_CR_NB_DUMMY ((uint8_t)0xC0) /*!< Number of dummy clock cycles */ + +#define MX25L512_FLASH_SIZE 0x4000000 // 512MBits => 64MBytes +#define MX25L512_SECTOR_SIZE 0x10000 // 1024 sectors of 64KBytes +#define MX25L512_SUBSECTOR_SIZE 0x1000 // 16384 subsectors of 4kBytes +#define MX25L512_PAGE_SIZE 0x100 // 262144 pages of 256 bytes + +#define MX25L512_SUBSECTOR_ERASE_MAX_TIME 800 +#define MX25L512_MANUFACTURER_ID ((uint8_t)0xC2) +#define MX25L512_DEVICE_ID_MEM_TYPE ((uint8_t)0x20) +#define MX25L512_DEVICE_ID_MEM_CAPACITY ((uint8_t)0x1A) + +//////////////////////////////// + +#define SPIFFS0_TOTAL_SIZE MX25L512_FLASH_SIZE +#define SPIFFS0_ERASE_BLOCK_SIZE MX25L512_SECTOR_SIZE +#define SPIFFS0_LOGICAL_BLOCK_SIZE (64 * 1024) + +#endif // TARGET_SPIFFS_H diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_adc_config.cpp b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_adc_config.cpp new file mode 100644 index 0000000000..c96f9c7908 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_adc_config.cpp @@ -0,0 +1,25 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { + + // ADC1 + {1, GPIOA, 6, ADC_CHANNEL_IN6}, + {1, GPIOA, 4, ADC_CHANNEL_IN4}, + {1, GPIOC, 2, ADC_CHANNEL_IN12}, + + // ADC3 + {3, GPIOF, 10, ADC_CHANNEL_IN8}, + {3, GPIOF, 8, ADC_CHANNEL_IN6}, + + // these are the internal sources, available only at ADC1 + {1, NULL, 0, ADC_CHANNEL_SENSOR}, + {1, NULL, 0, ADC_CHANNEL_VREFINT}, + {1, NULL, 0, ADC_CHANNEL_VBAT}, +}; + +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_dac_config.cpp b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_dac_config.cpp new file mode 100644 index 0000000000..948967e054 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_dac_config.cpp @@ -0,0 +1,14 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +const NF_PAL_DAC_PORT_PIN_CHANNEL DacPortPinConfig[] = { + + // DAC1, channel 1, GPIO port A, pin 4 + {1, 1, GPIOA, 4}, +}; + +const int DacChannelCount = ARRAYSIZE(DacPortPinConfig); diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_i2c_config.cpp b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_i2c_config.cpp new file mode 100644 index 0000000000..4083ad770d --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_i2c_config.cpp @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// I2C1 // +////////// + +// pin configuration for I2C1 +// port for SCL pin is: GPIOB +// port for SDA pin is: GPIOB +// SCL pin: is GPIOB_8 +// SDA pin: is GPIOB_9 +// GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, GPIOB, GPIOB, 8, 9, 4) diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_pwm_config.cpp b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_pwm_config.cpp new file mode 100644 index 0000000000..73cc6666d3 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_pwm_config.cpp @@ -0,0 +1,9 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_spi_config.cpp b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_spi_config.cpp new file mode 100644 index 0000000000..dc4a4d7863 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_spi_config.cpp @@ -0,0 +1,31 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// SPI2 // +////////// + +// pin configuration for SPI2 +// port for SCK pin is: PA12 (D13) +// port for MISO pin is: PB14 (D12) +// port for MOSI pin is: PB15 (D11) +// AF 5 + +// GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) +SPI_CONFIG_PINS(2, GPIOA, 12, GPIOB, 14, GPIOB, 15, 5) + +////////// +// SPI5 // +////////// + +// pin configuration for SPI5 +// port for SCK pin is: PF7 (D6) +// port for MISO pin is: PF8 (A4) +// port for MOSI pin is: PF9 (A5) + +// GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) +SPI_CONFIG_PINS(5, GPIOF, 7, GPIOF, 8, GPIOF, 9, 5) diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.cpp b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.cpp new file mode 100644 index 0000000000..4baa860216 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.cpp @@ -0,0 +1,153 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include "target_system_io_ports_config.h" +#include + +// /////////// +// // UART1 // +// /////////// + +// // pin configuration for UART1 +// // port for TX pin is: GPIOD +// // port for RX pin is: GPIOC +// // TX pin: is GPIOD_2 +// // RX pin: is GPIOC_12 +// // GPIO alternate pin function is 8 (see "Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate +// function mapping" in STM32F769I datasheet) UART_CONFIG_PINS(1, GPIOD, GPIOC, 2, 12, 8) + +// // initialization for UART1 +// UART_INIT(1) + +// // un-initialization for UART1 +// UART_UNINIT(1) + +// /////////// +// // UART2 // +// /////////// + +// // pin configuration for UART2 +// // port for TX pin is: GPIOD +// // port for RX pin is: GPIOC +// // TX pin: is GPIOD_2 +// // RX pin: is GPIOC_12 +// // GPIO alternate pin function is 8 (see "Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate +// function mapping" in STM32F769I datasheet) UART_CONFIG_PINS(2, GPIOD, GPIOC, 2, 12, 8) + +// // initialization for UART2 +// UART_INIT(2) + +// // un-initialization for UART2 +// UART_UNINIT(2) + +// /////////// +// // UART3 // +// /////////// + +// // pin configuration for UART3 +// // port for TX pin is: GPIOD +// // port for RX pin is: GPIOC +// // TX pin: is GPIOD_2 +// // RX pin: is GPIOC_12 +// // GPIO alternate pin function is 8 (see "Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate +// function mapping" in STM32F769I datasheet) UART_CONFIG_PINS(3, GPIOD, GPIOC, 2, 12, 8) + +// // initialization for UART3 +// UART_INIT(3) + +// // un-initialization for UART3 +// UART_UNINIT(3) + +// /////////// +// // UART4 // +// /////////// + +// // pin configuration for UART4 +// // port for TX pin is: GPIOD +// // port for RX pin is: GPIOC +// // TX pin: is GPIOD_2 +// // RX pin: is GPIOC_12 +// // GPIO alternate pin function is 8 (see "Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate +// function mapping" in STM32F769I datasheet) UART_CONFIG_PINS(4, GPIOD, GPIOC, 2, 12, 8) + +// // initialization for UART4 +// UART_INIT(4) + +// // un-initialization for UART4 +// UART_UNINIT(4) + +/////////// +// UART5 // +/////////// + +// pin configuration for UART5 +// port for TX pin is: GPIOD +// port for RX pin is: GPIOC +// TX pin: is GPIOD_2 +// RX pin: is GPIOC_12 +// GPIO alternate pin function is 8 (see "Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate +// function mapping" in STM32F769I datasheet) +UART_CONFIG_PINS(5, GPIOD, GPIOC, 2, 12, 8) + +// initialization for UART5 +UART_INIT(5) + +// un-initialization for UART5 +UART_UNINIT(5) + +/////////// +// UART6 // +/////////// + +// pin configuration for UART6 +// port for TX pin is: GPIOC +// port for RX pin is: GPIOC +// TX pin: is GPIOC_6 +// RX pin: is GPIOC_7 +// GPIO alternate pin function is 8 (see "Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate +// function mapping" in STM32F769I datasheet) +UART_CONFIG_PINS(6, GPIOC, GPIOC, 6, 7, 8) + +// initialization for UART6 +UART_INIT(6) + +// un-initialization for UART6 +UART_UNINIT(6) + +// /////////// +// // UART7 // +// /////////// + +// // pin configuration for UART7 +// // port for TX pin is: GPIOF +// // port for RX pin is: GPIOF +// // TX pin: is GPIOF_7 +// // RX pin: is GPIOF_6 +// // GPIO alternate pin function is 8 (see "Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate +// function mapping" in STM32F769I datasheet) UART_CONFIG_PINS(7, GPIOF, GPIOF, 7, 6, 8) + +// // initialization for UART7 +// UART_INIT(7) + +// // un-initialization for UART7 +// UART_UNINIT(7) + +// /////////// +// // UART8 // +// /////////// + +// // pin configuration for UART8 +// // port for TX pin is: GPIOC +// // port for RX pin is: GPIOC +// // TX pin: is GPIOC_6 +// // RX pin: is GPIOC_7 +// // GPIO alternate pin function is 8 (see "Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate +// function mapping" in STM32F769I datasheet) UART_CONFIG_PINS(8, GPIOC, GPIOC, 6, 7, 8) + +// // initialization for UART8 +// UART_INIT(8) + +// // un-initialization for UART8 +// UART_UNINIT(8) diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.h new file mode 100644 index 0000000000..5602811301 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.h @@ -0,0 +1,60 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// /////////// +// // UART1 // +// /////////// + +// // enable UART1 +// #define NF_SERIAL_COMM_STM32_UART_USE_UART1 TRUE + +// /////////// +// // UART2 // +// /////////// + +// // enable UART2 +// #define NF_SERIAL_COMM_STM32_UART_USE_UART2 TRUE + +// /////////// +// // UART3 // +// /////////// + +// // enable UART5 +// #define NF_SERIAL_COMM_STM32_UART_USE_UART3 TRUE + +// /////////// +// // UART4 // +// /////////// + +// // enable UART4 +// #define NF_SERIAL_COMM_STM32_UART_USE_UART4 TRUE + +/////////// +// UART5 // +/////////// + +// enable UART5 +#define NF_SERIAL_COMM_STM32_UART_USE_UART5 TRUE + +/////////// +// UART6 // +/////////// + +// enable USART6 +#define NF_SERIAL_COMM_STM32_UART_USE_USART6 TRUE + +// /////////// +// // UART7 // +// /////////// + +// // enable UART7 +// #define NF_SERIAL_COMM_STM32_UART_USE_UART7 TRUE + +// /////////// +// // UART8 // +// /////////// + +// // enable UART8 +// #define NF_SERIAL_COMM_STM32_UART_USE_UART8 TRUE diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_windows_storage_config.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_windows_storage_config.h new file mode 100644 index 0000000000..b19b630a24 --- /dev/null +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_windows_storage_config.h @@ -0,0 +1,10 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// maps the SD Card driver +// #define SD_CARD_DRIVER SDCD2 + +// maps the SD Card detect GPIO definition (in Target_Windows_Storage.c) to board GPIO line (in board.h) +// #define SDCARD_LINE_DETECT LINE_SD_DETECT From 206eb3b5fb7cde4b4db4ab49b8bafc40220fdd1f Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 8 Sep 2023 12:36:26 +0100 Subject: [PATCH 02/44] Fix names --- .../{build-chibios-targets.yml => build-chibios-target.yml} | 0 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json | 6 +++--- targets/ChibiOS/ST_STM32F767ZI_NUCLEO/README.md | 2 +- targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.h | 4 ++-- targets/ChibiOS/ST_STM32F767ZI_NUCLEO/launch.json | 4 ++-- .../ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/README.md | 2 +- ...TM32F769I_DISCOVERY.Adc.cs => STM32F767ZI_NUCLEO.Adc.cs} | 0 .../ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/halconf_nf.h | 6 ------ 8 files changed, 9 insertions(+), 15 deletions(-) rename .github/workflows/{build-chibios-targets.yml => build-chibios-target.yml} (100%) rename targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/{STM32F769I_DISCOVERY.Adc.cs => STM32F767ZI_NUCLEO.Adc.cs} (100%) diff --git a/.github/workflows/build-chibios-targets.yml b/.github/workflows/build-chibios-target.yml similarity index 100% rename from .github/workflows/build-chibios-targets.yml rename to .github/workflows/build-chibios-target.yml diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json index cd9fdabebf..b89059b2df 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json @@ -50,9 +50,9 @@ "buildPresets": [ { "inherits": "base-user", - "name": "ST_STM32F769I_DISCOVERY", - "displayName": "ST_STM32F769I_DISCOVERY", - "configurePreset": "ST_STM32F769I_DISCOVERY" + "name": "ST_STM32F767ZI_NUCLEO", + "displayName": "ST_STM32F767ZI_NUCLEO", + "configurePreset": "ST_STM32F767ZI_NUCLEO" } ] } diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/README.md b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/README.md index 5e6f15e70d..ed6e64b13b 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/README.md +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/README.md @@ -11,7 +11,7 @@ In _halconf.g_ (in both nanoBooter and nanoCLR folders), when compared with a de In _mcuconf.h_ (in both nanoBooter and nanoCLR folders), when compared with a default file available from (https://github.com/ChibiOS/ChibiOS/tree/master/demos/STM32/RT-STM32F769I-DISCOVERY): - STM32_SERIAL_USE_USART1 to TRUE -NOTE: this configuration was successfully tested in an ST_STM32F769I_DISCOVERY board using the Serial port through the onboard ST Link USB connection. +NOTE: this configuration was successfully tested in an ST_STM32F767ZI_NUCLEO board using the Serial port through the onboard ST Link USB connection. ## ADC configurations diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.h index 5a0b99cc14..a1add07ed7 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.h +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.h @@ -33,8 +33,8 @@ /* * Board identifier. */ -#define BOARD_ST_STM32F769I_DISCOVERY -#define BOARD_NAME "STMicroelectronics STM32F769I-Discovery" +#define BOARD_ST_STM32F767ZI_NUCLEO +#define BOARD_NAME "STMicroelectronics STM32F767ZI-NUCLEO" /* * Ethernet PHY type. diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/launch.json b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/launch.json index 1088b16113..5061983178 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/launch.json +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/launch.json @@ -2,7 +2,7 @@ "version": "0.2.0", "configurations": [ { - "name": "ST_STM32F769I_DISCOVERY nanoBooter", + "name": "ST_STM32F767ZI_NUCLEO nanoBooter", "type": "cppdbg", "request": "launch", "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", @@ -53,7 +53,7 @@ } }, { - "name": "ST_STM32F769I_DISCOVERY nanoCLR", + "name": "ST_STM32F767ZI_NUCLEO nanoCLR", "type": "cppdbg", "request": "launch", "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/README.md b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/README.md index ac46ddc7fd..77f9961073 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/README.md +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/README.md @@ -2,4 +2,4 @@ This folder contains helper classes to make developers life easier when coding for this target board. -* [Adc](STM32F769I_DISCOVERY.Adc.cs) +* [Adc](STM32F767ZI_NUCLEO.Adc.cs) diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/STM32F769I_DISCOVERY.Adc.cs b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/STM32F767ZI_NUCLEO.Adc.cs similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/STM32F769I_DISCOVERY.Adc.cs rename to targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/STM32F767ZI_NUCLEO.Adc.cs diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/halconf_nf.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/halconf_nf.h index d320122ed1..b71505cc8c 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/halconf_nf.h +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/halconf_nf.h @@ -11,12 +11,6 @@ #define HAL_NF_USE_STM32_FLASH TRUE #endif -// // Enable graphics low level hardware on STM32F769 - -// #if !defined(HAL_DSI_MODULE_ENABLED) -// #define HAL_DSI_MODULE_ENABLED TRUE -// #endif - // enable USB MSD (from ChibiOS Contrib) #define HAL_USBH_USE_MSD FALSE From 257d91ac013a715d1b0dbc719ea13beb7bb3263b Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 8 Sep 2023 12:40:10 +0100 Subject: [PATCH 03/44] Further fix for build --- targets/ChibiOS/CMakePresets.json | 3 ++- .../ST_STM32F767ZI_NUCLEO/managed_helpers/package.nuspec | 6 +++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/targets/ChibiOS/CMakePresets.json b/targets/ChibiOS/CMakePresets.json index a604509f8a..e39a4fcc1f 100644 --- a/targets/ChibiOS/CMakePresets.json +++ b/targets/ChibiOS/CMakePresets.json @@ -4,6 +4,7 @@ "ORGPAL_PALTHREE/CMakePresets.json", "ST_NUCLEO64_F091RC/CMakePresets.json", "ST_STM32F429I_DISCOVERY/CMakePresets.json", - "ST_STM32F769I_DISCOVERY/CMakePresets.json" + "ST_STM32F769I_DISCOVERY/CMakePresets.json", + "ST_STM32F767ZI_NUCLEO/CMakePresets.json" ] } diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/package.nuspec b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/package.nuspec index 25e7cfd184..2aee85bd8d 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/package.nuspec +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/package.nuspec @@ -1,13 +1,13 @@ - nanoFramework.Targets.ST_STM32F769I_DISCOVERY - nanoFramework.Targets.ST_STM32F769I_DISCOVERY + nanoFramework.Targets.ST_STM32F767ZI_NUCLEO + nanoFramework.Targets.ST_STM32F767ZI_NUCLEO 1.0.0 nanoframework false - Helper classes to use ST_STM32F769I_DISCOVERY target in C# applications. + Helper classes to use ST_STM32F767ZI_NUCLEO target in C# applications. From 7a6b45f7323487f66081ae9c9c73a67beead2c31 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 8 Sep 2023 12:56:09 +0100 Subject: [PATCH 04/44] Align chconf and halconf --- .../ST_STM32F767ZI_NUCLEO/nanoBooter/chconf.h | 241 ++++++++++-------- .../nanoBooter/halconf.h | 19 +- .../ST_STM32F767ZI_NUCLEO/nanoCLR/chconf.h | 241 ++++++++++-------- .../ST_STM32F767ZI_NUCLEO/nanoCLR/halconf.h | 30 +-- 4 files changed, 279 insertions(+), 252 deletions(-) diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/chconf.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/chconf.h index d24abc78a9..1902e34795 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/chconf.h +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/chconf.h @@ -4,6 +4,8 @@ // See LICENSE file in the project root for full license information. // +// clang-format off + /** * @file rt/templates/chconf.h * @brief Configuration file template. @@ -36,7 +38,7 @@ * direct interactions are handled by the OS. */ #if !defined(CH_CFG_SMP_MODE) -#define CH_CFG_SMP_MODE FALSE +#define CH_CFG_SMP_MODE FALSE #endif /** @} */ @@ -53,7 +55,7 @@ * @note Allowed values are 16, 32 or 64 bits. */ #if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 +#define CH_CFG_ST_RESOLUTION 32 #endif /** @@ -62,7 +64,7 @@ * setting also defines the system tick time unit. */ #if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 +#define CH_CFG_ST_FREQUENCY 10000 #endif /** @@ -70,7 +72,7 @@ * @note Allowed values are 16, 32 or 64 bits. */ #if !defined(CH_CFG_INTERVALS_SIZE) -#define CH_CFG_INTERVALS_SIZE 32 +#define CH_CFG_INTERVALS_SIZE 32 #endif /** @@ -78,7 +80,7 @@ * @note Allowed values are 16 or 32 bits. */ #if !defined(CH_CFG_TIME_TYPES_SIZE) -#define CH_CFG_TIME_TYPES_SIZE 32 +#define CH_CFG_TIME_TYPES_SIZE 32 #endif /** @@ -90,7 +92,7 @@ * this value. */ #if !defined(CH_CFG_ST_TIMEDELTA) -#define CH_CFG_ST_TIMEDELTA 2 +#define CH_CFG_ST_TIMEDELTA 2 #endif /** @} */ @@ -115,7 +117,7 @@ * must be set to zero in that case. */ #if !defined(CH_CFG_TIME_QUANTUM) -#define CH_CFG_TIME_QUANTUM 0 +#define CH_CFG_TIME_QUANTUM 0 #endif /** @@ -126,7 +128,20 @@ * infinite loop. */ #if !defined(CH_CFG_NO_IDLE_THREAD) -#define CH_CFG_NO_IDLE_THREAD FALSE +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 #endif /** @} */ @@ -147,7 +162,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED TRUE +#define CH_CFG_OPTIMIZE_SPEED TRUE #endif /** @} */ @@ -167,18 +182,17 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM FALSE +#define CH_CFG_USE_TM TRUE #endif /** * @brief Time Stamps APIs. - * @details If enabled then the time time stamps APIs are included in - * the kernel. + * @details If enabled then the time stamps APIs are included in the kernel. * * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_TIMESTAMP) -#define CH_CFG_USE_TIMESTAMP TRUE +#define CH_CFG_USE_TIMESTAMP TRUE #endif /** @@ -188,7 +202,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_REGISTRY) -#define CH_CFG_USE_REGISTRY TRUE +#define CH_CFG_USE_REGISTRY TRUE #endif /** @@ -199,7 +213,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_WAITEXIT) -#define CH_CFG_USE_WAITEXIT TRUE +#define CH_CFG_USE_WAITEXIT TRUE #endif /** @@ -209,7 +223,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_SEMAPHORES) -#define CH_CFG_USE_SEMAPHORES TRUE +#define CH_CFG_USE_SEMAPHORES TRUE #endif /** @@ -222,7 +236,7 @@ * @note Requires @p CH_CFG_USE_SEMAPHORES. */ #if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE #endif /** @@ -232,7 +246,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_MUTEXES) -#define CH_CFG_USE_MUTEXES FALSE +#define CH_CFG_USE_MUTEXES TRUE #endif /** @@ -244,7 +258,7 @@ * @note Requires @p CH_CFG_USE_MUTEXES. */ #if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE #endif /** @@ -256,7 +270,7 @@ * @note Requires @p CH_CFG_USE_MUTEXES. */ #if !defined(CH_CFG_USE_CONDVARS) -#define CH_CFG_USE_CONDVARS FALSE +#define CH_CFG_USE_CONDVARS TRUE #endif /** @@ -268,7 +282,7 @@ * @note Requires @p CH_CFG_USE_CONDVARS. */ #if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) -#define CH_CFG_USE_CONDVARS_TIMEOUT FALSE +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE #endif /** @@ -278,7 +292,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_EVENTS) -#define CH_CFG_USE_EVENTS TRUE +#define CH_CFG_USE_EVENTS TRUE #endif /** @@ -290,7 +304,7 @@ * @note Requires @p CH_CFG_USE_EVENTS. */ #if !defined(CH_CFG_USE_EVENTS_TIMEOUT) -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE #endif /** @@ -301,7 +315,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_MESSAGES) -#define CH_CFG_USE_MESSAGES FALSE +#define CH_CFG_USE_MESSAGES TRUE #endif /** @@ -314,7 +328,7 @@ * @note Requires @p CH_CFG_USE_MESSAGES. */ #if !defined(CH_CFG_USE_MESSAGES_PRIORITY) -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE #endif /** @@ -327,7 +341,7 @@ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. */ #if !defined(CH_CFG_USE_DYNAMIC) -#define CH_CFG_USE_DYNAMIC TRUE +#define CH_CFG_USE_DYNAMIC TRUE #endif /** @} */ @@ -348,7 +362,17 @@ * @note Requires @p CH_CFG_USE_SEMAPHORES. */ #if !defined(CH_CFG_USE_MAILBOXES) -#define CH_CFG_USE_MAILBOXES TRUE +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE #endif /** @@ -359,7 +383,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_MEMCORE) -#define CH_CFG_USE_MEMCORE TRUE +#define CH_CFG_USE_MEMCORE TRUE #endif /** @@ -374,7 +398,7 @@ * @note Requires @p CH_CFG_USE_MEMCORE. */ #if !defined(CH_CFG_MEMCORE_SIZE) -#define CH_CFG_MEMCORE_SIZE 0 +#define CH_CFG_MEMCORE_SIZE 0 #endif /** @@ -388,7 +412,7 @@ * @note Mutexes are recommended. */ #if !defined(CH_CFG_USE_HEAP) -#define CH_CFG_USE_HEAP TRUE +#define CH_CFG_USE_HEAP TRUE #endif /** @@ -399,7 +423,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_MEMPOOLS) -#define CH_CFG_USE_MEMPOOLS TRUE +#define CH_CFG_USE_MEMPOOLS TRUE #endif /** @@ -410,7 +434,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_OBJ_FIFOS) -#define CH_CFG_USE_OBJ_FIFOS TRUE +#define CH_CFG_USE_OBJ_FIFOS TRUE #endif /** @@ -421,7 +445,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_PIPES) -#define CH_CFG_USE_PIPES TRUE +#define CH_CFG_USE_PIPES TRUE #endif /** @@ -432,7 +456,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_OBJ_CACHES) -#define CH_CFG_USE_OBJ_CACHES FALSE +#define CH_CFG_USE_OBJ_CACHES TRUE #endif /** @@ -443,7 +467,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_DELEGATES) -#define CH_CFG_USE_DELEGATES FALSE +#define CH_CFG_USE_DELEGATES TRUE #endif /** @@ -454,7 +478,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_JOBS) -#define CH_CFG_USE_JOBS FALSE +#define CH_CFG_USE_JOBS TRUE #endif /** @} */ @@ -474,7 +498,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_CFG_USE_FACTORY) -#define CH_CFG_USE_FACTORY FALSE +#define CH_CFG_USE_FACTORY TRUE #endif /** @@ -483,49 +507,49 @@ * pointer but this could have unintended side effects. */ #if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) -#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 #endif /** * @brief Enables the registry of generic objects. */ #if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) -#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE #endif /** * @brief Enables factory for generic buffers. */ #if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) -#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE #endif /** * @brief Enables factory for semaphores. */ #if !defined(CH_CFG_FACTORY_SEMAPHORES) -#define CH_CFG_FACTORY_SEMAPHORES TRUE +#define CH_CFG_FACTORY_SEMAPHORES TRUE #endif /** * @brief Enables factory for mailboxes. */ #if !defined(CH_CFG_FACTORY_MAILBOXES) -#define CH_CFG_FACTORY_MAILBOXES TRUE +#define CH_CFG_FACTORY_MAILBOXES TRUE #endif /** * @brief Enables factory for objects FIFOs. */ #if !defined(CH_CFG_FACTORY_OBJ_FIFOS) -#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE #endif /** * @brief Enables factory for Pipes. */ #if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) -#define CH_CFG_FACTORY_PIPES TRUE +#define CH_CFG_FACTORY_PIPES TRUE #endif /** @} */ @@ -543,7 +567,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_STATISTICS) -#define CH_DBG_STATISTICS FALSE +#define CH_DBG_STATISTICS FALSE #endif /** @@ -554,7 +578,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#define CH_DBG_SYSTEM_STATE_CHECK FALSE #endif /** @@ -565,7 +589,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS FALSE +#define CH_DBG_ENABLE_CHECKS FALSE #endif /** @@ -577,7 +601,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS FALSE +#define CH_DBG_ENABLE_ASSERTS FALSE #endif /** @@ -587,7 +611,7 @@ * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. */ #if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED #endif /** @@ -596,7 +620,7 @@ * different from @p CH_DBG_TRACE_MASK_DISABLED. */ #if !defined(CH_DBG_TRACE_BUFFER_SIZE) -#define CH_DBG_TRACE_BUFFER_SIZE 128 +#define CH_DBG_TRACE_BUFFER_SIZE 128 #endif /** @@ -610,7 +634,7 @@ * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK FALSE +#define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** @@ -622,7 +646,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS FALSE +#define CH_DBG_FILL_THREADS FALSE #endif /** @@ -635,7 +659,7 @@ * tickless mode. */ #if !defined(CH_DBG_THREADS_PROFILING) -#define CH_DBG_THREADS_PROFILING FALSE +#define CH_DBG_THREADS_PROFILING FALSE #endif /** @} */ @@ -651,39 +675,40 @@ * @brief System structure extension. * @details User fields added to the end of the @p ch_system_t structure. */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS /* Add system custom fields here.*/ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ /** * @brief System initialization hook. * @details User initialization code added to the @p chSysInit() function * just before interrupts are enabled globally. */ -#define CH_CFG_SYSTEM_INIT_HOOK() \ - { \ - /* Add system initialization code here.*/ \ - } +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} /** * @brief OS instance structure extension. * @details User fields added to the end of the @p os_instance_t structure. */ -#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS /* Add OS instance custom fields here.*/ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ /** * @brief OS instance initialization hook. * * @param[in] oip pointer to the @p os_instance_t structure */ -#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) \ - { \ - /* Add OS instance initialization code here.*/ \ - } +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} /** * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p thread_t structure. */ -#define CH_CFG_THREAD_EXTRA_FIELDS /* Add threads custom fields here.*/ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ /** * @brief Threads initialization hook. @@ -694,10 +719,9 @@ * * @param[in] tp pointer to the @p thread_t structure */ -#define CH_CFG_THREAD_INIT_HOOK(tp) \ - { \ - /* Add threads initialization code here.*/ \ - } +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} /** * @brief Threads finalization hook. @@ -705,10 +729,9 @@ * * @param[in] tp pointer to the @p thread_t structure */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) \ - { \ - /* Add threads finalization code here.*/ \ - } +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} /** * @brief Context switch hook. @@ -717,26 +740,23 @@ * @param[in] ntp thread being switched in * @param[in] otp thread being switched out */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) \ - { \ - /* Context switch code here.*/ \ - } +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} /** * @brief ISR enter hook. */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() \ - { \ - /* IRQ prologue code here.*/ \ - } +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} /** * @brief ISR exit hook. */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() \ - { \ - /* IRQ epilogue code here.*/ \ - } +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} /** * @brief Idle thread enter hook. @@ -744,10 +764,9 @@ * should be invoked from here. * @note This macro can be used to activate a power saving mode. */ -#define CH_CFG_IDLE_ENTER_HOOK() \ - { \ - /* Idle-enter code here.*/ \ - } +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} /** * @brief Idle thread leave hook. @@ -755,58 +774,52 @@ * should be invoked from here. * @note This macro can be used to deactivate a power saving mode. */ -#define CH_CFG_IDLE_LEAVE_HOOK() \ - { \ - /* Idle-leave code here.*/ \ - } +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} /** * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ -#define CH_CFG_IDLE_LOOP_HOOK() \ - { \ - /* Idle loop code here.*/ \ - } +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} /** * @brief System tick event hook. * @details This hook is invoked in the system tick handler immediately * after processing the virtual timers queue. */ -#define CH_CFG_SYSTEM_TICK_HOOK() \ - { \ - /* System tick event code here.*/ \ - } +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} /** * @brief System halt hook. * @details This hook is invoked in case to a system halting error before * the system is halted. */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) \ - { \ - /* System halt code here.*/ \ - } +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} /** * @brief Trace hook. * @details This hook is invoked each time a new record is written in the * trace buffer. */ -#define CH_CFG_TRACE_HOOK(tep) \ - { \ - /* Trace code here.*/ \ - } +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} /** * @brief Runtime Faults Collection Unit hook. * @details This hook is invoked each time new faults are collected and stored. */ -#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) \ - { \ - /* Faults handling code here.*/ \ - } +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} /** @} */ @@ -814,6 +827,8 @@ /* Port-specific settings (override port settings defaulted in chcore.h). */ /*===========================================================================*/ -#endif /* CHCONF_H */ +#endif /* CHCONF_H */ /** @} */ + +// clang-format on diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/halconf.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/halconf.h index 22b723bec1..410839a60b 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/halconf.h +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/halconf.h @@ -327,15 +327,18 @@ /*===========================================================================*/ /** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE #endif /*===========================================================================*/ diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/chconf.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/chconf.h index 2cbe763aa7..1902e34795 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/chconf.h +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/chconf.h @@ -4,6 +4,8 @@ // See LICENSE file in the project root for full license information. // +// clang-format off + /** * @file rt/templates/chconf.h * @brief Configuration file template. @@ -36,7 +38,7 @@ * direct interactions are handled by the OS. */ #if !defined(CH_CFG_SMP_MODE) -#define CH_CFG_SMP_MODE FALSE +#define CH_CFG_SMP_MODE FALSE #endif /** @} */ @@ -53,7 +55,7 @@ * @note Allowed values are 16, 32 or 64 bits. */ #if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 +#define CH_CFG_ST_RESOLUTION 32 #endif /** @@ -62,7 +64,7 @@ * setting also defines the system tick time unit. */ #if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 +#define CH_CFG_ST_FREQUENCY 10000 #endif /** @@ -70,7 +72,7 @@ * @note Allowed values are 16, 32 or 64 bits. */ #if !defined(CH_CFG_INTERVALS_SIZE) -#define CH_CFG_INTERVALS_SIZE 32 +#define CH_CFG_INTERVALS_SIZE 32 #endif /** @@ -78,7 +80,7 @@ * @note Allowed values are 16 or 32 bits. */ #if !defined(CH_CFG_TIME_TYPES_SIZE) -#define CH_CFG_TIME_TYPES_SIZE 32 +#define CH_CFG_TIME_TYPES_SIZE 32 #endif /** @@ -90,7 +92,7 @@ * this value. */ #if !defined(CH_CFG_ST_TIMEDELTA) -#define CH_CFG_ST_TIMEDELTA 2 +#define CH_CFG_ST_TIMEDELTA 2 #endif /** @} */ @@ -115,7 +117,7 @@ * must be set to zero in that case. */ #if !defined(CH_CFG_TIME_QUANTUM) -#define CH_CFG_TIME_QUANTUM 0 +#define CH_CFG_TIME_QUANTUM 0 #endif /** @@ -126,7 +128,20 @@ * infinite loop. */ #if !defined(CH_CFG_NO_IDLE_THREAD) -#define CH_CFG_NO_IDLE_THREAD FALSE +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 #endif /** @} */ @@ -147,7 +162,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED TRUE +#define CH_CFG_OPTIMIZE_SPEED TRUE #endif /** @} */ @@ -167,18 +182,17 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM FALSE +#define CH_CFG_USE_TM TRUE #endif /** * @brief Time Stamps APIs. - * @details If enabled then the time time stamps APIs are included in - * the kernel. + * @details If enabled then the time stamps APIs are included in the kernel. * * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_TIMESTAMP) -#define CH_CFG_USE_TIMESTAMP TRUE +#define CH_CFG_USE_TIMESTAMP TRUE #endif /** @@ -188,7 +202,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_REGISTRY) -#define CH_CFG_USE_REGISTRY TRUE +#define CH_CFG_USE_REGISTRY TRUE #endif /** @@ -199,7 +213,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_WAITEXIT) -#define CH_CFG_USE_WAITEXIT TRUE +#define CH_CFG_USE_WAITEXIT TRUE #endif /** @@ -209,7 +223,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_SEMAPHORES) -#define CH_CFG_USE_SEMAPHORES TRUE +#define CH_CFG_USE_SEMAPHORES TRUE #endif /** @@ -222,7 +236,7 @@ * @note Requires @p CH_CFG_USE_SEMAPHORES. */ #if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE #endif /** @@ -232,7 +246,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_MUTEXES) -#define CH_CFG_USE_MUTEXES TRUE +#define CH_CFG_USE_MUTEXES TRUE #endif /** @@ -244,7 +258,7 @@ * @note Requires @p CH_CFG_USE_MUTEXES. */ #if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE #endif /** @@ -256,7 +270,7 @@ * @note Requires @p CH_CFG_USE_MUTEXES. */ #if !defined(CH_CFG_USE_CONDVARS) -#define CH_CFG_USE_CONDVARS TRUE +#define CH_CFG_USE_CONDVARS TRUE #endif /** @@ -268,7 +282,7 @@ * @note Requires @p CH_CFG_USE_CONDVARS. */ #if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE #endif /** @@ -278,7 +292,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_EVENTS) -#define CH_CFG_USE_EVENTS TRUE +#define CH_CFG_USE_EVENTS TRUE #endif /** @@ -290,7 +304,7 @@ * @note Requires @p CH_CFG_USE_EVENTS. */ #if !defined(CH_CFG_USE_EVENTS_TIMEOUT) -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE #endif /** @@ -301,7 +315,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_MESSAGES) -#define CH_CFG_USE_MESSAGES TRUE +#define CH_CFG_USE_MESSAGES TRUE #endif /** @@ -314,7 +328,7 @@ * @note Requires @p CH_CFG_USE_MESSAGES. */ #if !defined(CH_CFG_USE_MESSAGES_PRIORITY) -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE #endif /** @@ -327,7 +341,7 @@ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. */ #if !defined(CH_CFG_USE_DYNAMIC) -#define CH_CFG_USE_DYNAMIC TRUE +#define CH_CFG_USE_DYNAMIC TRUE #endif /** @} */ @@ -348,7 +362,17 @@ * @note Requires @p CH_CFG_USE_SEMAPHORES. */ #if !defined(CH_CFG_USE_MAILBOXES) -#define CH_CFG_USE_MAILBOXES TRUE +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE #endif /** @@ -359,7 +383,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_MEMCORE) -#define CH_CFG_USE_MEMCORE TRUE +#define CH_CFG_USE_MEMCORE TRUE #endif /** @@ -374,7 +398,7 @@ * @note Requires @p CH_CFG_USE_MEMCORE. */ #if !defined(CH_CFG_MEMCORE_SIZE) -#define CH_CFG_MEMCORE_SIZE 0 +#define CH_CFG_MEMCORE_SIZE 0 #endif /** @@ -388,7 +412,7 @@ * @note Mutexes are recommended. */ #if !defined(CH_CFG_USE_HEAP) -#define CH_CFG_USE_HEAP TRUE +#define CH_CFG_USE_HEAP TRUE #endif /** @@ -399,7 +423,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_MEMPOOLS) -#define CH_CFG_USE_MEMPOOLS TRUE +#define CH_CFG_USE_MEMPOOLS TRUE #endif /** @@ -410,7 +434,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_OBJ_FIFOS) -#define CH_CFG_USE_OBJ_FIFOS TRUE +#define CH_CFG_USE_OBJ_FIFOS TRUE #endif /** @@ -421,7 +445,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_PIPES) -#define CH_CFG_USE_PIPES TRUE +#define CH_CFG_USE_PIPES TRUE #endif /** @@ -432,7 +456,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_OBJ_CACHES) -#define CH_CFG_USE_OBJ_CACHES FALSE +#define CH_CFG_USE_OBJ_CACHES TRUE #endif /** @@ -443,7 +467,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_DELEGATES) -#define CH_CFG_USE_DELEGATES FALSE +#define CH_CFG_USE_DELEGATES TRUE #endif /** @@ -454,7 +478,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_JOBS) -#define CH_CFG_USE_JOBS FALSE +#define CH_CFG_USE_JOBS TRUE #endif /** @} */ @@ -474,7 +498,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_CFG_USE_FACTORY) -#define CH_CFG_USE_FACTORY FALSE +#define CH_CFG_USE_FACTORY TRUE #endif /** @@ -483,49 +507,49 @@ * pointer but this could have unintended side effects. */ #if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) -#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 #endif /** * @brief Enables the registry of generic objects. */ #if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) -#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE #endif /** * @brief Enables factory for generic buffers. */ #if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) -#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE #endif /** * @brief Enables factory for semaphores. */ #if !defined(CH_CFG_FACTORY_SEMAPHORES) -#define CH_CFG_FACTORY_SEMAPHORES TRUE +#define CH_CFG_FACTORY_SEMAPHORES TRUE #endif /** * @brief Enables factory for mailboxes. */ #if !defined(CH_CFG_FACTORY_MAILBOXES) -#define CH_CFG_FACTORY_MAILBOXES TRUE +#define CH_CFG_FACTORY_MAILBOXES TRUE #endif /** * @brief Enables factory for objects FIFOs. */ #if !defined(CH_CFG_FACTORY_OBJ_FIFOS) -#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE #endif /** * @brief Enables factory for Pipes. */ #if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) -#define CH_CFG_FACTORY_PIPES TRUE +#define CH_CFG_FACTORY_PIPES TRUE #endif /** @} */ @@ -543,7 +567,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_STATISTICS) -#define CH_DBG_STATISTICS FALSE +#define CH_DBG_STATISTICS FALSE #endif /** @@ -554,7 +578,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#define CH_DBG_SYSTEM_STATE_CHECK FALSE #endif /** @@ -565,7 +589,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS FALSE +#define CH_DBG_ENABLE_CHECKS FALSE #endif /** @@ -577,7 +601,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS FALSE +#define CH_DBG_ENABLE_ASSERTS FALSE #endif /** @@ -587,7 +611,7 @@ * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. */ #if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED #endif /** @@ -596,7 +620,7 @@ * different from @p CH_DBG_TRACE_MASK_DISABLED. */ #if !defined(CH_DBG_TRACE_BUFFER_SIZE) -#define CH_DBG_TRACE_BUFFER_SIZE 128 +#define CH_DBG_TRACE_BUFFER_SIZE 128 #endif /** @@ -610,7 +634,7 @@ * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK FALSE +#define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** @@ -622,7 +646,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS FALSE +#define CH_DBG_FILL_THREADS FALSE #endif /** @@ -635,7 +659,7 @@ * tickless mode. */ #if !defined(CH_DBG_THREADS_PROFILING) -#define CH_DBG_THREADS_PROFILING FALSE +#define CH_DBG_THREADS_PROFILING FALSE #endif /** @} */ @@ -651,39 +675,40 @@ * @brief System structure extension. * @details User fields added to the end of the @p ch_system_t structure. */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS /* Add system custom fields here.*/ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ /** * @brief System initialization hook. * @details User initialization code added to the @p chSysInit() function * just before interrupts are enabled globally. */ -#define CH_CFG_SYSTEM_INIT_HOOK() \ - { \ - /* Add system initialization code here.*/ \ - } +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} /** * @brief OS instance structure extension. * @details User fields added to the end of the @p os_instance_t structure. */ -#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS /* Add OS instance custom fields here.*/ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ /** * @brief OS instance initialization hook. * * @param[in] oip pointer to the @p os_instance_t structure */ -#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) \ - { \ - /* Add OS instance initialization code here.*/ \ - } +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} /** * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p thread_t structure. */ -#define CH_CFG_THREAD_EXTRA_FIELDS /* Add threads custom fields here.*/ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ /** * @brief Threads initialization hook. @@ -694,10 +719,9 @@ * * @param[in] tp pointer to the @p thread_t structure */ -#define CH_CFG_THREAD_INIT_HOOK(tp) \ - { \ - /* Add threads initialization code here.*/ \ - } +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} /** * @brief Threads finalization hook. @@ -705,10 +729,9 @@ * * @param[in] tp pointer to the @p thread_t structure */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) \ - { \ - /* Add threads finalization code here.*/ \ - } +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} /** * @brief Context switch hook. @@ -717,26 +740,23 @@ * @param[in] ntp thread being switched in * @param[in] otp thread being switched out */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) \ - { \ - /* Context switch code here.*/ \ - } +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} /** * @brief ISR enter hook. */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() \ - { \ - /* IRQ prologue code here.*/ \ - } +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} /** * @brief ISR exit hook. */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() \ - { \ - /* IRQ epilogue code here.*/ \ - } +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} /** * @brief Idle thread enter hook. @@ -744,10 +764,9 @@ * should be invoked from here. * @note This macro can be used to activate a power saving mode. */ -#define CH_CFG_IDLE_ENTER_HOOK() \ - { \ - /* Idle-enter code here.*/ \ - } +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} /** * @brief Idle thread leave hook. @@ -755,58 +774,52 @@ * should be invoked from here. * @note This macro can be used to deactivate a power saving mode. */ -#define CH_CFG_IDLE_LEAVE_HOOK() \ - { \ - /* Idle-leave code here.*/ \ - } +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} /** * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ -#define CH_CFG_IDLE_LOOP_HOOK() \ - { \ - /* Idle loop code here.*/ \ - } +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} /** * @brief System tick event hook. * @details This hook is invoked in the system tick handler immediately * after processing the virtual timers queue. */ -#define CH_CFG_SYSTEM_TICK_HOOK() \ - { \ - /* System tick event code here.*/ \ - } +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} /** * @brief System halt hook. * @details This hook is invoked in case to a system halting error before * the system is halted. */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) \ - { \ - /* System halt code here.*/ \ - } +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} /** * @brief Trace hook. * @details This hook is invoked each time a new record is written in the * trace buffer. */ -#define CH_CFG_TRACE_HOOK(tep) \ - { \ - /* Trace code here.*/ \ - } +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} /** * @brief Runtime Faults Collection Unit hook. * @details This hook is invoked each time new faults are collected and stored. */ -#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) \ - { \ - /* Faults handling code here.*/ \ - } +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} /** @} */ @@ -814,6 +827,8 @@ /* Port-specific settings (override port settings defaulted in chcore.h). */ /*===========================================================================*/ -#endif /* CHCONF_H */ +#endif /* CHCONF_H */ /** @} */ + +// clang-format on diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/halconf.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/halconf.h index 5df08fc9ba..ede93b01bf 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/halconf.h +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/halconf.h @@ -33,15 +33,6 @@ #define HAL_USE_PAL TRUE #endif -//Not in default template, added manually -#if !defined(FATFS_HAL_DEVICE) || defined(__DOXYGEN__) -//this board requires SDCD2 not SDCD1 -#define FATFS_HAL_DEVICE SDCD2 -#endif -//////// - -//#define STM32_SDC_SDMMC_50MHZ TRUE - /** * @brief Enables the ADC subsystem. */ @@ -90,7 +81,7 @@ /** * @brief Enables the I2C subsystem. */ -// this option is set at target_platform.h (from config file) + // this option is set at target_platform.h (from config file) // #if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) // #define HAL_USE_I2C FALSE // #endif @@ -348,15 +339,18 @@ /*===========================================================================*/ /** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE #endif /*===========================================================================*/ From 5be0dddc3376e8b036de7d40501f97c398256681 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 8 Sep 2023 13:03:40 +0100 Subject: [PATCH 05/44] Fix board definition from https://github.com/ArduPilot/ChibiOS.svn/blob/stable_21.11.x/os/hal/boards/ST_NUCLEO144_F767ZI/board.h --- targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.c | 14 +- targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.h | 2650 +++++++++-------- .../nanoBooter/mcuconf.h | 6 +- .../ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h | 6 +- 4 files changed, 1389 insertions(+), 1287 deletions(-) diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.c b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.c index d08d420349..4041ccf612 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.c +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.c @@ -1,5 +1,5 @@ /* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -220,8 +220,8 @@ void __early_init(void) { bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { (void)sdcp; - - return !palReadLine(LINE_SD_DETECT); + /* CHTODO: Fill the implementation.*/ + return true; } /** @@ -230,7 +230,7 @@ bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { bool sdc_lld_is_write_protected(SDCDriver *sdcp) { (void)sdcp; - /* TODO: Fill the implementation.*/ + /* CHTODO: Fill the implementation.*/ return false; } #endif /* HAL_USE_SDC */ @@ -242,7 +242,7 @@ bool sdc_lld_is_write_protected(SDCDriver *sdcp) { bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { (void)mmcp; - /* TODO: Fill the implementation.*/ + /* CHTODO: Fill the implementation.*/ return true; } @@ -252,14 +252,14 @@ bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { bool mmc_lld_is_write_protected(MMCDriver *mmcp) { (void)mmcp; - /* TODO: Fill the implementation.*/ + /* CHTODO: Fill the implementation.*/ return false; } #endif /** * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. + * @note You can add your board-specific code here. */ void boardInit(void) { diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.h index a1add07ed7..e46cad28f2 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.h +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.h @@ -1,5 +1,5 @@ /* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -27,14 +27,14 @@ /*===========================================================================*/ /* - * Setup for STMicroelectronics STM32F769I-Discovery board. + * Setup for STMicroelectronics STM32 Nucleo144-F767ZI board. */ /* * Board identifier. */ -#define BOARD_ST_STM32F767ZI_NUCLEO -#define BOARD_NAME "STMicroelectronics STM32F767ZI-NUCLEO" +#define BOARD_ST_NUCLEO144_F767ZI +#define BOARD_NAME "STMicroelectronics STM32 Nucleo144-F767ZI" /* * Ethernet PHY type. @@ -42,11 +42,6 @@ #define BOARD_PHY_ID MII_LAN8742A_ID #define BOARD_PHY_RMII -/* - * The board has an ULPI USB PHY. - */ -#define BOARD_OTG2_USES_ULPI - /* * Board oscillators-related settings. */ @@ -57,7 +52,7 @@ #define STM32_LSEDRV (3U << 3U) #if !defined(STM32_HSECLK) -#define STM32_HSECLK 25000000U +#define STM32_HSECLK 8000000U #endif #define STM32_HSE_BYPASS @@ -71,184 +66,257 @@ /* * MCU type as defined in the ST header. */ -#define STM32F769xx +#define STM32F767xx /* * IO pins assignments. */ -#define GPIOA_BUTTON_USER 0U +#define GPIOA_ZIO_D32 0U +#define GPIOA_TIM2_CH1 0U #define GPIOA_RMII_REF_CLK 1U #define GPIOA_RMII_MDIO 2U -#define GPIOA_ULPI_D0 3U -#define GPIOA_ARD_A1 4U -#define GPIOA_ULPI_CK 5U -#define GPIOA_ARD_A0 6U -#define GPIOA_RMII_CRS_DV 7U -#define GPIOA_CEC_CLK 8U -#define GPIOA_VCP_TX 9U -#define GPIOA_VCP_RX 10U -#define GPIOA_ARD_D10 11U -#define GPIOA_ARD_D13 12U +#define GPIOA_ARD_A0 3U +#define GPIOA_ADC123_IN3 3U +#define GPIOA_ZIO_D24 4U +#define GPIOA_SPI3_NSS 4U +#define GPIOA_ARD_D13 5U +#define GPIOA_SPI1_SCK 5U +#define GPIOA_ARD_D12 6U +#define GPIOA_SPI1_MISO 6U +#define GPIOA_ARD_D11 7U +#define GPIOA_SPI1_MOSI 7U +#define GPIOA_ZIO_D71 7U +#define GPIOA_RMII_RX_DV 7U +#define GPIOA_USB_SOF 8U +#define GPIOA_USB_VBUS 9U +#define GPIOA_USB_ID 10U +#define GPIOA_USB_DM 11U +#define GPIOA_USB_DP 12U #define GPIOA_SWDIO 13U #define GPIOA_SWCLK 14U -#define GPIOA_CEC 15U +#define GPIOA_ZIO_D20 15U +#define GPIOA_I2S3_WS 15U -#define GPIOB_ULPI_D1 0U -#define GPIOB_ULPI_D2 1U +#define GPIOB_ZIO_D33 0U +#define GPIOB_TIM3_CH3 0U +#define GPIOB_LED1 0U +#define GPIOB_ZIO_A6 1U +#define GPIOB_ADC12_IN9 1U +#define GPIOB_ZIO_D27 2U #define GPIOB_QSPI_CLK 2U -#define GPIOB_SD_D2 3U -#define GPIOB_SD_D3 4U -#define GPIOB_ULPI_D7 5U -#define GPIOB_QUADSPI_BK1_NCS 6U -#define GPIOB_AUDIO_SDA 7U -#define GPIOB_LCD_SDA 7U +#define GPIOB_ZIO_D23 3U +#define GPIOB_I2S3_CK 3U +#define GPIOB_ZIO_D25 4U +#define GPIOB_SPI3_MISO 4U +#define GPIOB_ZIO_D22 5U +#define GPIOB_I2S3_SD 5U +#define GPIOB_ZIO_D26 6U +#define GPIOB_QSPI_BK1_NCS 6U +#define GPIOB_LED2 7U #define GPIOB_ARD_D15 8U +#define GPIOB_I2C1_SCL 8U #define GPIOB_ARD_D14 9U -#define GPIOB_ULPI_D3 10U -#define GPIOB_ULPI_D4 11U -#define GPIOB_ULPI_D5 12U -#define GPIOB_ULPI_D6 13U -#define GPIOB_ARD_D12 14U -#define GPIOB_ARD_D11 15U +#define GPIOB_I2C1_SDA 9U +#define GPIOB_ZIO_D36 10U +#define GPIOB_TIM2_CH3 10U +#define GPIOB_ZIO_D35 11U +#define GPIOB_TIM2_CH4 11U +#define GPIOB_ZIO_D19 12U +#define GPIOB_I2S2_WS 12U +#define GPIOB_ZIO_D18 13U +#define GPIOB_I2S2_CK 13U +#define GPIOB_RMII_TXD1 13U +#define GPIOB_LED3 14U +#define GPIOB_ZIO_D17 15U +#define GPIOB_I2S2_SD 15U -#define GPIOC_ULPI_STP 0U +#define GPIOC_ARD_A1 0U +#define GPIOC_ADC123_IN10 0U #define GPIOC_RMII_MDC 1U -#define GPIOC_ARD_A2 2U -#define GPIOC_DFSDM_DATIN1 3U +#define GPIOC_ZIO_A7 2U +#define GPIOC_ADC123_IN12 2U +#define GPIOC_ARD_A2 3U +#define GPIOC_ADC123_IN13 3U #define GPIOC_RMII_RXD0 4U #define GPIOC_RMII_RXD1 5U -#define GPIOC_ARD_D1 6U -#define GPIOC_ARD_D0 7U -#define GPIOC_ARD_D5 8U -#define GPIOB_I2C1_SCL 8U -#define GPIOC_QSPI_D0 9U -#define GPIOB_I2C1_SDA 9U -#define GPIOC_QSPI_D1 10U -#define GPIOC_DFSDM_DATIN5 11U -#define GPIOC_WIFI_RX 12U -#define GPIOC_PIN13 13U +#define GPIOC_ZIO_D16 6U +#define GPIOC_I2S2_MCK 6U +#define GPIOC_ZIO_D21 7U +#define GPIOC_I2S3_MCK 7U +#define GPIOC_ZIO_D43 8U +#define GPIOC_SDMMC_D0 8U +#define GPIOC_ZIO_D44 9U +#define GPIOC_SDMMC_D1 9U +#define GPIOC_ZIO_D45 10U +#define GPIOC_SDMMC_D2 10U +#define GPIOC_ZIO_D46 11U +#define GPIOC_SDMMC_D3 11U +#define GPIOC_ZIO_D47 12U +#define GPIOC_SDMMC_CK 12U +#define GPIOC_BUTTON 13U #define GPIOC_OSC32_IN 14U #define GPIOC_OSC32_OUT 15U -#define GPIOD_FMC_D2 0U -#define GPIOD_FMC_D3 1U -#define GPIOD_WIFI_TX 2U -#define GPIOD_DFSDM_CKOUT 3U -#define GPIOD_OTG_HS_OVER_CURRENT 4U -#define GPIOD_RMII_RXER 5U -#define GPIOD_SD_CLK 6U -#define GPIOD_SD_CMD 7U -#define GPIOD_FMC_D13 8U -#define GPIOD_FMC_D14 9U -#define GPIOD_FMC_D15 10U -#define GPIOD_SPDIF_I2S 11U -#define GPIOD_AUDIO_SCL 12U -#define GPIOD_LCD_SCL 12U -#define GPIOD_QSPI_D3 13U -#define GPIOD_FMC_D0 14U -#define GPIOD_FMC_D1 15U +#define GPIOD_ZIO_D67 0U +#define GPIOD_CAN1_RX 0U +#define GPIOD_ZIO_D66 1U +#define GPIOD_CAN1_TX 1U +#define GPIOD_ZIO_D48 2U +#define GPIOD_SDMMC_CMD 2U +#define GPIOD_ZIO_D55 3U +#define GPIOD_USART2_CTS 3U +#define GPIOD_ZIO_D54 4U +#define GPIOD_USART2_RTS 4U +#define GPIOD_ZIO_D53 5U +#define GPIOD_USART2_TX 5U +#define GPIOD_ZIO_D52 6U +#define GPIOD_USART2_RX 6U +#define GPIOD_ZIO_D51 7U +#define GPIOD_USART2_SCLK 7U +#define GPIOD_USART3_RX 8U +#define GPIOD_STLK_RX 8U +#define GPIOD_USART3_TX 9U +#define GPIOD_STLK_TX 9U +#define GPIOD_PIN10 10U +#define GPIOD_ZIO_D30 11U +#define GPIOD_QSPI_BK1_IO0 11U +#define GPIOD_ZIO_D29 12U +#define GPIOD_QSPI_BK1_IO1 12U +#define GPIOD_ZIO_D28 13U +#define GPIOD_QSPI_BK1_IO3 13U +#define GPIOD_ARD_D10 14U +#define GPIOD_SPI1_NSS 14U +#define GPIOD_ARD_D9 15U +#define GPIOD_TIM4_CH4 15U -#define GPIOE_FMC_NBL0 0U -#define GPIOE_FMC_NBL1 1U -#define GPIOE_QSPI_D2 2U -#define GPIOE_SAI1_SDB 3U -#define GPIOE_SAI1_FSA 4U -#define GPIOE_SAI1_SCKA 5U -#define GPIOE_SAI1_SDA 6U -#define GPIOE_FMC_D4 7U -#define GPIOE_FMC_D5 8U -#define GPIOE_FMC_D6 9U -#define GPIOE_FMC_D7 10U -#define GPIOE_FMC_D8 11U -#define GPIOE_FMC_D9 12U -#define GPIOE_FMC_D10 13U -#define GPIOE_FMC_11 14U -#define GPIOE_FMC_D12 15U +#define GPIOE_ZIO_D34 0U +#define GPIOE_TIM4_ETR 0U +#define GPIOE_PIN1 1U +#define GPIOE_ZIO_D31 2U +#define GPIOE_ZIO_D56 2U +#define GPIOE_SAI1_MCLK_A 2U +#define GPIOE_ZIO_D60 3U +#define GPIOE_SAI1_SD_B 3U +#define GPIOE_ZIO_D57 4U +#define GPIOE_SAI1_FS_A 4U +#define GPIOE_ZIO_D58 5U +#define GPIOE_SAI1_SCK_A 5U +#define GPIOE_ZIO_D59 6U +#define GPIOE_SAI1_SD_A 6U +#define GPIOE_ZIO_D41 7U +#define GPIOE_TIM1_ETR 7U +#define GPIOE_ZIO_D42 8U +#define GPIOE_TIM1_CH1N 8U +#define GPIOE_ARD_D6 9U +#define GPIOE_TIM1_CH1 9U +#define GPIOE_ZIO_D40 10U +#define GPIOE_TIM1_CH2N 10U +#define GPIOE_ARD_D5 11U +#define GPIOE_TIM1_CH2 11U +#define GPIOE_ZIO_D39 12U +#define GPIOE_TIM1_CH3N 12U +#define GPIOE_ARD_D3 13U +#define GPIOE_TIM1_CH3 13U +#define GPIOE_ZIO_D38 14U +#define GPIOE_ZIO_D37 15U +#define GPIOE_TIM1_BKIN1 15U -#define GPIOF_FMC_A0 0U -#define GPIOF_FMC_A1 1U -#define GPIOF_FMC_A2 2U -#define GPIOF_FMC_A3 3U -#define GPIOF_FMC_A4 4U -#define GPIOF_FMC_A5 5U -#define GPIOF_ARD_D3 6U -#define GPIOF_ARD_D6 7U -#define GPIOF_ARD_A4 8U -#define GPIOF_ARD_A5 9U -#define GPIOF_ARD_A3 10U -#define GPIOF_FMC_SDNRAS 11U -#define GPIOF_FMC_A6 12U -#define GPIOF_FMC_A7 13U -#define GPIOF_FMC_A8 14U -#define GPIOF_FMC_A9 15U +#define GPIOF_ZIO_D68 0U +#define GPIOF_I2C2_SDA 0U +#define GPIOF_ZIO_D69 1U +#define GPIOF_I2C2_SCL 1U +#define GPIOF_ZIO_D70 2U +#define GPIOF_I2C2_SMBA 2U +#define GPIOF_ARD_A3 3U +#define GPIOF_ADC3_IN9 3U +#define GPIOF_ZIO_A8 4U +#define GPIOF_ADC3_IN14 4U +#define GPIOF_ARD_A4 5U +#define GPIOF_ADC3_IN15 5U +#define GPIOF_PIN6 6U +#define GPIOF_ZIO_D62 7U +#define GPIOF_SAI1_MCLK_B 7U +#define GPIOF_ZIO_D61 8U +#define GPIOF_SAI1_SCK_B 8U +#define GPIOF_ZIO_D63 9U +#define GPIOF_SAI1_FS_B 9U +#define GPIOF_ARD_A5 10U +#define GPIOF_ADC3_IN8 10U +#define GPIOF_PIN11 11U +#define GPIOF_ARD_D8 12U +#define GPIOF_ARD_D7 13U +#define GPIOF_ARD_D4 14U +#define GPIOF_ARD_D2 15U -#define GPIOG_FMC_A10 0U -#define GPIOG_FMC_A11 1U -#define GPIOG_FMC_A12 2U -#define GPIOG_EXT_SCL 3U -#define GPIOG_FMC_BA0 4U -#define GPIOG_FMC_BA1 5U -#define GPIOG_EXT_SDA 6U -#define GPIOG_SAI1_MCLKA 7U -#define GPIOG_FMC_SDCLK 8U -#define GPIOG_SD_D0 9U -#define GPIOG_SD_D1 10U +#define GPIOG_ZIO_D65 0U +#define GPIOG_ZIO_D64 1U +#define GPIOG_ZIO_D49 2U +#define GPIOG_ZIO_D50 3U +#define GPIOG_PIN4 4U +#define GPIOG_PIN5 5U +#define GPIOG_USB_GPIO_OUT 6U +#define GPIOG_USB_GPIO_IN 7U +#define GPIOG_PIN8 8U +#define GPIOG_ARD_D0 9U +#define GPIOG_USART6_RX 9U +#define GPIOG_PIN10 10U #define GPIOG_RMII_TX_EN 11U -#define GPIOG_SPDIF_RX 12U +#define GPIOG_PIN12 12U #define GPIOG_RMII_TXD0 13U -#define GPIOG_RMII_TXD1 14U -#define GPIOG_FMC_SDNCAS 15U +#define GPIOG_ARD_D1 14U +#define GPIOG_USART6_TX 14U +#define GPIOG_PIN15 15U #define GPIOH_OSC_IN 0U #define GPIOH_OSC_OUT 1U -#define GPIOH_FMC_SDCKE0 2U -#define GPIOH_FMC_SDNE0 3U -#define GPIOH_ULPI_NXT 4U -#define GPIOH_FMC_SDNWE 5U -#define GPIOH_ARD_D9 6U -#define GPIOH_EXT_RST 7U -#define GPIOH_FMC_D16 8U -#define GPIOH_FMC_D17 9U -#define GPIOH_FMC_D18 10U -#define GPIOH_FMC_D19 11U -#define GPIOH_FMC_D20 12U -#define GPIOH_FMC_D21 13U -#define GPIOH_FMC_D22 14U -#define GPIOH_FMC_D23 15U +#define GPIOH_PIN2 2U +#define GPIOH_PIN3 3U +#define GPIOH_PIN4 4U +#define GPIOH_PIN5 5U +#define GPIOH_PIN6 6U +#define GPIOH_PIN7 7U +#define GPIOH_PIN8 8U +#define GPIOH_PIN9 9U +#define GPIOH_PIN10 10U +#define GPIOH_PIN11 11U +#define GPIOH_PIN12 12U +#define GPIOH_PIN13 13U +#define GPIOH_PIN14 14U +#define GPIOH_PIN15 15U -#define GPIOI_FMC_D24 0U -#define GPIOI_FMC_D25 1U -#define GPIOI_FMC_D26 2U -#define GPIOI_FMC_D27 3U -#define GPIOI_FMC_NBL2 4U -#define GPIOI_FMC_NBL3 5U -#define GPIOI_FMC_D28 6U -#define GPIOI_FMC_D29 7U +#define GPIOI_PIN0 0U +#define GPIOI_PIN1 1U +#define GPIOI_PIN2 2U +#define GPIOI_PIN3 3U +#define GPIOI_PIN4 4U +#define GPIOI_PIN5 5U +#define GPIOI_PIN6 6U +#define GPIOI_PIN7 7U #define GPIOI_PIN8 8U -#define GPIOI_FMC_D30 9U -#define GPIOI_FMC_D31 10U -#define GPIOI_ULPI_DIR 11U +#define GPIOI_PIN9 9U +#define GPIOI_PIN10 10U +#define GPIOI_PIN11 11U #define GPIOI_PIN12 12U -#define GPIOI_LCD_INT 13U -#define GPIOI_LCD_BL_CTRL 14U -#define GPIOI_SD_DETECT 15U +#define GPIOI_PIN13 13U +#define GPIOI_PIN14 14U +#define GPIOI_PIN15 15U -#define GPIOJ_ARD_D4 0U -#define GPIOJ_ARD_D2 1U -#define GPIOJ_DSI_TE 2U -#define GPIOJ_ARD_D7 3U -#define GPIOJ_ARD_D8 4U -#define GPIOJ_LED2_GREEN 5U +#define GPIOJ_PIN0 0U +#define GPIOJ_PIN1 1U +#define GPIOJ_PIN2 2U +#define GPIOJ_PIN3 3U +#define GPIOJ_PIN4 4U +#define GPIOJ_PIN5 5U #define GPIOJ_PIN6 6U #define GPIOJ_PIN7 7U #define GPIOJ_PIN8 8U #define GPIOJ_PIN9 9U #define GPIOJ_PIN10 10U #define GPIOJ_PIN11 11U -#define GPIOJ_AUDIO_INT 12U -#define GPIOJ_LED1_RED 13U -#define GPIOJ_WIFI_RST 14U -#define GPIOJ_DSI_RESET 15U +#define GPIOJ_PIN12 12U +#define GPIOJ_PIN13 13U +#define GPIOJ_PIN14 14U +#define GPIOJ_PIN15 15U #define GPIOK_PIN0 0U #define GPIOK_PIN1 1U @@ -270,161 +338,187 @@ /* * IO lines assignments. */ -#define LINE_BUTTON_USER PAL_LINE(GPIOA, 0U) +#define LINE_ZIO_D32 PAL_LINE(GPIOA, 0U) +#define LINE_TIM2_CH1 PAL_LINE(GPIOA, 0U) #define LINE_RMII_REF_CLK PAL_LINE(GPIOA, 1U) #define LINE_RMII_MDIO PAL_LINE(GPIOA, 2U) -#define LINE_ULPI_D0 PAL_LINE(GPIOA, 3U) -#define LINE_ARD_A1 PAL_LINE(GPIOA, 4U) -#define LINE_ULPI_CK PAL_LINE(GPIOA, 5U) -#define LINE_ARD_A0 PAL_LINE(GPIOA, 6U) -#define LINE_RMII_CRS_DV PAL_LINE(GPIOA, 7U) -#define LINE_CEC_CLK PAL_LINE(GPIOA, 8U) -#define LINE_VCP_TX PAL_LINE(GPIOA, 9U) -#define LINE_VCP_RX PAL_LINE(GPIOA, 10U) -#define LINE_ARD_D10 PAL_LINE(GPIOA, 11U) -#define LINE_ARD_D13 PAL_LINE(GPIOA, 12U) +#define LINE_ARD_A0 PAL_LINE(GPIOA, 3U) +#define LINE_ADC123_IN3 PAL_LINE(GPIOA, 3U) +#define LINE_ZIO_D24 PAL_LINE(GPIOA, 4U) +#define LINE_SPI3_NSS PAL_LINE(GPIOA, 4U) +#define LINE_ARD_D13 PAL_LINE(GPIOA, 5U) +#define LINE_SPI1_SCK PAL_LINE(GPIOA, 5U) +#define LINE_ARD_D12 PAL_LINE(GPIOA, 6U) +#define LINE_SPI1_MISO PAL_LINE(GPIOA, 6U) +#define LINE_ARD_D11 PAL_LINE(GPIOA, 7U) +#define LINE_SPI1_MOSI PAL_LINE(GPIOA, 7U) +#define LINE_ZIO_D71 PAL_LINE(GPIOA, 7U) +#define LINE_RMII_RX_DV PAL_LINE(GPIOA, 7U) +#define LINE_USB_SOF PAL_LINE(GPIOA, 8U) +#define LINE_USB_VBUS PAL_LINE(GPIOA, 9U) +#define LINE_USB_ID PAL_LINE(GPIOA, 10U) +#define LINE_USB_DM PAL_LINE(GPIOA, 11U) +#define LINE_USB_DP PAL_LINE(GPIOA, 12U) #define LINE_SWDIO PAL_LINE(GPIOA, 13U) #define LINE_SWCLK PAL_LINE(GPIOA, 14U) -#define LINE_CEC PAL_LINE(GPIOA, 15U) -#define LINE_ULPI_D1 PAL_LINE(GPIOB, 0U) -#define LINE_ULPI_D2 PAL_LINE(GPIOB, 1U) +#define LINE_ZIO_D20 PAL_LINE(GPIOA, 15U) +#define LINE_I2S3_WS PAL_LINE(GPIOA, 15U) +#define LINE_ZIO_D33 PAL_LINE(GPIOB, 0U) +#define LINE_TIM3_CH3 PAL_LINE(GPIOB, 0U) +#define LINE_LED1 PAL_LINE(GPIOB, 0U) +#define LINE_ZIO_A6 PAL_LINE(GPIOB, 1U) +#define LINE_ADC12_IN9 PAL_LINE(GPIOB, 1U) +#define LINE_ZIO_D27 PAL_LINE(GPIOB, 2U) #define LINE_QSPI_CLK PAL_LINE(GPIOB, 2U) -#define LINE_SD_D2 PAL_LINE(GPIOB, 3U) -#define LINE_SD_D3 PAL_LINE(GPIOB, 4U) -#define LINE_ULPI_D7 PAL_LINE(GPIOB, 5U) -#define LINE_QUADSPI_BK1_NCS PAL_LINE(GPIOB, 6U) -#define LINE_AUDIO_SDA PAL_LINE(GPIOB, 7U) -#define LINE_LCD_SDA PAL_LINE(GPIOB, 7U) +#define LINE_ZIO_D23 PAL_LINE(GPIOB, 3U) +#define LINE_I2S3_CK PAL_LINE(GPIOB, 3U) +#define LINE_ZIO_D25 PAL_LINE(GPIOB, 4U) +#define LINE_SPI3_MISO PAL_LINE(GPIOB, 4U) +#define LINE_ZIO_D22 PAL_LINE(GPIOB, 5U) +#define LINE_I2S3_SD PAL_LINE(GPIOB, 5U) +#define LINE_ZIO_D26 PAL_LINE(GPIOB, 6U) +#define LINE_QSPI_BK1_NCS PAL_LINE(GPIOB, 6U) +#define LINE_LED2 PAL_LINE(GPIOB, 7U) #define LINE_ARD_D15 PAL_LINE(GPIOB, 8U) #define LINE_I2C1_SCL PAL_LINE(GPIOB, 8U) #define LINE_ARD_D14 PAL_LINE(GPIOB, 9U) #define LINE_I2C1_SDA PAL_LINE(GPIOB, 9U) -#define LINE_ULPI_D3 PAL_LINE(GPIOB, 10U) -#define LINE_ULPI_D4 PAL_LINE(GPIOB, 11U) -#define LINE_ULPI_D5 PAL_LINE(GPIOB, 12U) -#define LINE_ULPI_D6 PAL_LINE(GPIOB, 13U) -#define LINE_ARD_D12 PAL_LINE(GPIOB, 14U) -#define LINE_ARD_D11 PAL_LINE(GPIOB, 15U) -#define LINE_ULPI_STP PAL_LINE(GPIOC, 0U) +#define LINE_ZIO_D36 PAL_LINE(GPIOB, 10U) +#define LINE_TIM2_CH3 PAL_LINE(GPIOB, 10U) +#define LINE_ZIO_D35 PAL_LINE(GPIOB, 11U) +#define LINE_TIM2_CH4 PAL_LINE(GPIOB, 11U) +#define LINE_ZIO_D19 PAL_LINE(GPIOB, 12U) +#define LINE_I2S2_WS PAL_LINE(GPIOB, 12U) +#define LINE_ZIO_D18 PAL_LINE(GPIOB, 13U) +#define LINE_I2S2_CK PAL_LINE(GPIOB, 13U) +#define LINE_RMII_TXD1 PAL_LINE(GPIOB, 13U) +#define LINE_LED3 PAL_LINE(GPIOB, 14U) +#define LINE_ZIO_D17 PAL_LINE(GPIOB, 15U) +#define LINE_I2S2_SD PAL_LINE(GPIOB, 15U) +#define LINE_ARD_A1 PAL_LINE(GPIOC, 0U) +#define LINE_ADC123_IN10 PAL_LINE(GPIOC, 0U) #define LINE_RMII_MDC PAL_LINE(GPIOC, 1U) -#define LINE_ARD_A2 PAL_LINE(GPIOC, 2U) -#define LINE_DFSDM_DATIN1 PAL_LINE(GPIOC, 3U) +#define LINE_ZIO_A7 PAL_LINE(GPIOC, 2U) +#define LINE_ADC123_IN12 PAL_LINE(GPIOC, 2U) +#define LINE_ARD_A2 PAL_LINE(GPIOC, 3U) +#define LINE_ADC123_IN13 PAL_LINE(GPIOC, 3U) #define LINE_RMII_RXD0 PAL_LINE(GPIOC, 4U) #define LINE_RMII_RXD1 PAL_LINE(GPIOC, 5U) -#define LINE_ARD_D1 PAL_LINE(GPIOC, 6U) -#define LINE_ARD_D0 PAL_LINE(GPIOC, 7U) -#define LINE_ARD_D5 PAL_LINE(GPIOC, 8U) -#define LINE_QSPI_D0 PAL_LINE(GPIOC, 9U) -#define LINE_QSPI_D1 PAL_LINE(GPIOC, 10U) -#define LINE_DFSDM_DATIN5 PAL_LINE(GPIOC, 11U) -#define LINE_WIFI_RX PAL_LINE(GPIOC, 12U) +#define LINE_ZIO_D16 PAL_LINE(GPIOC, 6U) +#define LINE_I2S2_MCK PAL_LINE(GPIOC, 6U) +#define LINE_ZIO_D21 PAL_LINE(GPIOC, 7U) +#define LINE_I2S3_MCK PAL_LINE(GPIOC, 7U) +#define LINE_ZIO_D43 PAL_LINE(GPIOC, 8U) +#define LINE_SDMMC_D0 PAL_LINE(GPIOC, 8U) +#define LINE_ZIO_D44 PAL_LINE(GPIOC, 9U) +#define LINE_SDMMC_D1 PAL_LINE(GPIOC, 9U) +#define LINE_ZIO_D45 PAL_LINE(GPIOC, 10U) +#define LINE_SDMMC_D2 PAL_LINE(GPIOC, 10U) +#define LINE_ZIO_D46 PAL_LINE(GPIOC, 11U) +#define LINE_SDMMC_D3 PAL_LINE(GPIOC, 11U) +#define LINE_ZIO_D47 PAL_LINE(GPIOC, 12U) +#define LINE_SDMMC_CK PAL_LINE(GPIOC, 12U) +#define LINE_BUTTON PAL_LINE(GPIOC, 13U) #define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) #define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) -#define LINE_FMC_D2 PAL_LINE(GPIOD, 0U) -#define LINE_FMC_D3 PAL_LINE(GPIOD, 1U) -#define LINE_WIFI_TX PAL_LINE(GPIOD, 2U) -#define LINE_DFSDM_CKOUT PAL_LINE(GPIOD, 3U) -#define LINE_OTG_HS_OVER_CURRENT PAL_LINE(GPIOD, 4U) -#define LINE_RMII_RXER PAL_LINE(GPIOD, 5U) -#define LINE_SD_CLK PAL_LINE(GPIOD, 6U) -#define LINE_SD_CMD PAL_LINE(GPIOD, 7U) -#define LINE_FMC_D13 PAL_LINE(GPIOD, 8U) -#define LINE_FMC_D14 PAL_LINE(GPIOD, 9U) -#define LINE_FMC_D15 PAL_LINE(GPIOD, 10U) -#define LINE_SPDIF_I2S PAL_LINE(GPIOD, 11U) -#define LINE_AUDIO_SCL PAL_LINE(GPIOD, 12U) -#define LINE_LCD_SCL PAL_LINE(GPIOD, 12U) -#define LINE_QSPI_D3 PAL_LINE(GPIOD, 13U) -#define LINE_FMC_D0 PAL_LINE(GPIOD, 14U) -#define LINE_FMC_D1 PAL_LINE(GPIOD, 15U) -#define LINE_FMC_NBL0 PAL_LINE(GPIOE, 0U) -#define LINE_FMC_NBL1 PAL_LINE(GPIOE, 1U) -#define LINE_QSPI_D2 PAL_LINE(GPIOE, 2U) -#define LINE_SAI1_SDB PAL_LINE(GPIOE, 3U) -#define LINE_SAI1_FSA PAL_LINE(GPIOE, 4U) -#define LINE_SAI1_SCKA PAL_LINE(GPIOE, 5U) -#define LINE_SAI1_SDA PAL_LINE(GPIOE, 6U) -#define LINE_FMC_D4 PAL_LINE(GPIOE, 7U) -#define LINE_FMC_D5 PAL_LINE(GPIOE, 8U) -#define LINE_FMC_D6 PAL_LINE(GPIOE, 9U) -#define LINE_FMC_D7 PAL_LINE(GPIOE, 10U) -#define LINE_FMC_D8 PAL_LINE(GPIOE, 11U) -#define LINE_FMC_D9 PAL_LINE(GPIOE, 12U) -#define LINE_FMC_D10 PAL_LINE(GPIOE, 13U) -#define LINE_FMC_11 PAL_LINE(GPIOE, 14U) -#define LINE_FMC_D12 PAL_LINE(GPIOE, 15U) -#define LINE_FMC_A0 PAL_LINE(GPIOF, 0U) -#define LINE_FMC_A1 PAL_LINE(GPIOF, 1U) -#define LINE_FMC_A2 PAL_LINE(GPIOF, 2U) -#define LINE_FMC_A3 PAL_LINE(GPIOF, 3U) -#define LINE_FMC_A4 PAL_LINE(GPIOF, 4U) -#define LINE_FMC_A5 PAL_LINE(GPIOF, 5U) -#define LINE_ARD_D3 PAL_LINE(GPIOF, 6U) -#define LINE_ARD_D6 PAL_LINE(GPIOF, 7U) -#define LINE_ARD_A4 PAL_LINE(GPIOF, 8U) -#define LINE_ARD_A5 PAL_LINE(GPIOF, 9U) -#define LINE_ARD_A3 PAL_LINE(GPIOF, 10U) -#define LINE_FMC_SDNRAS PAL_LINE(GPIOF, 11U) -#define LINE_FMC_A6 PAL_LINE(GPIOF, 12U) -#define LINE_FMC_A7 PAL_LINE(GPIOF, 13U) -#define LINE_FMC_A8 PAL_LINE(GPIOF, 14U) -#define LINE_FMC_A9 PAL_LINE(GPIOF, 15U) -#define LINE_FMC_A10 PAL_LINE(GPIOG, 0U) -#define LINE_FMC_A11 PAL_LINE(GPIOG, 1U) -#define LINE_FMC_A12 PAL_LINE(GPIOG, 2U) -#define LINE_EXT_SCL PAL_LINE(GPIOG, 3U) -#define LINE_FMC_BA0 PAL_LINE(GPIOG, 4U) -#define LINE_FMC_BA1 PAL_LINE(GPIOG, 5U) -#define LINE_EXT_SDA PAL_LINE(GPIOG, 6U) -#define LINE_SAI1_MCLKA PAL_LINE(GPIOG, 7U) -#define LINE_FMC_SDCLK PAL_LINE(GPIOG, 8U) -#define LINE_SD_D0 PAL_LINE(GPIOG, 9U) -#define LINE_SD_D1 PAL_LINE(GPIOG, 10U) +#define LINE_ZIO_D67 PAL_LINE(GPIOD, 0U) +#define LINE_CAN1_RX PAL_LINE(GPIOD, 0U) +#define LINE_ZIO_D66 PAL_LINE(GPIOD, 1U) +#define LINE_CAN1_TX PAL_LINE(GPIOD, 1U) +#define LINE_ZIO_D48 PAL_LINE(GPIOD, 2U) +#define LINE_SDMMC_CMD PAL_LINE(GPIOD, 2U) +#define LINE_ZIO_D55 PAL_LINE(GPIOD, 3U) +#define LINE_USART2_CTS PAL_LINE(GPIOD, 3U) +#define LINE_ZIO_D54 PAL_LINE(GPIOD, 4U) +#define LINE_USART2_RTS PAL_LINE(GPIOD, 4U) +#define LINE_ZIO_D53 PAL_LINE(GPIOD, 5U) +#define LINE_USART2_TX PAL_LINE(GPIOD, 5U) +#define LINE_ZIO_D52 PAL_LINE(GPIOD, 6U) +#define LINE_USART2_RX PAL_LINE(GPIOD, 6U) +#define LINE_ZIO_D51 PAL_LINE(GPIOD, 7U) +#define LINE_USART2_SCLK PAL_LINE(GPIOD, 7U) +#define LINE_USART3_RX PAL_LINE(GPIOD, 8U) +#define LINE_STLK_RX PAL_LINE(GPIOD, 8U) +#define LINE_USART3_TX PAL_LINE(GPIOD, 9U) +#define LINE_STLK_TX PAL_LINE(GPIOD, 9U) +#define LINE_ZIO_D30 PAL_LINE(GPIOD, 11U) +#define LINE_QSPI_BK1_IO0 PAL_LINE(GPIOD, 11U) +#define LINE_ZIO_D29 PAL_LINE(GPIOD, 12U) +#define LINE_QSPI_BK1_IO1 PAL_LINE(GPIOD, 12U) +#define LINE_ZIO_D28 PAL_LINE(GPIOD, 13U) +#define LINE_QSPI_BK1_IO3 PAL_LINE(GPIOD, 13U) +#define LINE_ARD_D10 PAL_LINE(GPIOD, 14U) +#define LINE_SPI1_NSS PAL_LINE(GPIOD, 14U) +#define LINE_ARD_D9 PAL_LINE(GPIOD, 15U) +#define LINE_TIM4_CH4 PAL_LINE(GPIOD, 15U) +#define LINE_ZIO_D34 PAL_LINE(GPIOE, 0U) +#define LINE_TIM4_ETR PAL_LINE(GPIOE, 0U) +#define LINE_ZIO_D31 PAL_LINE(GPIOE, 2U) +#define LINE_ZIO_D56 PAL_LINE(GPIOE, 2U) +#define LINE_SAI1_MCLK_A PAL_LINE(GPIOE, 2U) +#define LINE_ZIO_D60 PAL_LINE(GPIOE, 3U) +#define LINE_SAI1_SD_B PAL_LINE(GPIOE, 3U) +#define LINE_ZIO_D57 PAL_LINE(GPIOE, 4U) +#define LINE_SAI1_FS_A PAL_LINE(GPIOE, 4U) +#define LINE_ZIO_D58 PAL_LINE(GPIOE, 5U) +#define LINE_SAI1_SCK_A PAL_LINE(GPIOE, 5U) +#define LINE_ZIO_D59 PAL_LINE(GPIOE, 6U) +#define LINE_SAI1_SD_A PAL_LINE(GPIOE, 6U) +#define LINE_ZIO_D41 PAL_LINE(GPIOE, 7U) +#define LINE_TIM1_ETR PAL_LINE(GPIOE, 7U) +#define LINE_ZIO_D42 PAL_LINE(GPIOE, 8U) +#define LINE_TIM1_CH1N PAL_LINE(GPIOE, 8U) +#define LINE_ARD_D6 PAL_LINE(GPIOE, 9U) +#define LINE_TIM1_CH1 PAL_LINE(GPIOE, 9U) +#define LINE_ZIO_D40 PAL_LINE(GPIOE, 10U) +#define LINE_TIM1_CH2N PAL_LINE(GPIOE, 10U) +#define LINE_ARD_D5 PAL_LINE(GPIOE, 11U) +#define LINE_TIM1_CH2 PAL_LINE(GPIOE, 11U) +#define LINE_ZIO_D39 PAL_LINE(GPIOE, 12U) +#define LINE_TIM1_CH3N PAL_LINE(GPIOE, 12U) +#define LINE_ARD_D3 PAL_LINE(GPIOE, 13U) +#define LINE_TIM1_CH3 PAL_LINE(GPIOE, 13U) +#define LINE_ZIO_D38 PAL_LINE(GPIOE, 14U) +#define LINE_ZIO_D37 PAL_LINE(GPIOE, 15U) +#define LINE_TIM1_BKIN1 PAL_LINE(GPIOE, 15U) +#define LINE_ZIO_D68 PAL_LINE(GPIOF, 0U) +#define LINE_I2C2_SDA PAL_LINE(GPIOF, 0U) +#define LINE_ZIO_D69 PAL_LINE(GPIOF, 1U) +#define LINE_I2C2_SCL PAL_LINE(GPIOF, 1U) +#define LINE_ZIO_D70 PAL_LINE(GPIOF, 2U) +#define LINE_I2C2_SMBA PAL_LINE(GPIOF, 2U) +#define LINE_ARD_A3 PAL_LINE(GPIOF, 3U) +#define LINE_ADC3_IN9 PAL_LINE(GPIOF, 3U) +#define LINE_ZIO_A8 PAL_LINE(GPIOF, 4U) +#define LINE_ADC3_IN14 PAL_LINE(GPIOF, 4U) +#define LINE_ARD_A4 PAL_LINE(GPIOF, 5U) +#define LINE_ADC3_IN15 PAL_LINE(GPIOF, 5U) +#define LINE_ZIO_D62 PAL_LINE(GPIOF, 7U) +#define LINE_SAI1_MCLK_B PAL_LINE(GPIOF, 7U) +#define LINE_ZIO_D61 PAL_LINE(GPIOF, 8U) +#define LINE_SAI1_SCK_B PAL_LINE(GPIOF, 8U) +#define LINE_ZIO_D63 PAL_LINE(GPIOF, 9U) +#define LINE_SAI1_FS_B PAL_LINE(GPIOF, 9U) +#define LINE_ARD_A5 PAL_LINE(GPIOF, 10U) +#define LINE_ADC3_IN8 PAL_LINE(GPIOF, 10U) +#define LINE_ARD_D8 PAL_LINE(GPIOF, 12U) +#define LINE_ARD_D7 PAL_LINE(GPIOF, 13U) +#define LINE_ARD_D4 PAL_LINE(GPIOF, 14U) +#define LINE_ARD_D2 PAL_LINE(GPIOF, 15U) +#define LINE_ZIO_D65 PAL_LINE(GPIOG, 0U) +#define LINE_ZIO_D64 PAL_LINE(GPIOG, 1U) +#define LINE_ZIO_D49 PAL_LINE(GPIOG, 2U) +#define LINE_ZIO_D50 PAL_LINE(GPIOG, 3U) +#define LINE_USB_GPIO_OUT PAL_LINE(GPIOG, 6U) +#define LINE_USB_GPIO_IN PAL_LINE(GPIOG, 7U) +#define LINE_ARD_D0 PAL_LINE(GPIOG, 9U) +#define LINE_USART6_RX PAL_LINE(GPIOG, 9U) #define LINE_RMII_TX_EN PAL_LINE(GPIOG, 11U) -#define LINE_SPDIF_RX PAL_LINE(GPIOG, 12U) #define LINE_RMII_TXD0 PAL_LINE(GPIOG, 13U) -#define LINE_RMII_TXD1 PAL_LINE(GPIOG, 14U) -#define LINE_FMC_SDNCAS PAL_LINE(GPIOG, 15U) +#define LINE_ARD_D1 PAL_LINE(GPIOG, 14U) +#define LINE_USART6_TX PAL_LINE(GPIOG, 14U) #define LINE_OSC_IN PAL_LINE(GPIOH, 0U) #define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) -#define LINE_FMC_SDCKE0 PAL_LINE(GPIOH, 2U) -#define LINE_FMC_SDNE0 PAL_LINE(GPIOH, 3U) -#define LINE_ULPI_NXT PAL_LINE(GPIOH, 4U) -#define LINE_FMC_SDNWE PAL_LINE(GPIOH, 5U) -#define LINE_ARD_D9 PAL_LINE(GPIOH, 6U) -#define LINE_EXT_RST PAL_LINE(GPIOH, 7U) -#define LINE_FMC_D16 PAL_LINE(GPIOH, 8U) -#define LINE_FMC_D17 PAL_LINE(GPIOH, 9U) -#define LINE_FMC_D18 PAL_LINE(GPIOH, 10U) -#define LINE_FMC_D19 PAL_LINE(GPIOH, 11U) -#define LINE_FMC_D20 PAL_LINE(GPIOH, 12U) -#define LINE_FMC_D21 PAL_LINE(GPIOH, 13U) -#define LINE_FMC_D22 PAL_LINE(GPIOH, 14U) -#define LINE_FMC_D23 PAL_LINE(GPIOH, 15U) -#define LINE_FMC_D24 PAL_LINE(GPIOI, 0U) -#define LINE_FMC_D25 PAL_LINE(GPIOI, 1U) -#define LINE_FMC_D26 PAL_LINE(GPIOI, 2U) -#define LINE_FMC_D27 PAL_LINE(GPIOI, 3U) -#define LINE_FMC_NBL2 PAL_LINE(GPIOI, 4U) -#define LINE_FMC_NBL3 PAL_LINE(GPIOI, 5U) -#define LINE_FMC_D28 PAL_LINE(GPIOI, 6U) -#define LINE_FMC_D29 PAL_LINE(GPIOI, 7U) -#define LINE_FMC_D30 PAL_LINE(GPIOI, 9U) -#define LINE_FMC_D31 PAL_LINE(GPIOI, 10U) -#define LINE_ULPI_DIR PAL_LINE(GPIOI, 11U) -#define LINE_LCD_INT PAL_LINE(GPIOI, 13U) -#define LINE_LCD_BL_CTRL PAL_LINE(GPIOI, 14U) -#define LINE_SD_DETECT PAL_LINE(GPIOI, 15U) -#define LINE_ARD_D4 PAL_LINE(GPIOJ, 0U) -#define LINE_ARD_D2 PAL_LINE(GPIOJ, 1U) -#define LINE_DSI_TE PAL_LINE(GPIOJ, 2U) -#define LINE_ARD_D7 PAL_LINE(GPIOJ, 3U) -#define LINE_ARD_D8 PAL_LINE(GPIOJ, 4U) -#define LINE_LED2_GREEN PAL_LINE(GPIOJ, 5U) -#define LINE_AUDIO_INT PAL_LINE(GPIOJ, 12U) -#define LINE_LED1_RED PAL_LINE(GPIOJ, 13U) -#define LINE_WIFI_RST PAL_LINE(GPIOJ, 14U) -#define LINE_DSI_RESET PAL_LINE(GPIOJ, 15U) /*===========================================================================*/ /* Driver pre-compile time settings. */ @@ -467,1192 +561,1192 @@ /* * GPIOA setup: * - * PA0 - BUTTON_USER (input floating). + * PA0 - ZIO_D32 TIM2_CH1 (input pullup). * PA1 - RMII_REF_CLK (alternate 11). * PA2 - RMII_MDIO (alternate 11). - * PA3 - ULPI_D0 (alternate 10). - * PA4 - ARD_A1 (input pullup). - * PA5 - ULPI_CK (alternate 10). - * PA6 - ARD_A0 (input pullup). - * PA7 - RMII_CRS_DV (alternate 11). - * PA8 - CEC_CLK (alternate 0). - * PA9 - VCP_TX (alternate 7). - * PA10 - VCP_RX (alternate 7). - * PA11 - ARD_D10 (input pullup). - * PA12 - ARD_D13 (input pullup). + * PA3 - ARD_A0 ADC123_IN3 (input pullup). + * PA4 - ZIO_D24 SPI3_NSS (input pullup). + * PA5 - ARD_D13 SPI1_SCK (input pullup). + * PA6 - ARD_D12 SPI1_MISO (input pullup). + * PA7 - ARD_D11 SPI1_MOSI ZIO_D71 RMII_RX_DV(alternate 11). + * PA8 - USB_SOF (alternate 10). + * PA9 - USB_VBUS (analog). + * PA10 - USB_ID (alternate 10). + * PA11 - USB_DM (alternate 10). + * PA12 - USB_DP (alternate 10). * PA13 - SWDIO (alternate 0). * PA14 - SWCLK (alternate 0). - * PA15 - CEC (alternate 3). + * PA15 - ZIO_D20 I2S3_WS (input pullup). */ -#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON_USER) | \ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_ZIO_D32) | \ PIN_MODE_ALTERNATE(GPIOA_RMII_REF_CLK) |\ PIN_MODE_ALTERNATE(GPIOA_RMII_MDIO) | \ - PIN_MODE_ALTERNATE(GPIOA_ULPI_D0) | \ - PIN_MODE_INPUT(GPIOA_ARD_A1) | \ - PIN_MODE_ALTERNATE(GPIOA_ULPI_CK) | \ PIN_MODE_INPUT(GPIOA_ARD_A0) | \ - PIN_MODE_ALTERNATE(GPIOA_RMII_CRS_DV) |\ - PIN_MODE_ALTERNATE(GPIOA_CEC_CLK) | \ - PIN_MODE_ALTERNATE(GPIOA_VCP_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_VCP_RX) | \ - PIN_MODE_INPUT(GPIOA_ARD_D10) | \ + PIN_MODE_INPUT(GPIOA_ZIO_D24) | \ PIN_MODE_INPUT(GPIOA_ARD_D13) | \ + PIN_MODE_INPUT(GPIOA_ARD_D12) | \ + PIN_MODE_ALTERNATE(GPIOA_ARD_D11) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_SOF) | \ + PIN_MODE_ANALOG(GPIOA_USB_VBUS) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_ID) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_DM) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_DP) | \ PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ - PIN_MODE_ALTERNATE(GPIOA_CEC)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON_USER) |\ + PIN_MODE_INPUT(GPIOA_ZIO_D20)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_ZIO_D32) | \ PIN_OTYPE_PUSHPULL(GPIOA_RMII_REF_CLK) |\ PIN_OTYPE_PUSHPULL(GPIOA_RMII_MDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_ULPI_D0) | \ - PIN_OTYPE_PUSHPULL(GPIOA_ARD_A1) | \ - PIN_OTYPE_PUSHPULL(GPIOA_ULPI_CK) | \ PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) | \ - PIN_OTYPE_PUSHPULL(GPIOA_RMII_CRS_DV) |\ - PIN_OTYPE_PUSHPULL(GPIOA_CEC_CLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_VCP_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_VCP_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_ARD_D10) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ZIO_D24) | \ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D13) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D12) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D11) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_SOF) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_VBUS) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_ID) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) | \ PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CEC)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_BUTTON_USER) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ZIO_D20)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_ZIO_D32) | \ PIN_OSPEED_HIGH(GPIOA_RMII_REF_CLK) | \ PIN_OSPEED_HIGH(GPIOA_RMII_MDIO) | \ - PIN_OSPEED_HIGH(GPIOA_ULPI_D0) | \ - PIN_OSPEED_HIGH(GPIOA_ARD_A1) | \ - PIN_OSPEED_HIGH(GPIOA_ULPI_CK) | \ PIN_OSPEED_HIGH(GPIOA_ARD_A0) | \ - PIN_OSPEED_VERYLOW(GPIOA_RMII_CRS_DV) |\ - PIN_OSPEED_HIGH(GPIOA_CEC_CLK) | \ - PIN_OSPEED_HIGH(GPIOA_VCP_TX) | \ - PIN_OSPEED_HIGH(GPIOA_VCP_RX) | \ - PIN_OSPEED_HIGH(GPIOA_ARD_D10) | \ + PIN_OSPEED_HIGH(GPIOA_ZIO_D24) | \ PIN_OSPEED_HIGH(GPIOA_ARD_D13) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D12) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D11) | \ + PIN_OSPEED_HIGH(GPIOA_USB_SOF) | \ + PIN_OSPEED_HIGH(GPIOA_USB_VBUS) | \ + PIN_OSPEED_HIGH(GPIOA_USB_ID) | \ + PIN_OSPEED_HIGH(GPIOA_USB_DM) | \ + PIN_OSPEED_HIGH(GPIOA_USB_DP) | \ PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ - PIN_OSPEED_HIGH(GPIOA_CEC)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON_USER) |\ + PIN_OSPEED_HIGH(GPIOA_ZIO_D20)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_ZIO_D32) | \ PIN_PUPDR_FLOATING(GPIOA_RMII_REF_CLK) |\ PIN_PUPDR_PULLUP(GPIOA_RMII_MDIO) | \ - PIN_PUPDR_FLOATING(GPIOA_ULPI_D0) | \ - PIN_PUPDR_PULLUP(GPIOA_ARD_A1) | \ - PIN_PUPDR_FLOATING(GPIOA_ULPI_CK) | \ PIN_PUPDR_PULLUP(GPIOA_ARD_A0) | \ - PIN_PUPDR_FLOATING(GPIOA_RMII_CRS_DV) |\ - PIN_PUPDR_FLOATING(GPIOA_CEC_CLK) | \ - PIN_PUPDR_FLOATING(GPIOA_VCP_TX) | \ - PIN_PUPDR_FLOATING(GPIOA_VCP_RX) | \ - PIN_PUPDR_PULLUP(GPIOA_ARD_D10) | \ + PIN_PUPDR_PULLUP(GPIOA_ZIO_D24) | \ PIN_PUPDR_PULLUP(GPIOA_ARD_D13) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_D12) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_D11) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_SOF) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_VBUS) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_ID) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_DM) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_DP) | \ PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \ PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \ - PIN_PUPDR_FLOATING(GPIOA_CEC)) -#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON_USER) | \ + PIN_PUPDR_PULLUP(GPIOA_ZIO_D20)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_ZIO_D32) | \ PIN_ODR_HIGH(GPIOA_RMII_REF_CLK) | \ PIN_ODR_HIGH(GPIOA_RMII_MDIO) | \ - PIN_ODR_HIGH(GPIOA_ULPI_D0) | \ - PIN_ODR_HIGH(GPIOA_ARD_A1) | \ - PIN_ODR_HIGH(GPIOA_ULPI_CK) | \ PIN_ODR_HIGH(GPIOA_ARD_A0) | \ - PIN_ODR_HIGH(GPIOA_RMII_CRS_DV) | \ - PIN_ODR_HIGH(GPIOA_CEC_CLK) | \ - PIN_ODR_HIGH(GPIOA_VCP_TX) | \ - PIN_ODR_HIGH(GPIOA_VCP_RX) | \ - PIN_ODR_HIGH(GPIOA_ARD_D10) | \ + PIN_ODR_HIGH(GPIOA_ZIO_D24) | \ PIN_ODR_HIGH(GPIOA_ARD_D13) | \ + PIN_ODR_HIGH(GPIOA_ARD_D12) | \ + PIN_ODR_HIGH(GPIOA_ARD_D11) | \ + PIN_ODR_HIGH(GPIOA_USB_SOF) | \ + PIN_ODR_HIGH(GPIOA_USB_VBUS) | \ + PIN_ODR_HIGH(GPIOA_USB_ID) | \ + PIN_ODR_HIGH(GPIOA_USB_DM) | \ + PIN_ODR_HIGH(GPIOA_USB_DP) | \ PIN_ODR_HIGH(GPIOA_SWDIO) | \ PIN_ODR_HIGH(GPIOA_SWCLK) | \ - PIN_ODR_HIGH(GPIOA_CEC)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON_USER, 0U) | \ + PIN_ODR_HIGH(GPIOA_ZIO_D20)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ZIO_D32, 0U) | \ PIN_AFIO_AF(GPIOA_RMII_REF_CLK, 11U) | \ PIN_AFIO_AF(GPIOA_RMII_MDIO, 11U) | \ - PIN_AFIO_AF(GPIOA_ULPI_D0, 10U) | \ - PIN_AFIO_AF(GPIOA_ARD_A1, 0U) | \ - PIN_AFIO_AF(GPIOA_ULPI_CK, 10U) | \ PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \ - PIN_AFIO_AF(GPIOA_RMII_CRS_DV, 11U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_CEC_CLK, 0U) | \ - PIN_AFIO_AF(GPIOA_VCP_TX, 7U) | \ - PIN_AFIO_AF(GPIOA_VCP_RX, 7U) | \ - PIN_AFIO_AF(GPIOA_ARD_D10, 0U) | \ + PIN_AFIO_AF(GPIOA_ZIO_D24, 0U) | \ PIN_AFIO_AF(GPIOA_ARD_D13, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D12, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D11, 11U)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_USB_SOF, 10U) | \ + PIN_AFIO_AF(GPIOA_USB_VBUS, 0U) | \ + PIN_AFIO_AF(GPIOA_USB_ID, 10U) | \ + PIN_AFIO_AF(GPIOA_USB_DM, 10U) | \ + PIN_AFIO_AF(GPIOA_USB_DP, 10U) | \ PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ - PIN_AFIO_AF(GPIOA_CEC, 3U)) + PIN_AFIO_AF(GPIOA_ZIO_D20, 0U)) /* * GPIOB setup: * - * PB0 - ULPI_D1 (alternate 10). - * PB1 - ULPI_D2 (alternate 10). - * PB2 - QSPI_CLK (alternate 9). - * PB3 - SD_D2 (alternate 10). - * PB4 - SD_D3 (alternate 10). - * PB5 - ULPI_D7 (alternate 10). - * PB6 - QUADSPI_BK1_NCS (alternate 10). - * PB7 - AUDIO_SDA LCD_SDA (alternate 11). - * PB8 - ARD_D15 (input pullup). - * PB9 - ARD_D14 (input pullup). - * PB10 - ULPI_D3 (alternate 10). - * PB11 - ULPI_D4 (alternate 10). - * PB12 - ULPI_D5 (alternate 10). - * PB13 - ULPI_D6 (alternate 10). - * PB14 - ARD_D12 (input pullup). - * PB15 - ARD_D11 (input pullup). + * PB0 - ZIO_D33 TIM3_CH3 LED1 (output pushpull maximum). + * PB1 - ZIO_A6 ADC12_IN9 (input pullup). + * PB2 - ZIO_D27 QSPI_CLK (input pullup). + * PB3 - ZIO_D23 I2S3_CK (input pullup). + * PB4 - ZIO_D25 SPI3_MISO (input pullup). + * PB5 - ZIO_D22 I2S3_SD (input pullup). + * PB6 - ZIO_D26 QSPI_BK1_NCS (input pullup). + * PB7 - LED2 (output pushpull maximum). + * PB8 - ARD_D15 I2C1_SCL (input pullup). + * PB9 - ARD_D14 I2C1_SDA (input pullup). + * PB10 - ZIO_D36 TIM2_CH3 (input pullup). + * PB11 - ZIO_D35 TIM2_CH4 (input pullup). + * PB12 - ZIO_D19 I2S2_WS (input pullup). + * PB13 - ZIO_D18 I2S2_CK RMII_TXD1 (alternate 11). + * PB14 - LED3 (output pushpull maximum). + * PB15 - ZIO_D17 I2S2_SD (input pullup). */ -#define VAL_GPIOB_MODER (PIN_MODE_ALTERNATE(GPIOB_ULPI_D1) | \ - PIN_MODE_ALTERNATE(GPIOB_ULPI_D2) | \ - PIN_MODE_ALTERNATE(GPIOB_QSPI_CLK) | \ - PIN_MODE_ALTERNATE(GPIOB_SD_D2) | \ - PIN_MODE_ALTERNATE(GPIOB_SD_D3) | \ - PIN_MODE_ALTERNATE(GPIOB_ULPI_D7) | \ - PIN_MODE_ALTERNATE(GPIOB_QUADSPI_BK1_NCS) | \ - PIN_MODE_ALTERNATE(GPIOB_AUDIO_SDA) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ - PIN_MODE_ALTERNATE(GPIOB_ULPI_D3) | \ - PIN_MODE_ALTERNATE(GPIOB_ULPI_D4) | \ - PIN_MODE_ALTERNATE(GPIOB_ULPI_D5) | \ - PIN_MODE_ALTERNATE(GPIOB_ULPI_D6) | \ - PIN_MODE_INPUT(GPIOB_ARD_D12) | \ - PIN_MODE_INPUT(GPIOB_ARD_D11)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_ULPI_D1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_ULPI_D2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_QSPI_CLK) | \ - PIN_OTYPE_PUSHPULL(GPIOB_SD_D2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_SD_D3) | \ - PIN_OTYPE_PUSHPULL(GPIOB_ULPI_D7) | \ - PIN_OTYPE_PUSHPULL(GPIOB_QUADSPI_BK1_NCS) | \ - PIN_OTYPE_PUSHPULL(GPIOB_AUDIO_SDA) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ - PIN_OTYPE_PUSHPULL(GPIOB_ULPI_D3) | \ - PIN_OTYPE_PUSHPULL(GPIOB_ULPI_D4) | \ - PIN_OTYPE_PUSHPULL(GPIOB_ULPI_D5) | \ - PIN_OTYPE_PUSHPULL(GPIOB_ULPI_D6) | \ - PIN_OTYPE_PUSHPULL(GPIOB_ARD_D12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_ARD_D11)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_ULPI_D1) | \ - PIN_OSPEED_HIGH(GPIOB_ULPI_D2) | \ - PIN_OSPEED_HIGH(GPIOB_QSPI_CLK) | \ - PIN_OSPEED_HIGH(GPIOB_SD_D2) | \ - PIN_OSPEED_HIGH(GPIOB_SD_D3) | \ - PIN_OSPEED_HIGH(GPIOB_ULPI_D7) | \ - PIN_OSPEED_HIGH(GPIOB_QUADSPI_BK1_NCS) | \ - PIN_OSPEED_HIGH(GPIOB_AUDIO_SDA) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SCL) | \ - PIN_OSPEED_HIGH(GPIOB_I2C1_SDA) | \ - PIN_OSPEED_HIGH(GPIOB_ULPI_D3) | \ - PIN_OSPEED_HIGH(GPIOB_ULPI_D4) | \ - PIN_OSPEED_HIGH(GPIOB_ULPI_D5) | \ - PIN_OSPEED_HIGH(GPIOB_ULPI_D6) | \ - PIN_OSPEED_HIGH(GPIOB_ARD_D12) | \ - PIN_OSPEED_HIGH(GPIOB_ARD_D11)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_ULPI_D1) | \ - PIN_PUPDR_FLOATING(GPIOB_ULPI_D2) | \ - PIN_PUPDR_FLOATING(GPIOB_QSPI_CLK) | \ - PIN_PUPDR_FLOATING(GPIOB_SD_D2) | \ - PIN_PUPDR_FLOATING(GPIOB_SD_D3) | \ - PIN_PUPDR_PULLUP(GPIOB_ULPI_D7) | \ - PIN_PUPDR_FLOATING(GPIOB_QUADSPI_BK1_NCS) | \ - PIN_PUPDR_FLOATING(GPIOB_AUDIO_SDA) | \ - PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \ - PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \ - PIN_PUPDR_FLOATING(GPIOB_ULPI_D3) | \ - PIN_PUPDR_FLOATING(GPIOB_ULPI_D4) | \ - PIN_PUPDR_FLOATING(GPIOB_ULPI_D5) | \ - PIN_PUPDR_FLOATING(GPIOB_ULPI_D6) | \ - PIN_PUPDR_PULLUP(GPIOB_ARD_D12) | \ - PIN_PUPDR_PULLUP(GPIOB_ARD_D11)) -#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_ULPI_D1) | \ - PIN_ODR_HIGH(GPIOB_ULPI_D2) | \ - PIN_ODR_HIGH(GPIOB_QSPI_CLK) | \ - PIN_ODR_HIGH(GPIOB_SD_D2) | \ - PIN_ODR_HIGH(GPIOB_SD_D3) | \ - PIN_ODR_HIGH(GPIOB_ULPI_D7) | \ - PIN_ODR_HIGH(GPIOB_QUADSPI_BK1_NCS) | \ - PIN_ODR_HIGH(GPIOB_AUDIO_SDA) | \ - PIN_ODR_LOW(GPIOB_I2C1_SCL) | \ - PIN_ODR_LOW(GPIOB_I2C1_SDA) | \ - PIN_ODR_HIGH(GPIOB_ULPI_D3) | \ - PIN_ODR_HIGH(GPIOB_ULPI_D4) | \ - PIN_ODR_HIGH(GPIOB_ULPI_D5) | \ - PIN_ODR_HIGH(GPIOB_ULPI_D6) | \ - PIN_ODR_HIGH(GPIOB_ARD_D12) | \ - PIN_ODR_HIGH(GPIOB_ARD_D11)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ULPI_D1, 10U) | \ - PIN_AFIO_AF(GPIOB_ULPI_D2, 10U) | \ - PIN_AFIO_AF(GPIOB_QSPI_CLK, 9U) | \ - PIN_AFIO_AF(GPIOB_SD_D2, 10U) | \ - PIN_AFIO_AF(GPIOB_SD_D3, 10U) | \ - PIN_AFIO_AF(GPIOB_ULPI_D7, 10U) | \ - PIN_AFIO_AF(GPIOB_QUADSPI_BK1_NCS, 10U) | \ - PIN_AFIO_AF(GPIOB_AUDIO_SDA, 11U)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4U) | \ - PIN_AFIO_AF(GPIOB_I2C1_SDA, 4U) | \ - PIN_AFIO_AF(GPIOB_ULPI_D3, 10U) | \ - PIN_AFIO_AF(GPIOB_ULPI_D4, 10U) | \ - PIN_AFIO_AF(GPIOB_ULPI_D5, 10U) | \ - PIN_AFIO_AF(GPIOB_ULPI_D6, 10U) | \ - PIN_AFIO_AF(GPIOB_ARD_D12, 0U) | \ - PIN_AFIO_AF(GPIOB_ARD_D11, 0U)) +#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_ZIO_D33) | \ + PIN_MODE_INPUT(GPIOB_ZIO_A6) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D27) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D23) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D25) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D22) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D26) | \ + PIN_MODE_OUTPUT(GPIOB_LED2) | \ + PIN_MODE_INPUT(GPIOB_ARD_D15) | \ + PIN_MODE_INPUT(GPIOB_ARD_D14) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D36) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D35) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D19) | \ + PIN_MODE_ALTERNATE(GPIOB_ZIO_D18) | \ + PIN_MODE_OUTPUT(GPIOB_LED3) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D17)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D33) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_A6) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D27) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D23) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D25) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D22) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D26) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LED2) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D15) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D14) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D36) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D35) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D19) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D18) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LED3) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D17)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_ZIO_D33) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_A6) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D27) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D23) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D25) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D22) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D26) | \ + PIN_OSPEED_HIGH(GPIOB_LED2) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D15) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D14) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D36) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D35) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D19) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D18) | \ + PIN_OSPEED_HIGH(GPIOB_LED3) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D17)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_ZIO_D33) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_A6) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D27) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D23) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D25) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D22) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D26) | \ + PIN_PUPDR_FLOATING(GPIOB_LED2) | \ + PIN_PUPDR_PULLUP(GPIOB_ARD_D15) | \ + PIN_PUPDR_PULLUP(GPIOB_ARD_D14) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D36) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D35) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D19) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D18) | \ + PIN_PUPDR_FLOATING(GPIOB_LED3) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D17)) +#define VAL_GPIOB_ODR (PIN_ODR_LOW(GPIOB_ZIO_D33) | \ + PIN_ODR_HIGH(GPIOB_ZIO_A6) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D27) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D23) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D25) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D22) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D26) | \ + PIN_ODR_LOW(GPIOB_LED2) | \ + PIN_ODR_HIGH(GPIOB_ARD_D15) | \ + PIN_ODR_HIGH(GPIOB_ARD_D14) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D36) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D35) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D19) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D18) | \ + PIN_ODR_LOW(GPIOB_LED3) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D17)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ZIO_D33, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_A6, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D27, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D23, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D25, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D22, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D26, 0U) | \ + PIN_AFIO_AF(GPIOB_LED2, 0U)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_ARD_D15, 0U) | \ + PIN_AFIO_AF(GPIOB_ARD_D14, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D36, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D35, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D19, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D18, 11U) | \ + PIN_AFIO_AF(GPIOB_LED3, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D17, 0U)) /* * GPIOC setup: * - * PC0 - ULPI_STP (alternate 10). + * PC0 - ARD_A1 ADC123_IN10 (input pullup). * PC1 - RMII_MDC (alternate 11). - * PC2 - ARD_A2 (input pullup). - * PC3 - DFSDM_DATIN1 (alternate 3). + * PC2 - ZIO_A7 ADC123_IN12 (input pullup). + * PC3 - ARD_A2 ADC123_IN13 (input pullup). * PC4 - RMII_RXD0 (alternate 11). * PC5 - RMII_RXD1 (alternate 11). - * PC6 - ARD_D1 (input pullup). - * PC7 - ARD_D0 (input floating). - * PC8 - ARD_D5 (input floating). - * PC9 - QSPI_D0 (alternate 9). - * PC10 - QSPI_D1 (alternate 9). - * PC11 - DFSDM_DATIN5 (alternate 3). - * PC12 - WIFI_RX (alternate 8). - * PC13 - PIN13 (input pullup). + * PC6 - ZIO_D16 I2S2_MCK (input pullup). + * PC7 - ZIO_D21 I2S3_MCK (input pullup). + * PC8 - ZIO_D43 SDMMC_D0 (input pullup). + * PC9 - ZIO_D44 SDMMC_D1 (input pullup). + * PC10 - ZIO_D45 SDMMC_D2 (input pullup). + * PC11 - ZIO_D46 SDMMC_D3 (input pullup). + * PC12 - ZIO_D47 SDMMC_CK (input pullup). + * PC13 - BUTTON (input floating). * PC14 - OSC32_IN (input floating). * PC15 - OSC32_OUT (input floating). */ -#define VAL_GPIOC_MODER (PIN_MODE_ALTERNATE(GPIOC_ULPI_STP) | \ +#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_ARD_A1) | \ PIN_MODE_ALTERNATE(GPIOC_RMII_MDC) | \ + PIN_MODE_INPUT(GPIOC_ZIO_A7) | \ PIN_MODE_INPUT(GPIOC_ARD_A2) | \ - PIN_MODE_ALTERNATE(GPIOC_DFSDM_DATIN1) |\ PIN_MODE_ALTERNATE(GPIOC_RMII_RXD0) | \ PIN_MODE_ALTERNATE(GPIOC_RMII_RXD1) | \ - PIN_MODE_INPUT(GPIOC_ARD_D1) | \ - PIN_MODE_INPUT(GPIOC_ARD_D0) | \ - PIN_MODE_INPUT(GPIOC_ARD_D5) | \ - PIN_MODE_ALTERNATE(GPIOC_QSPI_D0) | \ - PIN_MODE_ALTERNATE(GPIOC_QSPI_D1) | \ - PIN_MODE_ALTERNATE(GPIOC_DFSDM_DATIN5) |\ - PIN_MODE_ALTERNATE(GPIOC_WIFI_RX) | \ - PIN_MODE_INPUT(GPIOC_PIN13) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D16) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D21) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D43) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D44) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D45) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D46) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D47) | \ + PIN_MODE_INPUT(GPIOC_BUTTON) | \ PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ PIN_MODE_INPUT(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ULPI_STP) | \ +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ARD_A1) | \ PIN_OTYPE_PUSHPULL(GPIOC_RMII_MDC) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_A7) | \ PIN_OTYPE_PUSHPULL(GPIOC_ARD_A2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_DFSDM_DATIN1) |\ PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD0) | \ PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_ARD_D1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_ARD_D0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_ARD_D5) | \ - PIN_OTYPE_PUSHPULL(GPIOC_QSPI_D0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_QSPI_D1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_DFSDM_DATIN5) |\ - PIN_OTYPE_PUSHPULL(GPIOC_WIFI_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D16) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D21) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D43) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D44) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D45) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D46) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D47) | \ + PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_ULPI_STP) | \ +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_ARD_A1) | \ PIN_OSPEED_HIGH(GPIOC_RMII_MDC) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_A7) | \ PIN_OSPEED_HIGH(GPIOC_ARD_A2) | \ - PIN_OSPEED_HIGH(GPIOC_DFSDM_DATIN1) | \ PIN_OSPEED_HIGH(GPIOC_RMII_RXD0) | \ PIN_OSPEED_HIGH(GPIOC_RMII_RXD1) | \ - PIN_OSPEED_HIGH(GPIOC_ARD_D1) | \ - PIN_OSPEED_HIGH(GPIOC_ARD_D0) | \ - PIN_OSPEED_HIGH(GPIOC_ARD_D5) | \ - PIN_OSPEED_HIGH(GPIOC_QSPI_D0) | \ - PIN_OSPEED_HIGH(GPIOC_QSPI_D1) | \ - PIN_OSPEED_HIGH(GPIOC_DFSDM_DATIN5) | \ - PIN_OSPEED_HIGH(GPIOC_WIFI_RX) | \ - PIN_OSPEED_HIGH(GPIOC_PIN13) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D16) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D21) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D43) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D44) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D45) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D46) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D47) | \ + PIN_OSPEED_HIGH(GPIOC_BUTTON) | \ PIN_OSPEED_VERYLOW(GPIOC_OSC32_IN) | \ PIN_OSPEED_VERYLOW(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_ULPI_STP) | \ +#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_ARD_A1) | \ PIN_PUPDR_FLOATING(GPIOC_RMII_MDC) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_A7) | \ PIN_PUPDR_PULLUP(GPIOC_ARD_A2) | \ - PIN_PUPDR_FLOATING(GPIOC_DFSDM_DATIN1) |\ PIN_PUPDR_FLOATING(GPIOC_RMII_RXD0) | \ PIN_PUPDR_FLOATING(GPIOC_RMII_RXD1) | \ - PIN_PUPDR_PULLUP(GPIOC_ARD_D1) | \ - PIN_PUPDR_FLOATING(GPIOC_ARD_D0) | \ - PIN_PUPDR_FLOATING(GPIOC_ARD_D5) | \ - PIN_PUPDR_FLOATING(GPIOC_QSPI_D0) | \ - PIN_PUPDR_FLOATING(GPIOC_QSPI_D1) | \ - PIN_PUPDR_FLOATING(GPIOC_DFSDM_DATIN5) |\ - PIN_PUPDR_FLOATING(GPIOC_WIFI_RX) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D16) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D21) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D43) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D44) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D45) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D46) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D47) | \ + PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \ PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_ULPI_STP) | \ +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_ARD_A1) | \ PIN_ODR_HIGH(GPIOC_RMII_MDC) | \ + PIN_ODR_HIGH(GPIOC_ZIO_A7) | \ PIN_ODR_HIGH(GPIOC_ARD_A2) | \ - PIN_ODR_HIGH(GPIOC_DFSDM_DATIN1) | \ PIN_ODR_HIGH(GPIOC_RMII_RXD0) | \ PIN_ODR_HIGH(GPIOC_RMII_RXD1) | \ - PIN_ODR_HIGH(GPIOC_ARD_D1) | \ - PIN_ODR_HIGH(GPIOC_ARD_D0) | \ - PIN_ODR_HIGH(GPIOC_ARD_D5) | \ - PIN_ODR_HIGH(GPIOC_QSPI_D0) | \ - PIN_ODR_HIGH(GPIOC_QSPI_D1) | \ - PIN_ODR_HIGH(GPIOC_DFSDM_DATIN5) | \ - PIN_ODR_HIGH(GPIOC_WIFI_RX) | \ - PIN_ODR_HIGH(GPIOC_PIN13) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D16) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D21) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D43) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D44) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D45) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D46) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D47) | \ + PIN_ODR_HIGH(GPIOC_BUTTON) | \ PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ PIN_ODR_HIGH(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ULPI_STP, 10U) | \ +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ARD_A1, 0U) | \ PIN_AFIO_AF(GPIOC_RMII_MDC, 11U) | \ + PIN_AFIO_AF(GPIOC_ZIO_A7, 0U) | \ PIN_AFIO_AF(GPIOC_ARD_A2, 0U) | \ - PIN_AFIO_AF(GPIOC_DFSDM_DATIN1, 3U) | \ PIN_AFIO_AF(GPIOC_RMII_RXD0, 11U) | \ PIN_AFIO_AF(GPIOC_RMII_RXD1, 11U) | \ - PIN_AFIO_AF(GPIOC_ARD_D1, 0U) | \ - PIN_AFIO_AF(GPIOC_ARD_D0, 0U)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_ARD_D5, 0U) | \ - PIN_AFIO_AF(GPIOC_QSPI_D0, 9U) | \ - PIN_AFIO_AF(GPIOC_QSPI_D1, 9U) | \ - PIN_AFIO_AF(GPIOC_DFSDM_DATIN5, 3U) | \ - PIN_AFIO_AF(GPIOC_WIFI_RX, 8U) | \ - PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D16, 0U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D21, 0U)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_ZIO_D43, 0U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D44, 0U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D45, 0U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D46, 0U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D47, 0U) | \ + PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \ PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) /* * GPIOD setup: * - * PD0 - FMC_D2 (alternate 12). - * PD1 - FMC_D3 (alternate 12). - * PD2 - WIFI_TX (alternate 8). - * PD3 - DFSDM_CKOUT (alternate 3). - * PD4 - OTG_HS_OVER_CURRENT (input floating). - * PD5 - RMII_RXER (alternate 11). - * PD6 - SD_CLK (alternate 11). - * PD7 - SD_CMD (alternate 11). - * PD8 - FMC_D13 (alternate 12). - * PD9 - FMC_D14 (alternate 12). - * PD10 - FMC_D15 (alternate 12). - * PD11 - SPDIF_I2S (alternate 10). - * PD12 - AUDIO_SCL LCD_SCL (alternate 4). - * PD13 - QSPI_D3 (alternate 9). - * PD14 - FMC_D0 (alternate 12). - * PD15 - FMC_D1 (alternate 12). + * PD0 - ZIO_D67 CAN1_RX (input pullup). + * PD1 - ZIO_D66 CAN1_TX (input pullup). + * PD2 - ZIO_D48 SDMMC_CMD (input pullup). + * PD3 - ZIO_D55 USART2_CTS (input pullup). + * PD4 - ZIO_D54 USART2_RTS (input pullup). + * PD5 - ZIO_D53 USART2_TX (input pullup). + * PD6 - ZIO_D52 USART2_RX (input pullup). + * PD7 - ZIO_D51 USART2_SCLK (input pullup). + * PD8 - USART3_RX STLK_RX (alternate 7). + * PD9 - USART3_TX STLK_TX (alternate 7). + * PD10 - PIN10 (input pullup). + * PD11 - ZIO_D30 QSPI_BK1_IO0 (input pullup). + * PD12 - ZIO_D29 QSPI_BK1_IO1 (input pullup). + * PD13 - ZIO_D28 QSPI_BK1_IO3 (input pullup). + * PD14 - ARD_D10 SPI1_NSS (input pullup). + * PD15 - ARD_D9 TIM4_CH4 (input pullup). */ -#define VAL_GPIOD_MODER (PIN_MODE_ALTERNATE(GPIOD_FMC_D2) | \ - PIN_MODE_ALTERNATE(GPIOD_FMC_D3) | \ - PIN_MODE_ALTERNATE(GPIOD_WIFI_TX) | \ - PIN_MODE_ALTERNATE(GPIOD_DFSDM_CKOUT) |\ - PIN_MODE_INPUT(GPIOD_OTG_HS_OVER_CURRENT) |\ - PIN_MODE_ALTERNATE(GPIOD_RMII_RXER) | \ - PIN_MODE_ALTERNATE(GPIOD_SD_CLK) | \ - PIN_MODE_ALTERNATE(GPIOD_SD_CMD) | \ - PIN_MODE_ALTERNATE(GPIOD_FMC_D13) | \ - PIN_MODE_ALTERNATE(GPIOD_FMC_D14) | \ - PIN_MODE_ALTERNATE(GPIOD_FMC_D15) | \ - PIN_MODE_ALTERNATE(GPIOD_SPDIF_I2S) | \ - PIN_MODE_ALTERNATE(GPIOD_AUDIO_SCL) | \ - PIN_MODE_ALTERNATE(GPIOD_QSPI_D3) | \ - PIN_MODE_ALTERNATE(GPIOD_FMC_D0) | \ - PIN_MODE_ALTERNATE(GPIOD_FMC_D1)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_FMC_D2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_FMC_D3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_WIFI_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOD_DFSDM_CKOUT) |\ - PIN_OTYPE_PUSHPULL(GPIOD_OTG_HS_OVER_CURRENT) |\ - PIN_OTYPE_PUSHPULL(GPIOD_RMII_RXER) | \ - PIN_OTYPE_PUSHPULL(GPIOD_SD_CLK) | \ - PIN_OTYPE_PUSHPULL(GPIOD_SD_CMD) | \ - PIN_OTYPE_PUSHPULL(GPIOD_FMC_D13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_FMC_D14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_FMC_D15) | \ - PIN_OTYPE_PUSHPULL(GPIOD_SPDIF_I2S) | \ - PIN_OTYPE_PUSHPULL(GPIOD_AUDIO_SCL) | \ - PIN_OTYPE_PUSHPULL(GPIOD_QSPI_D3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_FMC_D0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_FMC_D1)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_FMC_D2) | \ - PIN_OSPEED_HIGH(GPIOD_FMC_D3) | \ - PIN_OSPEED_HIGH(GPIOD_WIFI_TX) | \ - PIN_OSPEED_HIGH(GPIOD_DFSDM_CKOUT) | \ - PIN_OSPEED_HIGH(GPIOD_OTG_HS_OVER_CURRENT) |\ - PIN_OSPEED_HIGH(GPIOD_RMII_RXER) | \ - PIN_OSPEED_HIGH(GPIOD_SD_CLK) | \ - PIN_OSPEED_HIGH(GPIOD_SD_CMD) | \ - PIN_OSPEED_HIGH(GPIOD_FMC_D13) | \ - PIN_OSPEED_HIGH(GPIOD_FMC_D14) | \ - PIN_OSPEED_HIGH(GPIOD_FMC_D15) | \ - PIN_OSPEED_HIGH(GPIOD_SPDIF_I2S) | \ - PIN_OSPEED_HIGH(GPIOD_AUDIO_SCL) | \ - PIN_OSPEED_HIGH(GPIOD_QSPI_D3) | \ - PIN_OSPEED_HIGH(GPIOD_FMC_D0) | \ - PIN_OSPEED_HIGH(GPIOD_FMC_D1)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_FMC_D2) | \ - PIN_PUPDR_FLOATING(GPIOD_FMC_D3) | \ - PIN_PUPDR_FLOATING(GPIOD_WIFI_TX) | \ - PIN_PUPDR_FLOATING(GPIOD_DFSDM_CKOUT) |\ - PIN_PUPDR_FLOATING(GPIOD_OTG_HS_OVER_CURRENT) |\ - PIN_PUPDR_FLOATING(GPIOD_RMII_RXER) | \ - PIN_PUPDR_FLOATING(GPIOD_SD_CLK) | \ - PIN_PUPDR_FLOATING(GPIOD_SD_CMD) | \ - PIN_PUPDR_FLOATING(GPIOD_FMC_D13) | \ - PIN_PUPDR_FLOATING(GPIOD_FMC_D14) | \ - PIN_PUPDR_FLOATING(GPIOD_FMC_D15) | \ - PIN_PUPDR_FLOATING(GPIOD_SPDIF_I2S) | \ - PIN_PUPDR_FLOATING(GPIOD_AUDIO_SCL) | \ - PIN_PUPDR_FLOATING(GPIOD_QSPI_D3) | \ - PIN_PUPDR_FLOATING(GPIOD_FMC_D0) | \ - PIN_PUPDR_FLOATING(GPIOD_FMC_D1)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_FMC_D2) | \ - PIN_ODR_HIGH(GPIOD_FMC_D3) | \ - PIN_ODR_HIGH(GPIOD_WIFI_TX) | \ - PIN_ODR_HIGH(GPIOD_DFSDM_CKOUT) | \ - PIN_ODR_HIGH(GPIOD_OTG_HS_OVER_CURRENT) |\ - PIN_ODR_HIGH(GPIOD_RMII_RXER) | \ - PIN_ODR_HIGH(GPIOD_SD_CLK) | \ - PIN_ODR_HIGH(GPIOD_SD_CMD) | \ - PIN_ODR_HIGH(GPIOD_FMC_D13) | \ - PIN_ODR_HIGH(GPIOD_FMC_D14) | \ - PIN_ODR_HIGH(GPIOD_FMC_D15) | \ - PIN_ODR_HIGH(GPIOD_SPDIF_I2S) | \ - PIN_ODR_HIGH(GPIOD_AUDIO_SCL) | \ - PIN_ODR_HIGH(GPIOD_QSPI_D3) | \ - PIN_ODR_LOW(GPIOD_FMC_D0) | \ - PIN_ODR_LOW(GPIOD_FMC_D1)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_FMC_D2, 12U) | \ - PIN_AFIO_AF(GPIOD_FMC_D3, 12U) | \ - PIN_AFIO_AF(GPIOD_WIFI_TX, 8U) | \ - PIN_AFIO_AF(GPIOD_DFSDM_CKOUT, 3U) | \ - PIN_AFIO_AF(GPIOD_OTG_HS_OVER_CURRENT, 0U) |\ - PIN_AFIO_AF(GPIOD_RMII_RXER, 11U) | \ - PIN_AFIO_AF(GPIOD_SD_CLK, 11U) | \ - PIN_AFIO_AF(GPIOD_SD_CMD, 11U)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_FMC_D13, 12U) | \ - PIN_AFIO_AF(GPIOD_FMC_D14, 12U) | \ - PIN_AFIO_AF(GPIOD_FMC_D15, 12U) | \ - PIN_AFIO_AF(GPIOD_SPDIF_I2S, 10U) | \ - PIN_AFIO_AF(GPIOD_AUDIO_SCL, 4U) | \ - PIN_AFIO_AF(GPIOD_QSPI_D3, 9U) | \ - PIN_AFIO_AF(GPIOD_FMC_D0, 12U) | \ - PIN_AFIO_AF(GPIOD_FMC_D1, 12U)) +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_ZIO_D67) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D66) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D48) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D55) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D54) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D53) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D52) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D51) | \ + PIN_MODE_ALTERNATE(GPIOD_USART3_RX) | \ + PIN_MODE_ALTERNATE(GPIOD_USART3_TX) | \ + PIN_MODE_INPUT(GPIOD_PIN10) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D30) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D29) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D28) | \ + PIN_MODE_INPUT(GPIOD_ARD_D10) | \ + PIN_MODE_INPUT(GPIOD_ARD_D9)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D67) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D66) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D48) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D55) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D54) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D53) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D52) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D51) | \ + PIN_OTYPE_PUSHPULL(GPIOD_USART3_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_USART3_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D30) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D29) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D28) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ARD_D10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ARD_D9)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_ZIO_D67) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D66) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D48) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D55) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D54) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D53) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D52) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D51) | \ + PIN_OSPEED_HIGH(GPIOD_USART3_RX) | \ + PIN_OSPEED_HIGH(GPIOD_USART3_TX) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN10) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D30) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D29) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D28) | \ + PIN_OSPEED_HIGH(GPIOD_ARD_D10) | \ + PIN_OSPEED_HIGH(GPIOD_ARD_D9)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_ZIO_D67) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D66) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D48) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D55) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D54) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D53) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D52) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D51) | \ + PIN_PUPDR_FLOATING(GPIOD_USART3_RX) | \ + PIN_PUPDR_FLOATING(GPIOD_USART3_TX) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D30) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D29) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D28) | \ + PIN_PUPDR_PULLUP(GPIOD_ARD_D10) | \ + PIN_PUPDR_PULLUP(GPIOD_ARD_D9)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_ZIO_D67) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D66) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D48) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D55) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D54) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D53) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D52) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D51) | \ + PIN_ODR_HIGH(GPIOD_USART3_RX) | \ + PIN_ODR_HIGH(GPIOD_USART3_TX) | \ + PIN_ODR_HIGH(GPIOD_PIN10) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D30) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D29) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D28) | \ + PIN_ODR_HIGH(GPIOD_ARD_D10) | \ + PIN_ODR_HIGH(GPIOD_ARD_D9)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_ZIO_D67, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D66, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D48, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D55, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D54, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D53, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D52, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D51, 0U)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_USART3_RX, 7U) | \ + PIN_AFIO_AF(GPIOD_USART3_TX, 7U) | \ + PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D30, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D29, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D28, 0U) | \ + PIN_AFIO_AF(GPIOD_ARD_D10, 0U) | \ + PIN_AFIO_AF(GPIOD_ARD_D9, 0U)) /* * GPIOE setup: * - * PE0 - FMC_NBL0 (alternate 12). - * PE1 - FMC_NBL1 (alternate 12). - * PE2 - QSPI_D2 (alternate 9). - * PE3 - SAI1_SDB (alternate 6). - * PE4 - SAI1_FSA (alternate 6). - * PE5 - SAI1_SCKA (alternate 6). - * PE6 - SAI1_SDA (alternate 6). - * PE7 - FMC_D4 (alternate 12). - * PE8 - FMC_D5 (alternate 12). - * PE9 - FMC_D6 (alternate 12). - * PE10 - FMC_D7 (alternate 12). - * PE11 - FMC_D8 (alternate 12). - * PE12 - FMC_D9 (alternate 12). - * PE13 - FMC_D10 (alternate 12). - * PE14 - FMC_11 (alternate 12). - * PE15 - FMC_D12 (alternate 12). + * PE0 - ZIO_D34 TIM4_ETR (input pullup). + * PE1 - PIN1 (input pullup). + * PE2 - ZIO_D31 ZIO_D56 SAI1_MCLK_A(input pullup). + * PE3 - ZIO_D60 SAI1_SD_B (input pullup). + * PE4 - ZIO_D57 SAI1_FS_A (input pullup). + * PE5 - ZIO_D58 SAI1_SCK_A (input pullup). + * PE6 - ZIO_D59 SAI1_SD_A (input pullup). + * PE7 - ZIO_D41 TIM1_ETR (input pullup). + * PE8 - ZIO_D42 TIM1_CH1N (input pullup). + * PE9 - ARD_D6 TIM1_CH1 (input pullup). + * PE10 - ZIO_D40 TIM1_CH2N (input pullup). + * PE11 - ARD_D5 TIM1_CH2 (input pullup). + * PE12 - ZIO_D39 TIM1_CH3N (input pullup). + * PE13 - ARD_D3 TIM1_CH3 (input pullup). + * PE14 - ZIO_D38 (input pullup). + * PE15 - ZIO_D37 TIM1_BKIN1 (input pullup). */ -#define VAL_GPIOE_MODER (PIN_MODE_ALTERNATE(GPIOE_FMC_NBL0) | \ - PIN_MODE_ALTERNATE(GPIOE_FMC_NBL1) | \ - PIN_MODE_ALTERNATE(GPIOE_QSPI_D2) | \ - PIN_MODE_ALTERNATE(GPIOE_SAI1_SDB) | \ - PIN_MODE_ALTERNATE(GPIOE_SAI1_FSA) | \ - PIN_MODE_ALTERNATE(GPIOE_SAI1_SCKA) | \ - PIN_MODE_ALTERNATE(GPIOE_SAI1_SDA) | \ - PIN_MODE_ALTERNATE(GPIOE_FMC_D4) | \ - PIN_MODE_ALTERNATE(GPIOE_FMC_D5) | \ - PIN_MODE_ALTERNATE(GPIOE_FMC_D6) | \ - PIN_MODE_ALTERNATE(GPIOE_FMC_D7) | \ - PIN_MODE_ALTERNATE(GPIOE_FMC_D8) | \ - PIN_MODE_ALTERNATE(GPIOE_FMC_D9) | \ - PIN_MODE_ALTERNATE(GPIOE_FMC_D10) | \ - PIN_MODE_ALTERNATE(GPIOE_FMC_11) | \ - PIN_MODE_ALTERNATE(GPIOE_FMC_D12)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_FMC_NBL0) | \ - PIN_OTYPE_PUSHPULL(GPIOE_FMC_NBL1) | \ - PIN_OTYPE_PUSHPULL(GPIOE_QSPI_D2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_SAI1_SDB) | \ - PIN_OTYPE_PUSHPULL(GPIOE_SAI1_FSA) | \ - PIN_OTYPE_PUSHPULL(GPIOE_SAI1_SCKA) | \ - PIN_OTYPE_PUSHPULL(GPIOE_SAI1_SDA) | \ - PIN_OTYPE_PUSHPULL(GPIOE_FMC_D4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_FMC_D5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_FMC_D6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_FMC_D7) | \ - PIN_OTYPE_PUSHPULL(GPIOE_FMC_D8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_FMC_D9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_FMC_D10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_FMC_11) | \ - PIN_OTYPE_PUSHPULL(GPIOE_FMC_D12)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_FMC_NBL0) | \ - PIN_OSPEED_HIGH(GPIOE_FMC_NBL1) | \ - PIN_OSPEED_HIGH(GPIOE_QSPI_D2) | \ - PIN_OSPEED_HIGH(GPIOE_SAI1_SDB) | \ - PIN_OSPEED_HIGH(GPIOE_SAI1_FSA) | \ - PIN_OSPEED_HIGH(GPIOE_SAI1_SCKA) | \ - PIN_OSPEED_HIGH(GPIOE_SAI1_SDA) | \ - PIN_OSPEED_HIGH(GPIOE_FMC_D4) | \ - PIN_OSPEED_HIGH(GPIOE_FMC_D5) | \ - PIN_OSPEED_HIGH(GPIOE_FMC_D6) | \ - PIN_OSPEED_HIGH(GPIOE_FMC_D7) | \ - PIN_OSPEED_HIGH(GPIOE_FMC_D8) | \ - PIN_OSPEED_HIGH(GPIOE_FMC_D9) | \ - PIN_OSPEED_HIGH(GPIOE_FMC_D10) | \ - PIN_OSPEED_HIGH(GPIOE_FMC_11) | \ - PIN_OSPEED_HIGH(GPIOE_FMC_D12)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_FMC_NBL0) | \ - PIN_PUPDR_FLOATING(GPIOE_FMC_NBL1) | \ - PIN_PUPDR_FLOATING(GPIOE_QSPI_D2) | \ - PIN_PUPDR_FLOATING(GPIOE_SAI1_SDB) | \ - PIN_PUPDR_FLOATING(GPIOE_SAI1_FSA) | \ - PIN_PUPDR_FLOATING(GPIOE_SAI1_SCKA) | \ - PIN_PUPDR_FLOATING(GPIOE_SAI1_SDA) | \ - PIN_PUPDR_FLOATING(GPIOE_FMC_D4) | \ - PIN_PUPDR_FLOATING(GPIOE_FMC_D5) | \ - PIN_PUPDR_FLOATING(GPIOE_FMC_D6) | \ - PIN_PUPDR_FLOATING(GPIOE_FMC_D7) | \ - PIN_PUPDR_FLOATING(GPIOE_FMC_D8) | \ - PIN_PUPDR_FLOATING(GPIOE_FMC_D9) | \ - PIN_PUPDR_FLOATING(GPIOE_FMC_D10) | \ - PIN_PUPDR_FLOATING(GPIOE_FMC_11) | \ - PIN_PUPDR_FLOATING(GPIOE_FMC_D12)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_FMC_NBL0) | \ - PIN_ODR_HIGH(GPIOE_FMC_NBL1) | \ - PIN_ODR_HIGH(GPIOE_QSPI_D2) | \ - PIN_ODR_HIGH(GPIOE_SAI1_SDB) | \ - PIN_ODR_HIGH(GPIOE_SAI1_FSA) | \ - PIN_ODR_HIGH(GPIOE_SAI1_SCKA) | \ - PIN_ODR_HIGH(GPIOE_SAI1_SDA) | \ - PIN_ODR_HIGH(GPIOE_FMC_D4) | \ - PIN_ODR_HIGH(GPIOE_FMC_D5) | \ - PIN_ODR_HIGH(GPIOE_FMC_D6) | \ - PIN_ODR_HIGH(GPIOE_FMC_D7) | \ - PIN_ODR_HIGH(GPIOE_FMC_D8) | \ - PIN_ODR_HIGH(GPIOE_FMC_D9) | \ - PIN_ODR_HIGH(GPIOE_FMC_D10) | \ - PIN_ODR_HIGH(GPIOE_FMC_11) | \ - PIN_ODR_HIGH(GPIOE_FMC_D12)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_FMC_NBL0, 12U) | \ - PIN_AFIO_AF(GPIOE_FMC_NBL1, 12U) | \ - PIN_AFIO_AF(GPIOE_QSPI_D2, 9U) | \ - PIN_AFIO_AF(GPIOE_SAI1_SDB, 6U) | \ - PIN_AFIO_AF(GPIOE_SAI1_FSA, 6U) | \ - PIN_AFIO_AF(GPIOE_SAI1_SCKA, 6U) | \ - PIN_AFIO_AF(GPIOE_SAI1_SDA, 6U) | \ - PIN_AFIO_AF(GPIOE_FMC_D4, 12U)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_FMC_D5, 12U) | \ - PIN_AFIO_AF(GPIOE_FMC_D6, 12U) | \ - PIN_AFIO_AF(GPIOE_FMC_D7, 12U) | \ - PIN_AFIO_AF(GPIOE_FMC_D8, 12U) | \ - PIN_AFIO_AF(GPIOE_FMC_D9, 12U) | \ - PIN_AFIO_AF(GPIOE_FMC_D10, 12U) | \ - PIN_AFIO_AF(GPIOE_FMC_11, 12U) | \ - PIN_AFIO_AF(GPIOE_FMC_D12, 12U)) +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_ZIO_D34) | \ + PIN_MODE_INPUT(GPIOE_PIN1) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D31) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D60) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D57) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D58) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D59) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D41) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D42) | \ + PIN_MODE_INPUT(GPIOE_ARD_D6) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D40) | \ + PIN_MODE_INPUT(GPIOE_ARD_D5) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D39) | \ + PIN_MODE_INPUT(GPIOE_ARD_D3) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D38) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D37)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D34) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D31) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D60) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D57) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D58) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D59) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D41) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D42) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ARD_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D40) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ARD_D5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D39) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ARD_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D38) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D37)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_ZIO_D34) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN1) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D31) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D60) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D57) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D58) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D59) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D41) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D42) | \ + PIN_OSPEED_HIGH(GPIOE_ARD_D6) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D40) | \ + PIN_OSPEED_HIGH(GPIOE_ARD_D5) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D39) | \ + PIN_OSPEED_HIGH(GPIOE_ARD_D3) | \ + PIN_OSPEED_VERYLOW(GPIOE_ZIO_D38) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D37)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_ZIO_D34) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D31) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D60) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D57) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D58) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D59) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D41) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D42) | \ + PIN_PUPDR_PULLUP(GPIOE_ARD_D6) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D40) | \ + PIN_PUPDR_PULLUP(GPIOE_ARD_D5) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D39) | \ + PIN_PUPDR_PULLUP(GPIOE_ARD_D3) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D38) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D37)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_ZIO_D34) | \ + PIN_ODR_HIGH(GPIOE_PIN1) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D31) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D60) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D57) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D58) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D59) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D41) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D42) | \ + PIN_ODR_HIGH(GPIOE_ARD_D6) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D40) | \ + PIN_ODR_HIGH(GPIOE_ARD_D5) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D39) | \ + PIN_ODR_HIGH(GPIOE_ARD_D3) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D38) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D37)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_ZIO_D34, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D31, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D60, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D57, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D58, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D59, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D41, 0U)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_ZIO_D42, 0U) | \ + PIN_AFIO_AF(GPIOE_ARD_D6, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D40, 0U) | \ + PIN_AFIO_AF(GPIOE_ARD_D5, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D39, 0U) | \ + PIN_AFIO_AF(GPIOE_ARD_D3, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D38, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D37, 0U)) /* * GPIOF setup: * - * PF0 - FMC_A0 (alternate 12). - * PF1 - FMC_A1 (alternate 12). - * PF2 - FMC_A2 (alternate 12). - * PF3 - FMC_A3 (alternate 12). - * PF4 - FMC_A4 (alternate 12). - * PF5 - FMC_A5 (alternate 12). - * PF6 - ARD_D3 (input pullup). - * PF7 - ARD_D6 (input pullup). - * PF8 - ARD_A4 (input pullup). - * PF9 - ARD_A5 (input pullup). - * PF10 - ARD_A3 (input pullup). - * PF11 - FMC_SDNRAS (alternate 12). - * PF12 - FMC_A6 (alternate 12). - * PF13 - FMC_A7 (alternate 12). - * PF14 - FMC_A8 (alternate 12). - * PF15 - FMC_A9 (alternate 12). + * PF0 - ZIO_D68 I2C2_SDA (input pullup). + * PF1 - ZIO_D69 I2C2_SCL (input pullup). + * PF2 - ZIO_D70 I2C2_SMBA (input pullup). + * PF3 - ARD_A3 ADC3_IN9 (input pullup). + * PF4 - ZIO_A8 ADC3_IN14 (input pullup). + * PF5 - ARD_A4 ADC3_IN15 (input pullup). + * PF6 - PIN6 (input pullup). + * PF7 - ZIO_D62 SAI1_MCLK_B (input pullup). + * PF8 - ZIO_D61 SAI1_SCK_B (input pullup). + * PF9 - ZIO_D63 SAI1_FS_B (input pullup). + * PF10 - ARD_A5 ADC3_IN8 (input pullup). + * PF11 - PIN11 (input pullup). + * PF12 - ARD_D8 (input pullup). + * PF13 - ARD_D7 (input pullup). + * PF14 - ARD_D4 (input pullup). + * PF15 - ARD_D2 (input pullup). */ -#define VAL_GPIOF_MODER (PIN_MODE_ALTERNATE(GPIOF_FMC_A0) | \ - PIN_MODE_ALTERNATE(GPIOF_FMC_A1) | \ - PIN_MODE_ALTERNATE(GPIOF_FMC_A2) | \ - PIN_MODE_ALTERNATE(GPIOF_FMC_A3) | \ - PIN_MODE_ALTERNATE(GPIOF_FMC_A4) | \ - PIN_MODE_ALTERNATE(GPIOF_FMC_A5) | \ - PIN_MODE_INPUT(GPIOF_ARD_D3) | \ - PIN_MODE_INPUT(GPIOF_ARD_D6) | \ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_ZIO_D68) | \ + PIN_MODE_INPUT(GPIOF_ZIO_D69) | \ + PIN_MODE_INPUT(GPIOF_ZIO_D70) | \ + PIN_MODE_INPUT(GPIOF_ARD_A3) | \ + PIN_MODE_INPUT(GPIOF_ZIO_A8) | \ PIN_MODE_INPUT(GPIOF_ARD_A4) | \ + PIN_MODE_INPUT(GPIOF_PIN6) | \ + PIN_MODE_INPUT(GPIOF_ZIO_D62) | \ + PIN_MODE_INPUT(GPIOF_ZIO_D61) | \ + PIN_MODE_INPUT(GPIOF_ZIO_D63) | \ PIN_MODE_INPUT(GPIOF_ARD_A5) | \ - PIN_MODE_INPUT(GPIOF_ARD_A3) | \ - PIN_MODE_ALTERNATE(GPIOF_FMC_SDNRAS) | \ - PIN_MODE_ALTERNATE(GPIOF_FMC_A6) | \ - PIN_MODE_ALTERNATE(GPIOF_FMC_A7) | \ - PIN_MODE_ALTERNATE(GPIOF_FMC_A8) | \ - PIN_MODE_ALTERNATE(GPIOF_FMC_A9)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_FMC_A0) | \ - PIN_OTYPE_PUSHPULL(GPIOF_FMC_A1) | \ - PIN_OTYPE_PUSHPULL(GPIOF_FMC_A2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_FMC_A3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_FMC_A4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_FMC_A5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_ARD_D3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_ARD_D6) | \ + PIN_MODE_INPUT(GPIOF_PIN11) | \ + PIN_MODE_INPUT(GPIOF_ARD_D8) | \ + PIN_MODE_INPUT(GPIOF_ARD_D7) | \ + PIN_MODE_INPUT(GPIOF_ARD_D4) | \ + PIN_MODE_INPUT(GPIOF_ARD_D2)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D68) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D69) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D70) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_A3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ZIO_A8) | \ PIN_OTYPE_PUSHPULL(GPIOF_ARD_A4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D62) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D61) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D63) | \ PIN_OTYPE_PUSHPULL(GPIOF_ARD_A5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_ARD_A3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_FMC_SDNRAS) | \ - PIN_OTYPE_PUSHPULL(GPIOF_FMC_A6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_FMC_A7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_FMC_A8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_FMC_A9)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_FMC_A0) | \ - PIN_OSPEED_HIGH(GPIOF_FMC_A1) | \ - PIN_OSPEED_HIGH(GPIOF_FMC_A2) | \ - PIN_OSPEED_HIGH(GPIOF_FMC_A3) | \ - PIN_OSPEED_HIGH(GPIOF_FMC_A4) | \ - PIN_OSPEED_HIGH(GPIOF_FMC_A5) | \ - PIN_OSPEED_HIGH(GPIOF_ARD_D3) | \ - PIN_OSPEED_HIGH(GPIOF_ARD_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_D8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_D7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_D4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_D2)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_ZIO_D68) | \ + PIN_OSPEED_HIGH(GPIOF_ZIO_D69) | \ + PIN_OSPEED_HIGH(GPIOF_ZIO_D70) | \ + PIN_OSPEED_HIGH(GPIOF_ARD_A3) | \ + PIN_OSPEED_HIGH(GPIOF_ZIO_A8) | \ PIN_OSPEED_HIGH(GPIOF_ARD_A4) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN6) | \ + PIN_OSPEED_HIGH(GPIOF_ZIO_D62) | \ + PIN_OSPEED_HIGH(GPIOF_ZIO_D61) | \ + PIN_OSPEED_HIGH(GPIOF_ZIO_D63) | \ PIN_OSPEED_HIGH(GPIOF_ARD_A5) | \ - PIN_OSPEED_HIGH(GPIOF_ARD_A3) | \ - PIN_OSPEED_HIGH(GPIOF_FMC_SDNRAS) | \ - PIN_OSPEED_HIGH(GPIOF_FMC_A6) | \ - PIN_OSPEED_HIGH(GPIOF_FMC_A7) | \ - PIN_OSPEED_HIGH(GPIOF_FMC_A8) | \ - PIN_OSPEED_HIGH(GPIOF_FMC_A9)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_FMC_A0) | \ - PIN_PUPDR_FLOATING(GPIOF_FMC_A1) | \ - PIN_PUPDR_FLOATING(GPIOF_FMC_A2) | \ - PIN_PUPDR_FLOATING(GPIOF_FMC_A3) | \ - PIN_PUPDR_FLOATING(GPIOF_FMC_A4) | \ - PIN_PUPDR_FLOATING(GPIOF_FMC_A5) | \ - PIN_PUPDR_PULLUP(GPIOF_ARD_D3) | \ - PIN_PUPDR_PULLUP(GPIOF_ARD_D6) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOF_ARD_D8) | \ + PIN_OSPEED_VERYLOW(GPIOF_ARD_D7) | \ + PIN_OSPEED_VERYLOW(GPIOF_ARD_D4) | \ + PIN_OSPEED_VERYLOW(GPIOF_ARD_D2)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_ZIO_D68) | \ + PIN_PUPDR_PULLUP(GPIOF_ZIO_D69) | \ + PIN_PUPDR_PULLUP(GPIOF_ZIO_D70) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_A3) | \ + PIN_PUPDR_PULLUP(GPIOF_ZIO_A8) | \ PIN_PUPDR_PULLUP(GPIOF_ARD_A4) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOF_ZIO_D62) | \ + PIN_PUPDR_PULLUP(GPIOF_ZIO_D61) | \ + PIN_PUPDR_PULLUP(GPIOF_ZIO_D63) | \ PIN_PUPDR_PULLUP(GPIOF_ARD_A5) | \ - PIN_PUPDR_PULLUP(GPIOF_ARD_A3) | \ - PIN_PUPDR_FLOATING(GPIOF_FMC_SDNRAS) | \ - PIN_PUPDR_FLOATING(GPIOF_FMC_A6) | \ - PIN_PUPDR_FLOATING(GPIOF_FMC_A7) | \ - PIN_PUPDR_FLOATING(GPIOF_FMC_A8) | \ - PIN_PUPDR_FLOATING(GPIOF_FMC_A9)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_FMC_A0) | \ - PIN_ODR_HIGH(GPIOF_FMC_A1) | \ - PIN_ODR_HIGH(GPIOF_FMC_A2) | \ - PIN_ODR_HIGH(GPIOF_FMC_A3) | \ - PIN_ODR_HIGH(GPIOF_FMC_A4) | \ - PIN_ODR_HIGH(GPIOF_FMC_A5) | \ - PIN_ODR_HIGH(GPIOF_ARD_D3) | \ - PIN_ODR_HIGH(GPIOF_ARD_D6) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_D8) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_D7) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_D4) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_D2)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_ZIO_D68) | \ + PIN_ODR_HIGH(GPIOF_ZIO_D69) | \ + PIN_ODR_HIGH(GPIOF_ZIO_D70) | \ + PIN_ODR_HIGH(GPIOF_ARD_A3) | \ + PIN_ODR_HIGH(GPIOF_ZIO_A8) | \ PIN_ODR_HIGH(GPIOF_ARD_A4) | \ + PIN_ODR_HIGH(GPIOF_PIN6) | \ + PIN_ODR_HIGH(GPIOF_ZIO_D62) | \ + PIN_ODR_HIGH(GPIOF_ZIO_D61) | \ + PIN_ODR_HIGH(GPIOF_ZIO_D63) | \ PIN_ODR_HIGH(GPIOF_ARD_A5) | \ - PIN_ODR_HIGH(GPIOF_ARD_A3) | \ - PIN_ODR_HIGH(GPIOF_FMC_SDNRAS) | \ - PIN_ODR_HIGH(GPIOF_FMC_A6) | \ - PIN_ODR_HIGH(GPIOF_FMC_A7) | \ - PIN_ODR_HIGH(GPIOF_FMC_A8) | \ - PIN_ODR_HIGH(GPIOF_FMC_A9)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_FMC_A0, 12U) | \ - PIN_AFIO_AF(GPIOF_FMC_A1, 12U) | \ - PIN_AFIO_AF(GPIOF_FMC_A2, 12U) | \ - PIN_AFIO_AF(GPIOF_FMC_A3, 12U) | \ - PIN_AFIO_AF(GPIOF_FMC_A4, 12U) | \ - PIN_AFIO_AF(GPIOF_FMC_A5, 12U) | \ - PIN_AFIO_AF(GPIOF_ARD_D3, 0U) | \ - PIN_AFIO_AF(GPIOF_ARD_D6, 0U)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_ARD_A4, 0U) | \ - PIN_AFIO_AF(GPIOF_ARD_A5, 0U) | \ + PIN_ODR_HIGH(GPIOF_PIN11) | \ + PIN_ODR_HIGH(GPIOF_ARD_D8) | \ + PIN_ODR_HIGH(GPIOF_ARD_D7) | \ + PIN_ODR_HIGH(GPIOF_ARD_D4) | \ + PIN_ODR_HIGH(GPIOF_ARD_D2)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_ZIO_D68, 0U) | \ + PIN_AFIO_AF(GPIOF_ZIO_D69, 0U) | \ + PIN_AFIO_AF(GPIOF_ZIO_D70, 0U) | \ PIN_AFIO_AF(GPIOF_ARD_A3, 0U) | \ - PIN_AFIO_AF(GPIOF_FMC_SDNRAS, 12U) | \ - PIN_AFIO_AF(GPIOF_FMC_A6, 12U) | \ - PIN_AFIO_AF(GPIOF_FMC_A7, 12U) | \ - PIN_AFIO_AF(GPIOF_FMC_A8, 12U) | \ - PIN_AFIO_AF(GPIOF_FMC_A9, 12U)) + PIN_AFIO_AF(GPIOF_ZIO_A8, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_A4, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOF_ZIO_D62, 0U)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_ZIO_D61, 0U) | \ + PIN_AFIO_AF(GPIOF_ZIO_D63, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_A5, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_D8, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_D7, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_D4, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_D2, 0U)) /* * GPIOG setup: * - * PG0 - FMC_A10 (alternate 12). - * PG1 - FMC_A11 (alternate 12). - * PG2 - FMC_A12 (alternate 12). - * PG3 - EXT_SCL (input pullup). - * PG4 - FMC_BA0 (alternate 12). - * PG5 - FMC_BA1 (alternate 12). - * PG6 - EXT_SDA (input pullup). - * PG7 - SAI1_MCLKA (alternate 6). - * PG8 - FMC_SDCLK (alternate 12). - * PG9 - SD_D0 (alternate 11). - * PG10 - SD_D1 (alternate 11). + * PG0 - ZIO_D65 (input pullup). + * PG1 - ZIO_D64 (input pullup). + * PG2 - ZIO_D49 (input pullup). + * PG3 - ZIO_D50 (input pullup). + * PG4 - PIN4 (input pullup). + * PG5 - PIN5 (input pullup). + * PG6 - USB_GPIO_OUT (input pullup). + * PG7 - USB_GPIO_IN (input pullup). + * PG8 - PIN8 (input pullup). + * PG9 - ARD_D0 USART6_RX (input pullup). + * PG10 - PIN10 (input pullup). * PG11 - RMII_TX_EN (alternate 11). - * PG12 - SPDIF_RX (alternate 7). + * PG12 - PIN12 (input pullup). * PG13 - RMII_TXD0 (alternate 11). - * PG14 - RMII_TXD1 (alternate 11). - * PG15 - FMC_SDNCAS (alternate 12). + * PG14 - ARD_D1 USART6_TX (input pullup). + * PG15 - PIN15 (input pullup). */ -#define VAL_GPIOG_MODER (PIN_MODE_ALTERNATE(GPIOG_FMC_A10) | \ - PIN_MODE_ALTERNATE(GPIOG_FMC_A11) | \ - PIN_MODE_ALTERNATE(GPIOG_FMC_A12) | \ - PIN_MODE_INPUT(GPIOG_EXT_SCL) | \ - PIN_MODE_ALTERNATE(GPIOG_FMC_BA0) | \ - PIN_MODE_ALTERNATE(GPIOG_FMC_BA1) | \ - PIN_MODE_INPUT(GPIOG_EXT_SDA) | \ - PIN_MODE_ALTERNATE(GPIOG_SAI1_MCLKA) | \ - PIN_MODE_ALTERNATE(GPIOG_FMC_SDCLK) | \ - PIN_MODE_ALTERNATE(GPIOG_SD_D0) | \ - PIN_MODE_ALTERNATE(GPIOG_SD_D1) | \ +#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_ZIO_D65) | \ + PIN_MODE_INPUT(GPIOG_ZIO_D64) | \ + PIN_MODE_INPUT(GPIOG_ZIO_D49) | \ + PIN_MODE_INPUT(GPIOG_ZIO_D50) | \ + PIN_MODE_INPUT(GPIOG_PIN4) | \ + PIN_MODE_INPUT(GPIOG_PIN5) | \ + PIN_MODE_INPUT(GPIOG_USB_GPIO_OUT) | \ + PIN_MODE_INPUT(GPIOG_USB_GPIO_IN) | \ + PIN_MODE_INPUT(GPIOG_PIN8) | \ + PIN_MODE_INPUT(GPIOG_ARD_D0) | \ + PIN_MODE_INPUT(GPIOG_PIN10) | \ PIN_MODE_ALTERNATE(GPIOG_RMII_TX_EN) | \ - PIN_MODE_ALTERNATE(GPIOG_SPDIF_RX) | \ + PIN_MODE_INPUT(GPIOG_PIN12) | \ PIN_MODE_ALTERNATE(GPIOG_RMII_TXD0) | \ - PIN_MODE_ALTERNATE(GPIOG_RMII_TXD1) | \ - PIN_MODE_ALTERNATE(GPIOG_FMC_SDNCAS)) -#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_FMC_A10) | \ - PIN_OTYPE_PUSHPULL(GPIOG_FMC_A11) | \ - PIN_OTYPE_PUSHPULL(GPIOG_FMC_A12) | \ - PIN_OTYPE_PUSHPULL(GPIOG_EXT_SCL) | \ - PIN_OTYPE_PUSHPULL(GPIOG_FMC_BA0) | \ - PIN_OTYPE_PUSHPULL(GPIOG_FMC_BA1) | \ - PIN_OTYPE_PUSHPULL(GPIOG_EXT_SDA) | \ - PIN_OTYPE_PUSHPULL(GPIOG_SAI1_MCLKA) | \ - PIN_OTYPE_PUSHPULL(GPIOG_FMC_SDCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOG_SD_D0) | \ - PIN_OTYPE_PUSHPULL(GPIOG_SD_D1) | \ + PIN_MODE_INPUT(GPIOG_ARD_D1) | \ + PIN_MODE_INPUT(GPIOG_PIN15)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_ZIO_D65) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ZIO_D64) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ZIO_D49) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ZIO_D50) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOG_USB_GPIO_OUT) |\ + PIN_OTYPE_PUSHPULL(GPIOG_USB_GPIO_IN) |\ + PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ARD_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ PIN_OTYPE_PUSHPULL(GPIOG_RMII_TX_EN) | \ - PIN_OTYPE_PUSHPULL(GPIOG_SPDIF_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ PIN_OTYPE_PUSHPULL(GPIOG_RMII_TXD0) | \ - PIN_OTYPE_PUSHPULL(GPIOG_RMII_TXD1) | \ - PIN_OTYPE_PUSHPULL(GPIOG_FMC_SDNCAS)) -#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_FMC_A10) | \ - PIN_OSPEED_HIGH(GPIOG_FMC_A11) | \ - PIN_OSPEED_HIGH(GPIOG_FMC_A12) | \ - PIN_OSPEED_HIGH(GPIOG_EXT_SCL) | \ - PIN_OSPEED_HIGH(GPIOG_FMC_BA0) | \ - PIN_OSPEED_HIGH(GPIOG_FMC_BA1) | \ - PIN_OSPEED_HIGH(GPIOG_EXT_SDA) | \ - PIN_OSPEED_HIGH(GPIOG_SAI1_MCLKA) | \ - PIN_OSPEED_HIGH(GPIOG_FMC_SDCLK) | \ - PIN_OSPEED_HIGH(GPIOG_SD_D0) | \ - PIN_OSPEED_HIGH(GPIOG_SD_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ARD_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOG_ZIO_D65) | \ + PIN_OSPEED_VERYLOW(GPIOG_ZIO_D64) | \ + PIN_OSPEED_VERYLOW(GPIOG_ZIO_D49) | \ + PIN_OSPEED_VERYLOW(GPIOG_ZIO_D50) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN5) | \ + PIN_OSPEED_HIGH(GPIOG_USB_GPIO_OUT) | \ + PIN_OSPEED_HIGH(GPIOG_USB_GPIO_IN) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN8) | \ + PIN_OSPEED_HIGH(GPIOG_ARD_D0) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN10) | \ PIN_OSPEED_HIGH(GPIOG_RMII_TX_EN) | \ - PIN_OSPEED_HIGH(GPIOG_SPDIF_RX) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN12) | \ PIN_OSPEED_HIGH(GPIOG_RMII_TXD0) | \ - PIN_OSPEED_HIGH(GPIOG_RMII_TXD1) | \ - PIN_OSPEED_HIGH(GPIOG_FMC_SDNCAS)) -#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_FMC_A10) | \ - PIN_PUPDR_FLOATING(GPIOG_FMC_A11) | \ - PIN_PUPDR_FLOATING(GPIOG_FMC_A12) | \ - PIN_PUPDR_PULLUP(GPIOG_EXT_SCL) | \ - PIN_PUPDR_FLOATING(GPIOG_FMC_BA0) | \ - PIN_PUPDR_FLOATING(GPIOG_FMC_BA1) | \ - PIN_PUPDR_PULLUP(GPIOG_EXT_SDA) | \ - PIN_PUPDR_PULLUP(GPIOG_SAI1_MCLKA) | \ - PIN_PUPDR_FLOATING(GPIOG_FMC_SDCLK) | \ - PIN_PUPDR_FLOATING(GPIOG_SD_D0) | \ - PIN_PUPDR_FLOATING(GPIOG_SD_D1) | \ + PIN_OSPEED_HIGH(GPIOG_ARD_D1) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN15)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_ZIO_D65) | \ + PIN_PUPDR_PULLUP(GPIOG_ZIO_D64) | \ + PIN_PUPDR_PULLUP(GPIOG_ZIO_D49) | \ + PIN_PUPDR_PULLUP(GPIOG_ZIO_D50) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOG_USB_GPIO_OUT) | \ + PIN_PUPDR_PULLUP(GPIOG_USB_GPIO_IN) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOG_ARD_D0) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN10) | \ PIN_PUPDR_FLOATING(GPIOG_RMII_TX_EN) | \ - PIN_PUPDR_FLOATING(GPIOG_SPDIF_RX) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN12) | \ PIN_PUPDR_FLOATING(GPIOG_RMII_TXD0) | \ - PIN_PUPDR_FLOATING(GPIOG_RMII_TXD1) | \ - PIN_PUPDR_FLOATING(GPIOG_FMC_SDNCAS)) -#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_FMC_A10) | \ - PIN_ODR_HIGH(GPIOG_FMC_A11) | \ - PIN_ODR_HIGH(GPIOG_FMC_A12) | \ - PIN_ODR_HIGH(GPIOG_EXT_SCL) | \ - PIN_ODR_HIGH(GPIOG_FMC_BA0) | \ - PIN_ODR_HIGH(GPIOG_FMC_BA1) | \ - PIN_ODR_HIGH(GPIOG_EXT_SDA) | \ - PIN_ODR_HIGH(GPIOG_SAI1_MCLKA) | \ - PIN_ODR_HIGH(GPIOG_FMC_SDCLK) | \ - PIN_ODR_HIGH(GPIOG_SD_D0) | \ - PIN_ODR_HIGH(GPIOG_SD_D1) | \ + PIN_PUPDR_PULLUP(GPIOG_ARD_D1) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN15)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_ZIO_D65) | \ + PIN_ODR_HIGH(GPIOG_ZIO_D64) | \ + PIN_ODR_HIGH(GPIOG_ZIO_D49) | \ + PIN_ODR_HIGH(GPIOG_ZIO_D50) | \ + PIN_ODR_HIGH(GPIOG_PIN4) | \ + PIN_ODR_HIGH(GPIOG_PIN5) | \ + PIN_ODR_HIGH(GPIOG_USB_GPIO_OUT) | \ + PIN_ODR_HIGH(GPIOG_USB_GPIO_IN) | \ + PIN_ODR_HIGH(GPIOG_PIN8) | \ + PIN_ODR_HIGH(GPIOG_ARD_D0) | \ + PIN_ODR_HIGH(GPIOG_PIN10) | \ PIN_ODR_HIGH(GPIOG_RMII_TX_EN) | \ - PIN_ODR_HIGH(GPIOG_SPDIF_RX) | \ + PIN_ODR_HIGH(GPIOG_PIN12) | \ PIN_ODR_HIGH(GPIOG_RMII_TXD0) | \ - PIN_ODR_HIGH(GPIOG_RMII_TXD1) | \ - PIN_ODR_HIGH(GPIOG_FMC_SDNCAS)) -#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_FMC_A10, 12U) | \ - PIN_AFIO_AF(GPIOG_FMC_A11, 12U) | \ - PIN_AFIO_AF(GPIOG_FMC_A12, 12U) | \ - PIN_AFIO_AF(GPIOG_EXT_SCL, 0U) | \ - PIN_AFIO_AF(GPIOG_FMC_BA0, 12U) | \ - PIN_AFIO_AF(GPIOG_FMC_BA1, 12U) | \ - PIN_AFIO_AF(GPIOG_EXT_SDA, 0U) | \ - PIN_AFIO_AF(GPIOG_SAI1_MCLKA, 6U)) -#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_FMC_SDCLK, 12U) | \ - PIN_AFIO_AF(GPIOG_SD_D0, 11U) | \ - PIN_AFIO_AF(GPIOG_SD_D1, 11U) | \ + PIN_ODR_HIGH(GPIOG_ARD_D1) | \ + PIN_ODR_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_ZIO_D65, 0U) | \ + PIN_AFIO_AF(GPIOG_ZIO_D64, 0U) | \ + PIN_AFIO_AF(GPIOG_ZIO_D49, 0U) | \ + PIN_AFIO_AF(GPIOG_ZIO_D50, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOG_USB_GPIO_OUT, 0U) | \ + PIN_AFIO_AF(GPIOG_USB_GPIO_IN, 0U)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOG_ARD_D0, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ PIN_AFIO_AF(GPIOG_RMII_TX_EN, 11U) | \ - PIN_AFIO_AF(GPIOG_SPDIF_RX, 7U) | \ + PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ PIN_AFIO_AF(GPIOG_RMII_TXD0, 11U) | \ - PIN_AFIO_AF(GPIOG_RMII_TXD1, 11U) | \ - PIN_AFIO_AF(GPIOG_FMC_SDNCAS, 12U)) + PIN_AFIO_AF(GPIOG_ARD_D1, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN15, 0U)) /* * GPIOH setup: * * PH0 - OSC_IN (input floating). * PH1 - OSC_OUT (input floating). - * PH2 - FMC_SDCKE0 (alternate 12). - * PH3 - FMC_SDNE0 (alternate 12). - * PH4 - ULPI_NXT (alternate 10). - * PH5 - FMC_SDNWE (alternate 12). - * PH6 - ARD_D9 (input pullup). - * PH7 - EXT_RST (input floating). - * PH8 - FMC_D16 (alternate 12). - * PH9 - FMC_D17 (alternate 12). - * PH10 - FMC_D18 (alternate 12). - * PH11 - FMC_D19 (alternate 12). - * PH12 - FMC_D20 (alternate 12). - * PH13 - FMC_D21 (alternate 12). - * PH14 - FMC_D22 (alternate 12). - * PH15 - FMC_D23 (alternate 12). + * PH2 - PIN2 (input pullup). + * PH3 - PIN3 (input pullup). + * PH4 - PIN4 (input pullup). + * PH5 - PIN5 (input pullup). + * PH6 - PIN6 (input pullup). + * PH7 - PIN7 (input pullup). + * PH8 - PIN8 (input pullup). + * PH9 - PIN9 (input pullup). + * PH10 - PIN10 (input pullup). + * PH11 - PIN11 (input pullup). + * PH12 - PIN12 (input pullup). + * PH13 - PIN13 (input pullup). + * PH14 - PIN14 (input pullup). + * PH15 - PIN15 (input pullup). */ #define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ - PIN_MODE_ALTERNATE(GPIOH_FMC_SDCKE0) | \ - PIN_MODE_ALTERNATE(GPIOH_FMC_SDNE0) | \ - PIN_MODE_ALTERNATE(GPIOH_ULPI_NXT) | \ - PIN_MODE_ALTERNATE(GPIOH_FMC_SDNWE) | \ - PIN_MODE_INPUT(GPIOH_ARD_D9) | \ - PIN_MODE_INPUT(GPIOH_EXT_RST) | \ - PIN_MODE_ALTERNATE(GPIOH_FMC_D16) | \ - PIN_MODE_ALTERNATE(GPIOH_FMC_D17) | \ - PIN_MODE_ALTERNATE(GPIOH_FMC_D18) | \ - PIN_MODE_ALTERNATE(GPIOH_FMC_D19) | \ - PIN_MODE_ALTERNATE(GPIOH_FMC_D20) | \ - PIN_MODE_ALTERNATE(GPIOH_FMC_D21) | \ - PIN_MODE_ALTERNATE(GPIOH_FMC_D22) | \ - PIN_MODE_ALTERNATE(GPIOH_FMC_D23)) + PIN_MODE_INPUT(GPIOH_PIN2) | \ + PIN_MODE_INPUT(GPIOH_PIN3) | \ + PIN_MODE_INPUT(GPIOH_PIN4) | \ + PIN_MODE_INPUT(GPIOH_PIN5) | \ + PIN_MODE_INPUT(GPIOH_PIN6) | \ + PIN_MODE_INPUT(GPIOH_PIN7) | \ + PIN_MODE_INPUT(GPIOH_PIN8) | \ + PIN_MODE_INPUT(GPIOH_PIN9) | \ + PIN_MODE_INPUT(GPIOH_PIN10) | \ + PIN_MODE_INPUT(GPIOH_PIN11) | \ + PIN_MODE_INPUT(GPIOH_PIN12) | \ + PIN_MODE_INPUT(GPIOH_PIN13) | \ + PIN_MODE_INPUT(GPIOH_PIN14) | \ + PIN_MODE_INPUT(GPIOH_PIN15)) #define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOH_FMC_SDCKE0) | \ - PIN_OTYPE_PUSHPULL(GPIOH_FMC_SDNE0) | \ - PIN_OTYPE_PUSHPULL(GPIOH_ULPI_NXT) | \ - PIN_OTYPE_PUSHPULL(GPIOH_FMC_SDNWE) | \ - PIN_OTYPE_PUSHPULL(GPIOH_ARD_D9) | \ - PIN_OTYPE_OPENDRAIN(GPIOH_EXT_RST) | \ - PIN_OTYPE_PUSHPULL(GPIOH_FMC_D16) | \ - PIN_OTYPE_PUSHPULL(GPIOH_FMC_D17) | \ - PIN_OTYPE_PUSHPULL(GPIOH_FMC_D18) | \ - PIN_OTYPE_PUSHPULL(GPIOH_FMC_D19) | \ - PIN_OTYPE_PUSHPULL(GPIOH_FMC_D20) | \ - PIN_OTYPE_PUSHPULL(GPIOH_FMC_D21) | \ - PIN_OTYPE_PUSHPULL(GPIOH_FMC_D22) | \ - PIN_OTYPE_PUSHPULL(GPIOH_FMC_D23)) + PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) #define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ - PIN_OSPEED_HIGH(GPIOH_FMC_SDCKE0) | \ - PIN_OSPEED_HIGH(GPIOH_FMC_SDNE0) | \ - PIN_OSPEED_HIGH(GPIOH_ULPI_NXT) | \ - PIN_OSPEED_HIGH(GPIOH_FMC_SDNWE) | \ - PIN_OSPEED_HIGH(GPIOH_ARD_D9) | \ - PIN_OSPEED_HIGH(GPIOH_EXT_RST) | \ - PIN_OSPEED_HIGH(GPIOH_FMC_D16) | \ - PIN_OSPEED_HIGH(GPIOH_FMC_D17) | \ - PIN_OSPEED_HIGH(GPIOH_FMC_D18) | \ - PIN_OSPEED_HIGH(GPIOH_FMC_D19) | \ - PIN_OSPEED_HIGH(GPIOH_FMC_D20) | \ - PIN_OSPEED_HIGH(GPIOH_FMC_D21) | \ - PIN_OSPEED_HIGH(GPIOH_FMC_D22) | \ - PIN_OSPEED_HIGH(GPIOH_FMC_D23)) + PIN_OSPEED_VERYLOW(GPIOH_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN15)) #define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ - PIN_PUPDR_FLOATING(GPIOH_FMC_SDCKE0) | \ - PIN_PUPDR_FLOATING(GPIOH_FMC_SDNE0) | \ - PIN_PUPDR_FLOATING(GPIOH_ULPI_NXT) | \ - PIN_PUPDR_FLOATING(GPIOH_FMC_SDNWE) | \ - PIN_PUPDR_PULLUP(GPIOH_ARD_D9) | \ - PIN_PUPDR_FLOATING(GPIOH_EXT_RST) | \ - PIN_PUPDR_FLOATING(GPIOH_FMC_D16) | \ - PIN_PUPDR_FLOATING(GPIOH_FMC_D17) | \ - PIN_PUPDR_FLOATING(GPIOH_FMC_D18) | \ - PIN_PUPDR_FLOATING(GPIOH_FMC_D19) | \ - PIN_PUPDR_FLOATING(GPIOH_FMC_D20) | \ - PIN_PUPDR_FLOATING(GPIOH_FMC_D21) | \ - PIN_PUPDR_FLOATING(GPIOH_FMC_D22) | \ - PIN_PUPDR_FLOATING(GPIOH_FMC_D23)) + PIN_PUPDR_PULLUP(GPIOH_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN15)) #define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ - PIN_ODR_HIGH(GPIOH_FMC_SDCKE0) | \ - PIN_ODR_HIGH(GPIOH_FMC_SDNE0) | \ - PIN_ODR_HIGH(GPIOH_ULPI_NXT) | \ - PIN_ODR_HIGH(GPIOH_FMC_SDNWE) | \ - PIN_ODR_HIGH(GPIOH_ARD_D9) | \ - PIN_ODR_HIGH(GPIOH_EXT_RST) | \ - PIN_ODR_HIGH(GPIOH_FMC_D16) | \ - PIN_ODR_HIGH(GPIOH_FMC_D17) | \ - PIN_ODR_HIGH(GPIOH_FMC_D18) | \ - PIN_ODR_HIGH(GPIOH_FMC_D19) | \ - PIN_ODR_HIGH(GPIOH_FMC_D20) | \ - PIN_ODR_HIGH(GPIOH_FMC_D21) | \ - PIN_ODR_HIGH(GPIOH_FMC_D22) | \ - PIN_ODR_HIGH(GPIOH_FMC_D23)) + PIN_ODR_HIGH(GPIOH_PIN2) | \ + PIN_ODR_HIGH(GPIOH_PIN3) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_PIN5) | \ + PIN_ODR_HIGH(GPIOH_PIN6) | \ + PIN_ODR_HIGH(GPIOH_PIN7) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) #define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ - PIN_AFIO_AF(GPIOH_FMC_SDCKE0, 12U) | \ - PIN_AFIO_AF(GPIOH_FMC_SDNE0, 12U) | \ - PIN_AFIO_AF(GPIOH_ULPI_NXT, 10U) | \ - PIN_AFIO_AF(GPIOH_FMC_SDNWE, 12U) | \ - PIN_AFIO_AF(GPIOH_ARD_D9, 0U) | \ - PIN_AFIO_AF(GPIOH_EXT_RST, 0U)) -#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_FMC_D16, 12U) | \ - PIN_AFIO_AF(GPIOH_FMC_D17, 12U) | \ - PIN_AFIO_AF(GPIOH_FMC_D18, 12U) | \ - PIN_AFIO_AF(GPIOH_FMC_D19, 12U) | \ - PIN_AFIO_AF(GPIOH_FMC_D20, 12U) | \ - PIN_AFIO_AF(GPIOH_FMC_D21, 12U) | \ - PIN_AFIO_AF(GPIOH_FMC_D22, 12U) | \ - PIN_AFIO_AF(GPIOH_FMC_D23, 12U)) + PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0U)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0U)) /* * GPIOI setup: * - * PI0 - FMC_D24 (alternate 12). - * PI1 - FMC_D25 (alternate 12). - * PI2 - FMC_D26 (alternate 12). - * PI3 - FMC_D27 (alternate 12). - * PI4 - FMC_NBL2 (alternate 12). - * PI5 - FMC_NBL3 (alternate 12). - * PI6 - FMC_D28 (alternate 12). - * PI7 - FMC_D29 (alternate 12). + * PI0 - PIN0 (input pullup). + * PI1 - PIN1 (input pullup). + * PI2 - PIN2 (input pullup). + * PI3 - PIN3 (input pullup). + * PI4 - PIN4 (input pullup). + * PI5 - PIN5 (input pullup). + * PI6 - PIN6 (input pullup). + * PI7 - PIN7 (input pullup). * PI8 - PIN8 (input pullup). - * PI9 - FMC_D30 (alternate 12). - * PI10 - FMC_D31 (alternate 12). - * PI11 - ULPI_DIR (alternate 10). + * PI9 - PIN9 (input pullup). + * PI10 - PIN10 (input pullup). + * PI11 - PIN11 (input pullup). * PI12 - PIN12 (input pullup). - * PI13 - LCD_INT (alternate 14). - * PI14 - LCD_BL_CTRL (alternate 14). - * PI15 - SD_DETECT (input pullup). + * PI13 - PIN13 (input pullup). + * PI14 - PIN14 (input pullup). + * PI15 - PIN15 (input pullup). */ -#define VAL_GPIOI_MODER (PIN_MODE_ALTERNATE(GPIOI_FMC_D24) | \ - PIN_MODE_ALTERNATE(GPIOI_FMC_D25) | \ - PIN_MODE_ALTERNATE(GPIOI_FMC_D26) | \ - PIN_MODE_ALTERNATE(GPIOI_FMC_D27) | \ - PIN_MODE_ALTERNATE(GPIOI_FMC_NBL2) | \ - PIN_MODE_ALTERNATE(GPIOI_FMC_NBL3) | \ - PIN_MODE_ALTERNATE(GPIOI_FMC_D28) | \ - PIN_MODE_ALTERNATE(GPIOI_FMC_D29) | \ +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ + PIN_MODE_INPUT(GPIOI_PIN1) | \ + PIN_MODE_INPUT(GPIOI_PIN2) | \ + PIN_MODE_INPUT(GPIOI_PIN3) | \ + PIN_MODE_INPUT(GPIOI_PIN4) | \ + PIN_MODE_INPUT(GPIOI_PIN5) | \ + PIN_MODE_INPUT(GPIOI_PIN6) | \ + PIN_MODE_INPUT(GPIOI_PIN7) | \ PIN_MODE_INPUT(GPIOI_PIN8) | \ - PIN_MODE_ALTERNATE(GPIOI_FMC_D30) | \ - PIN_MODE_ALTERNATE(GPIOI_FMC_D31) | \ - PIN_MODE_ALTERNATE(GPIOI_ULPI_DIR) | \ + PIN_MODE_INPUT(GPIOI_PIN9) | \ + PIN_MODE_INPUT(GPIOI_PIN10) | \ + PIN_MODE_INPUT(GPIOI_PIN11) | \ PIN_MODE_INPUT(GPIOI_PIN12) | \ - PIN_MODE_ALTERNATE(GPIOI_LCD_INT) | \ - PIN_MODE_ALTERNATE(GPIOI_LCD_BL_CTRL) |\ - PIN_MODE_INPUT(GPIOI_SD_DETECT)) -#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_FMC_D24) | \ - PIN_OTYPE_PUSHPULL(GPIOI_FMC_D25) | \ - PIN_OTYPE_PUSHPULL(GPIOI_FMC_D26) | \ - PIN_OTYPE_PUSHPULL(GPIOI_FMC_D27) | \ - PIN_OTYPE_PUSHPULL(GPIOI_FMC_NBL2) | \ - PIN_OTYPE_PUSHPULL(GPIOI_FMC_NBL3) | \ - PIN_OTYPE_PUSHPULL(GPIOI_FMC_D28) | \ - PIN_OTYPE_PUSHPULL(GPIOI_FMC_D29) | \ + PIN_MODE_INPUT(GPIOI_PIN13) | \ + PIN_MODE_INPUT(GPIOI_PIN14) | \ + PIN_MODE_INPUT(GPIOI_PIN15)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOI_FMC_D30) | \ - PIN_OTYPE_PUSHPULL(GPIOI_FMC_D31) | \ - PIN_OTYPE_PUSHPULL(GPIOI_ULPI_DIR) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOI_LCD_INT) | \ - PIN_OTYPE_PUSHPULL(GPIOI_LCD_BL_CTRL) |\ - PIN_OTYPE_PUSHPULL(GPIOI_SD_DETECT)) -#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_HIGH(GPIOI_FMC_D24) | \ - PIN_OSPEED_HIGH(GPIOI_FMC_D25) | \ - PIN_OSPEED_HIGH(GPIOI_FMC_D26) | \ - PIN_OSPEED_HIGH(GPIOI_FMC_D27) | \ - PIN_OSPEED_HIGH(GPIOI_FMC_NBL2) | \ - PIN_OSPEED_HIGH(GPIOI_FMC_NBL3) | \ - PIN_OSPEED_HIGH(GPIOI_FMC_D28) | \ - PIN_OSPEED_HIGH(GPIOI_FMC_D29) | \ - PIN_OSPEED_HIGH(GPIOI_PIN8) | \ - PIN_OSPEED_HIGH(GPIOI_FMC_D30) | \ - PIN_OSPEED_HIGH(GPIOI_FMC_D31) | \ - PIN_OSPEED_HIGH(GPIOI_ULPI_DIR) | \ - PIN_OSPEED_HIGH(GPIOI_PIN12) | \ - PIN_OSPEED_HIGH(GPIOI_LCD_INT) | \ - PIN_OSPEED_HIGH(GPIOI_LCD_BL_CTRL) | \ - PIN_OSPEED_HIGH(GPIOI_SD_DETECT)) -#define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(GPIOI_FMC_D24) | \ - PIN_PUPDR_FLOATING(GPIOI_FMC_D25) | \ - PIN_PUPDR_FLOATING(GPIOI_FMC_D26) | \ - PIN_PUPDR_FLOATING(GPIOI_FMC_D27) | \ - PIN_PUPDR_FLOATING(GPIOI_FMC_NBL2) | \ - PIN_PUPDR_FLOATING(GPIOI_FMC_NBL3) | \ - PIN_PUPDR_FLOATING(GPIOI_FMC_D28) | \ - PIN_PUPDR_FLOATING(GPIOI_FMC_D29) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOI_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN15)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN7) | \ PIN_PUPDR_PULLUP(GPIOI_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOI_FMC_D30) | \ - PIN_PUPDR_FLOATING(GPIOI_FMC_D31) | \ - PIN_PUPDR_FLOATING(GPIOI_ULPI_DIR) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN11) | \ PIN_PUPDR_PULLUP(GPIOI_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOI_LCD_INT) | \ - PIN_PUPDR_FLOATING(GPIOI_LCD_BL_CTRL) |\ - PIN_PUPDR_PULLUP(GPIOI_SD_DETECT)) -#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_FMC_D24) | \ - PIN_ODR_HIGH(GPIOI_FMC_D25) | \ - PIN_ODR_HIGH(GPIOI_FMC_D26) | \ - PIN_ODR_HIGH(GPIOI_FMC_D27) | \ - PIN_ODR_HIGH(GPIOI_FMC_NBL2) | \ - PIN_ODR_HIGH(GPIOI_FMC_NBL3) | \ - PIN_ODR_HIGH(GPIOI_FMC_D28) | \ - PIN_ODR_HIGH(GPIOI_FMC_D29) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN15)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ + PIN_ODR_HIGH(GPIOI_PIN1) | \ + PIN_ODR_HIGH(GPIOI_PIN2) | \ + PIN_ODR_HIGH(GPIOI_PIN3) | \ + PIN_ODR_HIGH(GPIOI_PIN4) | \ + PIN_ODR_HIGH(GPIOI_PIN5) | \ + PIN_ODR_HIGH(GPIOI_PIN6) | \ + PIN_ODR_HIGH(GPIOI_PIN7) | \ PIN_ODR_HIGH(GPIOI_PIN8) | \ - PIN_ODR_HIGH(GPIOI_FMC_D30) | \ - PIN_ODR_HIGH(GPIOI_FMC_D31) | \ - PIN_ODR_HIGH(GPIOI_ULPI_DIR) | \ + PIN_ODR_HIGH(GPIOI_PIN9) | \ + PIN_ODR_HIGH(GPIOI_PIN10) | \ + PIN_ODR_HIGH(GPIOI_PIN11) | \ PIN_ODR_HIGH(GPIOI_PIN12) | \ - PIN_ODR_HIGH(GPIOI_LCD_INT) | \ - PIN_ODR_HIGH(GPIOI_LCD_BL_CTRL) | \ - PIN_ODR_HIGH(GPIOI_SD_DETECT)) -#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_FMC_D24, 12U) | \ - PIN_AFIO_AF(GPIOI_FMC_D25, 12U) | \ - PIN_AFIO_AF(GPIOI_FMC_D26, 12U) | \ - PIN_AFIO_AF(GPIOI_FMC_D27, 12U) | \ - PIN_AFIO_AF(GPIOI_FMC_NBL2, 12U) | \ - PIN_AFIO_AF(GPIOI_FMC_NBL3, 12U) | \ - PIN_AFIO_AF(GPIOI_FMC_D28, 12U) | \ - PIN_AFIO_AF(GPIOI_FMC_D29, 12U)) + PIN_ODR_HIGH(GPIOI_PIN13) | \ + PIN_ODR_HIGH(GPIOI_PIN14) | \ + PIN_ODR_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN7, 0U)) #define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOI_FMC_D30, 12U) | \ - PIN_AFIO_AF(GPIOI_FMC_D31, 12U) | \ - PIN_AFIO_AF(GPIOI_ULPI_DIR, 10U) | \ + PIN_AFIO_AF(GPIOI_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN11, 0U) | \ PIN_AFIO_AF(GPIOI_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOI_LCD_INT, 14U) | \ - PIN_AFIO_AF(GPIOI_LCD_BL_CTRL, 14U) | \ - PIN_AFIO_AF(GPIOI_SD_DETECT, 0U)) + PIN_AFIO_AF(GPIOI_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN15, 0U)) /* * GPIOJ setup: * - * PJ0 - ARD_D4 (input floating). - * PJ1 - ARD_D2 (input floating). - * PJ2 - DSI_TE (alternate 13). - * PJ3 - ARD_D7 (input floating). - * PJ4 - ARD_D8 (input floating). - * PJ5 - LED2_GREEN (output pushpull maximum). - * PJ6 - PIN6 (input floating). - * PJ7 - PIN7 (input floating). - * PJ8 - PIN8 (input floating). - * PJ9 - PIN9 (input floating). - * PJ10 - PIN10 (input floating). - * PJ11 - PIN11 (input floating). - * PJ12 - AUDIO_INT (input floating). - * PJ13 - LED1_RED (output pushpull maximum). - * PJ14 - WIFI_RST (input floating). - * PJ15 - DSI_RESET (input floating). + * PJ0 - PIN0 (input pullup). + * PJ1 - PIN1 (input pullup). + * PJ2 - PIN2 (input pullup). + * PJ3 - PIN3 (input pullup). + * PJ4 - PIN4 (input pullup). + * PJ5 - PIN5 (input pullup). + * PJ6 - PIN6 (input pullup). + * PJ7 - PIN7 (input pullup). + * PJ8 - PIN8 (input pullup). + * PJ9 - PIN9 (input pullup). + * PJ10 - PIN10 (input pullup). + * PJ11 - PIN11 (input pullup). + * PJ12 - PIN12 (input pullup). + * PJ13 - PIN13 (input pullup). + * PJ14 - PIN14 (input pullup). + * PJ15 - PIN15 (input pullup). */ -#define VAL_GPIOJ_MODER (PIN_MODE_INPUT(GPIOJ_ARD_D4) | \ - PIN_MODE_INPUT(GPIOJ_ARD_D2) | \ - PIN_MODE_ALTERNATE(GPIOJ_DSI_TE) | \ - PIN_MODE_INPUT(GPIOJ_ARD_D7) | \ - PIN_MODE_INPUT(GPIOJ_ARD_D8) | \ - PIN_MODE_OUTPUT(GPIOJ_LED2_GREEN) | \ +#define VAL_GPIOJ_MODER (PIN_MODE_INPUT(GPIOJ_PIN0) | \ + PIN_MODE_INPUT(GPIOJ_PIN1) | \ + PIN_MODE_INPUT(GPIOJ_PIN2) | \ + PIN_MODE_INPUT(GPIOJ_PIN3) | \ + PIN_MODE_INPUT(GPIOJ_PIN4) | \ + PIN_MODE_INPUT(GPIOJ_PIN5) | \ PIN_MODE_INPUT(GPIOJ_PIN6) | \ PIN_MODE_INPUT(GPIOJ_PIN7) | \ PIN_MODE_INPUT(GPIOJ_PIN8) | \ PIN_MODE_INPUT(GPIOJ_PIN9) | \ PIN_MODE_INPUT(GPIOJ_PIN10) | \ PIN_MODE_INPUT(GPIOJ_PIN11) | \ - PIN_MODE_INPUT(GPIOJ_AUDIO_INT) | \ - PIN_MODE_OUTPUT(GPIOJ_LED1_RED) | \ - PIN_MODE_INPUT(GPIOJ_WIFI_RST) | \ - PIN_MODE_OUTPUT(GPIOJ_DSI_RESET)) // LCD/TFT -#define VAL_GPIOJ_OTYPER (PIN_OTYPE_PUSHPULL(GPIOJ_ARD_D4) | \ - PIN_OTYPE_PUSHPULL(GPIOJ_ARD_D2) | \ - PIN_OTYPE_PUSHPULL(GPIOJ_DSI_TE) | \ - PIN_OTYPE_PUSHPULL(GPIOJ_ARD_D7) | \ - PIN_OTYPE_PUSHPULL(GPIOJ_ARD_D8) | \ - PIN_OTYPE_PUSHPULL(GPIOJ_LED2_GREEN) | \ + PIN_MODE_INPUT(GPIOJ_PIN12) | \ + PIN_MODE_INPUT(GPIOJ_PIN13) | \ + PIN_MODE_INPUT(GPIOJ_PIN14) | \ + PIN_MODE_INPUT(GPIOJ_PIN15)) +#define VAL_GPIOJ_OTYPER (PIN_OTYPE_PUSHPULL(GPIOJ_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN5) | \ PIN_OTYPE_PUSHPULL(GPIOJ_PIN6) | \ PIN_OTYPE_PUSHPULL(GPIOJ_PIN7) | \ PIN_OTYPE_PUSHPULL(GPIOJ_PIN8) | \ PIN_OTYPE_PUSHPULL(GPIOJ_PIN9) | \ PIN_OTYPE_PUSHPULL(GPIOJ_PIN10) | \ PIN_OTYPE_PUSHPULL(GPIOJ_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOJ_AUDIO_INT) | \ - PIN_OTYPE_PUSHPULL(GPIOJ_LED1_RED) | \ - PIN_OTYPE_PUSHPULL(GPIOJ_WIFI_RST) | \ - PIN_OTYPE_PUSHPULL(GPIOJ_DSI_RESET)) -#define VAL_GPIOJ_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOJ_ARD_D4) | \ - PIN_OSPEED_VERYLOW(GPIOJ_ARD_D2) | \ - PIN_OSPEED_VERYLOW(GPIOJ_DSI_TE) | \ - PIN_OSPEED_VERYLOW(GPIOJ_ARD_D7) | \ - PIN_OSPEED_VERYLOW(GPIOJ_ARD_D8) | \ - PIN_OSPEED_HIGH(GPIOJ_LED2_GREEN) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN15)) +#define VAL_GPIOJ_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOJ_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN5) | \ PIN_OSPEED_VERYLOW(GPIOJ_PIN6) | \ PIN_OSPEED_VERYLOW(GPIOJ_PIN7) | \ PIN_OSPEED_VERYLOW(GPIOJ_PIN8) | \ PIN_OSPEED_VERYLOW(GPIOJ_PIN9) | \ PIN_OSPEED_VERYLOW(GPIOJ_PIN10) | \ PIN_OSPEED_VERYLOW(GPIOJ_PIN11) | \ - PIN_OSPEED_VERYLOW(GPIOJ_AUDIO_INT) | \ - PIN_OSPEED_HIGH(GPIOJ_LED1_RED) | \ - PIN_OSPEED_VERYLOW(GPIOJ_WIFI_RST) | \ - PIN_OSPEED_HIGH(GPIOJ_DSI_RESET)) -#define VAL_GPIOJ_PUPDR (PIN_PUPDR_FLOATING(GPIOJ_ARD_D4) | \ - PIN_PUPDR_FLOATING(GPIOJ_ARD_D2) | \ - PIN_PUPDR_FLOATING(GPIOJ_DSI_TE) | \ - PIN_PUPDR_FLOATING(GPIOJ_ARD_D7) | \ - PIN_PUPDR_FLOATING(GPIOJ_ARD_D8) | \ - PIN_PUPDR_FLOATING(GPIOJ_LED2_GREEN) | \ - PIN_PUPDR_FLOATING(GPIOJ_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOJ_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOJ_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOJ_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOJ_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOJ_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOJ_AUDIO_INT) | \ - PIN_PUPDR_FLOATING(GPIOJ_LED1_RED) | \ - PIN_PUPDR_FLOATING(GPIOJ_WIFI_RST) | \ - PIN_PUPDR_PULLUP(GPIOJ_DSI_RESET)) -#define VAL_GPIOJ_ODR (PIN_ODR_HIGH(GPIOJ_ARD_D4) | \ - PIN_ODR_HIGH(GPIOJ_ARD_D2) | \ - PIN_ODR_HIGH(GPIOJ_DSI_TE) | \ - PIN_ODR_HIGH(GPIOJ_ARD_D7) | \ - PIN_ODR_HIGH(GPIOJ_ARD_D8) | \ - PIN_ODR_LOW(GPIOJ_LED2_GREEN) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN15)) +#define VAL_GPIOJ_PUPDR (PIN_PUPDR_PULLUP(GPIOJ_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN15)) +#define VAL_GPIOJ_ODR (PIN_ODR_HIGH(GPIOJ_PIN0) | \ + PIN_ODR_HIGH(GPIOJ_PIN1) | \ + PIN_ODR_HIGH(GPIOJ_PIN2) | \ + PIN_ODR_HIGH(GPIOJ_PIN3) | \ + PIN_ODR_HIGH(GPIOJ_PIN4) | \ + PIN_ODR_HIGH(GPIOJ_PIN5) | \ PIN_ODR_HIGH(GPIOJ_PIN6) | \ PIN_ODR_HIGH(GPIOJ_PIN7) | \ PIN_ODR_HIGH(GPIOJ_PIN8) | \ PIN_ODR_HIGH(GPIOJ_PIN9) | \ PIN_ODR_HIGH(GPIOJ_PIN10) | \ PIN_ODR_HIGH(GPIOJ_PIN11) | \ - PIN_ODR_HIGH(GPIOJ_AUDIO_INT) | \ - PIN_ODR_LOW(GPIOJ_LED1_RED) | \ - PIN_ODR_HIGH(GPIOJ_WIFI_RST) | \ - PIN_ODR_HIGH(GPIOJ_DSI_RESET)) -#define VAL_GPIOJ_AFRL (PIN_AFIO_AF(GPIOJ_ARD_D4, 0U) | \ - PIN_AFIO_AF(GPIOJ_ARD_D2, 0U) | \ - PIN_AFIO_AF(GPIOJ_DSI_TE, 13U) | \ - PIN_AFIO_AF(GPIOJ_ARD_D7, 0U) | \ - PIN_AFIO_AF(GPIOJ_ARD_D8, 0U) | \ - PIN_AFIO_AF(GPIOJ_LED2_GREEN, 0U) | \ + PIN_ODR_HIGH(GPIOJ_PIN12) | \ + PIN_ODR_HIGH(GPIOJ_PIN13) | \ + PIN_ODR_HIGH(GPIOJ_PIN14) | \ + PIN_ODR_HIGH(GPIOJ_PIN15)) +#define VAL_GPIOJ_AFRL (PIN_AFIO_AF(GPIOJ_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN5, 0U) | \ PIN_AFIO_AF(GPIOJ_PIN6, 0U) | \ PIN_AFIO_AF(GPIOJ_PIN7, 0U)) #define VAL_GPIOJ_AFRH (PIN_AFIO_AF(GPIOJ_PIN8, 0U) | \ PIN_AFIO_AF(GPIOJ_PIN9, 0U) | \ PIN_AFIO_AF(GPIOJ_PIN10, 0U) | \ PIN_AFIO_AF(GPIOJ_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOJ_AUDIO_INT, 0U) | \ - PIN_AFIO_AF(GPIOJ_LED1_RED, 0U) | \ - PIN_AFIO_AF(GPIOJ_WIFI_RST, 0U) | \ - PIN_AFIO_AF(GPIOJ_DSI_RESET, 0U)) + PIN_AFIO_AF(GPIOJ_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN15, 0U)) /* * GPIOK setup: * - * PK0 - PIN0 (input floating). - * PK1 - PIN1 (input floating). - * PK2 - PIN2 (input floating). - * PK3 - PIN3 (input floating). - * PK4 - PIN4 (input floating). - * PK5 - PIN5 (input floating). - * PK6 - PIN6 (input floating). - * PK7 - PIN7 (input floating). - * PK8 - PIN8 (input floating). - * PK9 - PIN9 (input floating). - * PK10 - PIN10 (input floating). - * PK11 - PIN11 (input floating). - * PK12 - PIN12 (input floating). - * PK13 - PIN13 (input floating). - * PK14 - PIN14 (input floating). - * PK15 - PIN15 (input floating). + * PK0 - PIN0 (input pullup). + * PK1 - PIN1 (input pullup). + * PK2 - PIN2 (input pullup). + * PK3 - PIN3 (input pullup). + * PK4 - PIN4 (input pullup). + * PK5 - PIN5 (input pullup). + * PK6 - PIN6 (input pullup). + * PK7 - PIN7 (input pullup). + * PK8 - PIN8 (input pullup). + * PK9 - PIN9 (input pullup). + * PK10 - PIN10 (input pullup). + * PK11 - PIN11 (input pullup). + * PK12 - PIN12 (input pullup). + * PK13 - PIN13 (input pullup). + * PK14 - PIN14 (input pullup). + * PK15 - PIN15 (input pullup). */ #define VAL_GPIOK_MODER (PIN_MODE_INPUT(GPIOK_PIN0) | \ PIN_MODE_INPUT(GPIOK_PIN1) | \ @@ -1702,22 +1796,22 @@ PIN_OSPEED_VERYLOW(GPIOK_PIN13) | \ PIN_OSPEED_VERYLOW(GPIOK_PIN14) | \ PIN_OSPEED_VERYLOW(GPIOK_PIN15)) -#define VAL_GPIOK_PUPDR (PIN_PUPDR_FLOATING(GPIOK_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOK_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOK_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOK_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOK_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOK_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOK_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOK_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOK_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOK_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOK_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOK_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOK_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOK_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOK_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOK_PIN15)) +#define VAL_GPIOK_PUPDR (PIN_PUPDR_PULLUP(GPIOK_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN15)) #define VAL_GPIOK_ODR (PIN_ODR_HIGH(GPIOK_PIN0) | \ PIN_ODR_HIGH(GPIOK_PIN1) | \ PIN_ODR_HIGH(GPIOK_PIN2) | \ diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/mcuconf.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/mcuconf.h index aad75fe0bc..793d6b169b 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/mcuconf.h +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/mcuconf.h @@ -24,7 +24,11 @@ */ #define STM32F7xx_MCUCONF +#define STM32F765_MCUCONF #define STM32F767_MCUCONF +#define STM32F777_MCUCONF +#define STM32F769_MCUCONF +#define STM32F779_MCUCONF /* * General settings. @@ -34,7 +38,7 @@ /* * Memory attributes settings. */ -#define STM32_NOCACHE_ENABLE FALSE +#define STM32_NOCACHE_ENABLE TRUE #define STM32_NOCACHE_MPU_REGION MPU_REGION_6 #define STM32_NOCACHE_RBAR 0x2004C000U #define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h index aad75fe0bc..793d6b169b 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h @@ -24,7 +24,11 @@ */ #define STM32F7xx_MCUCONF +#define STM32F765_MCUCONF #define STM32F767_MCUCONF +#define STM32F777_MCUCONF +#define STM32F769_MCUCONF +#define STM32F779_MCUCONF /* * General settings. @@ -34,7 +38,7 @@ /* * Memory attributes settings. */ -#define STM32_NOCACHE_ENABLE FALSE +#define STM32_NOCACHE_ENABLE TRUE #define STM32_NOCACHE_MPU_REGION MPU_REGION_6 #define STM32_NOCACHE_RBAR 0x2004C000U #define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K From 0c94e5470517951a77e825b187388f383a926ef3 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 8 Sep 2023 13:10:34 +0100 Subject: [PATCH 06/44] Turn off periperals until we map them properly. --- .../ST_STM32F767ZI_NUCLEO/CMakePresets.json | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json index b89059b2df..77f9f8167a 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json @@ -30,15 +30,15 @@ "API_System.Math": "ON", "API_Hardware.Stm32": "ON", "API_System.Device.Gpio": "ON", - "API_System.Device.Spi": "ON", - "API_System.Device.I2c": "ON", - "API_System.Device.Pwm": "ON", - "API_System.IO.Ports": "ON", - "API_System.Device.Adc": "ON", - "API_System.Device.Dac": "ON", - "API_System.Net": "ON", + "API_System.Device.Spi": "OFF", + "API_System.Device.I2c": "OFF", + "API_System.Device.Pwm": "OFF", + "API_System.IO.Ports": "OFF", + "API_System.Device.Adc": "OFF", + "API_System.Device.Dac": "OFF", + "API_System.Net": "OFF", "API_nanoFramework.Device.OneWire": "OFF", - "API_nanoFramework.Device.Can": "ON", + "API_nanoFramework.Device.Can": "OFF", "API_nanoFramework.ResourceManager": "ON", "API_nanoFramework.System.Collections": "ON", "API_nanoFramework.System.Text": "ON", From f456bbda6b0d95c88fa322033414099d87263151 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 8 Sep 2023 13:32:46 +0100 Subject: [PATCH 07/44] Adjust main with (probably incorrect) values Also adjust Serial Driver. --- .../ST_STM32F767ZI_NUCLEO/common/serialcfg.h | 2 +- .../ChibiOS/ST_STM32F767ZI_NUCLEO/ffconf.h | 273 ------ .../ST_STM32F767ZI_NUCLEO/nanoBooter/main.c | 6 +- .../ST_STM32F767ZI_NUCLEO/spiffs_config.h | 370 -------- .../target_nf_dev_onewire_config.cpp | 50 +- .../target_nf_dev_onewire_config.h | 28 +- .../target_nf_device_can_config.cpp | 92 +- .../target_nf_device_can_config.h | 36 +- .../ST_STM32F767ZI_NUCLEO/target_spiffs.c | 864 ------------------ .../ST_STM32F767ZI_NUCLEO/target_spiffs.h | 138 --- .../target_system_device_adc_config.cpp | 28 +- .../target_system_device_dac_config.cpp | 10 +- .../target_system_device_i2c_config.cpp | 2 +- .../target_system_device_spi_config.cpp | 4 +- .../target_system_io_ports_config.cpp | 20 +- .../target_system_io_ports_config.h | 4 +- 16 files changed, 141 insertions(+), 1786 deletions(-) delete mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/ffconf.h delete mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/spiffs_config.h delete mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_spiffs.c delete mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_spiffs.h diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/serialcfg.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/serialcfg.h index b356b1736a..07b8bbd3ac 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/serialcfg.h +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/serialcfg.h @@ -7,7 +7,7 @@ #define SERIALCFG_H // define which serial driver the Wire Protocol will be using -#define SERIAL_DRIVER SD1 +#define SERIAL_DRIVER SD3 #endif /* SERIALCFG_H */ diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/ffconf.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/ffconf.h deleted file mode 100644 index 5890370a95..0000000000 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/ffconf.h +++ /dev/null @@ -1,273 +0,0 @@ -/* CHIBIOS FIX */ -#include "ch.h" - -/*---------------------------------------------------------------------------/ -/ FatFs Functional Configurations -/---------------------------------------------------------------------------*/ - -#define FFCONF_DEF 86631 /* Revision ID */ - -/*---------------------------------------------------------------------------/ -/ Function Configurations -/---------------------------------------------------------------------------*/ - -#define FF_FS_READONLY 0 -/* This option switches read-only configuration. (0:Read/Write or 1:Read-only) -/ Read-only configuration removes writing API functions, f_write(), f_sync(), -/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree() -/ and optional writing functions as well. */ - -#define FF_FS_MINIMIZE 0 -/* This option defines minimization level to remove some basic API functions. -/ -/ 0: Basic functions are fully enabled. -/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename() -/ are removed. -/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1. -/ 3: f_lseek() function is removed in addition to 2. */ - -#define FF_USE_FIND 1 -/* This option switches filtered directory read functions, f_findfirst() and -/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */ - -#define FF_USE_MKFS 0 -/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */ - -#define FF_USE_FASTSEEK 0 -/* This option switches fast seek function. (0:Disable or 1:Enable) */ - -#define FF_USE_EXPAND 0 -/* This option switches f_expand function. (0:Disable or 1:Enable) */ - -#define FF_USE_CHMOD 1 -/* This option switches attribute manipulation functions, f_chmod() and f_utime(). -/ (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */ - -#define FF_USE_LABEL 1 -/* This option switches volume label functions, f_getlabel() and f_setlabel(). -/ (0:Disable or 1:Enable) */ - -#define FF_USE_FORWARD 0 -/* This option switches f_forward() function. (0:Disable or 1:Enable) */ - -#define FF_USE_STRFUNC 1 -#define FF_PRINT_LLI 0 -#define FF_PRINT_FLOAT 0 -#define FF_STRF_ENCODE 3 -/* FF_USE_STRFUNC switches string functions, f_gets(), f_putc(), f_puts() and -/ f_printf(). -/ -/ 0: Disable. FF_PRINT_LLI, FF_PRINT_FLOAT and FF_STRF_ENCODE have no effect. -/ 1: Enable without LF-CRLF conversion. -/ 2: Enable with LF-CRLF conversion. -/ -/ FF_PRINT_LLI = 1 makes f_printf() support long long argument and FF_PRINT_FLOAT = 1/2 - makes f_printf() support floating point argument. These features want C99 or later. -/ When FF_LFN_UNICODE >= 1 with LFN enabled, string functions convert the character -/ encoding in it. FF_STRF_ENCODE selects assumption of character encoding ON THE FILE -/ to be read/written via those functions. -/ -/ 0: ANSI/OEM in current CP -/ 1: Unicode in UTF-16LE -/ 2: Unicode in UTF-16BE -/ 3: Unicode in UTF-8 -*/ - -/*---------------------------------------------------------------------------/ -/ Locale and Namespace Configurations -/---------------------------------------------------------------------------*/ - -#define FF_CODE_PAGE 850 -/* This option specifies the OEM code page to be used on the target system. -/ Incorrect code page setting can cause a file open failure. -/ -/ 437 - U.S. -/ 720 - Arabic -/ 737 - Greek -/ 771 - KBL -/ 775 - Baltic -/ 850 - Latin 1 -/ 852 - Latin 2 -/ 855 - Cyrillic -/ 857 - Turkish -/ 860 - Portuguese -/ 861 - Icelandic -/ 862 - Hebrew -/ 863 - Canadian French -/ 864 - Arabic -/ 865 - Nordic -/ 866 - Russian -/ 869 - Greek 2 -/ 932 - Japanese (DBCS) -/ 936 - Simplified Chinese (DBCS) -/ 949 - Korean (DBCS) -/ 950 - Traditional Chinese (DBCS) -/ 0 - Include all code pages above and configured by f_setcp() -*/ - -#define FF_USE_LFN 3 -#define FF_MAX_LFN 255 -/* The FF_USE_LFN switches the support for LFN (long file name). -/ -/ 0: Disable LFN. FF_MAX_LFN has no effect. -/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe. -/ 2: Enable LFN with dynamic working buffer on the STACK. -/ 3: Enable LFN with dynamic working buffer on the HEAP. -/ -/ To enable the LFN, ffunicode.c needs to be added to the project. The LFN function -/ requiers certain internal working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and -/ additional (FF_MAX_LFN + 44) / 15 * 32 bytes when exFAT is enabled. -/ The FF_MAX_LFN defines size of the working buffer in UTF-16 code unit and it can -/ be in range of 12 to 255. It is recommended to be set it 255 to fully support LFN -/ specification. -/ When use stack for the working buffer, take care on stack overflow. When use heap -/ memory for the working buffer, memory management functions, ff_memalloc() and -/ ff_memfree() exemplified in ffsystem.c, need to be added to the project. */ - -#define FF_LFN_UNICODE 0 -/* This option switches the character encoding on the API when LFN is enabled. -/ -/ 0: ANSI/OEM in current CP (TCHAR = char) -/ 1: Unicode in UTF-16 (TCHAR = WCHAR) -/ 2: Unicode in UTF-8 (TCHAR = char) -/ 3: Unicode in UTF-32 (TCHAR = DWORD) -/ -/ Also behavior of string I/O functions will be affected by this option. -/ When LFN is not enabled, this option has no effect. */ - -#define FF_LFN_BUF 255 -#define FF_SFN_BUF 12 -/* This set of options defines size of file name members in the FILINFO structure -/ which is used to read out directory items. These values should be suffcient for -/ the file names to read. The maximum possible length of the read file name depends -/ on character encoding. When LFN is not enabled, these options have no effect. */ - -#define FF_FS_RPATH 2 -/* This option configures support for relative path. -/ -/ 0: Disable relative path and remove related functions. -/ 1: Enable relative path. f_chdir() and f_chdrive() are available. -/ 2: f_getcwd() function is available in addition to 1. -*/ - -/*---------------------------------------------------------------------------/ -/ Drive/Volume Configurations -/---------------------------------------------------------------------------*/ - -#define FF_VOLUMES 3 -/* Number of volumes (logical drives) to be used. (1-10) */ - -#define FF_STR_VOLUME_ID 1 -#define FF_VOLUME_STRS "D", "E", "F" -/* FF_STR_VOLUME_ID switches support for volume ID in arbitrary strings. -/ When FF_STR_VOLUME_ID is set to 1 or 2, arbitrary strings can be used as drive -/ number in the path name. FF_VOLUME_STRS defines the volume ID strings for each -/ logical drives. Number of items must not be less than FF_VOLUMES. Valid -/ characters for the volume ID strings are A-Z, a-z and 0-9, however, they are -/ compared in case-insensitive. If FF_STR_VOLUME_ID >= 1 and FF_VOLUME_STRS is -/ not defined, a user defined volume string table needs to be defined as: -/ -/ const char* VolumeStr[FF_VOLUMES] = {"ram","flash","sd","usb",... -*/ - -#define FF_MULTI_PARTITION 0 -/* This option switches support for multiple volumes on the physical drive. -/ By default (0), each logical drive number is bound to the same physical drive -/ number and only an FAT volume found on the physical drive will be mounted. -/ When this function is enabled (1), each logical drive number can be bound to -/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk() -/ funciton will be available. */ - -#define FF_MIN_SS 512 -#define FF_MAX_SS 512 -/* This set of options configures the range of sector size to be supported. (512, -/ 1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and -/ harddisk, but a larger value may be required for on-board flash memory and some -/ type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured -/ for variable sector size mode and disk_ioctl() function needs to implement -/ GET_SECTOR_SIZE command. */ - -#define FF_LBA64 0 -/* This option switches support for 64-bit LBA. (0:Disable or 1:Enable) -/ To enable the 64-bit LBA, also exFAT needs to be enabled. (FF_FS_EXFAT == 1) */ - -#define FF_MIN_GPT 0x100000000 -/* Minimum number of sectors to switch GPT as partitioning format in f_mkfs and -/ f_fdisk function. 0x100000000 max. This option has no effect when FF_LBA64 == 0. */ - -#define FF_USE_TRIM 0 -/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable) -/ To enable Trim function, also CTRL_TRIM command should be implemented to the -/ disk_ioctl() function. */ - -/*---------------------------------------------------------------------------/ -/ System Configurations -/---------------------------------------------------------------------------*/ - -#define FF_FS_TINY 0 -/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny) -/ At the tiny configuration, size of file object (FIL) is shrinked FF_MAX_SS bytes. -/ Instead of private sector buffer eliminated from the file object, common sector -/ buffer in the filesystem object (FATFS) is used for the file data transfer. */ - -#define FF_FS_EXFAT 0 -/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable) -/ To enable exFAT, also LFN needs to be enabled. (FF_USE_LFN >= 1) -/ Note that enabling exFAT discards ANSI C (C89) compatibility. */ - -#define FF_FS_NORTC 1 -#define FF_NORTC_MON 1 -#define FF_NORTC_MDAY 1 -#define FF_NORTC_YEAR 2020 -/* The option FF_FS_NORTC switches timestamp functiton. If the system does not have -/ any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable -/ the timestamp function. Every object modified by FatFs will have a fixed timestamp -/ defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time. -/ To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be -/ added to the project to read current time form real-time clock. FF_NORTC_MON, -/ FF_NORTC_MDAY and FF_NORTC_YEAR have no effect. -/ These options have no effect in read-only configuration (FF_FS_READONLY = 1). */ - -#define FF_FS_NOFSINFO 0 -/* If you need to know correct free space on the FAT32 volume, set bit 0 of this -/ option, and f_getfree() function at first time after volume mount will force -/ a full FAT scan. Bit 1 controls the use of last allocated cluster number. -/ -/ bit0=0: Use free cluster count in the FSINFO if available. -/ bit0=1: Do not trust free cluster count in the FSINFO. -/ bit1=0: Use last allocated cluster number in the FSINFO if available. -/ bit1=1: Do not trust last allocated cluster number in the FSINFO. -*/ - -#define FF_FS_LOCK 0 -/* The option FF_FS_LOCK switches file lock function to control duplicated file open -/ and illegal operation to open objects. This option must be 0 when FF_FS_READONLY -/ is 1. -/ -/ 0: Disable file lock function. To avoid volume corruption, application program -/ should avoid illegal open, remove and rename to the open objects. -/ >0: Enable file lock function. The value defines how many files/sub-directories -/ can be opened simultaneously under file lock control. Note that the file -/ lock control is independent of re-entrancy. */ - -#define FF_FS_REENTRANT 1 -#define FF_FS_TIMEOUT TIME_MS2I(1000) -#define FF_SYNC_t semaphore_t * -/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs -/ module itself. Note that regardless of this option, file access to different -/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs() -/ and f_fdisk() function, are always not re-entrant. Only file/directory access -/ to the same volume is under control of this function. -/ -/ 0: Disable re-entrancy. FF_FS_TIMEOUT and FF_SYNC_t have no effect. -/ 1: Enable re-entrancy. Also user provided synchronization handlers, -/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj() -/ function, must be added to the project. Samples are available in -/ option/syscall.c. -/ -/ The FF_FS_TIMEOUT defines timeout period in unit of time tick. -/ The FF_SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*, -/ SemaphoreHandle_t and etc. A header file for O/S definitions needs to be -/ included somewhere in the scope of ff.h. */ - -/*--- End of configuration options ---*/ diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/main.c b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/main.c index c147f7feeb..e536b0e7b2 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/main.c +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/main.c @@ -47,7 +47,7 @@ int main(void) { // if the USER button (blue one) is pressed, skip the check for a valid CLR image and remain in booter // the user button in this board has a pull-up resistor so the check has to be inverted - if (!palReadLine(LINE_BUTTON_USER)) + if (!palReadLine(LINE_BUTTON)) { // check for valid CLR image // we are checking for a valid image right after the configuration block @@ -95,9 +95,9 @@ int main(void) // Normal main() thread while (true) { - palSetLine(LINE_LED2_GREEN); + palSetLine(GPIOB_LED1); osDelay(500); - palClearLine(LINE_LED2_GREEN); + palClearLine(GPIOB_LED1); osDelay(500); } } diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/spiffs_config.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/spiffs_config.h deleted file mode 100644 index 87356939c5..0000000000 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/spiffs_config.h +++ /dev/null @@ -1,370 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright (c) 2013, petera, All Rights Reserved -// See LICENSE file in the project root for full license information. -// - -///////////////////////////////////////////////////////////////////////////// -// the configurations below are tunned for the MX25L51245G (from MACRONIX) -// that's fitted in the STM32F769I-DISCO board -///////////////////////////////////////////////////////////////////////////// - -#ifndef SPIFFS_CONFIG_H -#define SPIFFS_CONFIG_H - -#include - -///////////////////////////////////// -// need to map these types -typedef int32_t s32_t; -typedef uint32_t u32_t; -typedef int16_t s16_t; -typedef uint16_t u16_t; -typedef int8_t s8_t; -typedef uint8_t u8_t; - -// compile time switches - -// Set generic spiffs debug output call. -#ifndef SPIFFS_DBG -#define SPIFFS_DBG(_f, ...) // printf(_f, ## __VA_ARGS__) -#endif -// Set spiffs debug output call for garbage collecting. -#ifndef SPIFFS_GC_DBG -#define SPIFFS_GC_DBG(_f, ...) // printf(_f, ## __VA_ARGS__) -#endif -// Set spiffs debug output call for caching. -#ifndef SPIFFS_CACHE_DBG -#define SPIFFS_CACHE_DBG(_f, ...) // printf(_f, ## __VA_ARGS__) -#endif -// Set spiffs debug output call for system consistency checks. -#ifndef SPIFFS_CHECK_DBG -#define SPIFFS_CHECK_DBG(_f, ...) // printf(_f, ## __VA_ARGS__) -#endif -// Set spiffs debug output call for all api invocations. -#ifndef SPIFFS_API_DBG -#define SPIFFS_API_DBG(_f, ...) // printf(_f, ## __VA_ARGS__) -#endif - -// Defines spiffs debug print formatters -// some general signed number -#ifndef _SPIPRIi -#define _SPIPRIi "%d" -#endif -// address -#ifndef _SPIPRIad -#define _SPIPRIad "%08x" -#endif -// block -#ifndef _SPIPRIbl -#define _SPIPRIbl "%04x" -#endif -// page -#ifndef _SPIPRIpg -#define _SPIPRIpg "%04x" -#endif -// span index -#ifndef _SPIPRIsp -#define _SPIPRIsp "%04x" -#endif -// file descriptor -#ifndef _SPIPRIfd -#define _SPIPRIfd "%d" -#endif -// file object id -#ifndef _SPIPRIid -#define _SPIPRIid "%04x" -#endif -// file flags -#ifndef _SPIPRIfl -#define _SPIPRIfl "%02x" -#endif - -// Enable/disable API functions to determine exact number of bytes -// for filedescriptor and cache buffers. Once decided for a configuration, -// this can be disabled to reduce flash. -#ifndef SPIFFS_BUFFER_HELP -#define SPIFFS_BUFFER_HELP 0 -#endif - -// Enables/disable memory read caching of nucleus file system operations. -// If enabled, memory area must be provided for cache in SPIFFS_mount. -#ifndef SPIFFS_CACHE -#define SPIFFS_CACHE 1 -#endif -#if SPIFFS_CACHE -// Enables memory write caching for file descriptors in hydrogen -#ifndef SPIFFS_CACHE_WR -#define SPIFFS_CACHE_WR 1 -#endif - -// Enable/disable statistics on caching. Debug/test purpose only. -#ifndef SPIFFS_CACHE_STATS -#define SPIFFS_CACHE_STATS 1 -#endif -#endif - -// Always check header of each accessed page to ensure consistent state. -// If enabled it will increase number of reads, will increase flash. -#ifndef SPIFFS_PAGE_CHECK -#define SPIFFS_PAGE_CHECK 1 -#endif - -// Define maximum number of gc runs to perform to reach desired free pages. -#ifndef SPIFFS_GC_MAX_RUNS -#define SPIFFS_GC_MAX_RUNS 5 -#endif - -// Enable/disable statistics on gc. Debug/test purpose only. -#ifndef SPIFFS_GC_STATS -#define SPIFFS_GC_STATS 1 -#endif - -// Garbage collecting examines all pages in a block which and sums up -// to a block score. Deleted pages normally gives positive score and -// used pages normally gives a negative score (as these must be moved). -// To have a fair wear-leveling, the erase age is also included in score, -// whose factor normally is the most positive. -// The larger the score, the more likely it is that the block will -// picked for garbage collection. - -// Garbage collecting heuristics - weight used for deleted pages. -#ifndef SPIFFS_GC_HEUR_W_DELET -#define SPIFFS_GC_HEUR_W_DELET (5) -#endif -// Garbage collecting heuristics - weight used for used pages. -#ifndef SPIFFS_GC_HEUR_W_USED -#define SPIFFS_GC_HEUR_W_USED (-1) -#endif -// Garbage collecting heuristics - weight used for time between -// last erased and erase of this block. -#ifndef SPIFFS_GC_HEUR_W_ERASE_AGE -#define SPIFFS_GC_HEUR_W_ERASE_AGE (50) -#endif - -// Object name maximum length. Note that this length include the -// zero-termination character, meaning maximum string of characters -// can at most be SPIFFS_OBJ_NAME_LEN - 1. -#ifndef SPIFFS_OBJ_NAME_LEN -#define SPIFFS_OBJ_NAME_LEN (256) -#endif - -// Maximum length of the metadata associated with an object. -// Setting to non-zero value enables metadata-related API but also -// changes the on-disk format, so the change is not backward-compatible. -// -// Do note: the meta length must never exceed -// logical_page_size - (SPIFFS_OBJ_NAME_LEN + 64) -// -// This is derived from following: -// logical_page_size - (SPIFFS_OBJ_NAME_LEN + sizeof(spiffs_page_header) + -// spiffs_object_ix_header fields + at least some LUT entries) -#ifndef SPIFFS_OBJ_META_LEN -#define SPIFFS_OBJ_META_LEN (0) -#endif - -// Size of buffer allocated on stack used when copying data. -// Lower value generates more read/writes. No meaning having it bigger -// than logical page size. -#ifndef SPIFFS_COPY_BUFFER_STACK -#define SPIFFS_COPY_BUFFER_STACK (64) -#endif - -// Enable this to have an identifiable spiffs filesystem. This will look for -// a magic in all sectors to determine if this is a valid spiffs system or -// not on mount point. If not, SPIFFS_format must be called prior to mounting -// again. -#ifndef SPIFFS_USE_MAGIC -#define SPIFFS_USE_MAGIC (0) -#endif - -#if SPIFFS_USE_MAGIC -// Only valid when SPIFFS_USE_MAGIC is enabled. If SPIFFS_USE_MAGIC_LENGTH is -// enabled, the magic will also be dependent on the length of the filesystem. -// For example, a filesystem configured and formatted for 4 megabytes will not -// be accepted for mounting with a configuration defining the filesystem as 2 -// megabytes. -#ifndef SPIFFS_USE_MAGIC_LENGTH -#define SPIFFS_USE_MAGIC_LENGTH (0) -#endif -#endif - -// SPIFFS_LOCK and SPIFFS_UNLOCK protects spiffs from reentrancy on api level -// These should be defined on a multithreaded system - -// define this to enter a mutex if you're running on a multithreaded system -#ifndef SPIFFS_LOCK -extern void hal_spiffs_lock(); -#define SPIFFS_LOCK(fs) hal_spiffs_lock(fs); -#endif -// define this to exit a mutex if you're running on a multithreaded system -#ifndef SPIFFS_UNLOCK -extern void hal_spiffs_unlock(); -#define SPIFFS_UNLOCK(fs) hal_spiffs_unlock(fs); -#endif - -// Enable if only one spiffs instance with constant configuration will exist -// on the target. This will reduce calculations, flash and memory accesses. -// Parts of configuration must be defined below instead of at time of mount. -#ifndef SPIFFS_SINGLETON -#define SPIFFS_SINGLETON 0 -#endif - -#if SPIFFS_SINGLETON -// Instead of giving parameters in config struct, singleton build must -// give parameters in defines below. -#ifndef SPIFFS_CFG_PHYS_SZ -#define SPIFFS_CFG_PHYS_SZ(ignore) (1024 * 1024 * 2) -#endif -#ifndef SPIFFS_CFG_PHYS_ERASE_SZ -#define SPIFFS_CFG_PHYS_ERASE_SZ(ignore) (65536) -#endif -#ifndef SPIFFS_CFG_PHYS_ADDR -#define SPIFFS_CFG_PHYS_ADDR(ignore) (0) -#endif -#ifndef SPIFFS_CFG_LOG_PAGE_SZ -#define SPIFFS_CFG_LOG_PAGE_SZ(ignore) (256) -#endif -#ifndef SPIFFS_CFG_LOG_BLOCK_SZ -#define SPIFFS_CFG_LOG_BLOCK_SZ(ignore) (65536) -#endif -#endif - -// Enable this if your target needs aligned data for index tables -#ifndef SPIFFS_ALIGNED_OBJECT_INDEX_TABLES -#define SPIFFS_ALIGNED_OBJECT_INDEX_TABLES 0 -#endif - -// Enable this if you want the HAL callbacks to be called with the spiffs struct -#ifndef SPIFFS_HAL_CALLBACK_EXTRA -#define SPIFFS_HAL_CALLBACK_EXTRA 0 -#endif - -// Enable this if you want to add an integer offset to all file handles -// (spiffs_file). This is useful if running multiple instances of spiffs on -// same target, in order to recognise to what spiffs instance a file handle -// belongs. -// NB: This adds config field fh_ix_offset in the configuration struct when -// mounting, which must be defined. -#ifndef SPIFFS_FILEHDL_OFFSET -#define SPIFFS_FILEHDL_OFFSET 0 -#endif - -// Enable this to compile a read only version of spiffs. -// This will reduce binary size of spiffs. All code comprising modification -// of the file system will not be compiled. Some config will be ignored. -// HAL functions for erasing and writing to spi-flash may be null. Cache -// can be disabled for even further binary size reduction (and ram savings). -// Functions modifying the fs will return SPIFFS_ERR_RO_NOT_IMPL. -// If the file system cannot be mounted due to aborted erase operation and -// SPIFFS_USE_MAGIC is enabled, SPIFFS_ERR_RO_ABORTED_OPERATION will be -// returned. -// Might be useful for e.g. bootloaders and such. -#ifndef SPIFFS_READ_ONLY -#define SPIFFS_READ_ONLY 0 -#endif - -// Enable this to add a temporal file cache using the fd buffer. -// The effects of the cache is that SPIFFS_open will find the file faster in -// certain cases. It will make it a lot easier for spiffs to find files -// opened frequently, reducing number of readings from the spi flash for -// finding those files. -// This will grow each fd by 6 bytes. If your files are opened in patterns -// with a degree of temporal locality, the system is optimized. -// Examples can be letting spiffs serve web content, where one file is the css. -// The css is accessed for each html file that is opened, meaning it is -// accessed almost every second time a file is opened. Another example could be -// a log file that is often opened, written, and closed. -// The size of the cache is number of given file descriptors, as it piggybacks -// on the fd update mechanism. The cache lives in the closed file descriptors. -// When closed, the fd know the whereabouts of the file. Instead of forgetting -// this, the temporal cache will keep handling updates to that file even if the -// fd is closed. If the file is opened again, the location of the file is found -// directly. If all available descriptors become opened, all cache memory is -// lost. -#ifndef SPIFFS_TEMPORAL_FD_CACHE -#define SPIFFS_TEMPORAL_FD_CACHE 1 -#endif - -// Temporal file cache hit score. Each time a file is opened, all cached files -// will lose one point. If the opened file is found in cache, that entry will -// gain SPIFFS_TEMPORAL_CACHE_HIT_SCORE points. One can experiment with this -// value for the specific access patterns of the application. However, it must -// be between 1 (no gain for hitting a cached entry often) and 255. -#ifndef SPIFFS_TEMPORAL_CACHE_HIT_SCORE -#define SPIFFS_TEMPORAL_CACHE_HIT_SCORE 4 -#endif - -// Enable to be able to map object indices to memory. -// This allows for faster and more deterministic reading if cases of reading -// large files and when changing file offset by seeking around a lot. -// When mapping a file's index, the file system will be scanned for index pages -// and the info will be put in memory provided by user. When reading, the -// memory map can be looked up instead of searching for index pages on the -// medium. This way, user can trade memory against performance. -// Whole, parts of, or future parts not being written yet can be mapped. The -// memory array will be owned by spiffs and updated accordingly during garbage -// collecting or when modifying the indices. The latter is invoked by when the -// file is modified in some way. The index buffer is tied to the file -// descriptor. -#ifndef SPIFFS_IX_MAP -#define SPIFFS_IX_MAP 1 -#endif - -// By default SPIFFS in some cases relies on the property of NOR flash that bits -// cannot be set from 0 to 1 by writing and that controllers will ignore such -// bit changes. This results in fewer reads as SPIFFS can in some cases perform -// blind writes, with all bits set to 1 and only those it needs reset set to 0. -// Most of the chips and controllers allow this behavior, so the default is to -// use this technique. If your controller is one of the rare ones that don't, -// turn this option on and SPIFFS will perform a read-modify-write instead. -#ifndef SPIFFS_NO_BLIND_WRITES -#define SPIFFS_NO_BLIND_WRITES 0 -#endif - -// SPIFFS_vis disabled -#define SPIFFS_TEST_VISUALISATION 0 - -#if SPIFFS_TEST_VISUALISATION -#ifndef spiffs_printf -#define spiffs_printf(...) printf(__VA_ARGS__) -#endif -// spiffs_printf argument for a free page -#ifndef SPIFFS_TEST_VIS_FREE_STR -#define SPIFFS_TEST_VIS_FREE_STR "_" -#endif -// spiffs_printf argument for a deleted page -#ifndef SPIFFS_TEST_VIS_DELE_STR -#define SPIFFS_TEST_VIS_DELE_STR "/" -#endif -// spiffs_printf argument for an index page for given object id -#ifndef SPIFFS_TEST_VIS_INDX_STR -#define SPIFFS_TEST_VIS_INDX_STR(id) "i" -#endif -// spiffs_printf argument for a data page for given object id -#ifndef SPIFFS_TEST_VIS_DATA_STR -#define SPIFFS_TEST_VIS_DATA_STR(id) "d" -#endif -#endif - -// Types depending on configuration such as the amount of flash bytes -// given to spiffs file system in total (spiffs_file_system_size), -// the logical block size (log_block_size), and the logical page size -// (log_page_size) - -// Block index type. Make sure the size of this type can hold -// the highest number of all blocks - i.e. spiffs_file_system_size / log_block_size -typedef u16_t spiffs_block_ix; -// Page index type. Make sure the size of this type can hold -// the highest page number of all pages - i.e. spiffs_file_system_size / log_page_size -typedef u16_t spiffs_page_ix; -// Object id type - most significant bit is reserved for index flag. Make sure the -// size of this type can hold the highest object id on a full system, -// i.e. 2 + (spiffs_file_system_size / (2*log_page_size))*2 -typedef u16_t spiffs_obj_id; -// Object span index type. Make sure the size of this type can -// hold the largest possible span index on the system - -// i.e. (spiffs_file_system_size / log_page_size) - 1 -typedef u16_t spiffs_span_ix; - -#endif // SPIFFS_CONFIG_H diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_dev_onewire_config.cpp b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_dev_onewire_config.cpp index d2fe09ebc0..af91e060e5 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_dev_onewire_config.cpp +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_dev_onewire_config.cpp @@ -1,29 +1,29 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// +// // +// // Copyright (c) .NET Foundation and Contributors +// // See LICENSE file in the project root for full license information. +// // -#include "target_nf_dev_onewire_config.h" -#include +// #include "target_nf_dev_onewire_config.h" +// #include -/////////// -// UART4 // -/////////// +// /////////// +// // UART4 // +// /////////// -// pin configuration for UART4 -// port for TX pin is: GPIOC -// TX pin: is GPIOC_10 -// GPIO alternate pin function is 8 -UART_CONFIG_PINS(4, GPIOC, 10, 8) +// // pin configuration for UART4 +// // port for TX pin is: GPIOC +// // TX pin: is GPIOC_10 +// // GPIO alternate pin function is 8 +// UART_CONFIG_PINS(4, GPIOC, 10, 8) -// buffers -// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary -// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) -#if defined(__GNUC__) -__attribute__((aligned(32))) -#endif -uint8_t Uart4_TxBuffer[UART4_TX_SIZE]; -#if defined(__GNUC__) -__attribute__((aligned(32))) -#endif -uint8_t Uart4_RxBuffer[UART4_RX_SIZE]; +// // buffers +// // buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// // because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +// #if defined(__GNUC__) +// __attribute__((aligned(32))) +// #endif +// uint8_t Uart4_TxBuffer[UART4_TX_SIZE]; +// #if defined(__GNUC__) +// __attribute__((aligned(32))) +// #endif +// uint8_t Uart4_RxBuffer[UART4_RX_SIZE]; diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_dev_onewire_config.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_dev_onewire_config.h index b4c3aba457..e75c421121 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_dev_onewire_config.h +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_dev_onewire_config.h @@ -1,17 +1,17 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// +// // +// // Copyright (c) .NET Foundation and Contributors +// // See LICENSE file in the project root for full license information. +// // -/////////// -// UART4 // -/////////// +// /////////// +// // UART4 // +// /////////// -// enable USART4 -#define NF_ONEWIRE_STM32_UART_USE_USART4 TRUE +// // enable USART4 +// #define NF_ONEWIRE_STM32_UART_USE_USART4 TRUE -// buffers size -// tx buffer size: 32 bytes -#define UART4_TX_SIZE 32 -// rx buffer size: 32 bytes -#define UART4_RX_SIZE 32 \ No newline at end of file +// // buffers size +// // tx buffer size: 32 bytes +// #define UART4_TX_SIZE 32 +// // rx buffer size: 32 bytes +// #define UART4_RX_SIZE 32 \ No newline at end of file diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.cpp b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.cpp index 4c83d9afa5..b59c0e7423 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.cpp +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.cpp @@ -1,46 +1,46 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include -#include "target_nf_device_can_config.h" -#include - -/////////// -// CAN1 // -/////////// - -// pin configuration for CAN1 -// port for TX pin is: GPIOB -// TX pin: is GPIOB_09 -// port for RX pin is: GPIOB -// RX pin: is GPIOB_08 -// GPIO alternate pin function is 9 (see "Table 9. STM32F405xx and STM32F407xx alternate function mapping" in -// STM32F405xx/STM32F407xx datasheet) -CAN_CONFIG_PINS(1, GPIOB, GPIOB, 9, 8, 9) - -// buffer -CANRxFrame Can1_MsgBuffer[CAN1_RX_BUFFER_SIZE]; - -// initialization for CAN1 -CAN_INIT(1, CAN1_RX_BUFFER_SIZE) - -/////////// -// CAN2 // -/////////// - -// pin configuration for CAN2 -// port for TX pin is: GPIOB -// TX pin: is GPIOB_06 -// port for RX pin is: GPIOB -// RX pin: is GPIOB_05 -// GPIO alternate pin function is 9 (see "Table 9. STM32F405xx and STM32F407xx alternate function mapping" in -// STM32F405xx/STM32F407xx datasheet) -CAN_CONFIG_PINS(2, GPIOB, GPIOB, 6, 5, 9) - -// buffer -CANRxFrame Can2_MsgBuffer[CAN2_RX_BUFFER_SIZE]; - -// initialization for CAN1 -CAN_INIT(2, CAN2_RX_BUFFER_SIZE) +// // +// // Copyright (c) .NET Foundation and Contributors +// // See LICENSE file in the project root for full license information. +// // + +// #include +// #include "target_nf_device_can_config.h" +// #include + +// /////////// +// // CAN1 // +// /////////// + +// // pin configuration for CAN1 +// // port for TX pin is: GPIOB +// // TX pin: is GPIOB_09 +// // port for RX pin is: GPIOB +// // RX pin: is GPIOB_08 +// // GPIO alternate pin function is 9 (see "Table 9. STM32F405xx and STM32F407xx alternate function mapping" in +// // STM32F405xx/STM32F407xx datasheet) +// CAN_CONFIG_PINS(1, GPIOB, GPIOB, 9, 8, 9) + +// // buffer +// CANRxFrame Can1_MsgBuffer[CAN1_RX_BUFFER_SIZE]; + +// // initialization for CAN1 +// CAN_INIT(1, CAN1_RX_BUFFER_SIZE) + +// /////////// +// // CAN2 // +// /////////// + +// // pin configuration for CAN2 +// // port for TX pin is: GPIOB +// // TX pin: is GPIOB_06 +// // port for RX pin is: GPIOB +// // RX pin: is GPIOB_05 +// // GPIO alternate pin function is 9 (see "Table 9. STM32F405xx and STM32F407xx alternate function mapping" in +// // STM32F405xx/STM32F407xx datasheet) +// CAN_CONFIG_PINS(2, GPIOB, GPIOB, 6, 5, 9) + +// // buffer +// CANRxFrame Can2_MsgBuffer[CAN2_RX_BUFFER_SIZE]; + +// // initialization for CAN1 +// CAN_INIT(2, CAN2_RX_BUFFER_SIZE) diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.h index 77cbceded5..f3bae8eb03 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.h +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.h @@ -1,24 +1,24 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// +// // +// // Copyright (c) .NET Foundation and Contributors +// // See LICENSE file in the project root for full license information. +// // -////////// -// CAN1 // -////////// +// ////////// +// // CAN1 // +// ////////// -// enable CAN1 -#define NF_CAN_STM32_CAN_USE_CAN1 TRUE +// // enable CAN1 +// #define NF_CAN_STM32_CAN_USE_CAN1 TRUE -// buffers size -#define CAN1_RX_BUFFER_SIZE 16 +// // buffers size +// #define CAN1_RX_BUFFER_SIZE 16 -////////// -// CAN2 // -////////// +// ////////// +// // CAN2 // +// ////////// -// enable CAN2 -#define NF_CAN_STM32_CAN_USE_CAN2 TRUE +// // enable CAN2 +// #define NF_CAN_STM32_CAN_USE_CAN2 TRUE -// buffers size -#define CAN2_RX_BUFFER_SIZE 16 +// // buffers size +// #define CAN2_RX_BUFFER_SIZE 16 diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_spiffs.c b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_spiffs.c deleted file mode 100644 index 78fd0575f6..0000000000 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_spiffs.c +++ /dev/null @@ -1,864 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright (c) 2016 STMicroelectronics. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#include -#include - -#ifdef __cplusplus -extern "C" -{ - void HAL_Delay(uint32_t delay); - -#endif - - static uint8_t QSPI_ResetMemory(QSPI_HandleTypeDef *hqspi); - static uint8_t QSPI_EnterFourBytesAddress(QSPI_HandleTypeDef *hqspi); - static uint8_t QSPI_DummyCyclesCfg(QSPI_HandleTypeDef *hqspi); - static uint8_t QSPI_EnterMemory_QPI(QSPI_HandleTypeDef *hqspi); - // static uint8_t QSPI_ExitMemory_QPI(QSPI_HandleTypeDef *hqspi); - static uint8_t QSPI_OutDrvStrengthCfg(QSPI_HandleTypeDef *hqspi); - static uint8_t QSPI_WriteEnable(QSPI_HandleTypeDef *hqspi); - static uint8_t QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi, uint32_t Timeout); - static uint8_t QSPI_ReadChipID(QSPI_HandleTypeDef *hqspi, uint8_t *buffer); - - uint8_t QSPI_Read(uint8_t *pData, uint32_t readAddr, uint32_t size); - uint8_t QSPI_Write(uint8_t *pData, uint32_t writeAddr, uint32_t size); - uint8_t QSPI_Erase_Block(uint32_t blockAddress); - - // initialization of everything required for SPIFFS - // for this target is the QSPI driver - uint8_t target_spiffs_init() - { - uint8_t device_id[3] = {0, 0, 0}; - - /* QSPI initialization */ - /* QSPI freq = SYSCLK /(1 + ClockPrescaler) = 216 MHz/(1+1) = 108 Mhz */ - QSPID1.Init.ClockPrescaler = 1; /* QSPI freq = 216 MHz/(1+1) = 108 Mhz */ - QSPID1.Init.FifoThreshold = 16; - QSPID1.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE; - QSPID1.Init.FlashSize = POSITION_VAL(MX25L512_FLASH_SIZE) - 1; - QSPID1.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE; /* Min 30ns for nonRead */ - QSPID1.Init.ClockMode = QSPI_CLOCK_MODE_0; - QSPID1.Init.FlashID = QSPI_FLASH_ID_1; - QSPID1.Init.DualFlash = QSPI_DUALFLASH_DISABLE; - - // init driver - qspiStart(&QSPID1); - - if (HAL_QSPI_Init(&QSPID1) != HAL_OK) - { - return QSPI_ERROR; - } - - /* QSPI memory reset */ - if (QSPI_ResetMemory(&QSPID1) != QSPI_OK) - { - return QSPI_NOT_SUPPORTED; - } - - /* Put QSPI memory in QPI mode */ - if (QSPI_EnterMemory_QPI(&QSPID1) != QSPI_OK) - { - return QSPI_NOT_SUPPORTED; - } - - /* Set the QSPI memory in 4-bytes address mode */ - if (QSPI_EnterFourBytesAddress(&QSPID1) != QSPI_OK) - { - return QSPI_NOT_SUPPORTED; - } - - /* Configuration of the dummy cycles on QSPI memory side */ - if (QSPI_DummyCyclesCfg(&QSPID1) != QSPI_OK) - { - return QSPI_NOT_SUPPORTED; - } - - /* Configuration of the Output driver strength on memory side */ - if (QSPI_OutDrvStrengthCfg(&QSPID1) != QSPI_OK) - { - return QSPI_NOT_SUPPORTED; - } - - HAL_Delay(10); - - // sanity check: read device ID and unique ID - if (QSPI_ReadChipID(&QSPID1, device_id) != QSPI_OK) - { - return QSPI_ERROR; - } - - // // invalidate cache over read buffer to ensure that content from DMA is read - // // (only required for Cortex-M7) - // cacheBufferInvalidate(device_id, 3); - - // constants from ID Definitions table in MX25L51245G datasheet - ASSERT(device_id[0] == MX25L512_MANUFACTURER_ID); - ASSERT(device_id[1] == MX25L512_DEVICE_ID_MEM_TYPE); - ASSERT(device_id[2] == MX25L512_DEVICE_ID_MEM_CAPACITY); - - return QSPI_OK; - } - - // target specific implementation of hal_spiffs_erase - s32_t hal_spiffs_erase_0(u32_t addr, u32_t size) - { - uint32_t i = 0; - - // how many sectors need to be erased? - uint32_t erase_count = (size + SPIFFS0_ERASE_BLOCK_SIZE - 1) / SPIFFS0_ERASE_BLOCK_SIZE; - - for (i = 0; i < erase_count; i++) - { - if (QSPI_Erase_Block(addr) != QSPI_OK) - { - return SPIFFS_ERROR; - } - - // adjust sector address - addr += i * SPIFFS0_ERASE_BLOCK_SIZE; - } - - return SPIFFS_SUCCESS; - } - - // target specific implementation of hal_spiffs_read - s32_t hal_spiffs_read_0(u32_t addr, u32_t size, u8_t *dst) - { - if (QSPI_Read(dst, addr, size) != QSPI_OK) - { - return SPIFFS_ERROR; - } - - return SPIFFS_SUCCESS; - } - - // target specific implementation of hal_spiffs_write - s32_t hal_spiffs_write_0(u32_t addr, u32_t size, u8_t *src) - { - if (QSPI_Write(src, addr, size) != QSPI_OK) - { - return SPIFFS_ERROR; - } - - return SPIFFS_SUCCESS; - } - - static uint8_t QSPI_ResetMemory(QSPI_HandleTypeDef *hqspi) - { - QSPI_CommandTypeDef s_command; - QSPI_AutoPollingTypeDef s_config; - uint8_t reg; - - /* Send command RESET command in QPI mode (QUAD I/Os) */ - /* Initialize the reset enable command */ - s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; - s_command.Instruction = RESET_ENABLE_CMD; - s_command.AddressMode = QSPI_ADDRESS_NONE; - s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; - s_command.DataMode = QSPI_DATA_NONE; - s_command.DummyCycles = 0; - s_command.DdrMode = QSPI_DDR_MODE_DISABLE; - s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; - s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; - /* Send the command */ - if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* Send the reset memory command */ - s_command.Instruction = RESET_MEMORY_CMD; - if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* Send command RESET command in SPI mode */ - /* Initialize the reset enable command */ - s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE; - s_command.Instruction = RESET_ENABLE_CMD; - /* Send the command */ - if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - /* Send the reset memory command */ - s_command.Instruction = RESET_MEMORY_CMD; - if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* After reset CMD, 1000ms requested if QSPI memory SWReset occured during full chip erase operation */ - HAL_Delay(1000); - - /* Configure automatic polling mode to wait the WIP bit=0 */ - s_config.Match = 0; - s_config.Mask = MX25L512_SR_WIP; - s_config.MatchMode = QSPI_MATCH_MODE_AND; - s_config.StatusBytesSize = 1; - s_config.Interval = 0x10; - s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; - - s_command.Instruction = READ_STATUS_REG_CMD; - s_command.DataMode = QSPI_DATA_1_LINE; - - if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* Initialize the reading of status register */ - s_command.Instruction = READ_STATUS_REG_CMD; - s_command.NbData = 1; - - /* Configure the command */ - if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* Reception of the data */ - if (HAL_QSPI_Receive(hqspi, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* Enable write operations, command in 1 bit */ - /* Enable write operations */ - s_command.Instruction = WRITE_ENABLE_CMD; - s_command.DataMode = QSPI_DATA_NONE; - s_command.DummyCycles = 0; - s_command.NbData = 0; - - if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* Configure automatic polling mode to wait for write enabling */ - s_config.Match = MX25L512_SR_WREN; - s_config.Mask = MX25L512_SR_WREN; - s_config.MatchMode = QSPI_MATCH_MODE_AND; - s_config.StatusBytesSize = 1; - s_config.Interval = 0x10; - s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; - - s_command.Instruction = READ_STATUS_REG_CMD; - s_command.DataMode = QSPI_DATA_1_LINE; - s_command.NbData = 0; - - if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* Update the configuration register with new dummy cycles */ - s_command.Instruction = WRITE_STATUS_CFG_REG_CMD; - s_command.DataMode = QSPI_DATA_1_LINE; - s_command.NbData = 1; - - /* Enable the Quad IO on the QSPI memory (Non-volatile bit) */ - reg |= MX25L512_SR_QUADEN; - - /* Configure the command */ - if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* Transmission of the data */ - if (HAL_QSPI_Transmit(hqspi, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* 40ms Write Status/Configuration Register Cycle Time */ - HAL_Delay(40); - - // read back register to check MX25L512_SR_QUADEN - s_command.Instruction = READ_STATUS_REG_CMD; - s_command.DataMode = QSPI_DATA_1_LINE; - s_command.DummyCycles = 0; - s_command.NbData = 1; - - /* Configure the command */ - if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* Reception of the data */ - if (HAL_QSPI_Receive(hqspi, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - if (reg & MX25L512_SR_QUADEN) - { - return QSPI_OK; - } - else - { - return QSPI_ERROR; - } - } - - static uint8_t QSPI_DummyCyclesCfg(QSPI_HandleTypeDef *hqspi) - { - QSPI_CommandTypeDef s_command; - uint8_t reg[2]; - - /* Initialize the reading of status register */ - s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; - s_command.Instruction = READ_STATUS_REG_CMD; - s_command.AddressMode = QSPI_ADDRESS_NONE; - s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; - s_command.DataMode = QSPI_DATA_4_LINES; - s_command.DummyCycles = 0; - s_command.NbData = 1; - s_command.DdrMode = QSPI_DDR_MODE_DISABLE; - s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; - s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; - - /* Configure the command */ - if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* Reception of the data */ - if (HAL_QSPI_Receive(hqspi, &(reg[0]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* Initialize the reading of configuration register */ - s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; - s_command.Instruction = READ_CFG_REG_CMD; - s_command.AddressMode = QSPI_ADDRESS_NONE; - s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; - s_command.DataMode = QSPI_DATA_4_LINES; - s_command.DummyCycles = 0; - s_command.NbData = 1; - s_command.DdrMode = QSPI_DDR_MODE_DISABLE; - s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; - s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; - - /* Configure the command */ - if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* Reception of the data */ - if (HAL_QSPI_Receive(hqspi, &(reg[1]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* Enable write operations */ - if (QSPI_WriteEnable(hqspi) != QSPI_OK) - { - return QSPI_ERROR; - } - - /* Update the configuration register with new dummy cycles */ - s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; - s_command.Instruction = WRITE_STATUS_CFG_REG_CMD; - s_command.AddressMode = QSPI_ADDRESS_NONE; - s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; - s_command.DataMode = QSPI_DATA_4_LINES; - s_command.DummyCycles = 0; - s_command.NbData = 2; - s_command.DdrMode = QSPI_DDR_MODE_DISABLE; - s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; - s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; - - /* MX25L512_DUMMY_CYCLES_READ_QUAD = 3 for 10 cycles in QPI mode */ - MODIFY_REG( - reg[1], - MX25L512_CR_NB_DUMMY, - (MX25L512_DUMMY_CYCLES_READ_QUAD << POSITION_VAL(MX25L512_CR_NB_DUMMY))); - - /* Configure the write volatile configuration register command */ - if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* Transmission of the data */ - if (HAL_QSPI_Transmit(hqspi, &(reg[0]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* 40ms Write Status/Configuration Register Cycle Time */ - HAL_Delay(40); - - return QSPI_OK; - } - - static uint8_t QSPI_EnterMemory_QPI(QSPI_HandleTypeDef *hqspi) - { - QSPI_CommandTypeDef s_command; - QSPI_AutoPollingTypeDef s_config; - - /* Initialize the QPI enable command */ - /* QSPI memory is supported to be in SPI mode, so CMD on 1 LINE */ - s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE; - s_command.Instruction = ENTER_QUAD_CMD; - s_command.AddressMode = QSPI_ADDRESS_NONE; - s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; - s_command.DataMode = QSPI_DATA_NONE; - s_command.DummyCycles = 0; - s_command.DdrMode = QSPI_DDR_MODE_DISABLE; - s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; - s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; - - /* Send the command */ - if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* Configure automatic polling mode to wait the QUADEN bit=1 and WIP bit=0 */ - s_config.Match = MX25L512_SR_QUADEN; - s_config.Mask = MX25L512_SR_QUADEN | MX25L512_SR_WIP; - s_config.MatchMode = QSPI_MATCH_MODE_AND; - s_config.StatusBytesSize = 1; - s_config.Interval = 0x10; - s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; - - s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; - s_command.Instruction = READ_STATUS_REG_CMD; - s_command.DataMode = QSPI_DATA_4_LINES; - - if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - return QSPI_OK; - } - - // static uint8_t QSPI_ExitMemory_QPI( QSPI_HandleTypeDef *hqspi) - // { - // QSPI_CommandTypeDef s_command; - - // /* Initialize the QPI enable command */ - // /* QSPI memory is supported to be in QPI mode, so CMD on 4 LINES */ - // s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; - // s_command.Instruction = EXIT_QUAD_CMD; - // s_command.AddressMode = QSPI_ADDRESS_NONE; - // s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; - // s_command.DataMode = QSPI_DATA_NONE; - // s_command.DummyCycles = 0; - // s_command.DdrMode = QSPI_DDR_MODE_DISABLE; - // s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; - // s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; - - // /* Send the command */ - // if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - // { - // return QSPI_ERROR; - // } - - // return QSPI_OK; - // } - - static uint8_t QSPI_EnterFourBytesAddress(QSPI_HandleTypeDef *hqspi) - { - QSPI_CommandTypeDef s_command; - - /* Initialize the command */ - s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; - s_command.Instruction = ENTER_4_BYTE_ADDR_MODE_CMD; - s_command.AddressMode = QSPI_ADDRESS_NONE; - s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; - s_command.DataMode = QSPI_DATA_NONE; - s_command.DummyCycles = 0; - s_command.DdrMode = QSPI_DDR_MODE_DISABLE; - s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; - s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; - - /* Enable write operations */ - if (QSPI_WriteEnable(hqspi) != QSPI_OK) - { - return QSPI_ERROR; - } - - /* Send the command */ - if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* Configure automatic polling mode to wait the memory is ready */ - if (QSPI_AutoPollingMemReady(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK) - { - return QSPI_ERROR; - } - - return QSPI_OK; - } - - static uint8_t QSPI_WriteEnable(QSPI_HandleTypeDef *hqspi) - { - - // HAL_QSPI_Abort(&QSPID1); - - QSPI_CommandTypeDef s_command; - QSPI_AutoPollingTypeDef s_config; - - /* Enable write operations */ - s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; - s_command.Instruction = WRITE_ENABLE_CMD; - s_command.AddressMode = QSPI_ADDRESS_NONE; - s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; - s_command.DataMode = QSPI_DATA_NONE; - s_command.DummyCycles = 0; - s_command.DdrMode = QSPI_DDR_MODE_DISABLE; - s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; - s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; - - if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* Configure automatic polling mode to wait for write enabling */ - s_config.Match = MX25L512_SR_WREN; - s_config.Mask = MX25L512_SR_WREN; - s_config.MatchMode = QSPI_MATCH_MODE_AND; - s_config.StatusBytesSize = 1; - s_config.Interval = 0x10; - s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; - - s_command.Instruction = READ_STATUS_REG_CMD; - s_command.DataMode = QSPI_DATA_4_LINES; - - if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - return QSPI_OK; - } - - static uint8_t QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) - { - QSPI_CommandTypeDef s_command; - QSPI_AutoPollingTypeDef s_config; - - /* Configure automatic polling mode to wait for memory ready */ - s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; - s_command.Instruction = READ_STATUS_REG_CMD; - s_command.AddressMode = QSPI_ADDRESS_NONE; - s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; - s_command.DataMode = QSPI_DATA_4_LINES; - s_command.DummyCycles = 0; - s_command.DdrMode = QSPI_DDR_MODE_DISABLE; - s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; - s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; - - s_config.Match = 0; - s_config.Mask = MX25L512_SR_WIP; - s_config.MatchMode = QSPI_MATCH_MODE_AND; - s_config.StatusBytesSize = 1; - s_config.Interval = 0x10; - s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; - - if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, Timeout) != HAL_OK) - { - return QSPI_ERROR; - } - - return QSPI_OK; - } - - static uint8_t QSPI_OutDrvStrengthCfg(QSPI_HandleTypeDef *hqspi) - { - QSPI_CommandTypeDef s_command; - uint8_t reg[2]; - - /* Initialize the reading of status register */ - s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; - s_command.Instruction = READ_STATUS_REG_CMD; - s_command.AddressMode = QSPI_ADDRESS_NONE; - s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; - s_command.DataMode = QSPI_DATA_4_LINES; - s_command.DummyCycles = 0; - s_command.NbData = 1; - s_command.DdrMode = QSPI_DDR_MODE_DISABLE; - s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; - s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; - - /* Configure the command */ - if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* Reception of the data */ - if (HAL_QSPI_Receive(hqspi, &(reg[0]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* Initialize the reading of configuration register */ - s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; - s_command.Instruction = READ_CFG_REG_CMD; - s_command.AddressMode = QSPI_ADDRESS_NONE; - s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; - s_command.DataMode = QSPI_DATA_4_LINES; - s_command.DummyCycles = 0; - s_command.NbData = 1; - s_command.DdrMode = QSPI_DDR_MODE_DISABLE; - s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; - s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; - - /* Configure the command */ - if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* Reception of the data */ - if (HAL_QSPI_Receive(hqspi, &(reg[1]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* Enable write operations */ - if (QSPI_WriteEnable(&QSPID1) != QSPI_OK) - { - return QSPI_ERROR; - } - - /* Update the configuration register with new output driver strength */ - s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; - s_command.Instruction = WRITE_STATUS_CFG_REG_CMD; - s_command.AddressMode = QSPI_ADDRESS_NONE; - s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; - s_command.DataMode = QSPI_DATA_4_LINES; - s_command.DummyCycles = 0; - s_command.NbData = 2; - s_command.DdrMode = QSPI_DDR_MODE_DISABLE; - s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; - s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; - - /* Set Output Strength of the QSPI memory 15 ohms */ - MODIFY_REG(reg[1], MX25L512_CR_ODS, (MX25L512_CR_ODS_15 << POSITION_VAL(MX25L512_CR_ODS))); - - /* Configure the write volatile configuration register command */ - if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* Transmission of the data */ - if (HAL_QSPI_Transmit(hqspi, &(reg[0]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - return QSPI_OK; - } - - static uint8_t QSPI_ReadChipID(QSPI_HandleTypeDef *hqspi, uint8_t *buffer) - { - QSPI_CommandTypeDef s_command; - - /* Initialize the reading of status register */ - s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; - s_command.Instruction = MULTIPLE_IO_READ_ID_CMD; - s_command.AddressMode = QSPI_ADDRESS_NONE; - s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; - s_command.DataMode = QSPI_DATA_4_LINES; - s_command.DummyCycles = 0; - s_command.NbData = 3; - s_command.DdrMode = QSPI_DDR_MODE_DISABLE; - s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; - s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; - - /* Configure the command */ - if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* Reception of the data */ - if (HAL_QSPI_Receive(hqspi, buffer, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - return QSPI_OK; - } - - uint8_t QSPI_Read(uint8_t *pData, uint32_t readAddr, uint32_t size) - { - QSPI_CommandTypeDef s_command; - - /* Initialize the read command */ - s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; - s_command.Instruction = QSPI_READ_4_BYTE_ADDR_CMD; - s_command.AddressMode = QSPI_ADDRESS_4_LINES; - s_command.AddressSize = QSPI_ADDRESS_32_BITS; - s_command.Address = readAddr; - s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; - s_command.DataMode = QSPI_DATA_4_LINES; - s_command.DummyCycles = MX25L512_DUMMY_CYCLES_READ_QUAD_IO; - s_command.NbData = size; - s_command.DdrMode = QSPI_DDR_MODE_DISABLE; - s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; - s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; - - /* Configure the command */ - if (HAL_QSPI_Command(&QSPID1, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* Set S# timing for Read command */ - MODIFY_REG(QSPID1.Instance->DCR, QUADSPI_DCR_CSHT, QSPI_CS_HIGH_TIME_1_CYCLE); - - /* Reception of the data */ - if (HAL_QSPI_Receive(&QSPID1, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - // // invalidate cache over read buffer to ensure that content from DMA is read - // // (only required for Cortex-M7) - // cacheBufferInvalidate(pData, size); - - /* Restore S# timing for nonRead commands */ - MODIFY_REG(QSPID1.Instance->DCR, QUADSPI_DCR_CSHT, QSPI_CS_HIGH_TIME_4_CYCLE); - - SET_BIT(QSPID1.Instance->CR, QUADSPI_CR_ABORT); - - return QSPI_OK; - } - - uint8_t QSPI_Write(uint8_t *pData, uint32_t writeAddr, uint32_t size) - { - QSPI_CommandTypeDef s_command; - uint32_t end_addr, current_size, current_addr; - - /* Calculation of the size between the write address and the end of the page */ - current_size = MX25L512_PAGE_SIZE - (writeAddr % MX25L512_PAGE_SIZE); - - /* Check if the size of the data is less than the remaining place in the page */ - if (current_size > size) - { - current_size = size; - } - - /* Initialize the address variables */ - current_addr = writeAddr; - end_addr = writeAddr + size; - - /* Initialize the program command */ - s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; - s_command.Instruction = PAGE_PROG_CMD; - s_command.AddressMode = QSPI_ADDRESS_4_LINES; - s_command.AddressSize = QSPI_ADDRESS_32_BITS; - s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; - s_command.DataMode = QSPI_DATA_4_LINES; - s_command.DummyCycles = 0; - s_command.DdrMode = QSPI_DDR_MODE_DISABLE; - s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; - s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; - - /* Perform the write page by page */ - do - { - s_command.Address = current_addr; - s_command.NbData = current_size; - - /* Enable write operations */ - if (QSPI_WriteEnable(&QSPID1) != QSPI_OK) - { - return QSPI_ERROR; - } - - /* Configure the command */ - if (HAL_QSPI_Command(&QSPID1, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - // // flush DMA buffer to ensure cache coherency - // // (only required for Cortex-M7) - // cacheBufferFlush(pData, current_size); - - /* Transmission of the data */ - if (HAL_QSPI_Transmit(&QSPID1, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* Configure automatic polling mode to wait for end of program */ - if (QSPI_AutoPollingMemReady(&QSPID1, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK) - { - return QSPI_ERROR; - } - - /* Update the address and size variables for next page programming */ - current_addr += current_size; - pData += current_size; - current_size = - ((current_addr + MX25L512_PAGE_SIZE) > end_addr) ? (end_addr - current_addr) : MX25L512_PAGE_SIZE; - - } while (current_addr < end_addr); - - return QSPI_OK; - } - - uint8_t QSPI_Erase_Block(uint32_t blockAddress) - { - QSPI_CommandTypeDef s_command; - - /* Initialize the erase command */ - s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; - s_command.Instruction = SECTOR_ERASE_4_BYTE_ADDR_CMD; - s_command.AddressMode = QSPI_ADDRESS_4_LINES; - s_command.AddressSize = QSPI_ADDRESS_32_BITS; - s_command.Address = blockAddress; - s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; - s_command.DataMode = QSPI_DATA_NONE; - s_command.DummyCycles = 0; - s_command.DdrMode = QSPI_DDR_MODE_DISABLE; - s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; - s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; - - /* Enable write operations */ - if (QSPI_WriteEnable(&QSPID1) != QSPI_OK) - { - return QSPI_ERROR; - } - - /* Send the command */ - if (HAL_QSPI_Command(&QSPID1, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - return QSPI_ERROR; - } - - /* Configure automatic polling mode to wait for end of erase */ - if (QSPI_AutoPollingMemReady(&QSPID1, MX25L512_SECTOR_ERASE_MAX_TIME) != QSPI_OK) - { - return QSPI_ERROR; - } - - return QSPI_OK; - } - -#ifdef __cplusplus -} -#endif diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_spiffs.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_spiffs.h deleted file mode 100644 index 6e83b339bb..0000000000 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_spiffs.h +++ /dev/null @@ -1,138 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#ifndef TARGET_SPIFFS_H -#define TARGET_SPIFFS_H - -#include -#include -#include -#include - -#define SPIFFS_DRIVER_QSPI (1) - -// MX25L512 Configuration -#define MX25L512_FLASH_SIZE 0x4000000 /* 512 MBits => 64MBytes */ -#define MX25L512_SECTOR_SIZE 0x10000 /* 1024 sectors of 64KBytes */ -#define MX25L512_SUBSECTOR_SIZE 0x1000 /* 16384 subsectors of 4kBytes */ -#define MX25L512_PAGE_SIZE 0x100 /* 262144 pages of 256 bytes */ -#define MX25L512_DUMMY_CYCLES_READ_QUAD 3 -#define MX25L512_DUMMY_CYCLES_READ 8 -#define MX25L512_DUMMY_CYCLES_READ_QUAD_IO 10 -#define MX25L512_DUMMY_CYCLES_READ_DTR 6 -#define MX25L512_DUMMY_CYCLES_READ_QUAD_DTR 8 -#define MX25L512_BULK_ERASE_MAX_TIME 600000 -#define MX25L512_SECTOR_ERASE_MAX_TIME 2000 -#define MX25L512_SUBSECTOR_ERASE_MAX_TIME 800 - -// MX25L512 Commands -/* Reset Operations */ -#define RESET_ENABLE_CMD 0x66 -#define RESET_MEMORY_CMD 0x99 - -/* Identification Operations */ -#define READ_ID_CMD 0x9F -#define MULTIPLE_IO_READ_ID_CMD 0xAF -#define READ_SERIAL_FLASH_DISCO_PARAM_CMD 0x5A - -/* Read Operations */ -#define READ_CMD 0x03 -#define READ_4_BYTE_ADDR_CMD 0x13 -#define FAST_READ_CMD 0x0B -#define FAST_READ_DTR_CMD 0x0D -#define FAST_READ_4_BYTE_ADDR_CMD 0x0C -#define DUAL_OUT_FAST_READ_CMD 0x3B -#define DUAL_OUT_FAST_READ_4_BYTE_ADDR_CMD 0x3C -#define DUAL_INOUT_FAST_READ_CMD 0xBB -#define DUAL_INOUT_FAST_READ_DTR_CMD 0xBD -#define DUAL_INOUT_FAST_READ_4_BYTE_ADDR_CMD 0xBC -#define QUAD_OUT_FAST_READ_CMD 0x6B -#define QUAD_OUT_FAST_READ_4_BYTE_ADDR_CMD 0x6C -#define QUAD_INOUT_FAST_READ_CMD 0xEB -#define QUAD_INOUT_FAST_READ_DTR_CMD 0xED -#define QSPI_READ_4_BYTE_ADDR_CMD 0xEC - -/* Write Operations */ -#define WRITE_ENABLE_CMD 0x06 -#define WRITE_DISABLE_CMD 0x04 - -/* Register Operations */ -#define READ_STATUS_REG_CMD 0x05 -#define READ_CFG_REG_CMD 0x15 -#define WRITE_STATUS_CFG_REG_CMD 0x01 -#define READ_LOCK_REG_CMD 0x2D -#define WRITE_LOCK_REG_CMD 0x2C -#define READ_EXT_ADDR_REG_CMD 0xC8 -#define WRITE_EXT_ADDR_REG_CMD 0xC5 - -/* Program Operations */ -#define PAGE_PROG_CMD 0x02 -#define QSPI_PAGE_PROG_4_BYTE_ADDR_CMD 0x12 -#define QUAD_IN_FAST_PROG_CMD 0x38 -#define EXT_QUAD_IN_FAST_PROG_CMD 0x38 -#define QUAD_IN_FAST_PROG_4_BYTE_ADDR_CMD 0x3E - -/* Erase Operations */ -#define SUBSECTOR_ERASE_CMD 0x20 -#define SUBSECTOR_ERASE_4_BYTE_ADDR_CMD 0x21 -#define SECTOR_ERASE_CMD 0xD8 -#define SECTOR_ERASE_4_BYTE_ADDR_CMD 0xDC -#define BULK_ERASE_CMD 0xC7 -#define PROG_ERASE_RESUME_CMD 0x30 -#define PROG_ERASE_SUSPEND_CMD 0xB0 - -/* 4-byte Address Mode Operations */ -#define ENTER_4_BYTE_ADDR_MODE_CMD 0xB7 -#define EXIT_4_BYTE_ADDR_MODE_CMD 0xE9 - -/* Quad Operations */ -#define ENTER_QUAD_CMD 0x35 -#define EXIT_QUAD_CMD 0xF5 - -/* Added for compatibility */ -#define QPI_READ_4_BYTE_ADDR_CMD QSPI_READ_4_BYTE_ADDR_CMD -#define QPI_PAGE_PROG_4_BYTE_ADDR_CMD QSPI_PAGE_PROG_4_BYTE_ADDR_CMD - -// MX25L512 Registers -/* Status Register */ -#define MX25L512_SR_WIP ((uint8_t)0x01) /*!< Write in progress */ -#define MX25L512_SR_WREN ((uint8_t)0x02) /*!< Write enable latch */ -#define MX25L512_SR_BLOCKPR ((uint8_t)0x5C) /*!< Block protected against program and erase operations */ -#define MX25L512_SR_PRBOTTOM \ - ((uint8_t)0x20) /*!< Protected memory area defined by BLOCKPR starts from top or bottom \ - */ -#define MX25L512_SR_QUADEN ((uint8_t)0x40) /*!< Quad IO mode enabled if =1 */ -#define MX25L512_SR_SRWREN ((uint8_t)0x80) /*!< Status register write enable/disable */ - -/* Configuration Register */ -#define MX25L512_CR_ODS ((uint8_t)0x07) /*!< Output driver strength */ -#define MX25L512_CR_ODS_30 ((uint8_t)0x07) /*!< Output driver strength 30 ohms (default)*/ -#define MX25L512_CR_ODS_15 ((uint8_t)0x06) /*!< Output driver strength 15 ohms */ -#define MX25L512_CR_ODS_20 ((uint8_t)0x05) /*!< Output driver strength 20 ohms */ -#define MX25L512_CR_ODS_45 ((uint8_t)0x03) /*!< Output driver strength 45 ohms */ -#define MX25L512_CR_ODS_60 ((uint8_t)0x02) /*!< Output driver strength 60 ohms */ -#define MX25L512_CR_ODS_90 ((uint8_t)0x01) /*!< Output driver strength 90 ohms */ -#define MX25L512_CR_TB ((uint8_t)0x08) /*!< Top/Bottom bit used to configure the block protect area */ -#define MX25L512_CR_PBE ((uint8_t)0x10) /*!< Preamble Bit Enable */ -#define MX25L512_CR_4BYTE ((uint8_t)0x20) /*!< 3-bytes or 4-bytes addressing */ -#define MX25L512_CR_NB_DUMMY ((uint8_t)0xC0) /*!< Number of dummy clock cycles */ - -#define MX25L512_FLASH_SIZE 0x4000000 // 512MBits => 64MBytes -#define MX25L512_SECTOR_SIZE 0x10000 // 1024 sectors of 64KBytes -#define MX25L512_SUBSECTOR_SIZE 0x1000 // 16384 subsectors of 4kBytes -#define MX25L512_PAGE_SIZE 0x100 // 262144 pages of 256 bytes - -#define MX25L512_SUBSECTOR_ERASE_MAX_TIME 800 -#define MX25L512_MANUFACTURER_ID ((uint8_t)0xC2) -#define MX25L512_DEVICE_ID_MEM_TYPE ((uint8_t)0x20) -#define MX25L512_DEVICE_ID_MEM_CAPACITY ((uint8_t)0x1A) - -//////////////////////////////// - -#define SPIFFS0_TOTAL_SIZE MX25L512_FLASH_SIZE -#define SPIFFS0_ERASE_BLOCK_SIZE MX25L512_SECTOR_SIZE -#define SPIFFS0_LOGICAL_BLOCK_SIZE (64 * 1024) - -#endif // TARGET_SPIFFS_H diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_adc_config.cpp b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_adc_config.cpp index c96f9c7908..7d50929fef 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_adc_config.cpp +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_adc_config.cpp @@ -5,21 +5,21 @@ #include -const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { +// const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { - // ADC1 - {1, GPIOA, 6, ADC_CHANNEL_IN6}, - {1, GPIOA, 4, ADC_CHANNEL_IN4}, - {1, GPIOC, 2, ADC_CHANNEL_IN12}, +// // ADC1 +// {1, GPIOA, 6, ADC_CHANNEL_IN6}, +// {1, GPIOA, 4, ADC_CHANNEL_IN4}, +// {1, GPIOC, 2, ADC_CHANNEL_IN12}, - // ADC3 - {3, GPIOF, 10, ADC_CHANNEL_IN8}, - {3, GPIOF, 8, ADC_CHANNEL_IN6}, +// // ADC3 +// {3, GPIOF, 10, ADC_CHANNEL_IN8}, +// {3, GPIOF, 8, ADC_CHANNEL_IN6}, - // these are the internal sources, available only at ADC1 - {1, NULL, 0, ADC_CHANNEL_SENSOR}, - {1, NULL, 0, ADC_CHANNEL_VREFINT}, - {1, NULL, 0, ADC_CHANNEL_VBAT}, -}; +// // these are the internal sources, available only at ADC1 +// {1, NULL, 0, ADC_CHANNEL_SENSOR}, +// {1, NULL, 0, ADC_CHANNEL_VREFINT}, +// {1, NULL, 0, ADC_CHANNEL_VBAT}, +// }; -const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); +// const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_dac_config.cpp b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_dac_config.cpp index 948967e054..c85ba3f3d2 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_dac_config.cpp +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_dac_config.cpp @@ -5,10 +5,10 @@ #include -const NF_PAL_DAC_PORT_PIN_CHANNEL DacPortPinConfig[] = { +// const NF_PAL_DAC_PORT_PIN_CHANNEL DacPortPinConfig[] = { - // DAC1, channel 1, GPIO port A, pin 4 - {1, 1, GPIOA, 4}, -}; +// // DAC1, channel 1, GPIO port A, pin 4 +// {1, 1, GPIOA, 4}, +// }; -const int DacChannelCount = ARRAYSIZE(DacPortPinConfig); +// const int DacChannelCount = ARRAYSIZE(DacPortPinConfig); diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_i2c_config.cpp b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_i2c_config.cpp index 4083ad770d..7b4463e385 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_i2c_config.cpp +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_i2c_config.cpp @@ -15,4 +15,4 @@ // SCL pin: is GPIOB_8 // SDA pin: is GPIOB_9 // GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet) -I2C_CONFIG_PINS(1, GPIOB, GPIOB, 8, 9, 4) +// I2C_CONFIG_PINS(1, GPIOB, GPIOB, 8, 9, 4) diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_spi_config.cpp b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_spi_config.cpp index dc4a4d7863..951a89bfcc 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_spi_config.cpp +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_spi_config.cpp @@ -16,7 +16,7 @@ // AF 5 // GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) -SPI_CONFIG_PINS(2, GPIOA, 12, GPIOB, 14, GPIOB, 15, 5) +// SPI_CONFIG_PINS(2, GPIOA, 12, GPIOB, 14, GPIOB, 15, 5) ////////// // SPI5 // @@ -28,4 +28,4 @@ SPI_CONFIG_PINS(2, GPIOA, 12, GPIOB, 14, GPIOB, 15, 5) // port for MOSI pin is: PF9 (A5) // GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) -SPI_CONFIG_PINS(5, GPIOF, 7, GPIOF, 8, GPIOF, 9, 5) +// SPI_CONFIG_PINS(5, GPIOF, 7, GPIOF, 8, GPIOF, 9, 5) diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.cpp b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.cpp index 4baa860216..d6e5d2f390 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.cpp +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.cpp @@ -89,13 +89,13 @@ // RX pin: is GPIOC_12 // GPIO alternate pin function is 8 (see "Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate // function mapping" in STM32F769I datasheet) -UART_CONFIG_PINS(5, GPIOD, GPIOC, 2, 12, 8) +// UART_CONFIG_PINS(5, GPIOD, GPIOC, 2, 12, 8) -// initialization for UART5 -UART_INIT(5) +// // initialization for UART5 +// UART_INIT(5) -// un-initialization for UART5 -UART_UNINIT(5) +// // un-initialization for UART5 +// UART_UNINIT(5) /////////// // UART6 // @@ -108,13 +108,13 @@ UART_UNINIT(5) // RX pin: is GPIOC_7 // GPIO alternate pin function is 8 (see "Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate // function mapping" in STM32F769I datasheet) -UART_CONFIG_PINS(6, GPIOC, GPIOC, 6, 7, 8) +// UART_CONFIG_PINS(6, GPIOC, GPIOC, 6, 7, 8) -// initialization for UART6 -UART_INIT(6) +// // initialization for UART6 +// UART_INIT(6) -// un-initialization for UART6 -UART_UNINIT(6) +// // un-initialization for UART6 +// UART_UNINIT(6) // /////////// // // UART7 // diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.h index 5602811301..7e8e83d965 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.h +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.h @@ -36,14 +36,14 @@ /////////// // enable UART5 -#define NF_SERIAL_COMM_STM32_UART_USE_UART5 TRUE +// #define NF_SERIAL_COMM_STM32_UART_USE_UART5 TRUE /////////// // UART6 // /////////// // enable USART6 -#define NF_SERIAL_COMM_STM32_UART_USE_USART6 TRUE +// #define NF_SERIAL_COMM_STM32_UART_USE_USART6 TRUE // /////////// // // UART7 // From 36253f0f0ca7e398c57aded6dd143169aea9a7c6 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 8 Sep 2023 13:50:25 +0100 Subject: [PATCH 08/44] Comment out watchdog (for the moment) Remove SPIFFS and SD/MSD. --- .github/workflows/build-chibios-target.yml | 2 +- .../ST_STM32F767ZI_NUCLEO/nanoCLR/main.c | 29 ++----------------- 2 files changed, 3 insertions(+), 28 deletions(-) diff --git a/.github/workflows/build-chibios-target.yml b/.github/workflows/build-chibios-target.yml index 5dfbb4aa6b..89b279c762 100644 --- a/.github/workflows/build-chibios-target.yml +++ b/.github/workflows/build-chibios-target.yml @@ -16,7 +16,7 @@ jobs: matrix: # Add the target and build type you wish to generate firmware for: include: [ - { target: ST_STM32F767ZI_NUCLEO, build-type: MinSizeRel }, + # { target: ST_STM32F767ZI_NUCLEO, build-type: MinSizeRel }, { target: ST_STM32F767ZI_NUCLEO, build-type: Debug }, # { target: ST_STM32F769I_DISCOVERY, build-type: MinSizeRel }, diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/main.c b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/main.c index f4b3d4ea75..53ec8dc4cc 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/main.c +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/main.c @@ -18,22 +18,12 @@ #include #include -extern uint8_t hal_spiffs_config(); // need to declare the Receiver thread here osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); // declare CLRStartup thread here osThreadDef(CLRStartupThread, osPriorityNormal, 4096, "CLRStartupThread"); -#if HAL_USE_SDC -// declare SD Card working thread here -osThreadDef(SdCardWorkingThread, osPriorityNormal, 1024, "SDCWT"); -#endif -#if HAL_USBH_USE_MSD -// declare USB MSD thread here -osThreadDef(UsbMsdWorkingThread, osPriorityNormal, 1024, "USBMSDWT"); -#endif - // Application entry point. int main(void) { @@ -54,7 +44,7 @@ int main(void) osKernelInitialize(); // start watchdog - Watchdog_Init(); + // FIXME: Watchdog_Init(); !!! #if (HAL_NF_USE_STM32_CRC == TRUE) // startup crc @@ -65,11 +55,6 @@ int main(void) // this has to be called after osKernelInitialize, otherwise an hard fault will occur Target_ExternalMemoryInit(); -#if (NF_FEATURE_USE_SPIFFS == TRUE) - // config and init SPIFFS - hal_spiffs_config(); -#endif - // starts the serial driver sdStart(&SERIAL_DRIVER, NULL); @@ -87,16 +72,6 @@ int main(void) // create the CLR Startup thread osThreadCreate(osThread(CLRStartupThread), &clrSettings); -#if HAL_USE_SDC - // creates the SD card working thread - osThreadCreate(osThread(SdCardWorkingThread), NULL); -#endif - -#if HAL_USBH_USE_MSD - // create the USB MSD working thread - osThreadCreate(osThread(UsbMsdWorkingThread), &MSBLKD[0]); -#endif - // start kernel, after this main() will behave like a thread with priority osPriorityNormal osKernelStart(); @@ -104,4 +79,4 @@ int main(void) { osDelay(100); } -} \ No newline at end of file +} From 13f4c906866d8db405bffd15757b1c5edf1c061d Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 8 Sep 2023 14:20:56 +0100 Subject: [PATCH 09/44] Turn on LSI for watchdog. Align block storage and ld for debug. --- .github/workflows/build-chibios-target.yml | 4 +- .../common/Device_BlockStorage.c | 106 +++++++++--------- .../nanoCLR/STM32F76xx_CLR.ld | 6 +- .../ST_STM32F767ZI_NUCLEO/nanoCLR/main.c | 2 +- .../ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h | 2 +- .../target_windows_storage_config.h | 10 -- 6 files changed, 62 insertions(+), 68 deletions(-) delete mode 100644 targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_windows_storage_config.h diff --git a/.github/workflows/build-chibios-target.yml b/.github/workflows/build-chibios-target.yml index 89b279c762..ea4353b595 100644 --- a/.github/workflows/build-chibios-target.yml +++ b/.github/workflows/build-chibios-target.yml @@ -109,9 +109,9 @@ jobs: # Move into the .devcontainer directory pushd .devcontainer # We could target the chibios container for a quicker build - # sed -i -- 's|"dockerFile": "Dockerfile.All"|"dockerFile": "Dockerfile.ChibiOS"|g' devcontainer.json + sed -i -- 's|"dockerFile": "Dockerfile.All"|"dockerFile": "Dockerfile.ChibiOS"|g' devcontainer.json # But we actually require a change to the available devcontainer image, so we target the source instead (which takes a little longer to build). - sed -i -- 's|"dockerFile": "Dockerfile.All"|"dockerFile": "sources/Dockerfile.ChibiOS"|g' devcontainer.json + # sed -i -- 's|"dockerFile": "Dockerfile.All"|"dockerFile": "sources/Dockerfile.ChibiOS"|g' devcontainer.json # For the CI, we need to remove the unsupported (azure cli) mount directive. sed -i -- 's|"source=${env:HOME}${env:USERPROFILE}/.azure,target=/home/vscode/.azure,type=bind"|//"source=${env:HOME}${env:USERPROFILE}/.azure,target=/home/vscode/.azure,type=bind",|g' devcontainer.json # Move out of the .devcontainer directory diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/Device_BlockStorage.c b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/Device_BlockStorage.c index 717f0fc94e..05c8653805 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/Device_BlockStorage.c +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/Device_BlockStorage.c @@ -7,96 +7,100 @@ #include // 32kB blocks -const BlockRange BlockRange1[] = { - {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 0}, // 0x08000000 nanoBooter +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 0 }, // 08000000 nanoBooter /////////////////////////////////////////////////////////////////////////////////////// // because this target is using a configuration block need to add the // configuration manager files to the CMake and call ConfigurationManager_Initialize() // in nanoBooter so the configuration can be managed when in booter mode /////////////////////////////////////////////////////////////////////////////////////// - {BlockRange_BLOCKTYPE_CONFIG, 1, 1}, // 0x08008000 configuration block + { BlockRange_BLOCKTYPE_CONFIG , 1, 1 }, // 08008000 configuration block /////////////////////////////////////////////////////////////////////////////////////// - - {BlockRange_BLOCKTYPE_CODE, 2, 3} // 0x08010000 nanoCLR + + { BlockRange_BLOCKTYPE_CODE , 2, 3 } // 08010000 nanoCLR }; -// 128kB block -const BlockRange BlockRange2[] = { - {BlockRange_BLOCKTYPE_CODE, 0, 0} // 0x08020000 nanoCLR +//128kB block +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 08020000 nanoCLR }; // 256kB blocks -const BlockRange BlockRange3[] = { - {BlockRange_BLOCKTYPE_CODE, 0, 1}, // 08040000 nanoCLR - {BlockRange_BLOCKTYPE_DEPLOYMENT, 2, 6} // 080C0000 deployment +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 2 }, // 08040000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 3, 6 } // 08100000 deployment }; -const BlockRegionInfo BlockRegions[] = { +const BlockRegionInfo BlockRegions[] = +{ { - (0), // no attributes for this region - 0x08000000, // start address for block region - 4, // total number of blocks in this region - 0x8000, // total number of bytes per block + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x8000, // total number of bytes per block ARRAYSIZE_CONST_EXPR(BlockRange1), BlockRange1, }, { - (0), // no attributes for this region - 0x08020000, // start address for block region - 1, // total number of blocks in this region - 0x20000, // total number of bytes per block + (0), // no attributes for this region + 0x08020000, // start address for block region + 1, // total number of blocks in this region + 0x20000, // total number of bytes per block ARRAYSIZE_CONST_EXPR(BlockRange2), BlockRange2, }, { - (0), // no attributes for this region - 0x08040000, // start address for block region - 7, // total number of blocks in this region - 0x40000, // total number of bytes per block + (0), // no attributes for this region + 0x08040000, // start address for block region + 7, // total number of blocks in this region + 0x40000, // total number of bytes per block ARRAYSIZE_CONST_EXPR(BlockRange3), BlockRange3, }, }; -const DeviceBlockInfo Device_BlockInfo = { - (MediaAttribute_SupportsXIP), // STM32 flash memory is XIP - 2, // UINT32 BytesPerSector - ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; - (BlockRegionInfo *)BlockRegions, // const BlockRegionInfo* pRegions; +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), // STM32 flash memory is XIP + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; }; -MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { - { - // BLOCK_CONFIG +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG { - 0, // GPIO_PIN Pin; - false, // BOOL ActiveState; + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; }, - (DeviceBlockInfo *)&Device_BlockInfo, // BlockDeviceinfo + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo }, - { - // CPU_MEMORY_CONFIG - 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; - true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; - 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; - 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; - 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; - 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; - 0x00200000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; - 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable - 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead - 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00200000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable }, - 0, // UINT32 ChipProtection; - 0, // UINT32 ManufacturerCode; - 0, // UINT32 DeviceCode; + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; }; -BlockStorageDevice Device_BlockStorage; +BlockStorageDevice Device_BlockStorage; diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/STM32F76xx_CLR.ld b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/STM32F76xx_CLR.ld index b067340e01..81a1ad82e7 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/STM32F76xx_CLR.ld +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/STM32F76xx_CLR.ld @@ -18,8 +18,8 @@ */ MEMORY { - flash0 (rx) : org = 0x08010000, len = 2M - 32k - 32k - 1280k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ - flash1 (rx) : org = 0x00210000, len = 2M - 32k - 32k - 1280k + flash0 (rx) : org = 0x08010000, len = 2M - 32k - 32k - 1024k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + flash1 (rx) : org = 0x00210000, len = 2M - 32k - 32k - 1024k flash2 (rx) : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0 @@ -27,7 +27,7 @@ MEMORY flash6 (rx) : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0 config (rw) : org = 0x08008000, len = 32k /* space reserved for configuration block */ - deployment (rx) : org = 0x080C0000, len = 1280k /* space reserved for application deployment */ + deployment (rx) : org = 0x08100000, len = 1024k /* space reserved for application deployment */ ramvt (wx) : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ ram0 (wx) : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */ ram1 (wx) : org = 0x20020000, len = 368k /* SRAM1 */ diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/main.c b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/main.c index 53ec8dc4cc..8451ba48aa 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/main.c +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/main.c @@ -44,7 +44,7 @@ int main(void) osKernelInitialize(); // start watchdog - // FIXME: Watchdog_Init(); !!! + Watchdog_Init(); #if (HAL_NF_USE_STM32_CRC == TRUE) // startup crc diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h index 793d6b169b..67247e46d1 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h @@ -50,7 +50,7 @@ #define STM32_PLS STM32_PLS_LEV0 #define STM32_BKPRAM_ENABLE FALSE #define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED FALSE +#define STM32_LSI_ENABLED TRUE #define STM32_HSE_ENABLED TRUE #define STM32_LSE_ENABLED TRUE #define STM32_CLOCK48_REQUIRED TRUE diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_windows_storage_config.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_windows_storage_config.h deleted file mode 100644 index b19b630a24..0000000000 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_windows_storage_config.h +++ /dev/null @@ -1,10 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -// maps the SD Card driver -// #define SD_CARD_DRIVER SDCD2 - -// maps the SD Card detect GPIO definition (in Target_Windows_Storage.c) to board GPIO line (in board.h) -// #define SDCARD_LINE_DETECT LINE_SD_DETECT From 8ebb87d9b0062a9d48acb327f0fe151323fa79b4 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 8 Sep 2023 14:37:28 +0100 Subject: [PATCH 10/44] Try turning off watchdog. --- targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json | 1 + targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/halconf.h | 2 ++ .../ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/halconf_nf.h | 8 ++++---- targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h | 2 +- 4 files changed, 8 insertions(+), 5 deletions(-) diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json index 77f9f8167a..fa75a812f9 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json @@ -25,6 +25,7 @@ "NF_FEATURE_RTC": "ON", "NF_FEATURE_HAS_SDCARD": "OFF", "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", + "NF_FEATURE_WATCHDOG": "OFF", "SWO_OUTPUT": "OFF", "NF_BUILD_RTM": "OFF", "API_System.Math": "ON", diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/halconf.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/halconf.h index ede93b01bf..a129779b01 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/halconf.h +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/halconf.h @@ -555,6 +555,8 @@ // header for nanoFramework overlay #include "halconf_nf.h" + + #endif /* HALCONF_H */ /** @} */ diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/halconf_nf.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/halconf_nf.h index 59eeb3c570..a5696a1bda 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/halconf_nf.h +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/halconf_nf.h @@ -21,10 +21,10 @@ #define HAL_NF_USE_STM32_QSPI FALSE #endif -// enable STM32 graphics -#if !defined(HAL_DSI_MODULE_ENABLED) -#define HAL_DSI_MODULE_ENABLED TRUE -#endif +// // enable STM32 graphics +// #if !defined(HAL_DSI_MODULE_ENABLED) +// #define HAL_DSI_MODULE_ENABLED TRUE +// #endif #if !defined(HAL_LTDC_MODULE_ENABLED) #define HAL_LTDC_MODULE_ENABLED TRUE diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h index 67247e46d1..793d6b169b 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h @@ -50,7 +50,7 @@ #define STM32_PLS STM32_PLS_LEV0 #define STM32_BKPRAM_ENABLE FALSE #define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE #define STM32_HSE_ENABLED TRUE #define STM32_LSE_ENABLED TRUE #define STM32_CLOCK48_REQUIRED TRUE From e3e900e9780209cde93c1f61b50013aedb08aad7 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 8 Sep 2023 15:48:28 +0100 Subject: [PATCH 11/44] Fix missing include for mcuconf Start adjusting some port configurations --- .../nanoBooter/mcuconf.h | 4 - .../ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h | 9 +- .../target_nf_device_can_config.cpp | 78 ++++---- .../target_nf_device_can_config.h | 28 +-- .../target_system_device_adc_config.cpp | 39 ++-- .../target_system_device_i2c_config.cpp | 26 +++ .../target_system_io_ports_config.cpp | 166 ++++++------------ .../target_system_io_ports_config.h | 14 +- 8 files changed, 160 insertions(+), 204 deletions(-) diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/mcuconf.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/mcuconf.h index 793d6b169b..d1ece4579d 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/mcuconf.h +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/mcuconf.h @@ -24,11 +24,7 @@ */ #define STM32F7xx_MCUCONF -#define STM32F765_MCUCONF #define STM32F767_MCUCONF -#define STM32F777_MCUCONF -#define STM32F769_MCUCONF -#define STM32F779_MCUCONF /* * General settings. diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h index 793d6b169b..428e4ff2ca 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h @@ -24,11 +24,7 @@ */ #define STM32F7xx_MCUCONF -#define STM32F765_MCUCONF #define STM32F767_MCUCONF -#define STM32F777_MCUCONF -#define STM32F769_MCUCONF -#define STM32F779_MCUCONF /* * General settings. @@ -436,6 +432,9 @@ #define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1 -// clang-format on +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" #endif /* MCUCONF_H */ + +// clang-format on diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.cpp b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.cpp index b59c0e7423..d393b8737e 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.cpp +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.cpp @@ -1,46 +1,32 @@ -// // -// // Copyright (c) .NET Foundation and Contributors -// // See LICENSE file in the project root for full license information. -// // - -// #include -// #include "target_nf_device_can_config.h" -// #include - -// /////////// -// // CAN1 // -// /////////// - -// // pin configuration for CAN1 -// // port for TX pin is: GPIOB -// // TX pin: is GPIOB_09 -// // port for RX pin is: GPIOB -// // RX pin: is GPIOB_08 -// // GPIO alternate pin function is 9 (see "Table 9. STM32F405xx and STM32F407xx alternate function mapping" in -// // STM32F405xx/STM32F407xx datasheet) -// CAN_CONFIG_PINS(1, GPIOB, GPIOB, 9, 8, 9) - -// // buffer -// CANRxFrame Can1_MsgBuffer[CAN1_RX_BUFFER_SIZE]; - -// // initialization for CAN1 -// CAN_INIT(1, CAN1_RX_BUFFER_SIZE) - -// /////////// -// // CAN2 // -// /////////// - -// // pin configuration for CAN2 -// // port for TX pin is: GPIOB -// // TX pin: is GPIOB_06 -// // port for RX pin is: GPIOB -// // RX pin: is GPIOB_05 -// // GPIO alternate pin function is 9 (see "Table 9. STM32F405xx and STM32F407xx alternate function mapping" in -// // STM32F405xx/STM32F407xx datasheet) -// CAN_CONFIG_PINS(2, GPIOB, GPIOB, 6, 5, 9) - -// // buffer -// CANRxFrame Can2_MsgBuffer[CAN2_RX_BUFFER_SIZE]; - -// // initialization for CAN1 -// CAN_INIT(2, CAN2_RX_BUFFER_SIZE) +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_nf_device_can_config.h" +#include + +/////////// +// CAN1 // +/////////// + +// pin configuration for CAN1 +// port for TX pin is: GPIOD +// TX pin: is GPIOB_01 +// port for RX pin is: GPIOD +// RX pin: is GPIOB_00 +// GPIO alternate pin function is 8 (see alternate function mapping table in device datasheet) +CAN_CONFIG_PINS(1, GPIOD, GPIOD, 1, 0, 8) + +// buffer +CANRxFrame Can1_MsgBuffer[CAN1_RX_BUFFER_SIZE]; + +// initialization for CAN1 +CAN_INIT(1, CAN1_RX_BUFFER_SIZE) + +/////////// +// CAN2 // +/////////// + +// NOT AVAILABLE diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.h index f3bae8eb03..88af94efca 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.h +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.h @@ -1,21 +1,21 @@ -// // -// // Copyright (c) .NET Foundation and Contributors -// // See LICENSE file in the project root for full license information. -// // +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// -// ////////// -// // CAN1 // -// ////////// +////////// +// CAN1 // +////////// -// // enable CAN1 -// #define NF_CAN_STM32_CAN_USE_CAN1 TRUE +// enable CAN1 +#define NF_CAN_STM32_CAN_USE_CAN1 TRUE -// // buffers size -// #define CAN1_RX_BUFFER_SIZE 16 +// buffers size +#define CAN1_RX_BUFFER_SIZE 16 -// ////////// -// // CAN2 // -// ////////// +////////// +// CAN2 // +////////// // // enable CAN2 // #define NF_CAN_STM32_CAN_USE_CAN2 TRUE diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_adc_config.cpp b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_adc_config.cpp index 7d50929fef..4064c0ffc7 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_adc_config.cpp +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_adc_config.cpp @@ -5,21 +5,32 @@ #include -// const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { +const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { -// // ADC1 -// {1, GPIOA, 6, ADC_CHANNEL_IN6}, -// {1, GPIOA, 4, ADC_CHANNEL_IN4}, -// {1, GPIOC, 2, ADC_CHANNEL_IN12}, + // ADC1 + {1, GPIOA, 2, ADC_CHANNEL_IN2}, + {1, GPIOA, 3, ADC_CHANNEL_IN3}, + {1, GPIOB, 1, ADC_CHANNEL_IN9}, + {1, GPIOA, 0, ADC_CHANNEL_IN10}, + {1, GPIOC, 1, ADC_CHANNEL_IN11}, + {1, GPIOC, 2, ADC_CHANNEL_IN12}, + {1, GPIOC, 3, ADC_CHANNEL_IN13}, + {1, GPIOC, 4, ADC_CHANNEL_IN14}, + {1, GPIOC, 5, ADC_CHANNEL_IN15}, -// // ADC3 -// {3, GPIOF, 10, ADC_CHANNEL_IN8}, -// {3, GPIOF, 8, ADC_CHANNEL_IN6}, -// // these are the internal sources, available only at ADC1 -// {1, NULL, 0, ADC_CHANNEL_SENSOR}, -// {1, NULL, 0, ADC_CHANNEL_VREFINT}, -// {1, NULL, 0, ADC_CHANNEL_VBAT}, -// }; + // ADC3 + {3, GPIOB, 1, ADC_CHANNEL_IN1}, + {3, GPIOF, 3, ADC_CHANNEL_IN9}, + {3, GPIOF, 4, ADC_CHANNEL_IN14}, -// const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); + // ADC12 + {12, GPIOC, 2, ADC_CHANNEL_IN8}, + + // these are the internal sources, available only at ADC1 + // {1, NULL, 0, ADC_CHANNEL_SENSOR}, + // {1, NULL, 0, ADC_CHANNEL_VREFINT}, + // {1, NULL, 0, ADC_CHANNEL_VBAT}, +}; + +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_i2c_config.cpp b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_i2c_config.cpp index 7b4463e385..7f7ab0e963 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_i2c_config.cpp +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_i2c_config.cpp @@ -9,6 +9,32 @@ // I2C1 // ////////// +// pin configuration for I2C1 +// port for SCL pin is: GPIOB +// port for SDA pin is: GPIOB +// SCL pin: is GPIOB_8 +// SDA pin: is GPIOB_9 +// GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, GPIOB, GPIOB, 8, 9, 4) + + +////////// +// I2C2 // +////////// + +// pin configuration for I2C1 +// port for SCL pin is: GPIOB +// port for SDA pin is: GPIOB +// SCL pin: is GPIOB_8 +// SDA pin: is GPIOB_9 +// GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet) +// I2C_CONFIG_PINS(1, GPIOB, GPIOB, 8, 9, 4) + + +////////// +// I2C3 // +////////// + // pin configuration for I2C1 // port for SCL pin is: GPIOB // port for SDA pin is: GPIOB diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.cpp b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.cpp index d6e5d2f390..9dddbdd256 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.cpp +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.cpp @@ -6,148 +6,86 @@ #include "target_system_io_ports_config.h" #include -// /////////// -// // UART1 // -// /////////// - -// // pin configuration for UART1 -// // port for TX pin is: GPIOD -// // port for RX pin is: GPIOC -// // TX pin: is GPIOD_2 -// // RX pin: is GPIOC_12 -// // GPIO alternate pin function is 8 (see "Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate -// function mapping" in STM32F769I datasheet) UART_CONFIG_PINS(1, GPIOD, GPIOC, 2, 12, 8) - -// // initialization for UART1 -// UART_INIT(1) +/////////// +// UART1 // +/////////// -// // un-initialization for UART1 -// UART_UNINIT(1) +// pin configuration for UART1 +// port for TX pin is: GPIOC +// port for RX pin is: GPIOC +// TX pin: is GPIOC_4 +// RX pin: is GPIOC_5 +// GPIO alternate pin function is 8 (see alternate function mapping table in device datasheet) +UART_CONFIG_PINS(1, GPIOC, GPIOC, 4, 5, 8) -// /////////// -// // UART2 // -// /////////// +// initialization for UART1 +UART_INIT(1) -// // pin configuration for UART2 -// // port for TX pin is: GPIOD -// // port for RX pin is: GPIOC -// // TX pin: is GPIOD_2 -// // RX pin: is GPIOC_12 -// // GPIO alternate pin function is 8 (see "Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate -// function mapping" in STM32F769I datasheet) UART_CONFIG_PINS(2, GPIOD, GPIOC, 2, 12, 8) +// un-initialization for UART1 +UART_UNINIT(1) -// // initialization for UART2 -// UART_INIT(2) +/////////// +// UART2 // +/////////// -// // un-initialization for UART2 -// UART_UNINIT(2) +// pin configuration for UART2 +// port for TX pin is: GPIOD +// port for RX pin is: GPIOD +// TX pin: is GPIOD_5 +// RX pin: is GPIOC_6 +// GPIO alternate pin function is 8 (see alternate function mapping table in device datasheet) +UART_CONFIG_PINS(2, GPIOD, GPIOD, 5, 6, 8) -// /////////// -// // UART3 // -// /////////// +// initialization for UART2 +UART_INIT(2) -// // pin configuration for UART3 -// // port for TX pin is: GPIOD -// // port for RX pin is: GPIOC -// // TX pin: is GPIOD_2 -// // RX pin: is GPIOC_12 -// // GPIO alternate pin function is 8 (see "Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate -// function mapping" in STM32F769I datasheet) UART_CONFIG_PINS(3, GPIOD, GPIOC, 2, 12, 8) +// un-initialization for UART2 +UART_UNINIT(2) -// // initialization for UART3 -// UART_INIT(3) +/////////// +// UART3 // +/////////// -// // un-initialization for UART3 -// UART_UNINIT(3) +// Used for STLINK. // /////////// // // UART4 // // /////////// -// // pin configuration for UART4 -// // port for TX pin is: GPIOD -// // port for RX pin is: GPIOC -// // TX pin: is GPIOD_2 -// // RX pin: is GPIOC_12 -// // GPIO alternate pin function is 8 (see "Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate -// function mapping" in STM32F769I datasheet) UART_CONFIG_PINS(4, GPIOD, GPIOC, 2, 12, 8) - -// // initialization for UART4 -// UART_INIT(4) - -// // un-initialization for UART4 -// UART_UNINIT(4) +// NOT AVAILABLE /////////// // UART5 // /////////// -// pin configuration for UART5 -// port for TX pin is: GPIOD -// port for RX pin is: GPIOC -// TX pin: is GPIOD_2 -// RX pin: is GPIOC_12 -// GPIO alternate pin function is 8 (see "Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate -// function mapping" in STM32F769I datasheet) -// UART_CONFIG_PINS(5, GPIOD, GPIOC, 2, 12, 8) - -// // initialization for UART5 -// UART_INIT(5) - -// // un-initialization for UART5 -// UART_UNINIT(5) +// NOT AVAILABLE /////////// // UART6 // /////////// // pin configuration for UART6 -// port for TX pin is: GPIOC -// port for RX pin is: GPIOC -// TX pin: is GPIOC_6 -// RX pin: is GPIOC_7 -// GPIO alternate pin function is 8 (see "Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate -// function mapping" in STM32F769I datasheet) -// UART_CONFIG_PINS(6, GPIOC, GPIOC, 6, 7, 8) - -// // initialization for UART6 -// UART_INIT(6) - -// // un-initialization for UART6 -// UART_UNINIT(6) - -// /////////// -// // UART7 // -// /////////// - -// // pin configuration for UART7 -// // port for TX pin is: GPIOF -// // port for RX pin is: GPIOF -// // TX pin: is GPIOF_7 -// // RX pin: is GPIOF_6 -// // GPIO alternate pin function is 8 (see "Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate -// function mapping" in STM32F769I datasheet) UART_CONFIG_PINS(7, GPIOF, GPIOF, 7, 6, 8) +// port for TX pin is: GPIOG +// port for RX pin is: GPIOG +// TX pin: is GPIOC_14 +// RX pin: is GPIOC_9 +// GPIO alternate pin function is 8 (see alternate function mapping table in device datasheet) +UART_CONFIG_PINS(6, GPIOG, GPIOG, 14, 9, 8) -// // initialization for UART7 -// UART_INIT(7) +// initialization for UART6 +UART_INIT(6) -// // un-initialization for UART7 -// UART_UNINIT(7) +// un-initialization for UART6 +UART_UNINIT(6) -// /////////// -// // UART8 // -// /////////// +/////////// +// UART7 // +/////////// -// // pin configuration for UART8 -// // port for TX pin is: GPIOC -// // port for RX pin is: GPIOC -// // TX pin: is GPIOC_6 -// // RX pin: is GPIOC_7 -// // GPIO alternate pin function is 8 (see "Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate -// function mapping" in STM32F769I datasheet) UART_CONFIG_PINS(8, GPIOC, GPIOC, 6, 7, 8) +// NOT AVAILABLE -// // initialization for UART8 -// UART_INIT(8) +/////////// +// UART8 // +/////////// -// // un-initialization for UART8 -// UART_UNINIT(8) +// NOT AVAILABLE diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.h index 7e8e83d965..f4b76b9e43 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.h +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.h @@ -7,21 +7,21 @@ // // UART1 // // /////////// -// // enable UART1 -// #define NF_SERIAL_COMM_STM32_UART_USE_UART1 TRUE +// enable UART1 +#define NF_SERIAL_COMM_STM32_UART_USE_UART1 TRUE // /////////// // // UART2 // // /////////// -// // enable UART2 -// #define NF_SERIAL_COMM_STM32_UART_USE_UART2 TRUE +// enable UART2 +#define NF_SERIAL_COMM_STM32_UART_USE_UART2 TRUE // /////////// // // UART3 // // /////////// -// // enable UART5 +// // enable UART3 // #define NF_SERIAL_COMM_STM32_UART_USE_UART3 TRUE // /////////// @@ -36,14 +36,14 @@ /////////// // enable UART5 -// #define NF_SERIAL_COMM_STM32_UART_USE_UART5 TRUE +// #define NF_SERIAL_COMM_STM32_UART_USE_UART5 TRUE /////////// // UART6 // /////////// // enable USART6 -// #define NF_SERIAL_COMM_STM32_UART_USE_USART6 TRUE +#define NF_SERIAL_COMM_STM32_UART_USE_USART6 TRUE // /////////// // // UART7 // From 864e20594fcb9afd7b67b12415c7e5c1bb35ec1d Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 8 Sep 2023 15:54:55 +0100 Subject: [PATCH 12/44] Enable watchdog and uart ports --- targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json index fa75a812f9..6a58a78111 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json @@ -25,7 +25,6 @@ "NF_FEATURE_RTC": "ON", "NF_FEATURE_HAS_SDCARD": "OFF", "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", - "NF_FEATURE_WATCHDOG": "OFF", "SWO_OUTPUT": "OFF", "NF_BUILD_RTM": "OFF", "API_System.Math": "ON", @@ -34,7 +33,7 @@ "API_System.Device.Spi": "OFF", "API_System.Device.I2c": "OFF", "API_System.Device.Pwm": "OFF", - "API_System.IO.Ports": "OFF", + "API_System.IO.Ports": "ON", "API_System.Device.Adc": "OFF", "API_System.Device.Dac": "OFF", "API_System.Net": "OFF", From f3fc00147006cf87cf2b2a1b2626c1b6e953ab11 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 8 Sep 2023 16:18:49 +0100 Subject: [PATCH 13/44] Test nanobooter button --- .../ST_STM32F767ZI_NUCLEO/CMakePresets.json | 1 + .../ST_STM32F767ZI_NUCLEO/nanoBooter/main.c | 40 ++++++++++++------- 2 files changed, 26 insertions(+), 15 deletions(-) diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json index 6a58a78111..36d2363f85 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json @@ -25,6 +25,7 @@ "NF_FEATURE_RTC": "ON", "NF_FEATURE_HAS_SDCARD": "OFF", "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", + "NF_FEATURE_WATCHDOG": "OFF", "SWO_OUTPUT": "OFF", "NF_BUILD_RTM": "OFF", "API_System.Math": "ON", diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/main.c b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/main.c index e536b0e7b2..253bd19a4e 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/main.c +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/main.c @@ -78,26 +78,36 @@ int main(void) // start kernel, after this main() will behave like a thread with priority osPriorityNormal osKernelStart(); - // initialize block storage list and devices - // in CLR this is called in nanoHAL_Initialize() - // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command - BlockStorageList_Initialize(); - BlockStorage_AddDevices(); + // // initialize block storage list and devices + // // in CLR this is called in nanoHAL_Initialize() + // // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + // BlockStorageList_Initialize(); + // BlockStorage_AddDevices(); - // initialize configuration manager - // in CLR this is called in nanoHAL_Initialize() - // for nanoBooter we have to init it here to have access to network configuration blocks - ConfigurationManager_Initialize(); + // // initialize configuration manager + // // in CLR this is called in nanoHAL_Initialize() + // // for nanoBooter we have to init it here to have access to network configuration blocks + // ConfigurationManager_Initialize(); - // report successfull nanoBooter execution - ReportSuccessfullNanoBooter(); + // // report successfull nanoBooter execution + // ReportSuccessfullNanoBooter(); // Normal main() thread while (true) { - palSetLine(GPIOB_LED1); - osDelay(500); - palClearLine(GPIOB_LED1); - osDelay(500); + if (!palReadLine(LINE_BUTTON)) + { + palSetLine(GPIOB_LED1); + osDelay(500); + palClearLine(GPIOB_LED1); + osDelay(500); + } + else + { + palSetLine(GPIOB_LED2); + osDelay(500); + palClearLine(GPIOB_LED2); + osDelay(500); + } } } From 7096672cf1ff83d524a2cdc0757b0332f8a273df Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 8 Sep 2023 16:21:53 +0100 Subject: [PATCH 14/44] Turn ports back off. --- targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json index 36d2363f85..fa75a812f9 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json @@ -34,7 +34,7 @@ "API_System.Device.Spi": "OFF", "API_System.Device.I2c": "OFF", "API_System.Device.Pwm": "OFF", - "API_System.IO.Ports": "ON", + "API_System.IO.Ports": "OFF", "API_System.Device.Adc": "OFF", "API_System.Device.Dac": "OFF", "API_System.Net": "OFF", From f33b9dd7269bc52b938a34cd4ecbc9030d24128d Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 8 Sep 2023 16:48:20 +0100 Subject: [PATCH 15/44] Turn off no cache as test --- .../ST_STM32F767ZI_NUCLEO/CMakePresets.json | 4 +- .../ST_STM32F767ZI_NUCLEO/nanoBooter/main.c | 42 +++++++------------ .../ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h | 2 +- 3 files changed, 19 insertions(+), 29 deletions(-) diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json index fa75a812f9..d1ef46931f 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json @@ -34,12 +34,12 @@ "API_System.Device.Spi": "OFF", "API_System.Device.I2c": "OFF", "API_System.Device.Pwm": "OFF", - "API_System.IO.Ports": "OFF", + "API_System.IO.Ports": "ON", "API_System.Device.Adc": "OFF", "API_System.Device.Dac": "OFF", "API_System.Net": "OFF", "API_nanoFramework.Device.OneWire": "OFF", - "API_nanoFramework.Device.Can": "OFF", + "API_nanoFramework.Device.Can": "ON", "API_nanoFramework.ResourceManager": "ON", "API_nanoFramework.System.Collections": "ON", "API_nanoFramework.System.Text": "ON", diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/main.c b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/main.c index 253bd19a4e..504a0b1c22 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/main.c +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/main.c @@ -78,36 +78,26 @@ int main(void) // start kernel, after this main() will behave like a thread with priority osPriorityNormal osKernelStart(); - // // initialize block storage list and devices - // // in CLR this is called in nanoHAL_Initialize() - // // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command - // BlockStorageList_Initialize(); - // BlockStorage_AddDevices(); + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); - // // initialize configuration manager - // // in CLR this is called in nanoHAL_Initialize() - // // for nanoBooter we have to init it here to have access to network configuration blocks - // ConfigurationManager_Initialize(); + // initialize configuration manager + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it here to have access to network configuration blocks + ConfigurationManager_Initialize(); - // // report successfull nanoBooter execution - // ReportSuccessfullNanoBooter(); + // report successfull nanoBooter execution + ReportSuccessfullNanoBooter(); // Normal main() thread while (true) { - if (!palReadLine(LINE_BUTTON)) - { - palSetLine(GPIOB_LED1); - osDelay(500); - palClearLine(GPIOB_LED1); - osDelay(500); - } - else - { - palSetLine(GPIOB_LED2); - osDelay(500); - palClearLine(GPIOB_LED2); - osDelay(500); - } + + palSetLine(GPIOB_LED1); + osDelay(500); + palClearLine(GPIOB_LED1); + osDelay(500); } -} diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h index 428e4ff2ca..1fb6488610 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h @@ -34,7 +34,7 @@ /* * Memory attributes settings. */ -#define STM32_NOCACHE_ENABLE TRUE +#define STM32_NOCACHE_ENABLE FALSE #define STM32_NOCACHE_MPU_REGION MPU_REGION_6 #define STM32_NOCACHE_RBAR 0x2004C000U #define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K From ef9203dadd57f44729a0b5fe8e0167a272d9bf4d Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 8 Sep 2023 16:51:22 +0100 Subject: [PATCH 16/44] Fix issue with last commit --- targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/main.c b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/main.c index 504a0b1c22..e536b0e7b2 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/main.c +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/main.c @@ -95,9 +95,9 @@ int main(void) // Normal main() thread while (true) { - palSetLine(GPIOB_LED1); osDelay(500); palClearLine(GPIOB_LED1); osDelay(500); } +} From b157f0fda43ccab029aeeb9cbd947d39b59e898a Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 8 Sep 2023 17:22:49 +0100 Subject: [PATCH 17/44] Fix port mappings --- .../target_nf_device_can_config.cpp | 8 ++++---- .../target_system_io_ports_config.cpp | 16 ++++++++-------- .../target_system_io_ports_config.h | 8 ++++---- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.cpp b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.cpp index d393b8737e..32280e6d5d 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.cpp +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.cpp @@ -13,11 +13,11 @@ // pin configuration for CAN1 // port for TX pin is: GPIOD -// TX pin: is GPIOB_01 +// TX pin: is GPIOD_01 // port for RX pin is: GPIOD -// RX pin: is GPIOB_00 -// GPIO alternate pin function is 8 (see alternate function mapping table in device datasheet) -CAN_CONFIG_PINS(1, GPIOD, GPIOD, 1, 0, 8) +// RX pin: is GPIOD_00 +// GPIO alternate pin function is 9 (see alternate function mapping table in device datasheet) +CAN_CONFIG_PINS(1, GPIOD, GPIOD, 1, 0, 9) // buffer CANRxFrame Can1_MsgBuffer[CAN1_RX_BUFFER_SIZE]; diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.cpp b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.cpp index 9dddbdd256..ccb0e82067 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.cpp +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.cpp @@ -15,14 +15,14 @@ // port for RX pin is: GPIOC // TX pin: is GPIOC_4 // RX pin: is GPIOC_5 -// GPIO alternate pin function is 8 (see alternate function mapping table in device datasheet) -UART_CONFIG_PINS(1, GPIOC, GPIOC, 4, 5, 8) +// GPIO alternate pin function is 7 (see alternate function mapping table in device datasheet) +// UART_CONFIG_PINS(1, GPIOC, GPIOC, 4, 5, 4) -// initialization for UART1 -UART_INIT(1) +// // initialization for UART1 +// UART_INIT(1) -// un-initialization for UART1 -UART_UNINIT(1) +// // un-initialization for UART1 +// UART_UNINIT(1) /////////// // UART2 // @@ -33,8 +33,8 @@ UART_UNINIT(1) // port for RX pin is: GPIOD // TX pin: is GPIOD_5 // RX pin: is GPIOC_6 -// GPIO alternate pin function is 8 (see alternate function mapping table in device datasheet) -UART_CONFIG_PINS(2, GPIOD, GPIOD, 5, 6, 8) +// GPIO alternate pin function is 7 (see alternate function mapping table in device datasheet) +UART_CONFIG_PINS(2, GPIOD, GPIOD, 5, 6, 7) // initialization for UART2 UART_INIT(2) diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.h index f4b76b9e43..17f75e1958 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.h +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.h @@ -8,11 +8,11 @@ // /////////// // enable UART1 -#define NF_SERIAL_COMM_STM32_UART_USE_UART1 TRUE +// #define NF_SERIAL_COMM_STM32_UART_USE_UART1 TRUE -// /////////// -// // UART2 // -// /////////// +/////////// +// UART2 // +/////////// // enable UART2 #define NF_SERIAL_COMM_STM32_UART_USE_UART2 TRUE From a30e3d53d64ead8fd7b4b2fadf2e7d0b767ec723 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 8 Sep 2023 17:29:02 +0100 Subject: [PATCH 18/44] Turn off ports and can. Turn on net --- targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json | 6 +++--- targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json index d1ef46931f..35ef675bf7 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json @@ -34,12 +34,12 @@ "API_System.Device.Spi": "OFF", "API_System.Device.I2c": "OFF", "API_System.Device.Pwm": "OFF", - "API_System.IO.Ports": "ON", + "API_System.IO.Ports": "OFF", "API_System.Device.Adc": "OFF", "API_System.Device.Dac": "OFF", - "API_System.Net": "OFF", + "API_System.Net": "ON", "API_nanoFramework.Device.OneWire": "OFF", - "API_nanoFramework.Device.Can": "ON", + "API_nanoFramework.Device.Can": "OFF", "API_nanoFramework.ResourceManager": "ON", "API_nanoFramework.System.Collections": "ON", "API_nanoFramework.System.Text": "ON", diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h index 1fb6488610..428e4ff2ca 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h @@ -34,7 +34,7 @@ /* * Memory attributes settings. */ -#define STM32_NOCACHE_ENABLE FALSE +#define STM32_NOCACHE_ENABLE TRUE #define STM32_NOCACHE_MPU_REGION MPU_REGION_6 #define STM32_NOCACHE_RBAR 0x2004C000U #define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K From 091a53086e58abc28923ce4546667a67cd6fb7fc Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Sun, 10 Sep 2023 16:42:31 +0100 Subject: [PATCH 19/44] Work on sensor channels --- .../ST_STM32F767ZI_NUCLEO/target_common.h.in | 2 +- .../target_system_device_adc_config.cpp | 30 +++++++++++-------- .../target_system_device_i2c_config.cpp | 12 ++++---- .../target_system_device_spi_config.cpp | 27 +++++++++-------- 4 files changed, 38 insertions(+), 33 deletions(-) diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_common.h.in b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_common.h.in index bbc95e8294..dd32c876cc 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_common.h.in +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_common.h.in @@ -41,7 +41,7 @@ ///////////////////////////////////// ///////////////////////////////////// -//#define EVENTS_HEART_BEAT palToggleLine(LINE_LED2_GREEN) +//#define EVENTS_HEART_BEAT palToggleLine(LINE_LED2) ///////////////////////////////////// #endif // TARGET_COMMON_H diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_adc_config.cpp b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_adc_config.cpp index 4064c0ffc7..7291c3e031 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_adc_config.cpp +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_adc_config.cpp @@ -8,29 +8,33 @@ const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { // ADC1 - {1, GPIOA, 2, ADC_CHANNEL_IN2}, {1, GPIOA, 3, ADC_CHANNEL_IN3}, {1, GPIOB, 1, ADC_CHANNEL_IN9}, - {1, GPIOA, 0, ADC_CHANNEL_IN10}, - {1, GPIOC, 1, ADC_CHANNEL_IN11}, + {1, GPIOC, 0, ADC_CHANNEL_IN10}, {1, GPIOC, 2, ADC_CHANNEL_IN12}, {1, GPIOC, 3, ADC_CHANNEL_IN13}, - {1, GPIOC, 4, ADC_CHANNEL_IN14}, - {1, GPIOC, 5, ADC_CHANNEL_IN15}, + // ADC 2 + {2, GPIOA, 3, ADC_CHANNEL_IN3}, + {2, GPIOB, 1, ADC_CHANNEL_IN9}, + {2, GPIOC, 0, ADC_CHANNEL_IN10}, + {2, GPIOC, 2, ADC_CHANNEL_IN12}, + {2, GPIOC, 3, ADC_CHANNEL_IN13}, // ADC3 - {3, GPIOB, 1, ADC_CHANNEL_IN1}, + {3, GPIOA, 3, ADC_CHANNEL_IN3}, + {3, GPIOF, 10, ADC_CHANNEL_IN8}, {3, GPIOF, 3, ADC_CHANNEL_IN9}, + {3, GPIOC, 0, ADC_CHANNEL_IN10}, + {3, GPIOC, 2, ADC_CHANNEL_IN12}, + {3, GPIOC, 3, ADC_CHANNEL_IN13}, {3, GPIOF, 4, ADC_CHANNEL_IN14}, - - // ADC12 - {12, GPIOC, 2, ADC_CHANNEL_IN8}, - + {3, GPIOF, 5, ADC_CHANNEL_IN15}, + // these are the internal sources, available only at ADC1 - // {1, NULL, 0, ADC_CHANNEL_SENSOR}, - // {1, NULL, 0, ADC_CHANNEL_VREFINT}, - // {1, NULL, 0, ADC_CHANNEL_VBAT}, + {1, NULL, 0, ADC_CHANNEL_SENSOR}, + {1, NULL, 0, ADC_CHANNEL_VREFINT}, + {1, NULL, 0, ADC_CHANNEL_VBAT}, }; const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_i2c_config.cpp b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_i2c_config.cpp index 7f7ab0e963..635d8dc4c8 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_i2c_config.cpp +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_i2c_config.cpp @@ -22,13 +22,13 @@ I2C_CONFIG_PINS(1, GPIOB, GPIOB, 8, 9, 4) // I2C2 // ////////// -// pin configuration for I2C1 -// port for SCL pin is: GPIOB -// port for SDA pin is: GPIOB -// SCL pin: is GPIOB_8 -// SDA pin: is GPIOB_9 +// pin configuration for I2C2 +// port for SCL pin is: GPIOF +// port for SDA pin is: GPIOF +// SCL pin: is GPIOF_1 +// SDA pin: is GPIOB_0 // GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet) -// I2C_CONFIG_PINS(1, GPIOB, GPIOB, 8, 9, 4) +I2C_CONFIG_PINS(1, GPIOB, GPIOB, 1, 0, 4) ////////// diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_spi_config.cpp b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_spi_config.cpp index 951a89bfcc..75ea5ba56a 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_spi_config.cpp +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_spi_config.cpp @@ -6,26 +6,27 @@ #include ////////// -// SPI2 // +// SPI1 // ////////// -// pin configuration for SPI2 -// port for SCK pin is: PA12 (D13) -// port for MISO pin is: PB14 (D12) -// port for MOSI pin is: PB15 (D11) +// pin configuration for SPI1 +// port for SCK pin is: PA5 (D13) +// port for MISO pin is: PA6 (D12) +// port for MOSI pin is: PA7 (D11) // AF 5 // GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) -// SPI_CONFIG_PINS(2, GPIOA, 12, GPIOB, 14, GPIOB, 15, 5) +SPI_CONFIG_PINS(1, GPIOA, 5, GPIOA, 6, GPIOA, 7, 5) ////////// -// SPI5 // +// SPI3 // ////////// -// pin configuration for SPI5 -// port for SCK pin is: PF7 (D6) -// port for MISO pin is: PF8 (A4) -// port for MOSI pin is: PF9 (A5) +// pin configuration for SPI3 +// port for SCK pin is: PB3 (D23) +// port for MISO pin is: PB4 (D25) +// port for MOSI pin is: PB5 (D22) +// AF 5 -// GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) -// SPI_CONFIG_PINS(5, GPIOF, 7, GPIOF, 8, GPIOF, 9, 5) +// GPIO alternate pin function is 6 (see alternate function mapping table in device datasheet) +SPI_CONFIG_PINS(3, GPIOB, 3, GPIOB, 4, GPIOB, 5, 6) From b39de3c2abbe4ba1812303cd565f76690c58fcd9 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Sun, 10 Sep 2023 16:48:57 +0100 Subject: [PATCH 20/44] Enable SPI and I2C --- targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json index 35ef675bf7..0796b65c3b 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json +++ b/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json @@ -31,8 +31,8 @@ "API_System.Math": "ON", "API_Hardware.Stm32": "ON", "API_System.Device.Gpio": "ON", - "API_System.Device.Spi": "OFF", - "API_System.Device.I2c": "OFF", + "API_System.Device.Spi": "ON", + "API_System.Device.I2c": "ON", "API_System.Device.Pwm": "OFF", "API_System.IO.Ports": "OFF", "API_System.Device.Adc": "OFF", From 4a5469d9ca84efc5dd65df05f5b97f66b3521487 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Sun, 10 Sep 2023 17:10:16 +0100 Subject: [PATCH 21/44] Rename board for alignment. --- .github/workflows/build-chibios-target.yml | 4 ++-- targets/ChibiOS/CMakePresets.json | 2 +- .../CMakeLists.txt | 0 .../CMakePresets.json | 8 ++++---- .../README.md | 2 +- .../board.c | 0 .../board.h | 0 .../common/CMakeLists.txt | 0 .../common/Device_BlockStorage-DEBUG.c | 0 .../common/Device_BlockStorage.c | 0 .../common/serialcfg.h | 0 .../common/targetHAL_ConfigurationManager.cpp | 0 .../launch.json | 4 ++-- .../managed_helpers/README.md | 0 .../managed_helpers/STM32F767ZI_NUCLEO.Adc.cs | 0 .../managed_helpers/package.nuspec | 6 +++--- .../mbedtls_config.h | 0 .../nanoBooter/CMakeLists.txt | 0 .../nanoBooter/STM32F76xx_booter-DEBUG.ld | 0 .../nanoBooter/STM32F76xx_booter.ld | 0 .../nanoBooter/chconf.h | 0 .../nanoBooter/halconf.h | 0 .../nanoBooter/halconf_nf.h | 0 .../nanoBooter/main.c | 0 .../nanoBooter/mcuconf.h | 0 .../nanoBooter/mcuconf_nf.h | 0 .../nanoBooter/target_board.h.in | 0 .../nanoCLR/CMakeLists.txt | 0 .../nanoCLR/STM32F76xx_CLR-DEBUG.ld | 0 .../nanoCLR/STM32F76xx_CLR.ld | 0 .../nanoCLR/chconf.h | 0 .../nanoCLR/halconf.h | 0 .../nanoCLR/halconf_nf.h | 0 .../nanoCLR/main.c | 0 .../nanoCLR/mcuconf.h | 0 .../nanoCLR/mcuconf_nf.h | 0 .../nanoCLR/nanoHAL.cpp | 0 .../nanoCLR/target_board.h.in | 0 .../stm32f7xx_hal_conf.h | 0 .../target_BlockStorage.c | 0 .../target_BlockStorage.h | 0 .../target_common.c | 0 .../target_common.h.in | 0 .../target_external_memory.c | 0 .../target_lwip_sntp_opts.h | 0 .../target_lwipopts.h | 0 .../target_nf_dev_onewire_config.cpp | 0 .../target_nf_dev_onewire_config.h | 0 .../target_nf_device_can_config.cpp | 0 .../target_nf_device_can_config.h | 0 .../target_system_device_adc_config.cpp | 0 .../target_system_device_dac_config.cpp | 0 .../target_system_device_i2c_config.cpp | 0 .../target_system_device_pwm_config.cpp | 0 .../target_system_device_spi_config.cpp | 0 .../target_system_io_ports_config.cpp | 0 .../target_system_io_ports_config.h | 0 57 files changed, 13 insertions(+), 13 deletions(-) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/CMakeLists.txt (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/CMakePresets.json (90%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/README.md (89%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/board.c (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/board.h (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/common/CMakeLists.txt (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/common/Device_BlockStorage-DEBUG.c (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/common/Device_BlockStorage.c (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/common/serialcfg.h (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/common/targetHAL_ConfigurationManager.cpp (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/launch.json (97%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/managed_helpers/README.md (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/managed_helpers/STM32F767ZI_NUCLEO.Adc.cs (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/managed_helpers/package.nuspec (80%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/mbedtls_config.h (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/nanoBooter/CMakeLists.txt (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/nanoBooter/STM32F76xx_booter-DEBUG.ld (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/nanoBooter/STM32F76xx_booter.ld (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/nanoBooter/chconf.h (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/nanoBooter/halconf.h (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/nanoBooter/halconf_nf.h (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/nanoBooter/main.c (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/nanoBooter/mcuconf.h (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/nanoBooter/mcuconf_nf.h (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/nanoBooter/target_board.h.in (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/nanoCLR/CMakeLists.txt (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/nanoCLR/STM32F76xx_CLR-DEBUG.ld (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/nanoCLR/STM32F76xx_CLR.ld (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/nanoCLR/chconf.h (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/nanoCLR/halconf.h (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/nanoCLR/halconf_nf.h (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/nanoCLR/main.c (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/nanoCLR/mcuconf.h (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/nanoCLR/mcuconf_nf.h (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/nanoCLR/nanoHAL.cpp (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/nanoCLR/target_board.h.in (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/stm32f7xx_hal_conf.h (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/target_BlockStorage.c (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/target_BlockStorage.h (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/target_common.c (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/target_common.h.in (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/target_external_memory.c (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/target_lwip_sntp_opts.h (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/target_lwipopts.h (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/target_nf_dev_onewire_config.cpp (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/target_nf_dev_onewire_config.h (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/target_nf_device_can_config.cpp (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/target_nf_device_can_config.h (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/target_system_device_adc_config.cpp (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/target_system_device_dac_config.cpp (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/target_system_device_i2c_config.cpp (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/target_system_device_pwm_config.cpp (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/target_system_device_spi_config.cpp (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/target_system_io_ports_config.cpp (100%) rename targets/ChibiOS/{ST_STM32F767ZI_NUCLEO => ST_NUCLEO144_F767ZI}/target_system_io_ports_config.h (100%) diff --git a/.github/workflows/build-chibios-target.yml b/.github/workflows/build-chibios-target.yml index ea4353b595..415709bfdb 100644 --- a/.github/workflows/build-chibios-target.yml +++ b/.github/workflows/build-chibios-target.yml @@ -16,8 +16,8 @@ jobs: matrix: # Add the target and build type you wish to generate firmware for: include: [ - # { target: ST_STM32F767ZI_NUCLEO, build-type: MinSizeRel }, - { target: ST_STM32F767ZI_NUCLEO, build-type: Debug }, + # { target: ST_NUCLEO144_F767ZI, build-type: MinSizeRel }, + { target: ST_NUCLEO144_F767ZI, build-type: Debug }, # { target: ST_STM32F769I_DISCOVERY, build-type: MinSizeRel }, # { target: ST_STM32F769I_DISCOVERY, build-type: Debug }, diff --git a/targets/ChibiOS/CMakePresets.json b/targets/ChibiOS/CMakePresets.json index e39a4fcc1f..a81d70b47e 100644 --- a/targets/ChibiOS/CMakePresets.json +++ b/targets/ChibiOS/CMakePresets.json @@ -5,6 +5,6 @@ "ST_NUCLEO64_F091RC/CMakePresets.json", "ST_STM32F429I_DISCOVERY/CMakePresets.json", "ST_STM32F769I_DISCOVERY/CMakePresets.json", - "ST_STM32F767ZI_NUCLEO/CMakePresets.json" + "ST_NUCLEO144_F767ZI/CMakePresets.json" ] } diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakeLists.txt b/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakeLists.txt similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakeLists.txt rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakeLists.txt diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json b/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json similarity index 90% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json index 0796b65c3b..59429b6b00 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/CMakePresets.json +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json @@ -7,7 +7,7 @@ ], "configurePresets": [ { - "name": "ST_STM32F767ZI_NUCLEO", + "name": "ST_NUCLEO144_F767ZI", "inherits": [ "arm-gcc-cortex-preset", "user-tools-repos", @@ -51,9 +51,9 @@ "buildPresets": [ { "inherits": "base-user", - "name": "ST_STM32F767ZI_NUCLEO", - "displayName": "ST_STM32F767ZI_NUCLEO", - "configurePreset": "ST_STM32F767ZI_NUCLEO" + "name": "ST_NUCLEO144_F767ZI", + "displayName": "ST_NUCLEO144_F767ZI", + "configurePreset": "ST_NUCLEO144_F767ZI" } ] } diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/README.md b/targets/ChibiOS/ST_NUCLEO144_F767ZI/README.md similarity index 89% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/README.md rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/README.md index ed6e64b13b..3ddc3ec045 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/README.md +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/README.md @@ -11,7 +11,7 @@ In _halconf.g_ (in both nanoBooter and nanoCLR folders), when compared with a de In _mcuconf.h_ (in both nanoBooter and nanoCLR folders), when compared with a default file available from (https://github.com/ChibiOS/ChibiOS/tree/master/demos/STM32/RT-STM32F769I-DISCOVERY): - STM32_SERIAL_USE_USART1 to TRUE -NOTE: this configuration was successfully tested in an ST_STM32F767ZI_NUCLEO board using the Serial port through the onboard ST Link USB connection. +NOTE: this configuration was successfully tested in an ST_NUCLEO144_F767ZI board using the Serial port through the onboard ST Link USB connection. ## ADC configurations diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.c b/targets/ChibiOS/ST_NUCLEO144_F767ZI/board.c similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.c rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/board.c diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/board.h similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/board.h rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/board.h diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/CMakeLists.txt b/targets/ChibiOS/ST_NUCLEO144_F767ZI/common/CMakeLists.txt similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/CMakeLists.txt rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/common/CMakeLists.txt diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/Device_BlockStorage-DEBUG.c b/targets/ChibiOS/ST_NUCLEO144_F767ZI/common/Device_BlockStorage-DEBUG.c similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/Device_BlockStorage-DEBUG.c rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/common/Device_BlockStorage-DEBUG.c diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/Device_BlockStorage.c b/targets/ChibiOS/ST_NUCLEO144_F767ZI/common/Device_BlockStorage.c similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/Device_BlockStorage.c rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/common/Device_BlockStorage.c diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/serialcfg.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/common/serialcfg.h similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/serialcfg.h rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/common/serialcfg.h diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/targetHAL_ConfigurationManager.cpp b/targets/ChibiOS/ST_NUCLEO144_F767ZI/common/targetHAL_ConfigurationManager.cpp similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/common/targetHAL_ConfigurationManager.cpp rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/common/targetHAL_ConfigurationManager.cpp diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/launch.json b/targets/ChibiOS/ST_NUCLEO144_F767ZI/launch.json similarity index 97% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/launch.json rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/launch.json index 5061983178..ef75fa3ed9 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/launch.json +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/launch.json @@ -2,7 +2,7 @@ "version": "0.2.0", "configurations": [ { - "name": "ST_STM32F767ZI_NUCLEO nanoBooter", + "name": "ST_NUCLEO144_F767ZI nanoBooter", "type": "cppdbg", "request": "launch", "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", @@ -53,7 +53,7 @@ } }, { - "name": "ST_STM32F767ZI_NUCLEO nanoCLR", + "name": "ST_NUCLEO144_F767ZI nanoCLR", "type": "cppdbg", "request": "launch", "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/README.md b/targets/ChibiOS/ST_NUCLEO144_F767ZI/managed_helpers/README.md similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/README.md rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/managed_helpers/README.md diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/STM32F767ZI_NUCLEO.Adc.cs b/targets/ChibiOS/ST_NUCLEO144_F767ZI/managed_helpers/STM32F767ZI_NUCLEO.Adc.cs similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/STM32F767ZI_NUCLEO.Adc.cs rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/managed_helpers/STM32F767ZI_NUCLEO.Adc.cs diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/package.nuspec b/targets/ChibiOS/ST_NUCLEO144_F767ZI/managed_helpers/package.nuspec similarity index 80% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/package.nuspec rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/managed_helpers/package.nuspec index 2aee85bd8d..81af53f3d6 100644 --- a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/managed_helpers/package.nuspec +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/managed_helpers/package.nuspec @@ -1,13 +1,13 @@ - nanoFramework.Targets.ST_STM32F767ZI_NUCLEO - nanoFramework.Targets.ST_STM32F767ZI_NUCLEO + nanoFramework.Targets.ST_NUCLEO144_F767ZI + nanoFramework.Targets.ST_NUCLEO144_F767ZI 1.0.0 nanoframework false - Helper classes to use ST_STM32F767ZI_NUCLEO target in C# applications. + Helper classes to use ST_NUCLEO144_F767ZI target in C# applications. diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/mbedtls_config.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/mbedtls_config.h similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/mbedtls_config.h rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/mbedtls_config.h diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/CMakeLists.txt b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/CMakeLists.txt similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/CMakeLists.txt rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/CMakeLists.txt diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/STM32F76xx_booter-DEBUG.ld b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/STM32F76xx_booter-DEBUG.ld similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/STM32F76xx_booter-DEBUG.ld rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/STM32F76xx_booter-DEBUG.ld diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/STM32F76xx_booter.ld b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/STM32F76xx_booter.ld similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/STM32F76xx_booter.ld rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/STM32F76xx_booter.ld diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/chconf.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/chconf.h similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/chconf.h rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/chconf.h diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/halconf.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/halconf.h similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/halconf.h rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/halconf.h diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/halconf_nf.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/halconf_nf.h similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/halconf_nf.h rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/halconf_nf.h diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/main.c b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/main.c similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/main.c rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/main.c diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/mcuconf.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/mcuconf.h similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/mcuconf.h rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/mcuconf.h diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/mcuconf_nf.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/mcuconf_nf.h similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/mcuconf_nf.h rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/mcuconf_nf.h diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/target_board.h.in b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/target_board.h.in similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoBooter/target_board.h.in rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/target_board.h.in diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/CMakeLists.txt b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/CMakeLists.txt similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/CMakeLists.txt rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/CMakeLists.txt diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/STM32F76xx_CLR-DEBUG.ld b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR-DEBUG.ld similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/STM32F76xx_CLR-DEBUG.ld rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR-DEBUG.ld diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/STM32F76xx_CLR.ld b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR.ld similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/STM32F76xx_CLR.ld rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR.ld diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/chconf.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/chconf.h similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/chconf.h rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/chconf.h diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/halconf.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/halconf.h similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/halconf.h rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/halconf.h diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/halconf_nf.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/halconf_nf.h similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/halconf_nf.h rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/halconf_nf.h diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/main.c b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/main.c similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/main.c rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/main.c diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf.h rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf_nf.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf_nf.h similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/mcuconf_nf.h rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf_nf.h diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/nanoHAL.cpp b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/nanoHAL.cpp similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/nanoHAL.cpp rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/nanoHAL.cpp diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/target_board.h.in b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/target_board.h.in similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/nanoCLR/target_board.h.in rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/target_board.h.in diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/stm32f7xx_hal_conf.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/stm32f7xx_hal_conf.h similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/stm32f7xx_hal_conf.h rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/stm32f7xx_hal_conf.h diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_BlockStorage.c b/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_BlockStorage.c similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_BlockStorage.c rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/target_BlockStorage.c diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_BlockStorage.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_BlockStorage.h similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_BlockStorage.h rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/target_BlockStorage.h diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_common.c b/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_common.c similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_common.c rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/target_common.c diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_common.h.in b/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_common.h.in similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_common.h.in rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/target_common.h.in diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_external_memory.c b/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_external_memory.c similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_external_memory.c rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/target_external_memory.c diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_lwip_sntp_opts.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_lwip_sntp_opts.h similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_lwip_sntp_opts.h rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/target_lwip_sntp_opts.h diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_lwipopts.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_lwipopts.h similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_lwipopts.h rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/target_lwipopts.h diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_dev_onewire_config.cpp b/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_nf_dev_onewire_config.cpp similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_dev_onewire_config.cpp rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/target_nf_dev_onewire_config.cpp diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_dev_onewire_config.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_nf_dev_onewire_config.h similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_dev_onewire_config.h rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/target_nf_dev_onewire_config.h diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.cpp b/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_nf_device_can_config.cpp similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.cpp rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/target_nf_device_can_config.cpp diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_nf_device_can_config.h similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_nf_device_can_config.h rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/target_nf_device_can_config.h diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_adc_config.cpp b/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_adc_config.cpp similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_adc_config.cpp rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_adc_config.cpp diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_dac_config.cpp b/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_dac_config.cpp similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_dac_config.cpp rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_dac_config.cpp diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_i2c_config.cpp b/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_i2c_config.cpp similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_i2c_config.cpp rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_i2c_config.cpp diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_pwm_config.cpp b/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_pwm_config.cpp similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_pwm_config.cpp rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_pwm_config.cpp diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_spi_config.cpp b/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_spi_config.cpp similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_device_spi_config.cpp rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_spi_config.cpp diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.cpp b/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_io_ports_config.cpp similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.cpp rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_io_ports_config.cpp diff --git a/targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_io_ports_config.h similarity index 100% rename from targets/ChibiOS/ST_STM32F767ZI_NUCLEO/target_system_io_ports_config.h rename to targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_io_ports_config.h From 82225bb8a04b1733226067376996d7ebafa35afc Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Sun, 10 Sep 2023 18:11:09 +0100 Subject: [PATCH 22/44] Try building verbose. Add to azure pipelines. --- .github/workflows/build-chibios-target.yml | 4 ++-- azure-pipelines-nightly.yml | 8 ++++++++ .../target_system_device_spi_config.cpp | 2 +- 3 files changed, 11 insertions(+), 3 deletions(-) diff --git a/.github/workflows/build-chibios-target.yml b/.github/workflows/build-chibios-target.yml index 415709bfdb..4c1e99b19a 100644 --- a/.github/workflows/build-chibios-target.yml +++ b/.github/workflows/build-chibios-target.yml @@ -17,7 +17,7 @@ jobs: matrix: # Add the target and build type you wish to generate firmware for: include: [ # { target: ST_NUCLEO144_F767ZI, build-type: MinSizeRel }, - { target: ST_NUCLEO144_F767ZI, build-type: Debug }, + { target: ST_NUCLEO144_F767ZI, build-type: Debug, extra-build-options: '-DBUILD_VERBOSE' }, # { target: ST_STM32F769I_DISCOVERY, build-type: MinSizeRel }, # { target: ST_STM32F769I_DISCOVERY, build-type: Debug }, @@ -132,7 +132,7 @@ jobs: push: never runCmd: | # Build target: - cmake --preset=${{ matrix.target }} -DCMAKE_BUILD_TYPE=${{ matrix.build-type }} + cmake --preset=${{ matrix.target }} -DCMAKE_BUILD_TYPE=${{ matrix.build-type }} ${{ matrix.extra-build-options }} cmake --build build - name: Upload Artifact diff --git a/azure-pipelines-nightly.yml b/azure-pipelines-nightly.yml index 6e63f0cbe2..1e8618d688 100644 --- a/azure-pipelines-nightly.yml +++ b/azure-pipelines-nightly.yml @@ -276,6 +276,14 @@ jobs: NeedsSRECORD: true CMakePreset: ST_NUCLEO64_F091RC + ST_NUCLEO144_F767ZI: + TargetBoard: ST_NUCLEO144_F767ZI + TargetSeries: 'stm32f7xx' + BuildOptions: + NeedsDFU: false + NeedsSRECORD: true + CMakePreset: ST_NUCLEO144_F767ZI + variables: DOTNET_NOLOGO: true # creates a counter and assigns it to the revision variable diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_spi_config.cpp b/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_spi_config.cpp index 75ea5ba56a..7a61d4fb55 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_spi_config.cpp +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_spi_config.cpp @@ -26,7 +26,7 @@ SPI_CONFIG_PINS(1, GPIOA, 5, GPIOA, 6, GPIOA, 7, 5) // port for SCK pin is: PB3 (D23) // port for MISO pin is: PB4 (D25) // port for MOSI pin is: PB5 (D22) -// AF 5 +// AF 6 // GPIO alternate pin function is 6 (see alternate function mapping table in device datasheet) SPI_CONFIG_PINS(3, GPIOB, 3, GPIOB, 4, GPIOB, 5, 6) From 9606fa9fdad96de5548876f636839fd30f4f73cd Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Sun, 10 Sep 2023 18:13:02 +0100 Subject: [PATCH 23/44] Try again. --- .github/workflows/build-chibios-target.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/build-chibios-target.yml b/.github/workflows/build-chibios-target.yml index 4c1e99b19a..ac817cb548 100644 --- a/.github/workflows/build-chibios-target.yml +++ b/.github/workflows/build-chibios-target.yml @@ -132,8 +132,8 @@ jobs: push: never runCmd: | # Build target: - cmake --preset=${{ matrix.target }} -DCMAKE_BUILD_TYPE=${{ matrix.build-type }} ${{ matrix.extra-build-options }} - cmake --build build + cmake --preset=${{ matrix.target }} -DCMAKE_BUILD_TYPE=${{ matrix.build-type }} + cmake --build build ${{ matrix.extra-build-options }} - name: Upload Artifact uses: actions/upload-artifact@v3 From dc9064d3ee213545b8e92c211e63e905a9d33e2e Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Sun, 10 Sep 2023 18:16:39 +0100 Subject: [PATCH 24/44] And again. --- .github/workflows/build-chibios-target.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/build-chibios-target.yml b/.github/workflows/build-chibios-target.yml index ac817cb548..c0ecd5b9d2 100644 --- a/.github/workflows/build-chibios-target.yml +++ b/.github/workflows/build-chibios-target.yml @@ -17,7 +17,7 @@ jobs: matrix: # Add the target and build type you wish to generate firmware for: include: [ # { target: ST_NUCLEO144_F767ZI, build-type: MinSizeRel }, - { target: ST_NUCLEO144_F767ZI, build-type: Debug, extra-build-options: '-DBUILD_VERBOSE' }, + { target: ST_NUCLEO144_F767ZI, build-type: Debug }, # extra-build-options: '-DBUILD_VERBOSE' # { target: ST_STM32F769I_DISCOVERY, build-type: MinSizeRel }, # { target: ST_STM32F769I_DISCOVERY, build-type: Debug }, @@ -132,8 +132,8 @@ jobs: push: never runCmd: | # Build target: - cmake --preset=${{ matrix.target }} -DCMAKE_BUILD_TYPE=${{ matrix.build-type }} - cmake --build build ${{ matrix.extra-build-options }} + cmake --preset=${{ matrix.target }} -DCMAKE_BUILD_TYPE=${{ matrix.build-type }} # ${{ matrix.extra-build-options }} + cmake --build build --verbose - name: Upload Artifact uses: actions/upload-artifact@v3 From 8749af9d03cd310c875aa8eaf095647e9290e873 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Sun, 10 Sep 2023 18:47:47 +0100 Subject: [PATCH 25/44] Turn off SPI and I2C Correct booter LED --- .github/workflows/build-chibios-target.yml | 6 +++--- .../ST_NUCLEO144_F767ZI/CMakePresets.json | 4 ++-- targets/ChibiOS/ST_NUCLEO144_F767ZI/README.md | 19 +------------------ .../ST_NUCLEO144_F767ZI/nanoBooter/main.c | 4 ++-- 4 files changed, 8 insertions(+), 25 deletions(-) diff --git a/.github/workflows/build-chibios-target.yml b/.github/workflows/build-chibios-target.yml index c0ecd5b9d2..415709bfdb 100644 --- a/.github/workflows/build-chibios-target.yml +++ b/.github/workflows/build-chibios-target.yml @@ -17,7 +17,7 @@ jobs: matrix: # Add the target and build type you wish to generate firmware for: include: [ # { target: ST_NUCLEO144_F767ZI, build-type: MinSizeRel }, - { target: ST_NUCLEO144_F767ZI, build-type: Debug }, # extra-build-options: '-DBUILD_VERBOSE' + { target: ST_NUCLEO144_F767ZI, build-type: Debug }, # { target: ST_STM32F769I_DISCOVERY, build-type: MinSizeRel }, # { target: ST_STM32F769I_DISCOVERY, build-type: Debug }, @@ -132,8 +132,8 @@ jobs: push: never runCmd: | # Build target: - cmake --preset=${{ matrix.target }} -DCMAKE_BUILD_TYPE=${{ matrix.build-type }} # ${{ matrix.extra-build-options }} - cmake --build build --verbose + cmake --preset=${{ matrix.target }} -DCMAKE_BUILD_TYPE=${{ matrix.build-type }} + cmake --build build - name: Upload Artifact uses: actions/upload-artifact@v3 diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json b/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json index 59429b6b00..29fa5d098a 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json @@ -31,8 +31,8 @@ "API_System.Math": "ON", "API_Hardware.Stm32": "ON", "API_System.Device.Gpio": "ON", - "API_System.Device.Spi": "ON", - "API_System.Device.I2c": "ON", + "API_System.Device.Spi": "OFF", + "API_System.Device.I2c": "OFF", "API_System.Device.Pwm": "OFF", "API_System.IO.Ports": "OFF", "API_System.Device.Adc": "OFF", diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/README.md b/targets/ChibiOS/ST_NUCLEO144_F767ZI/README.md index 3ddc3ec045..3ff0e108e6 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/README.md +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/README.md @@ -9,24 +9,7 @@ In _halconf.g_ (in both nanoBooter and nanoCLR folders), when compared with a de - SERIAL_DEFAULT_BITRATE to 921600 In _mcuconf.h_ (in both nanoBooter and nanoCLR folders), when compared with a default file available from (https://github.com/ChibiOS/ChibiOS/tree/master/demos/STM32/RT-STM32F769I-DISCOVERY): -- STM32_SERIAL_USE_USART1 to TRUE +- STM32_SERIAL_USE_USART3 to TRUE NOTE: this configuration was successfully tested in an ST_NUCLEO144_F767ZI board using the Serial port through the onboard ST Link USB connection. -## ADC configurations - -The following ADC channels (and respective GPIO pins) are available to the managed API, in the respective index: -- PA6, ADC1 IN6 -- PA4 ADC1 IN4 -- PC2 ADC1 IN12 -- PF10 ADC1 IN8 -- PF8 ADC3 IN6 -- PB8 ADC3 IN7 -- Temp Sensor ADC1 -- VrefInt ADC1 -- Vbatt ADC1 - -## Floating point - -The current build is set to add support for single-precision floating point. -Meaning that `System.Math` API supports only the `float` overloads. The `double` ones will throw a `NotImplementedException`. diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/main.c b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/main.c index e536b0e7b2..71171354ec 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/main.c +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/main.c @@ -95,9 +95,9 @@ int main(void) // Normal main() thread while (true) { - palSetLine(GPIOB_LED1); + palSetLine(LINE_LED1); osDelay(500); - palClearLine(GPIOB_LED1); + palClearLine(LINE_LED1); osDelay(500); } } From 6766dbf920d884eedd62d0975cd38ac70f8d1274 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Sun, 10 Sep 2023 19:24:02 +0100 Subject: [PATCH 26/44] Fix define. --- targets/ChibiOS/ST_NUCLEO144_F767ZI/stm32f7xx_hal_conf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/stm32f7xx_hal_conf.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/stm32f7xx_hal_conf.h index 7f681bc7ce..9a60c6178d 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/stm32f7xx_hal_conf.h +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/stm32f7xx_hal_conf.h @@ -7,7 +7,7 @@ #ifndef STM32F7xx_HAL_CONF_H #define STM32F7xx_HAL_CONF_H -#define STM32F769xx +#define STM32F767xx #ifdef __cplusplus extern "C" { From 54f1af4422fcaff7fb4a1926574db11f9e25977b Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Sun, 10 Sep 2023 19:26:39 +0100 Subject: [PATCH 27/44] Test SPI on --- targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json | 2 +- .../sys_dev_pwm_native_System_Device_Pwm_PwmChannel.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json b/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json index 29fa5d098a..9029d4aa09 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json @@ -31,7 +31,7 @@ "API_System.Math": "ON", "API_Hardware.Stm32": "ON", "API_System.Device.Gpio": "ON", - "API_System.Device.Spi": "OFF", + "API_System.Device.Spi": "ON", "API_System.Device.I2c": "OFF", "API_System.Device.Pwm": "OFF", "API_System.IO.Ports": "OFF", diff --git a/targets/ChibiOS/_nanoCLR/System.Device.Pwm/sys_dev_pwm_native_System_Device_Pwm_PwmChannel.cpp b/targets/ChibiOS/_nanoCLR/System.Device.Pwm/sys_dev_pwm_native_System_Device_Pwm_PwmChannel.cpp index 24b614e49c..3de3efcf99 100644 --- a/targets/ChibiOS/_nanoCLR/System.Device.Pwm/sys_dev_pwm_native_System_Device_Pwm_PwmChannel.cpp +++ b/targets/ChibiOS/_nanoCLR/System.Device.Pwm/sys_dev_pwm_native_System_Device_Pwm_PwmChannel.cpp @@ -431,7 +431,7 @@ int GetChannelPwm(int pin, int timerId) break; } #endif -#if defined(STM32F769xx) || defined(STM32F765xx) +#if defined(STM32F769xx) || defined(STM32F765xx) || defined(STM32F767xx) switch (timerId) { case 1: From 2aa19099cd42383d0f6fe63e712b1e316f2690e1 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Sun, 10 Sep 2023 19:31:32 +0100 Subject: [PATCH 28/44] SPI off again. --- targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json b/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json index 9029d4aa09..29fa5d098a 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json @@ -31,7 +31,7 @@ "API_System.Math": "ON", "API_Hardware.Stm32": "ON", "API_System.Device.Gpio": "ON", - "API_System.Device.Spi": "ON", + "API_System.Device.Spi": "OFF", "API_System.Device.I2c": "OFF", "API_System.Device.Pwm": "OFF", "API_System.IO.Ports": "OFF", From 0a1d5ef31033a4ca5d71f528294442e10236c2cc Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Sun, 10 Sep 2023 20:25:17 +0100 Subject: [PATCH 29/44] Minor fixes --- .../managed_helpers/STM32F767ZI_NUCLEO.Adc.cs | 53 ------------------- .../ST_NUCLEO144_F767ZI.Adc.cs | 53 +++++++++++++++++++ .../ST_NUCLEO144_F767ZI/stm32f7xx_hal_conf.h | 2 +- 3 files changed, 54 insertions(+), 54 deletions(-) delete mode 100644 targets/ChibiOS/ST_NUCLEO144_F767ZI/managed_helpers/STM32F767ZI_NUCLEO.Adc.cs create mode 100644 targets/ChibiOS/ST_NUCLEO144_F767ZI/managed_helpers/ST_NUCLEO144_F767ZI.Adc.cs diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/managed_helpers/STM32F767ZI_NUCLEO.Adc.cs b/targets/ChibiOS/ST_NUCLEO144_F767ZI/managed_helpers/STM32F767ZI_NUCLEO.Adc.cs deleted file mode 100644 index b5cde5b8eb..0000000000 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/managed_helpers/STM32F767ZI_NUCLEO.Adc.cs +++ /dev/null @@ -1,53 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -namespace nanoFramework.Targets.STM32F767ZI_NUCLEO -{ - /// - /// Enumeration of ADC channels available in STM32F769I_DISCOVERY - /// - public static class AdcChannels - { - /// - /// Channel 0, exposed on A0, connected to PA6 (ADC1 - IN6) - /// - public const int Channel_0 = 0; - - /// - /// Channel 1, exposed on A1, connected to PA4 (ADC1 - IN4) - /// - public const int Channel_1 = 1; - - /// - /// Channel 2, exposed on A2, connected to PC2 (ADC1 - IN12) - /// - public const int Channel_2 = 2; - - /// - /// Channel 3, exposed on A3, connected to PF10 (ADC3 - IN8) - /// - public const int Channel_3 = 3; - - /// - /// Channel 4, exposed on A4, connected to PF8 (ADC3 - IN6) - /// - public const int Channel_4 = 4; - - /// - /// Channel 5, internal temperature sensor, connected to ADC1 - /// - public const int Channel_TemperatureSensor = 5; - - /// - /// Channel 6, internal voltage reference, connected to ADC1 - /// - public const int Channel_VrefIn = 6; - - /// - /// Channel 7, connected to VBatt pin, ADC1 - /// - public const int Channel_Vbatt = 7; - } -} diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/managed_helpers/ST_NUCLEO144_F767ZI.Adc.cs b/targets/ChibiOS/ST_NUCLEO144_F767ZI/managed_helpers/ST_NUCLEO144_F767ZI.Adc.cs new file mode 100644 index 0000000000..00e9efe59e --- /dev/null +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/managed_helpers/ST_NUCLEO144_F767ZI.Adc.cs @@ -0,0 +1,53 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +namespace nanoFramework.Targets.ST_NUCLEO144_F767ZI +{ + /// + /// Enumeration of ADC channels available for ST_NUCLEO144_F767ZI + /// + public static class AdcChannels + { + // /// + // /// Channel 0, exposed on A0, connected to PA6 (ADC1 - IN6) + // /// + // public const int Channel_0 = 0; + + // /// + // /// Channel 1, exposed on A1, connected to PA4 (ADC1 - IN4) + // /// + // public const int Channel_1 = 1; + + // /// + // /// Channel 2, exposed on A2, connected to PC2 (ADC1 - IN12) + // /// + // public const int Channel_2 = 2; + + // /// + // /// Channel 3, exposed on A3, connected to PF10 (ADC3 - IN8) + // /// + // public const int Channel_3 = 3; + + // /// + // /// Channel 4, exposed on A4, connected to PF8 (ADC3 - IN6) + // /// + // public const int Channel_4 = 4; + + // /// + // /// Channel 5, internal temperature sensor, connected to ADC1 + // /// + // public const int Channel_TemperatureSensor = 5; + + // /// + // /// Channel 6, internal voltage reference, connected to ADC1 + // /// + // public const int Channel_VrefIn = 6; + + // /// + // /// Channel 7, connected to VBatt pin, ADC1 + // /// + // public const int Channel_Vbatt = 7; + } +} diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/stm32f7xx_hal_conf.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/stm32f7xx_hal_conf.h index 9a60c6178d..997ab81029 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/stm32f7xx_hal_conf.h +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/stm32f7xx_hal_conf.h @@ -43,7 +43,7 @@ * @retval None */ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) - void assert_failed(uint8_t* file, uint32_t line); + void assert_failed(uint8_t *file, uint32_t line); #else #define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ From ba5da4277ac746df21b075c98f027df661d8f1e1 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Tue, 12 Sep 2023 12:31:37 +0100 Subject: [PATCH 30/44] mcuconf adjustments wdg, spi, i2c, uart --- .../ST_NUCLEO144_F767ZI/CMakePresets.json | 8 ++++---- .../ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h | 16 ++++++++-------- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json b/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json index 29fa5d098a..7a12d78850 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json @@ -25,16 +25,16 @@ "NF_FEATURE_RTC": "ON", "NF_FEATURE_HAS_SDCARD": "OFF", "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", - "NF_FEATURE_WATCHDOG": "OFF", + "NF_FEATURE_WATCHDOG": "ON", "SWO_OUTPUT": "OFF", "NF_BUILD_RTM": "OFF", "API_System.Math": "ON", "API_Hardware.Stm32": "ON", "API_System.Device.Gpio": "ON", - "API_System.Device.Spi": "OFF", - "API_System.Device.I2c": "OFF", + "API_System.Device.Spi": "ON", + "API_System.Device.I2c": "ON", "API_System.Device.Pwm": "OFF", - "API_System.IO.Ports": "OFF", + "API_System.IO.Ports": "ON", "API_System.Device.Adc": "OFF", "API_System.Device.Dac": "OFF", "API_System.Net": "ON", diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h index 428e4ff2ca..07669e7860 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h @@ -46,7 +46,7 @@ #define STM32_PLS STM32_PLS_LEV0 #define STM32_BKPRAM_ENABLE FALSE #define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED FALSE +#define STM32_LSI_ENABLED TRUE #define STM32_HSE_ENABLED TRUE #define STM32_LSE_ENABLED TRUE #define STM32_CLOCK48_REQUIRED TRUE @@ -207,8 +207,8 @@ /* * I2C driver system settings. */ -#define STM32_I2C_USE_I2C1 FALSE -#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C2 TRUE #define STM32_I2C_USE_I2C3 FALSE #define STM32_I2C_USE_I2C4 FALSE #define STM32_I2C_BUSY_TIMEOUT 50 @@ -330,9 +330,9 @@ /* * SPI driver system settings. */ -#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI1 TRUE #define STM32_SPI_USE_SPI2 FALSE -#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI3 TRUE #define STM32_SPI_USE_SPI4 FALSE #define STM32_SPI_USE_SPI5 FALSE #define STM32_SPI_USE_SPI6 FALSE @@ -377,11 +377,11 @@ * UART driver system settings. */ #define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART2 TRUE #define STM32_UART_USE_USART3 FALSE #define STM32_UART_USE_UART4 FALSE #define STM32_UART_USE_UART5 FALSE -#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USE_USART6 TRUE #define STM32_UART_USE_UART7 FALSE #define STM32_UART_USE_UART8 FALSE #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) @@ -423,7 +423,7 @@ /* * WDG driver system settings. */ -#define STM32_WDG_USE_IWDG FALSE +#define STM32_WDG_USE_IWDG TRUE /* * WSPI driver system settings. From 503c7575d7cc3b31eeb6629391d4058f1dba88b8 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Tue, 12 Sep 2023 12:37:13 +0100 Subject: [PATCH 31/44] Fix I2C2 turn on CAN1 in mcuconf --- targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json | 1 - targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h | 2 +- .../ST_NUCLEO144_F767ZI/target_system_device_i2c_config.cpp | 2 +- 3 files changed, 2 insertions(+), 3 deletions(-) diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json b/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json index 7a12d78850..52b20bb9d2 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json @@ -25,7 +25,6 @@ "NF_FEATURE_RTC": "ON", "NF_FEATURE_HAS_SDCARD": "OFF", "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", - "NF_FEATURE_WATCHDOG": "ON", "SWO_OUTPUT": "OFF", "NF_BUILD_RTM": "OFF", "API_System.Math": "ON", diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h index 07669e7860..6d5f1d0878 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h @@ -163,7 +163,7 @@ /* * CAN driver system settings. */ -#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN1 TRUE #define STM32_CAN_USE_CAN2 FALSE #define STM32_CAN_USE_CAN3 FALSE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_i2c_config.cpp b/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_i2c_config.cpp index 635d8dc4c8..1e6b259407 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_i2c_config.cpp +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_device_i2c_config.cpp @@ -28,7 +28,7 @@ I2C_CONFIG_PINS(1, GPIOB, GPIOB, 8, 9, 4) // SCL pin: is GPIOF_1 // SDA pin: is GPIOB_0 // GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet) -I2C_CONFIG_PINS(1, GPIOB, GPIOB, 1, 0, 4) +I2C_CONFIG_PINS(2, GPIOB, GPIOB, 1, 0, 4) ////////// From 3997b649c7551891a6b8c7b1530a1ccfb1afc435 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Tue, 12 Sep 2023 12:44:18 +0100 Subject: [PATCH 32/44] Turn off ports Turn on CAN --- targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json b/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json index 52b20bb9d2..8de1f4e730 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json @@ -33,12 +33,12 @@ "API_System.Device.Spi": "ON", "API_System.Device.I2c": "ON", "API_System.Device.Pwm": "OFF", - "API_System.IO.Ports": "ON", + "API_System.IO.Ports": "OFF", "API_System.Device.Adc": "OFF", "API_System.Device.Dac": "OFF", "API_System.Net": "ON", "API_nanoFramework.Device.OneWire": "OFF", - "API_nanoFramework.Device.Can": "OFF", + "API_nanoFramework.Device.Can": "ON", "API_nanoFramework.ResourceManager": "ON", "API_nanoFramework.System.Collections": "ON", "API_nanoFramework.System.Text": "ON", From 03506496b061e98f560dab6730b0f01d514b2911 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Tue, 12 Sep 2023 12:49:12 +0100 Subject: [PATCH 33/44] Turn on ADC --- targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json | 2 +- targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json b/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json index 8de1f4e730..aff4758977 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json @@ -34,7 +34,7 @@ "API_System.Device.I2c": "ON", "API_System.Device.Pwm": "OFF", "API_System.IO.Ports": "OFF", - "API_System.Device.Adc": "OFF", + "API_System.Device.Adc": "ON", "API_System.Device.Dac": "OFF", "API_System.Net": "ON", "API_nanoFramework.Device.OneWire": "OFF", diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h index 6d5f1d0878..1cc32ceb65 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h @@ -146,9 +146,9 @@ * ADC driver system settings. */ #define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 -#define STM32_ADC_USE_ADC1 FALSE -#define STM32_ADC_USE_ADC2 FALSE -#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 TRUE +#define STM32_ADC_USE_ADC3 TRUE #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) #define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) From 57c52f65ed2e2c9262512c8c1100547db9e30dfa Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Tue, 12 Sep 2023 13:01:08 +0100 Subject: [PATCH 34/44] Tuen on ports again See if we can discover the issue. --- targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json b/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json index aff4758977..773bbe79f9 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json @@ -33,7 +33,7 @@ "API_System.Device.Spi": "ON", "API_System.Device.I2c": "ON", "API_System.Device.Pwm": "OFF", - "API_System.IO.Ports": "OFF", + "API_System.IO.Ports": "ON", "API_System.Device.Adc": "ON", "API_System.Device.Dac": "OFF", "API_System.Net": "ON", From 401835db42321e19cbe7d3f2c24f23ad0279cbd1 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Tue, 12 Sep 2023 13:06:07 +0100 Subject: [PATCH 35/44] Fix port definition --- .../ChibiOS/ST_NUCLEO144_F767ZI/target_system_io_ports_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_io_ports_config.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_io_ports_config.h index 17f75e1958..bf538a8c6b 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_io_ports_config.h +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_io_ports_config.h @@ -15,7 +15,7 @@ /////////// // enable UART2 -#define NF_SERIAL_COMM_STM32_UART_USE_UART2 TRUE +#define NF_SERIAL_COMM_STM32_UART_USE_USART2 TRUE // /////////// // // UART3 // From 0d7828751d28209fc49282852c10af45fd0e51a1 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Tue, 12 Sep 2023 13:21:58 +0100 Subject: [PATCH 36/44] Enable PWM --- .../ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json | 2 +- .../ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h | 10 +++++----- .../target_system_io_ports_config.cpp | 14 +------------- 3 files changed, 7 insertions(+), 19 deletions(-) diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json b/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json index 773bbe79f9..43465a08ba 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/CMakePresets.json @@ -32,7 +32,7 @@ "API_System.Device.Gpio": "ON", "API_System.Device.Spi": "ON", "API_System.Device.I2c": "ON", - "API_System.Device.Pwm": "OFF", + "API_System.Device.Pwm": "ON", "API_System.IO.Ports": "ON", "API_System.Device.Adc": "ON", "API_System.Device.Dac": "OFF", diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h index 1cc32ceb65..5dcaca2d6e 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h @@ -263,10 +263,10 @@ /* * PWM driver system settings. */ -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM2 TRUE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM4 TRUE #define STM32_PWM_USE_TIM5 FALSE #define STM32_PWM_USE_TIM8 FALSE #define STM32_PWM_USE_TIM9 FALSE @@ -274,7 +274,7 @@ #define STM32_PWM_USE_TIM11 FALSE #define STM32_PWM_USE_TIM12 FALSE #define STM32_PWM_USE_TIM13 FALSE -#define STM32_PWM_USE_TIM14 FALSE +#define STM32_PWM_USE_TIM14 TRUE #define STM32_PWM_USE_TIM15 FALSE #define STM32_PWM_USE_TIM16 FALSE #define STM32_PWM_USE_TIM17 FALSE diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_io_ports_config.cpp b/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_io_ports_config.cpp index ccb0e82067..49a10c745f 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_io_ports_config.cpp +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/target_system_io_ports_config.cpp @@ -10,19 +10,7 @@ // UART1 // /////////// -// pin configuration for UART1 -// port for TX pin is: GPIOC -// port for RX pin is: GPIOC -// TX pin: is GPIOC_4 -// RX pin: is GPIOC_5 -// GPIO alternate pin function is 7 (see alternate function mapping table in device datasheet) -// UART_CONFIG_PINS(1, GPIOC, GPIOC, 4, 5, 4) - -// // initialization for UART1 -// UART_INIT(1) - -// // un-initialization for UART1 -// UART_UNINIT(1) +// NOT AVAILABLE /////////// // UART2 // From b4a13023e931550b90179c8adcf25f11b19ff41f Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Tue, 12 Sep 2023 13:28:20 +0100 Subject: [PATCH 37/44] Turn off TIM2 in mcuconf --- .github/workflows/build-chibios-target.yml | 2 +- targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/build-chibios-target.yml b/.github/workflows/build-chibios-target.yml index 415709bfdb..7223369f99 100644 --- a/.github/workflows/build-chibios-target.yml +++ b/.github/workflows/build-chibios-target.yml @@ -16,7 +16,7 @@ jobs: matrix: # Add the target and build type you wish to generate firmware for: include: [ - # { target: ST_NUCLEO144_F767ZI, build-type: MinSizeRel }, + { target: ST_NUCLEO144_F767ZI, build-type: MinSizeRel }, { target: ST_NUCLEO144_F767ZI, build-type: Debug }, # { target: ST_STM32F769I_DISCOVERY, build-type: MinSizeRel }, diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h index 5dcaca2d6e..61de24ece8 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf.h @@ -264,7 +264,7 @@ * PWM driver system settings. */ #define STM32_PWM_USE_TIM1 TRUE -#define STM32_PWM_USE_TIM2 TRUE +#define STM32_PWM_USE_TIM2 FALSE #define STM32_PWM_USE_TIM3 TRUE #define STM32_PWM_USE_TIM4 TRUE #define STM32_PWM_USE_TIM5 FALSE From a01c497ae2971864eaef28dcf7d3781a4b66b1b1 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Tue, 12 Sep 2023 13:35:25 +0100 Subject: [PATCH 38/44] Add STM32_PWM_USE_ADVANCED --- targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf_nf.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf_nf.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf_nf.h index bae0152d36..f3e7d185bc 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf_nf.h +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/mcuconf_nf.h @@ -19,4 +19,10 @@ #define STM32_SDRAM_USE_FSMC_SDRAM1 TRUE #define STM32_SDRAM_USE_FSMC_SDRAM2 FALSE +/* + * PWM driver system settings. + */ + #define STM32_PWM_USE_ADVANCED TRUE + + #endif // MCUCONF_NF_H From 3420ea87cab6dacd3384c0741aa048994544f161 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Tue, 12 Sep 2023 15:56:32 +0100 Subject: [PATCH 39/44] Update readme [skip ci] --- targets/ChibiOS/ST_NUCLEO144_F767ZI/README.md | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/README.md b/targets/ChibiOS/ST_NUCLEO144_F767ZI/README.md index 3ff0e108e6..a25cfca0eb 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/README.md +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/README.md @@ -4,12 +4,8 @@ For a successful build the following changes are required: For memory maps, uuid etc. the reference document used was: http://www.st.com/content/ccc/resource/technical/document/reference_manual/group0/96/8b/0d/ec/16/22/43/71/DM00224583/files/DM00224583.pdf/jcr:content/translations/en.DM00224583.pdf -In _halconf.g_ (in both nanoBooter and nanoCLR folders), when compared with a default file available from (https://github.com/ChibiOS/ChibiOS/tree/master/demos/STM32/RT-STM32F769I-DISCOVERY): -- HAL_USE_SERIAL to TRUE -- SERIAL_DEFAULT_BITRATE to 921600 - -In _mcuconf.h_ (in both nanoBooter and nanoCLR folders), when compared with a default file available from (https://github.com/ChibiOS/ChibiOS/tree/master/demos/STM32/RT-STM32F769I-DISCOVERY): -- STM32_SERIAL_USE_USART3 to TRUE +For port maps: +https://www.st.com/resource/en/user_manual/um1974-stm32-nucleo144-boards-mb1137-stmicroelectronics.pdf NOTE: this configuration was successfully tested in an ST_NUCLEO144_F767ZI board using the Serial port through the onboard ST Link USB connection. From af92a7da05d44cebe38ff670721d3a4cbbcdea7d Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Sat, 16 Sep 2023 11:45:04 +0100 Subject: [PATCH 40/44] Code style fixes --- targets/ChibiOS/ST_NUCLEO144_F767ZI/board.c | 4 ++++ targets/ChibiOS/ST_NUCLEO144_F767ZI/board.h | 4 ++++ .../ST_NUCLEO144_F767ZI/common/Device_BlockStorage-DEBUG.c | 4 ++++ .../ChibiOS/ST_NUCLEO144_F767ZI/common/Device_BlockStorage.c | 4 ++++ targets/ChibiOS/ST_NUCLEO144_F767ZI/common/serialcfg.h | 5 ++++- targets/ChibiOS/ST_NUCLEO144_F767ZI/mbedtls_config.h | 4 ++-- 6 files changed, 22 insertions(+), 3 deletions(-) diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/board.c b/targets/ChibiOS/ST_NUCLEO144_F767ZI/board.c index 4041ccf612..851aeb4c2f 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/board.c +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/board.c @@ -19,6 +19,8 @@ * generator plugin. Do not edit manually. */ +// clang-format off + #include "hal.h" #include "stm32_gpio.h" @@ -264,3 +266,5 @@ bool mmc_lld_is_write_protected(MMCDriver *mmcp) { void boardInit(void) { } + +// clang-format on diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/board.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/board.h index e46cad28f2..2f8ce3c282 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/board.h +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/board.h @@ -19,6 +19,8 @@ * generator plugin. Do not edit manually. */ + // clang-format off + #ifndef BOARD_H #define BOARD_H @@ -1860,3 +1862,5 @@ extern "C" { #endif /* _FROM_ASM_ */ #endif /* BOARD_H */ + +// clang-format on diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/common/Device_BlockStorage-DEBUG.c b/targets/ChibiOS/ST_NUCLEO144_F767ZI/common/Device_BlockStorage-DEBUG.c index 05c8653805..9ff4bb4d94 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/common/Device_BlockStorage-DEBUG.c +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/common/Device_BlockStorage-DEBUG.c @@ -3,6 +3,8 @@ // See LICENSE file in the project root for full license information. // +// clang-format off + #include #include @@ -104,3 +106,5 @@ MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = }; BlockStorageDevice Device_BlockStorage; + +// clang-format on diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/common/Device_BlockStorage.c b/targets/ChibiOS/ST_NUCLEO144_F767ZI/common/Device_BlockStorage.c index 05c8653805..9ff4bb4d94 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/common/Device_BlockStorage.c +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/common/Device_BlockStorage.c @@ -3,6 +3,8 @@ // See LICENSE file in the project root for full license information. // +// clang-format off + #include #include @@ -104,3 +106,5 @@ MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = }; BlockStorageDevice Device_BlockStorage; + +// clang-format on diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/common/serialcfg.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/common/serialcfg.h index 07b8bbd3ac..d862be8583 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/common/serialcfg.h +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/common/serialcfg.h @@ -3,13 +3,16 @@ // See LICENSE file in the project root for full license information. // +// clang-format off + #ifndef SERIALCFG_H #define SERIALCFG_H // define which serial driver the Wire Protocol will be using #define SERIAL_DRIVER SD3 -#endif /* SERIALCFG_H */ +#endif /* SERIALCFG_H */ /** @} */ +// clang-format on diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/mbedtls_config.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/mbedtls_config.h index f70dd41e40..e2c2fff627 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/mbedtls_config.h +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/mbedtls_config.h @@ -25,7 +25,7 @@ // #define MBEDTLS_VERSION_C // uncomment the defines below to enable static memory allocation feature -#if 0 +#if 0 #define MBEDTLS_MEMORY_BUFFER_ALLOC_C #define MBEDTLS_PLATFORM_MEMORY #endif @@ -35,7 +35,7 @@ #define MBEDTLS_PLATFORM_PRINTF_MACRO LCD_UsrLog #endif -// uncomment the defines bellow to generate debug output +// uncomment the defines bellow to generate debug output // set below the threshold level for debug messages // check Mbed TLS mbedtls/debug.h header for details. // Debug levels: From f1c6c3af948da70acb0ecb821046f834385a94ba Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Sat, 16 Sep 2023 11:48:59 +0100 Subject: [PATCH 41/44] Further fix --- targets/ChibiOS/ST_NUCLEO144_F767ZI/board.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/board.h b/targets/ChibiOS/ST_NUCLEO144_F767ZI/board.h index 2f8ce3c282..9a2d748cb2 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/board.h +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/board.h @@ -19,7 +19,7 @@ * generator plugin. Do not edit manually. */ - // clang-format off +// clang-format off #ifndef BOARD_H #define BOARD_H From eabd4bef1d14e61d1909b5e59a518827b91e69a4 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Wed, 27 Sep 2023 22:19:06 +0100 Subject: [PATCH 42/44] Update linker files --- .../nanoBooter/STM32F76xx_booter-DEBUG.ld | 52 +++++++++++-------- .../nanoBooter/STM32F76xx_booter.ld | 52 +++++++++++-------- .../nanoCLR/STM32F76xx_CLR-DEBUG.ld | 39 +++++--------- .../nanoCLR/STM32F76xx_CLR.ld | 39 +++++--------- 4 files changed, 88 insertions(+), 94 deletions(-) diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/STM32F76xx_booter-DEBUG.ld b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/STM32F76xx_booter-DEBUG.ld index 5b9a6050cd..7ce269e0d9 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/STM32F76xx_booter-DEBUG.ld +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/STM32F76xx_booter-DEBUG.ld @@ -7,7 +7,7 @@ */ /* - * STM32F76xx generic setup. + * STM32F76xxI generic setup. * * RAM0 - Data, Heap. * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH. @@ -17,26 +17,34 @@ */ MEMORY { - flash0 (rx) : org = 0x08000000, len = 32k /* space reserved for nanoBooter (1st sector 0x08000000 to 0x08008000)*/ - flash1 (rx) : org = 0x00200000, len = 32k - flash2 (rx) : org = 0x00000000, len = 0 - flash3 (rx) : org = 0x00000000, len = 0 - flash4 (rx) : org = 0x00000000, len = 0 - flash5 (rx) : org = 0x00000000, len = 0 - flash6 (rx) : org = 0x00000000, len = 0 - flash7 (rx) : org = 0x00000000, len = 0 - config (rw) : org = 0x08008000, len = 32k /* space reserved for configuration block */ - deployment (rx) : org = 0x00000000, len = 0 /* space reserved for application deployment */ - ramvt (wx) : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ - ram0 (wx) : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */ - ram1 (wx) : org = 0x20020000, len = 368k /* SRAM1 */ - ram2 (wx) : org = 0x2007C000, len = 16k /* SRAM2 */ - ram3 (wx) : org = 0x20000030, len = 128k-48 /* DTCM-RAM */ - ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */ - ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */ - ram6 (wx) : org = 0x00000000, len = 0 - ram7 (wx) : org = 0x00000000, len = 0 - bootclpbrd (wx) : org = 0x20000000, len = 48 /* boot clipboard area */ + /* for flash0 and flash1 regions + * they are the same flash but accessed through different addresses + * taking into account: + * only the booter region to use the first 32k + * the config region is already using 32k + * the application deployment region needs to use 1024k + */ + flash0 (rx) : org = 0x08000000, len = 32k /* Flash region as AXIM (writable) */ + flash1 (rx) : org = 0x00200000, len = 32k /* Flash region as ITCM */ + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (wx) : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */ + ram1 (wx) : org = 0x20020000, len = 368k /* SRAM1 */ + ram2 (wx) : org = 0x2007C000, len = 16k /* SRAM2 */ + ram3 (wx) : org = 0x20000030, len = 128k-48 /* DTCM-RAM */ + ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */ + ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 + + config (rw) : org = 0x08008000, len = 32k /* address space reserved for configuration block */ + deployment (rx) : org = 0x08100000, len = 1024k /* address space reserved for application deployment */ + ramvt (wx) : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table (should use chibios) */ + bootclpbrd (wx) : org = 0x20000000, len = 48 /* boot clipboard area */ } /* For each data/text section two region are defined, a virtual region @@ -86,7 +94,7 @@ REGION_ALIAS("HEAP_RAM", ram0); /* RAM region to be used for the boot clipboard.*/ REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); -/* rules inclusion.*/ +/* Stack rules inclusion.*/ INCLUDE rules_stacks.ld /*===========================================================================*/ diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/STM32F76xx_booter.ld b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/STM32F76xx_booter.ld index 5b9a6050cd..415aee153c 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/STM32F76xx_booter.ld +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoBooter/STM32F76xx_booter.ld @@ -7,7 +7,7 @@ */ /* - * STM32F76xx generic setup. + * STM32F76xxI generic setup. * * RAM0 - Data, Heap. * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH. @@ -17,26 +17,34 @@ */ MEMORY { - flash0 (rx) : org = 0x08000000, len = 32k /* space reserved for nanoBooter (1st sector 0x08000000 to 0x08008000)*/ - flash1 (rx) : org = 0x00200000, len = 32k - flash2 (rx) : org = 0x00000000, len = 0 - flash3 (rx) : org = 0x00000000, len = 0 - flash4 (rx) : org = 0x00000000, len = 0 - flash5 (rx) : org = 0x00000000, len = 0 - flash6 (rx) : org = 0x00000000, len = 0 - flash7 (rx) : org = 0x00000000, len = 0 - config (rw) : org = 0x08008000, len = 32k /* space reserved for configuration block */ - deployment (rx) : org = 0x00000000, len = 0 /* space reserved for application deployment */ - ramvt (wx) : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ - ram0 (wx) : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */ - ram1 (wx) : org = 0x20020000, len = 368k /* SRAM1 */ - ram2 (wx) : org = 0x2007C000, len = 16k /* SRAM2 */ - ram3 (wx) : org = 0x20000030, len = 128k-48 /* DTCM-RAM */ - ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */ - ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */ - ram6 (wx) : org = 0x00000000, len = 0 - ram7 (wx) : org = 0x00000000, len = 0 - bootclpbrd (wx) : org = 0x20000000, len = 48 /* boot clipboard area */ + /* for flash0 and flash1 regions + * they are the same flash but accessed through different addresses + * taking into account: + * only the booter region to use the first 32k + * the config region is already using 32k + * the application deployment region needs to use 1024k + */ + flash0 (rx) : org = 0x08000000, len = 32k /* Flash region as AXIM (writable) */ + flash1 (rx) : org = 0x00200000, len = 32k /* Flash region as ITCM */ + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (wx) : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */ + ram1 (wx) : org = 0x20020000, len = 368k /* SRAM1 */ + ram2 (wx) : org = 0x2007C000, len = 16k /* SRAM2 */ + ram3 (wx) : org = 0x20000030, len = 128k-48 /* DTCM-RAM */ + ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */ + ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 + + config (rw) : org = 0x08008000, len = 32k /* address space reserved for configuration block */ + deployment (rx) : org = 0x08100000, len = 1024k /* address space reserved for application deployment */ + ramvt (wx) : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table (should use chibios) */ + bootclpbrd (wx) : org = 0x20000000, len = 48 /* boot clipboard area */ } /* For each data/text section two region are defined, a virtual region @@ -86,7 +94,7 @@ REGION_ALIAS("HEAP_RAM", ram0); /* RAM region to be used for the boot clipboard.*/ REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); -/* rules inclusion.*/ +/* Stack rules inclusion.*/ INCLUDE rules_stacks.ld /*===========================================================================*/ diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR-DEBUG.ld b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR-DEBUG.ld index 81a1ad82e7..adca6b00e4 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR-DEBUG.ld +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR-DEBUG.ld @@ -14,21 +14,24 @@ * * Notes: * BSS is placed in DTCM RAM in order to simplify DMA buffers management. - * When updating the flash0 address below make sure to update the address in nf_generate_bin_package */ MEMORY { - flash0 (rx) : org = 0x08010000, len = 2M - 32k - 32k - 1024k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ - flash1 (rx) : org = 0x00210000, len = 2M - 32k - 32k - 1024k + /* for flash0 and flash1 regions + * they are the same flash but accessed through different addresses + * taking into account: + * the booter region is already using the first 32k + * the config region is already using 32k + * the application deployment region needs to use 1024k + */ + flash0 (rx) : org = 0x08010000, len = 2M - 32k - 32k - 1024k /* Flash region as AXIM (writable) */ + flash1 (rx) : org = 0x00210000, len = 2M - 32k - 32k - 1024k /* Flash region as ITCM */ flash2 (rx) : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0 - config (rw) : org = 0x08008000, len = 32k /* space reserved for configuration block */ - deployment (rx) : org = 0x08100000, len = 1024k /* space reserved for application deployment */ - ramvt (wx) : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ ram0 (wx) : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */ ram1 (wx) : org = 0x20020000, len = 368k /* SRAM1 */ ram2 (wx) : org = 0x2007C000, len = 16k /* SRAM2 */ @@ -38,9 +41,10 @@ MEMORY ram6 (wx) : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0 ext_ram (wx) : org = 0xC0000000, len = 13631488 /* external SDRAM */ - graphics_ram (wx) : org = 0xC0D00000, len = 2377728 /* external graphics ram for frame buffer and bitmaps*/ - graphics_vfb (wx) : org = 0xC0F44800, len = 768000 /* Frame buffer for video output mode 800*480*2 bytes ( 16 bits RGB565 )*/ - bootclpbrd (wx) : org = 0x20000000, len = 48 /* boot clipboard area */ + + config (rw) : org = 0x08008000, len = 32k /* address space reserved for configuration block */ + deployment (rx) : org = 0x08100000, len = 1024k /* address space reserved for application deployment */ + ramvt (wx) : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table (should use chibios) */ } /* For each data/text section two region are defined, a virtual region @@ -90,16 +94,7 @@ REGION_ALIAS("HEAP_RAM", ram0); /* RAM region to be used for the nanoFramework CLR managed heap.*/ REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ext_ram); -/* RAM region to be used for the nanoFramework graphics heap.*/ -REGION_ALIAS("GRAPHICS_HEAP_RAM", graphics_ram); - -/* RAM region to be used for the nanoFramework graphics heap.*/ -REGION_ALIAS("GRAPHICS_VIDEO_FRAME_BUFFER", graphics_vfb); - -/* RAM region to be used for the boot clipboard.*/ -REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); - -/* rules inclusion.*/ +/* Stack rules inclusion.*/ INCLUDE rules_stacks.ld /*===========================================================================*/ @@ -148,9 +143,3 @@ INCLUDE rules_memory.ld /* nanoCLR rules inclusion.*/ INCLUDE rules_clr.ld - -/* Graphics rules inclusion.*/ -INCLUDE rules_graphics.ld - -/* boot clipboard rules inclusion.*/ -INCLUDE rules_bootclipboard.ld diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR.ld b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR.ld index 81a1ad82e7..adca6b00e4 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR.ld +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR.ld @@ -14,21 +14,24 @@ * * Notes: * BSS is placed in DTCM RAM in order to simplify DMA buffers management. - * When updating the flash0 address below make sure to update the address in nf_generate_bin_package */ MEMORY { - flash0 (rx) : org = 0x08010000, len = 2M - 32k - 32k - 1024k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ - flash1 (rx) : org = 0x00210000, len = 2M - 32k - 32k - 1024k + /* for flash0 and flash1 regions + * they are the same flash but accessed through different addresses + * taking into account: + * the booter region is already using the first 32k + * the config region is already using 32k + * the application deployment region needs to use 1024k + */ + flash0 (rx) : org = 0x08010000, len = 2M - 32k - 32k - 1024k /* Flash region as AXIM (writable) */ + flash1 (rx) : org = 0x00210000, len = 2M - 32k - 32k - 1024k /* Flash region as ITCM */ flash2 (rx) : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0 - config (rw) : org = 0x08008000, len = 32k /* space reserved for configuration block */ - deployment (rx) : org = 0x08100000, len = 1024k /* space reserved for application deployment */ - ramvt (wx) : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ ram0 (wx) : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */ ram1 (wx) : org = 0x20020000, len = 368k /* SRAM1 */ ram2 (wx) : org = 0x2007C000, len = 16k /* SRAM2 */ @@ -38,9 +41,10 @@ MEMORY ram6 (wx) : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0 ext_ram (wx) : org = 0xC0000000, len = 13631488 /* external SDRAM */ - graphics_ram (wx) : org = 0xC0D00000, len = 2377728 /* external graphics ram for frame buffer and bitmaps*/ - graphics_vfb (wx) : org = 0xC0F44800, len = 768000 /* Frame buffer for video output mode 800*480*2 bytes ( 16 bits RGB565 )*/ - bootclpbrd (wx) : org = 0x20000000, len = 48 /* boot clipboard area */ + + config (rw) : org = 0x08008000, len = 32k /* address space reserved for configuration block */ + deployment (rx) : org = 0x08100000, len = 1024k /* address space reserved for application deployment */ + ramvt (wx) : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table (should use chibios) */ } /* For each data/text section two region are defined, a virtual region @@ -90,16 +94,7 @@ REGION_ALIAS("HEAP_RAM", ram0); /* RAM region to be used for the nanoFramework CLR managed heap.*/ REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ext_ram); -/* RAM region to be used for the nanoFramework graphics heap.*/ -REGION_ALIAS("GRAPHICS_HEAP_RAM", graphics_ram); - -/* RAM region to be used for the nanoFramework graphics heap.*/ -REGION_ALIAS("GRAPHICS_VIDEO_FRAME_BUFFER", graphics_vfb); - -/* RAM region to be used for the boot clipboard.*/ -REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); - -/* rules inclusion.*/ +/* Stack rules inclusion.*/ INCLUDE rules_stacks.ld /*===========================================================================*/ @@ -148,9 +143,3 @@ INCLUDE rules_memory.ld /* nanoCLR rules inclusion.*/ INCLUDE rules_clr.ld - -/* Graphics rules inclusion.*/ -INCLUDE rules_graphics.ld - -/* boot clipboard rules inclusion.*/ -INCLUDE rules_bootclipboard.ld From edd2b9d2132b1dfc126c4a8898a2e6298b823eab Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Wed, 27 Sep 2023 23:17:12 +0100 Subject: [PATCH 43/44] Test fix external RAM for managed heap --- .../ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR-DEBUG.ld | 2 +- targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR.ld | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR-DEBUG.ld b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR-DEBUG.ld index adca6b00e4..83c32cea54 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR-DEBUG.ld +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR-DEBUG.ld @@ -40,7 +40,7 @@ MEMORY ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */ ram6 (wx) : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0 - ext_ram (wx) : org = 0xC0000000, len = 13631488 /* external SDRAM */ + ext_ram (wx) : org = 0xD0000000, len = 8M /* external SDRAM */ config (rw) : org = 0x08008000, len = 32k /* address space reserved for configuration block */ deployment (rx) : org = 0x08100000, len = 1024k /* address space reserved for application deployment */ diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR.ld b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR.ld index adca6b00e4..83c32cea54 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR.ld +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR.ld @@ -40,7 +40,7 @@ MEMORY ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */ ram6 (wx) : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0 - ext_ram (wx) : org = 0xC0000000, len = 13631488 /* external SDRAM */ + ext_ram (wx) : org = 0xD0000000, len = 8M /* external SDRAM */ config (rw) : org = 0x08008000, len = 32k /* address space reserved for configuration block */ deployment (rx) : org = 0x08100000, len = 1024k /* address space reserved for application deployment */ From b853eb1186c339a7c5230c045bf6c4fe1df1e3e5 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Wed, 27 Sep 2023 23:35:41 +0100 Subject: [PATCH 44/44] No external SRAM --- .../ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR-DEBUG.ld | 3 +-- targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR.ld | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR-DEBUG.ld b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR-DEBUG.ld index 83c32cea54..27afcecc31 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR-DEBUG.ld +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR-DEBUG.ld @@ -40,7 +40,6 @@ MEMORY ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */ ram6 (wx) : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0 - ext_ram (wx) : org = 0xD0000000, len = 8M /* external SDRAM */ config (rw) : org = 0x08008000, len = 32k /* address space reserved for configuration block */ deployment (rx) : org = 0x08100000, len = 1024k /* address space reserved for application deployment */ @@ -92,7 +91,7 @@ REGION_ALIAS("BSS_RAM", ram3); REGION_ALIAS("HEAP_RAM", ram0); /* RAM region to be used for the nanoFramework CLR managed heap.*/ -REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ext_ram); +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); /* Stack rules inclusion.*/ INCLUDE rules_stacks.ld diff --git a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR.ld b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR.ld index 83c32cea54..27afcecc31 100644 --- a/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR.ld +++ b/targets/ChibiOS/ST_NUCLEO144_F767ZI/nanoCLR/STM32F76xx_CLR.ld @@ -40,7 +40,6 @@ MEMORY ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */ ram6 (wx) : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0 - ext_ram (wx) : org = 0xD0000000, len = 8M /* external SDRAM */ config (rw) : org = 0x08008000, len = 32k /* address space reserved for configuration block */ deployment (rx) : org = 0x08100000, len = 1024k /* address space reserved for application deployment */ @@ -92,7 +91,7 @@ REGION_ALIAS("BSS_RAM", ram3); REGION_ALIAS("HEAP_RAM", ram0); /* RAM region to be used for the nanoFramework CLR managed heap.*/ -REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ext_ram); +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); /* Stack rules inclusion.*/ INCLUDE rules_stacks.ld