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STM32G031.svd
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STM32G031.svd
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<?xml version="1.0" encoding="utf-8" standalone="no"?>
<!--
Copyright (c) 2022 STMicroelectronics.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
-->
<device schemaVersion="1.1"
xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>STM32G031</name>
<version>1.3</version>
<description>STM32G031</description>
<cpu>
<name>CM0</name>
<revision>r0p1</revision>
<endian>little</endian>
<mpuPresent>true</mpuPresent>
<fpuPresent>false</fpuPresent>
<nvicPrioBits>4</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<size>0x20</size>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<peripherals>
<peripheral>
<name>IWDG</name>
<description>Independent watchdog</description>
<groupName>IWDG</groupName>
<baseAddress>0x40003000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>KR</name>
<displayName>KR</displayName>
<description>Key register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>KEY</name>
<description>Key value (write only, read
0x0000)</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PR</name>
<displayName>PR</displayName>
<description>Prescaler register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PR</name>
<description>Prescaler divider</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR</name>
<displayName>RLR</displayName>
<description>Reload register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000FFF</resetValue>
<fields>
<field>
<name>RL</name>
<description>Watchdog counter reload
value</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>Status register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WVU</name>
<description>Watchdog counter window value
update</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RVU</name>
<description>Watchdog counter reload value
update</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PVU</name>
<description>Watchdog prescaler value
update</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WINR</name>
<displayName>WINR</displayName>
<description>Window register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000FFF</resetValue>
<fields>
<field>
<name>WIN</name>
<description>Watchdog counter window
value</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>WWDG</name>
<description>System window watchdog</description>
<groupName>WWDG</groupName>
<baseAddress>0x40002C00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>WWDG</name>
<description>Window watchdog interrupt</description>
<value>0</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>Control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000007F</resetValue>
<fields>
<field>
<name>WDGA</name>
<description>Activation bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T</name>
<description>7-bit counter (MSB to LSB)</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFR</name>
<displayName>CFR</displayName>
<description>Configuration register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000007F</resetValue>
<fields>
<field>
<name>WDGTB</name>
<description>Timer base</description>
<bitOffset>11</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>EWI</name>
<description>Early wakeup interrupt</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>W</name>
<description>7-bit window value</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>Status register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EWIF</name>
<description>Early wakeup interrupt
flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FLASH</name>
<description>Flash</description>
<groupName>Flash</groupName>
<baseAddress>0x40022000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>FLASH</name>
<description>Flash global interrupt</description>
<value>3</value>
</interrupt>
<registers>
<register>
<name>ACR</name>
<displayName>ACR</displayName>
<description>Access control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000600</resetValue>
<fields>
<field>
<name>LATENCY</name>
<description>Latency</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>PRFTEN</name>
<description>Prefetch enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ICEN</name>
<description>Instruction cache enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ICRST</name>
<description>Instruction cache reset</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EMPTY</name>
<description>Flash User area empty</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_SWEN</name>
<description>Debug access software
enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR</name>
<displayName>KEYR</displayName>
<description>Flash key register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>KEYR</name>
<description>KEYR</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OPTKEYR</name>
<displayName>OPTKEYR</displayName>
<description>Option byte key register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OPTKEYR</name>
<description>Option byte key</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>Status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EOP</name>
<description>End of operation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPERR</name>
<description>Operation error</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PROGERR</name>
<description>Programming error</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRPERR</name>
<description>Write protected error</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PGAERR</name>
<description>Programming alignment
error</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIZERR</name>
<description>Size error</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PGSERR</name>
<description>Programming sequence error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MISERR</name>
<description>Fast programming data miss
error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FASTERR</name>
<description>Fast programming error</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDERR</name>
<description>PCROP read error</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPTVERR</name>
<description>Option and Engineering bits loading
validity error</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BSY</name>
<description>Busy</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFGBSY</name>
<description>Programming or erase configuration
busy.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>Flash control register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xC0000000</resetValue>
<fields>
<field>
<name>PG</name>
<description>Programming</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PER</name>
<description>Page erase</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MER</name>
<description>Mass erase</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PNB</name>
<description>Page number</description>
<bitOffset>3</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>STRT</name>
<description>Start</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPTSTRT</name>
<description>Options modification start</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTPG</name>
<description>Fast programming</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOPIE</name>
<description>End of operation interrupt
enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRIE</name>
<description>Error interrupt enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDERRIE</name>
<description>PCROP read error interrupt
enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OBL_LAUNCH</name>
<description>Force the option byte
loading</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SEC_PROT</name>
<description>Securable memory area protection
enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPTLOCK</name>
<description>Options Lock</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>FLASH_CR Lock</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ECCR</name>
<displayName>ECCR</displayName>
<description>Flash ECC register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADDR_ECC</name>
<description>ECC fail address</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SYSF_ECC</name>
<description>ECC fail for Corrected ECC Error or
Double ECC Error in info block</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ECCIE</name>
<description>ECC correction interrupt
enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ECCC</name>
<description>ECC correction</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ECCD</name>
<description>ECC detection</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OPTR</name>
<displayName>OPTR</displayName>
<description>Flash option register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xF0000000</resetValue>
<fields>
<field>
<name>RDP</name>
<description>Read protection level</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>BOREN</name>
<description>BOR reset Level</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BORF_LEV</name>
<description>These bits contain the VDD supply level
threshold that activates the reset</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>BORR_LEV</name>
<description>These bits contain the VDD supply level
threshold that releases the reset.</description>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>nRST_STOP</name>
<description>nRST_STOP</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nRST_STDBY</name>
<description>nRST_STDBY</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nRSTS_HDW</name>
<description>nRSTS_HDW</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDWG_SW</name>
<description>Independent watchdog
selection</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IWDG_STOP</name>
<description>Independent watchdog counter freeze in
Stop mode</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IWDG_STDBY</name>
<description>Independent watchdog counter freeze in
Standby mode</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WWDG_SW</name>
<description>Window watchdog selection</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RAM_PARITY_CHECK</name>
<description>SRAM parity check control</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nBOOT_SEL</name>
<description>nBOOT_SEL</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nBOOT1</name>
<description>Boot configuration</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nBOOT0</name>
<description>nBOOT0 option bit</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NRST_MODE</name>
<description>NRST_MODE</description>
<bitOffset>27</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IRHEN</name>
<description>Internal reset holder enable
bit</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCROP1ASR</name>
<displayName>PCROP1ASR</displayName>
<description>Flash PCROP zone A Start address
register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0xF0000000</resetValue>
<fields>
<field>
<name>PCROP1A_STRT</name>
<description>PCROP1A area start offset</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCROP1AER</name>
<displayName>PCROP1AER</displayName>
<description>Flash PCROP zone A End address
register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0xF0000000</resetValue>
<fields>
<field>
<name>PCROP1A_END</name>
<description>PCROP1A area end offset</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PCROP_RDP</name>
<description>PCROP area preserved when RDP level
decreased</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WRP1AR</name>
<displayName>WRP1AR</displayName>
<description>Flash WRP area A address
register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0xF0000000</resetValue>
<fields>
<field>
<name>WRP1A_STRT</name>
<description>WRP area A start offset</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>WRP1A_END</name>
<description>WRP area A end offset</description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>WRP1BR</name>
<displayName>WRP1BR</displayName>
<description>Flash WRP area B address
register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0xF0000000</resetValue>
<fields>
<field>
<name>WRP1B_STRT</name>
<description>WRP area B start offset</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>WRP1B_END</name>
<description>WRP area B end offset</description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCROP1BSR</name>
<displayName>PCROP1BSR</displayName>
<description>Flash PCROP zone B Start address
register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0xF0000000</resetValue>
<fields>
<field>
<name>PCROP1B_STRT</name>
<description>PCROP1B area start offset</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCROP1BER</name>
<displayName>PCROP1BER</displayName>
<description>Flash PCROP zone B End address
register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0xF0000000</resetValue>
<fields>
<field>
<name>PCROP1B_END</name>
<description>PCROP1B area end offset</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SECR</name>
<displayName>SECR</displayName>
<description>Flash Security register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0xF0000000</resetValue>
<fields>
<field>
<name>SEC_SIZE</name>
<description>Securable memory area size</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>BOOT_LOCK</name>
<description>used to force boot from user
area</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RCC</name>
<description>Reset and clock control</description>
<groupName>RCC</groupName>
<baseAddress>0x40021000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>RCC</name>
<description>RCC global interrupt</description>
<value>4</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>Clock control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000063</resetValue>
<fields>
<field>
<name>HSION</name>
<description>HSI16 clock enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSIKERON</name>
<description>HSI16 always enable for peripheral
kernels</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSIRDY</name>
<description>HSI16 clock ready flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSIDIV</name>
<description>HSI16 clock division
factor</description>
<bitOffset>11</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>HSEON</name>
<description>HSE clock enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSERDY</name>
<description>HSE clock ready flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSEBYP</name>
<description>HSE crystal oscillator
bypass</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSSON</name>
<description>Clock security system
enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLLON</name>
<description>PLL enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLLRDY</name>
<description>PLL clock ready flag</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICSCR</name>
<displayName>ICSCR</displayName>
<description>Internal clock sources calibration
register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<resetValue>0x10000000</resetValue>
<fields>
<field>
<name>HSICAL</name>
<description>HSI16 clock calibration</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HSITRIM</name>
<description>HSI16 clock trimming</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CFGR</name>
<displayName>CFGR</displayName>
<description>Clock configuration register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MCOPRE</name>
<description>Microcontroller clock output
prescaler</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MCOSEL</name>
<description>Microcontroller clock
output</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PPRE</name>
<description>APB prescaler</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>