From e9f6916065b7ea2cab333d6aab978fa17ec4ffa1 Mon Sep 17 00:00:00 2001
From: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Date: Wed, 27 Nov 2024 09:41:27 +0100
Subject: [PATCH] drivers: mspi: Mode and structures

added mode support for SINGLE,QUAD,QUAD_1_4_4,QUAD_1_1_4 and custom Ipc mspi structures

Signed-off-by: Michal Frankiewicz <michal.frankiewicz@nordicsemi.no>
---
 drivers/mspi/mspi_nrfe.c         | 15 ++++++------
 include/drivers/mspi/nrfe_mspi.h | 42 ++++++++++++++++++++------------
 2 files changed, 34 insertions(+), 23 deletions(-)

diff --git a/drivers/mspi/mspi_nrfe.c b/drivers/mspi/mspi_nrfe.c
index 41477d707eea..bbf82f58ed68 100644
--- a/drivers/mspi/mspi_nrfe.c
+++ b/drivers/mspi/mspi_nrfe.c
@@ -104,10 +104,11 @@ static void ep_recv(const void *data, size_t len, void *priv)
 }
 
 static struct ipc_ept_cfg ep_cfg = {
-	.cb = {
-		.bound = ep_bound,
-		.received = ep_recv,
-	},
+	.cb =
+		{
+			.bound = ep_bound,
+			.received = ep_recv,
+		},
 };
 
 /**
@@ -386,15 +387,13 @@ static int api_config(const struct mspi_dt_spec *spec)
 	}
 
 	/* Send pinout configuration to FLPR */
-	ret = send_config(NRFE_MSPI_CONFIG_PINS, (const void *)pins_cfg.pin,
-				sizeof(pins_cfg));
+	ret = send_config(NRFE_MSPI_CONFIG_PINS, (const void *)pins_cfg.pin, sizeof(pins_cfg));
 	if (ret < 0) {
 		return ret;
 	}
 
 	/* Send controller configuration to FLPR */
-	return send_config(NRFE_MSPI_CONFIG_CTRL, (const void *)config,
-				sizeof(struct mspi_cfg));
+	return send_config(NRFE_MSPI_CONFIG_CTRL, (const void *)config, sizeof(struct mspi_cfg));
 }
 
 static int check_io_mode(enum mspi_io_mode io_mode)
diff --git a/include/drivers/mspi/nrfe_mspi.h b/include/drivers/mspi/nrfe_mspi.h
index 467b6806739c..f404a42e1d8a 100644
--- a/include/drivers/mspi/nrfe_mspi.h
+++ b/include/drivers/mspi/nrfe_mspi.h
@@ -8,42 +8,34 @@
 #define DRIVERS_MSPI_NRFE_MSPI_H
 
 #include <zephyr/drivers/pinctrl.h>
+#include <zephyr/drivers/mspi.h>
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 #ifdef CONFIG_SOC_NRF54L15
-#define NRFE_MSPI_PORT_NUMBER    2 /* Physical port number */
+
+#define NRFE_MSPI_PORT_NUMBER	 2 /* Physical port number */
 #define NRFE_MSPI_SCK_PIN_NUMBER 1 /* Physical pins number on port 2 */
 #define NRFE_MSPI_DQ0_PIN_NUMBER 2
 #define NRFE_MSPI_DQ1_PIN_NUMBER 4
 #define NRFE_MSPI_DQ2_PIN_NUMBER 3
 #define NRFE_MSPI_DQ3_PIN_NUMBER 0
 #define NRFE_MSPI_CS0_PIN_NUMBER 5
-#define NRFE_MSPI_PINS_MAX       6
-
-#define NRFE_MSPI_SCK_PIN_NUMBER_VIO 0 /* FLPR VIO SCLK pin number */
-#define NRFE_MSPI_DQ0_PIN_NUMBER_VIO 1
-#define NRFE_MSPI_DQ1_PIN_NUMBER_VIO 2
-#define NRFE_MSPI_DQ2_PIN_NUMBER_VIO 3
-#define NRFE_MSPI_DQ3_PIN_NUMBER_VIO 4
-#define NRFE_MSPI_CS0_PIN_NUMBER_VIO 5
+#define NRFE_MSPI_PINS_MAX	 6
 
-#define VIO(_pin_) _pin_##_VIO
 #else
 #error "Unsupported SoC for SDP MSPI"
 #endif
 
-#define NRFE_MSPI_MAX_CE_PINS_COUNT 5 /* Ex. CE0 CE1 CE2 CE3 CE4 */
-
 /** @brief eMSPI opcodes. */
 enum nrfe_mspi_opcode {
 	NRFE_MSPI_EP_BOUNDED = 0,
 	NRFE_MSPI_CONFIG_PINS,
-	NRFE_MSPI_CONFIG_CTRL,		/* struct mspi_cfg */
-	NRFE_MSPI_CONFIG_DEV,		/* struct mspi_dev_cfg */
-	NRFE_MSPI_CONFIG_XFER,		/* struct mspi_xfer */
+	NRFE_MSPI_CONFIG_CTRL, /* struct mspi_cfg */
+	NRFE_MSPI_CONFIG_DEV,  /* struct mspi_dev_cfg */
+	NRFE_MSPI_CONFIG_XFER, /* struct mspi_xfer */
 	NRFE_MSPI_TX,
 	NRFE_MSPI_TXRX,
 	NRFE_MSPI_WRONG_OPCODE,
@@ -60,6 +52,26 @@ typedef struct __packed {
 	uint8_t data;
 } nrfe_mspi_flpr_response_t;
 
+typedef struct __packed {
+	uint8_t opcode;
+	struct mspi_cfg cfg;
+} nrfe_mspi_cfg_t;
+
+typedef struct __packed {
+	uint8_t opcode;
+	struct mspi_dev_cfg cfg;
+} nrfe_mspi_dev_cfg_t;
+
+typedef struct __packed {
+	uint8_t opcode;
+	struct mspi_xfer xfer;
+} nrfe_mspi_xfer_t;
+
+typedef struct __packed {
+	uint8_t opcode;
+	struct mspi_xfer_packet packet;
+} nrfe_mspi_xfer_packet_t;
+
 #ifdef __cplusplus
 }
 #endif