drivers: mspi: added mode support up to QUAD_1_1_4 and custom Ipc str…

…uctures
mif1-nordic · Jan 8, 2025 · e6faca9 · e6faca9
1 parent fd6a31a
commit e6faca9
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Showing 2 changed files with 33 additions and 14 deletions.
diff --git a/drivers/mspi/mspi_nrfe.c b/drivers/mspi/mspi_nrfe.c
@@ -401,9 +401,15 @@ static int check_io_mode(enum mspi_io_mode io_mode)
 {
 	switch (io_mode) {
 	case MSPI_IO_MODE_SINGLE:
+	case MSPI_IO_MODE_DUAL:
+	case MSPI_IO_MODE_DUAL_1_1_2:
+	case MSPI_IO_MODE_DUAL_1_2_2:
 	case MSPI_IO_MODE_QUAD:
 	case MSPI_IO_MODE_QUAD_1_1_4:
 	case MSPI_IO_MODE_QUAD_1_4_4:
+	case MSPI_IO_MODE_OCTAL:
+	case MSPI_IO_MODE_OCTAL_1_1_8:
+	case MSPI_IO_MODE_OCTAL_1_8_8:
 		break;
 	default:
 		LOG_ERR("IO mode %d not supported", io_mode);
@@ -733,14 +739,14 @@ static int check_pins_config(const struct pinctrl_dev_config *config, uint8_t id
 				return -ENOTSUP;
 			}
 			break;
+		case NRF_FUN_SDP_MSPI_DQ4: /* Only single, dual and QSPI modes are supported */
+		case NRF_FUN_SDP_MSPI_DQ5:
+		case NRF_FUN_SDP_MSPI_DQ6:
+		case NRF_FUN_SDP_MSPI_DQ7:
 		case NRF_FUN_SDP_MSPI_CS1: /* TODO: Support more CS */
 		case NRF_FUN_SDP_MSPI_CS2:
 		case NRF_FUN_SDP_MSPI_CS3:
 		case NRF_FUN_SDP_MSPI_CS4:
-		case NRF_FUN_SDP_MSPI_DQ4: /* Only single and QSPI modes are supported */
-		case NRF_FUN_SDP_MSPI_DQ5:
-		case NRF_FUN_SDP_MSPI_DQ6:
-		case NRF_FUN_SDP_MSPI_DQ7:
 		default:
 			LOG_ERR("Not supported function: %d for GPIO pin number: %d!", fun, psel);
 			return -ENOTSUP;

diff --git a/include/drivers/mspi/nrfe_mspi.h b/include/drivers/mspi/nrfe_mspi.h
@@ -8,34 +8,27 @@
 #define DRIVERS_MSPI_NRFE_MSPI_H
 
 #include <zephyr/drivers/pinctrl.h>
+#include <zephyr/drivers/mspi.h>
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 #ifdef CONFIG_SOC_NRF54L15
+
 #define NRFE_MSPI_PORT_NUMBER    2 /* Physical port number */
 #define NRFE_MSPI_SCK_PIN_NUMBER 1 /* Physical pins number on port 2 */
 #define NRFE_MSPI_DQ0_PIN_NUMBER 2
 #define NRFE_MSPI_DQ1_PIN_NUMBER 4
 #define NRFE_MSPI_DQ2_PIN_NUMBER 3
 #define NRFE_MSPI_DQ3_PIN_NUMBER 0
 #define NRFE_MSPI_CS0_PIN_NUMBER 5
-#define NRFE_MSPI_PINS_MAX       6
-
-#define NRFE_MSPI_SCK_PIN_NUMBER_VIO 0 /* FLPR VIO SCLK pin number */
-#define NRFE_MSPI_DQ0_PIN_NUMBER_VIO 1
-#define NRFE_MSPI_DQ1_PIN_NUMBER_VIO 2
-#define NRFE_MSPI_DQ2_PIN_NUMBER_VIO 3
-#define NRFE_MSPI_DQ3_PIN_NUMBER_VIO 4
-#define NRFE_MSPI_CS0_PIN_NUMBER_VIO 5
+#define NRFE_MSPI_PINS_MAX 6
 
-#define VIO(_pin_) _pin_##_VIO
 #else
 #error "Unsupported SoC for SDP MSPI"
 #endif
 
-#define NRFE_MSPI_MAX_CE_PINS_COUNT 5 /* Ex. CE0 CE1 CE2 CE3 CE4 */
 
 /** @brief eMSPI opcodes. */
 enum nrfe_mspi_opcode {
@@ -60,6 +53,26 @@ typedef struct __packed {
 	uint8_t data;
 } nrfe_mspi_flpr_response_t;
 
+typedef struct __packed {
+	uint8_t opcode;
+	struct mspi_cfg cfg;
+} nrfe_mspi_cfg_t;
+
+typedef struct __packed {
+	uint8_t opcode;
+	struct mspi_dev_cfg cfg;
+} nrfe_mspi_dev_cfg_t;
+
+typedef struct __packed {
+	uint8_t opcode;
+	struct mspi_xfer xfer;
+} nrfe_mspi_xfer_t;
+
+typedef struct __packed {
+	uint8_t opcode;
+	struct mspi_xfer_packet packet;
+} nrfe_mspi_xfer_packet_t;
+
 #ifdef __cplusplus
 }
 #endif