From c046b83bc758d0be42880e64b947777b9275e1fc Mon Sep 17 00:00:00 2001 From: Michal Frankiewicz Date: Tue, 7 Jan 2025 14:00:37 +0100 Subject: [PATCH] application: sdp: mspi: Hrt Prepare and transfer data --- applications/sdp/mspi/src/hrt/hrt.c | 271 ++++++++++++++-------------- applications/sdp/mspi/src/hrt/hrt.h | 71 ++++++++ applications/sdp/mspi/src/main.c | 130 ++++++++++++- 3 files changed, 332 insertions(+), 140 deletions(-) diff --git a/applications/sdp/mspi/src/hrt/hrt.c b/applications/sdp/mspi/src/hrt/hrt.c index b4588856e1e9..8865da0e898f 100644 --- a/applications/sdp/mspi/src/hrt/hrt.c +++ b/applications/sdp/mspi/src/hrt/hrt.c @@ -6,183 +6,176 @@ #include "hrt.h" #include #include +#include +#include -#define CLK_FIRST_CYCLE_MULTIPLICATOR (3) +/*TODO: Jira ticket NRFX-6910 move this to nrf_vpr_csr_vio.h */ -void write_single_by_word(volatile struct hrt_ll_xfer xfer_ll_params) +/** @brief Shift control configuration. */ +typedef struct __packed { - uint16_t dir; - uint16_t out; - nrf_vpr_csr_vio_config_t config; - nrf_vpr_csr_vio_mode_out_t out_mode = { - .mode = NRF_VPR_CSR_VIO_SHIFT_OUTB_TOGGLE, - .frame_width = 1, - }; - - NRFX_ASSERT(xfer_ll_params.word_size <= MAX_WORD_SIZE); - /* Configuration step */ - dir = nrf_vpr_csr_vio_dir_get(); - nrf_vpr_csr_vio_dir_set(dir | PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ0_PIN_NUMBER))); + uint8_t shift_count : 6; + uint8_t reserved_1 : 2; + nrf_vpr_csr_vio_shift_t out_mode : 3; + uint8_t reserved_2 : 1; + uint8_t frame_width : 5; + uint8_t reserved_3 : 3; + nrf_vpr_csr_vio_mode_in_t in_mode : 2; + uint16_t reserved_4 : 10; +} nrf_vpr_csr_vio_shift_ctrl_t; + +/*TODO: Jira ticket NRFX-6910 move this to nrf_vpr_csr_vio.h */ +NRF_STATIC_INLINE void nrf_vpr_csr_vio_shift_ctrl_buffered_set(nrf_vpr_csr_vio_shift_ctrl_t const * p_shift_ctrl) +{ + nrf_csr_write(VPRCSR_NORDIC_SHIFTCTRLB, *(uint32_t*)p_shift_ctrl); +} - out = nrf_vpr_csr_vio_out_get(); - nrf_vpr_csr_vio_out_set(out | PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_DQ0_PIN_NUMBER))); - - nrf_vpr_csr_vio_mode_out_set(&out_mode); - nrf_vpr_csr_vio_mode_in_buffered_set(NRF_VPR_CSR_VIO_MODE_IN_CONTINUOUS); - - nrf_vpr_csr_vio_config_get(&config); - config.input_sel = false; - nrf_vpr_csr_vio_config_set(&config); - - /* Fix position of data if word size < MAX_WORD_SIZE, - * so that leading zeros would not be printed instead of data bits. - */ - if (xfer_ll_params.word_size < MAX_WORD_SIZE) { - for (uint8_t i = 0; i < xfer_ll_params.data_len; i++) { - xfer_ll_params.data_to_send[i] = - xfer_ll_params.data_to_send[i] - << (MAX_WORD_SIZE - xfer_ll_params.word_size); - } +static void hrt_tx(struct hrt_xfer_data *xfer_data, uint8_t frame_width, bool *counter_running, uint16_t counter_value) +{ + if(xfer_data->words == 0) + { + return; } - /* Counter settings */ - nrf_vpr_csr_vtim_count_mode_set(0, NRF_VPR_CSR_VTIM_COUNT_RELOAD); - nrf_vpr_csr_vtim_simple_counter_top_set(0, xfer_ll_params.counter_top); + nrf_vpr_csr_vio_shift_ctrl_t shift_ctrl = { + .shift_count = BITS_IN_WORD / frame_width - 1, + .out_mode = NRF_VPR_CSR_VIO_SHIFT_OUTB_TOGGLE, + .frame_width = frame_width, + .in_mode = NRF_VPR_CSR_VIO_MODE_IN_CONTINUOUS, + }; - /* Set number of shifts before OUTB needs to be updated. - * First shift needs to be increased by 1. - */ - nrf_vpr_csr_vio_shift_cnt_out_set(xfer_ll_params.word_size); - nrf_vpr_csr_vio_shift_cnt_out_buffered_set(xfer_ll_params.word_size - 1); - /* Enable CS */ - out = nrf_vpr_csr_vio_out_get(); - out &= ~PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)); - out |= xfer_ll_params.ce_enable_state ? PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)) - : PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)); - nrf_vpr_csr_vio_out_set(out); + nrf_vpr_csr_vio_shift_ctrl_buffered_set(&shift_ctrl); - /* Start counter */ - nrf_vpr_csr_vtim_simple_counter_set(0, CLK_FIRST_CYCLE_MULTIPLICATOR * - xfer_ll_params.counter_top); + for (uint32_t i = 0; i < xfer_data->words; i++) { - /* Send data */ - for (uint8_t i = 0; i < xfer_ll_params.data_len; i++) { - nrf_vpr_csr_vio_out_buffered_reversed_byte_set(xfer_ll_params.data_to_send[i]); - } - - /* Clear all bits, wait until the last word is sent */ - nrf_vpr_csr_vio_out_buffered_set(0); + switch (xfer_data->words - i) { + case 1: /* Last transfer */ + shift_ctrl.shift_count = xfer_data->last_word_clocks - 1; + nrf_vpr_csr_vio_shift_ctrl_buffered_set(&shift_ctrl); - /* Final configuration */ - out_mode.mode = NRF_VPR_CSR_VIO_SHIFT_NONE; - nrf_vpr_csr_vio_mode_out_buffered_set(&out_mode); - nrf_vpr_csr_vio_mode_in_buffered_set(NRF_VPR_CSR_VIO_MODE_IN_CONTINUOUS); + xfer_data->vio_out_set(xfer_data->last_word); + break; + case 2: /* Last but one transfer.*/ + shift_ctrl.shift_count = xfer_data->penultimate_word_clocks - 1; + nrf_vpr_csr_vio_shift_ctrl_buffered_set(&shift_ctrl); + default: /* Intentional fallthrough */ + xfer_data->vio_out_set(((uint32_t *)xfer_data->data)[i]); + } - /* Disable CS */ - if (!xfer_ll_params.ce_hold) { - out = nrf_vpr_csr_vio_out_get(); - out &= ~(PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)) | - PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER))); - out |= xfer_ll_params.ce_enable_state - ? PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)) - : PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)); - nrf_vpr_csr_vio_out_set(out); + if ((i == 0) && (!*counter_running)) { + /* Start counter */ + nrf_vpr_csr_vtim_simple_counter_set(0, counter_value); + *counter_running = true; + } } - - /* Stop counter */ - nrf_vpr_csr_vtim_count_mode_set(0, NRF_VPR_CSR_VTIM_COUNT_STOP); } -void write_quad_by_word(volatile struct hrt_ll_xfer xfer_ll_params) +void hrt_write(struct hrt_xfer *xfer_ll_params) { - uint16_t dir; uint16_t out; - nrf_vpr_csr_vio_config_t config; - nrf_vpr_csr_vio_mode_out_t out_mode = { - .mode = NRF_VPR_CSR_VIO_SHIFT_OUTB_TOGGLE, + bool counter_running = false; + nrf_vpr_csr_vio_shift_ctrl_t shift_ctrl = { + .shift_count = 1, + .out_mode = NRF_VPR_CSR_VIO_SHIFT_NONE, .frame_width = 4, + .in_mode = NRF_VPR_CSR_VIO_MODE_IN_CONTINUOUS, + }; + + nrf_vpr_csr_vio_mode_out_t out_mode = { + .mode = NRF_VPR_CSR_VIO_SHIFT_OUTB_TOGGLE }; - NRFX_ASSERT(xfer_ll_params.word_size % 4 == 0); - NRFX_ASSERT(xfer_ll_params.word_size <= MAX_WORD_SIZE); - /* Configuration step */ - dir = nrf_vpr_csr_vio_dir_get(); + NRFX_ASSERT((xfer_ll_data.last_word_clocks != 1) || (xfer_ll_data.words == 1)) - nrf_vpr_csr_vio_dir_set(dir | PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ0_PIN_NUMBER)) | - PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ1_PIN_NUMBER)) | - PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ2_PIN_NUMBER)) | - PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ3_PIN_NUMBER))); + /* Configure clock and pins */ + nrf_vpr_csr_vio_dir_set(xfer_ll_params->tx_direction_mask); - out = nrf_vpr_csr_vio_out_get(); + for(uint8_t i=0; ixfer_data[i].words == 0) + { + break; + } + + switch(i) { + case HRT_FE_COMMAND: + out_mode.frame_width = xfer_ll_params->io_mode.command; + break; + case HRT_FE_ADDRESS: + out_mode.frame_width = xfer_ll_params->io_mode.address; + break; + case HRT_FE_DATA: + out_mode.frame_width = xfer_ll_params->io_mode.data; + break; } - } - /* Counter settings */ - nrf_vpr_csr_vtim_count_mode_set(0, NRF_VPR_CSR_VTIM_COUNT_RELOAD); - nrf_vpr_csr_vtim_simple_counter_top_set(0, xfer_ll_params.counter_top); + nrf_vpr_csr_vtim_count_mode_set(0, NRF_VPR_CSR_VTIM_COUNT_RELOAD); + nrf_vpr_csr_vtim_simple_counter_top_set(0, xfer_ll_params->counter_value); + nrf_vpr_csr_vio_mode_in_set(NRF_VPR_CSR_VIO_MODE_IN_CONTINUOUS); + + nrf_vpr_csr_vio_mode_out_set(&out_mode); + + switch(xfer_ll_params->xfer_data[i].words) { + case 1: + nrf_vpr_csr_vio_shift_cnt_out_set(xfer_ll_params->xfer_data[i].last_word_clocks); + break; + case 2: + nrf_vpr_csr_vio_shift_cnt_out_set(xfer_ll_params->xfer_data[i].penultimate_word_clocks); + break; + default: + nrf_vpr_csr_vio_shift_cnt_out_set(BITS_IN_WORD / out_mode.frame_width); + } - /* Set number of shifts before OUTB needs to be updated. - * First shift needs to be increased by 1. - */ - nrf_vpr_csr_vio_shift_cnt_out_set(xfer_ll_params.word_size / 4); - nrf_vpr_csr_vio_shift_cnt_out_buffered_set(xfer_ll_params.word_size / 4 - 1); + break; + } /* Enable CS */ out = nrf_vpr_csr_vio_out_get(); - out &= ~PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)); - out |= xfer_ll_params.ce_enable_state ? PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)) - : PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)); + + if (xfer_ll_params->ce_polarity == MSPI_CE_ACTIVE_LOW) { + out = BIT_SET_VALUE(out, xfer_ll_params->ce_vio, VPRCSR_NORDIC_OUT_LOW); + } else { + out = BIT_SET_VALUE(out, xfer_ll_params->ce_vio, VPRCSR_NORDIC_OUT_HIGH); + } nrf_vpr_csr_vio_out_set(out); - /* Start counter */ - nrf_vpr_csr_vtim_simple_counter_set(0, 3 * xfer_ll_params.counter_top); + /* Transfer command */ + hrt_tx(&xfer_ll_params->xfer_data[HRT_FE_COMMAND], xfer_ll_params->io_mode.command, &counter_running, xfer_ll_params->counter_value); + /* Transfer address */ + hrt_tx(&xfer_ll_params->xfer_data[HRT_FE_ADDRESS], xfer_ll_params->io_mode.address, &counter_running, xfer_ll_params->counter_value); + /* Transfer data */ + hrt_tx(&xfer_ll_params->xfer_data[HRT_FE_DATA], xfer_ll_params->io_mode.data, &counter_running, xfer_ll_params->counter_value); - /* Send data */ - for (uint8_t i = 0; i < xfer_ll_params.data_len; i++) { - nrf_vpr_csr_vio_out_buffered_reversed_byte_set(xfer_ll_params.data_to_send[i]); - } + if (xfer_ll_params->eliminate_last_pulse) { - /* Clear all bits, wait until the last word is sent */ - nrf_vpr_csr_vio_out_buffered_set(0); + /* Wait until the last word is sent */ + while(nrf_vpr_csr_vio_shift_cnt_out_get() != 0){} + + /* TODO: Jira ticket NRFX-6798 fix surplus edge problem for higher frequencies. + * This is a partial solution to surplus clock edge problem in modes 1 and 3. + * This solution works only for counter values above 20. + */ + nrf_vpr_csr_vtim_simple_wait_set(0, false, 0); + } /* Final configuration */ - out_mode.mode = NRF_VPR_CSR_VIO_SHIFT_NONE; - nrf_vpr_csr_vio_mode_out_buffered_set(&out_mode); - nrf_vpr_csr_vio_mode_in_buffered_set(NRF_VPR_CSR_VIO_MODE_IN_CONTINUOUS); + nrf_vpr_csr_vio_shift_ctrl_buffered_set(&shift_ctrl); + nrf_vpr_csr_vio_out_buffered_reversed_word_set(0x00); + + /* Stop counter */ + nrf_vpr_csr_vtim_count_mode_set(0, NRF_VPR_CSR_VTIM_COUNT_STOP); /* Disable CS */ - if (!xfer_ll_params.ce_hold) { + if (!xfer_ll_params->ce_hold) { + out = nrf_vpr_csr_vio_out_get(); - out &= ~(PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)) | - PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER))); - out |= xfer_ll_params.ce_enable_state - ? PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)) - : PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)); + + if (xfer_ll_params->ce_polarity == MSPI_CE_ACTIVE_LOW) { + out = BIT_SET_VALUE(out, xfer_ll_params->ce_vio, VPRCSR_NORDIC_OUT_HIGH); + } else { + out = BIT_SET_VALUE(out, xfer_ll_params->ce_vio, VPRCSR_NORDIC_OUT_LOW); + } nrf_vpr_csr_vio_out_set(out); } - - /* Stop counter */ - nrf_vpr_csr_vtim_count_mode_set(0, NRF_VPR_CSR_VTIM_COUNT_STOP); } diff --git a/applications/sdp/mspi/src/hrt/hrt.h b/applications/sdp/mspi/src/hrt/hrt.h index 6f3fa0d0935b..11c7be73620f 100644 --- a/applications/sdp/mspi/src/hrt/hrt.h +++ b/applications/sdp/mspi/src/hrt/hrt.h @@ -23,9 +23,80 @@ #define BITS_IN_WORD 32 #define BITS_IN_BYTE 8 +enum hrt_frame_element { + HRT_FE_COMMAND, + HRT_FE_ADDRESS, + HRT_FE_DATA, + HRT_FE_MAX +}; + +/** @brief Structure for holding bus width of individual xfer parts */ +struct hrt_xfer_io_mode_cfg { + uint8_t command; + uint8_t address; + uint8_t data; +}; + +struct hrt_xfer_data { + /** @brief Buffer for RX/TX data */ + uint8_t *data; + + /** @brief Data length in 4 byte words, + * calculated as CEIL(buffer_length_bits/32). + */ + uint32_t words; + + /** @brief Amount of clock pulses for last word. + * Due to hardware limitation, in case when last word clock pulse count is 1, + * the penultimate word has to share its bits with last word, + * for example: + * buffer length = 36bits, + * io_mode = QUAD, + * last_word_clocks would be:(buffer_length%32)/QUAD = 1 + * so: + * penultimate_word_clocks = 32-BITS_IN_BYTE + * last_word_clocks = (buffer_length%32)/QUAD + BITS_IN_BYTE + * last_word = penultimate_word>>24 | last_word<<8 + */ + uint8_t last_word_clocks; + + /** @brief Amount of clock pulses for penultimate word. + * For more info see last_word_clocks. + */ + uint8_t penultimate_word_clocks; + + /** @brief Value of last word. + * For more info see last_word_clocks. + */ + uint32_t last_word; + + /** @brief Function for writing to buffered out register. */ + void (*vio_out_set)(uint32_t value); +}; + + /** @brief Low level transfer parameters. */ struct hrt_xfer { + /** @brief Data for all transfer parts */ + struct hrt_xfer_data xfer_data[HRT_FE_MAX]; + + /** @brief This xfer parts bus widths */ + struct hrt_xfer_io_mode_cfg io_mode; + + /** @brief Timer value, used for setting clock frequency + */ + uint16_t counter_value; + + /** @brief Index of CE VIO pin */ + uint8_t ce_vio; + + /** @brief If true chip enable pin will be left active after transfer */ + uint8_t ce_hold; + + /** @brief Chip enable pin polarity in enabled state. */ + enum mspi_ce_polarity ce_polarity; + /** @brief When true clock signal makes 1 transition less. * It is required for spi modes 1 and 3 due to hardware issue. */ diff --git a/applications/sdp/mspi/src/main.c b/applications/sdp/mspi/src/main.c index d9e0ce671b4f..f428e29f1a90 100644 --- a/applications/sdp/mspi/src/main.c +++ b/applications/sdp/mspi/src/main.c @@ -30,6 +30,9 @@ #define VEVIF_IRQN(vevif) VEVIF_IRQN_1(vevif) #define VEVIF_IRQN_1(vevif) VPRCLIC_##vevif##_IRQn +/* In OCTAL mode 4 bytes for address + 32 bytes for up to 32 dummy cycles*/ +#define ADDR_AND_CYCLES_MAX_SIZE 36 + static const uint8_t pin_to_vio_map[] = { 4, /* Physical pin 0 */ 0, /* Physical pin 1 */ @@ -44,6 +47,19 @@ static const uint8_t pin_to_vio_map[] = { 10, /* Physical pin 10 */ }; +static const struct hrt_xfer_io_mode_cfg io_modes[] = { + {1, 1, 1}, /* MSPI_IO_MODE_SINGLE */ + {2, 2, 2}, /* MSPI_IO_MODE_DUAL */ + {1, 1, 2}, /* MSPI_IO_MODE_DUAL_1_1_2 */ + {1, 2, 2}, /* MSPI_IO_MODE_DUAL_1_2_2 */ + {4, 4, 4}, /* MSPI_IO_MODE_QUAD */ + {1, 1, 4}, /* MSPI_IO_MODE_QUAD_1_1_4 */ + {1, 4, 4}, /* MSPI_IO_MODE_QUAD_1_4_4 */ + {8, 8, 8}, /* MSPI_IO_MODE_OCTAL */ + {1, 1, 8}, /* MSPI_IO_MODE_OCTAL_1_1_8 */ + {1, 8, 8}, /* MSPI_IO_MODE_OCTAL_1_8_8 */ +}; + static volatile uint8_t ce_vios_count; static volatile uint8_t ce_vios[CE_PINS_MAX]; static volatile uint8_t data_vios_count; @@ -52,10 +68,68 @@ static volatile struct mspi_cfg nrfe_mspi_cfg; static volatile struct mspi_dev_cfg nrfe_mspi_dev_cfg; static volatile struct mspi_xfer nrfe_mspi_xfer; static struct hrt_xfer xfer_params; +static volatile uint8_t address_and_dummy_cycles[ADDR_AND_CYCLES_MAX_SIZE]; static struct ipc_ept ep; static atomic_t ipc_atomic_sem = ATOMIC_INIT(0); +static struct hrt_xfer_data prepare_transfer_data(uint16_t frame_width, uint32_t data_length, + void (*vio_out_set)(uint32_t value), + uint8_t *data) +{ + struct hrt_xfer_data xfer_data; + + if (data_length == 0) { + xfer_data.data = data; + xfer_data.words = 0; + xfer_data.last_word_clocks = 0; + xfer_data.penultimate_word_clocks = 0; + xfer_data.last_word = 0; + xfer_data.vio_out_set = vio_out_set; + + return xfer_data; + } + + /* Due to hardware limitation, it is not possible to send only 1 clock pulse. */ + NRFX_ASSERT(data_length / frame_width >= 1); + NRFX_ASSERT(data_vios_count >= frame_width); + NRFX_ASSERT(data_length % frame_width == 0); + + xfer_data.data = data; + xfer_data.vio_out_set = vio_out_set; + + uint8_t last_word_length = data_length % BITS_IN_WORD; + uint8_t penultimate_word_length = BITS_IN_WORD; + + xfer_data.words = NRFX_CEIL_DIV(data_length, BITS_IN_WORD); + xfer_data.last_word = ((uint32_t *)xfer_data.data)[xfer_data.words - 1]; + + /* Due to hardware limitations it is nt possible to send only 1 clock cycle. + * Therefore when data_length%32==1 last word is sent shorter (24bits) + * and the remaining byte and 1 bit is sent together. + */ + if (last_word_length == 0) { + + last_word_length = BITS_IN_WORD; + xfer_data.last_word = ((uint32_t *)xfer_data.data)[xfer_data.words - 1]; + + } else if ((last_word_length / frame_width == 1) && (xfer_data.words > 1)) { + + penultimate_word_length -= BITS_IN_BYTE; + last_word_length += BITS_IN_BYTE; + + xfer_data.last_word = ((uint32_t *)xfer_data.data)[xfer_data.words - 2] >> + (BITS_IN_WORD - BITS_IN_BYTE) | + ((uint32_t *)xfer_data.data)[xfer_data.words - 1] + << BITS_IN_BYTE; + } + + xfer_data.last_word_clocks = last_word_length / frame_width; + xfer_data.penultimate_word_clocks = penultimate_word_length / frame_width; + + return xfer_data; +} + static void configure_clock(enum mspi_cpp_mode cpp_mode) { nrf_vpr_csr_vio_config_t vio_config = { @@ -98,6 +172,60 @@ static void configure_clock(enum mspi_cpp_mode cpp_mode) nrf_vpr_csr_vio_config_set(&vio_config); } +static void prepare_and_send_data(struct mspi_xfer_packet xfer_packet) +{ + NRFX_ASSERT(nrfe_mspi_dev_cfg.ce_num < ce_vios_count); + NRFX_ASSERT(nrfe_mspi_dev_cfg.io_mode < sizeof(io_modes) / sizeof(io_modes[0])); + + /* TODO: Jira ticket: NRFX-6703 + * Top value of VTIM. This will determine clock frequency + * (SPI_CLOCK ~= CPU_CLOCK / (2 * TOP)). + * Calculate this value based on frequency + */ + xfer_params.counter_value = 4; + xfer_params.ce_vio = ce_vios[nrfe_mspi_dev_cfg.ce_num]; + xfer_params.ce_hold = nrfe_mspi_xfer.hold_ce; + xfer_params.ce_polarity = nrfe_mspi_dev_cfg.ce_polarity; + xfer_params.io_mode = io_modes[nrfe_mspi_dev_cfg.io_mode]; + + xfer_packet.address = + xfer_packet.address + << (BITS_IN_WORD - nrfe_mspi_xfer.addr_length * BITS_IN_BYTE); + xfer_packet.cmd = xfer_packet.cmd + << (BITS_IN_WORD - nrfe_mspi_xfer.cmd_length * BITS_IN_BYTE); + + xfer_params.xfer_data[HRT_FE_COMMAND] = + prepare_transfer_data(io_modes[nrfe_mspi_dev_cfg.io_mode].command, + nrfe_mspi_xfer.cmd_length * BITS_IN_BYTE, + &nrf_vpr_csr_vio_out_buffered_reversed_word_set, + (uint8_t *)&xfer_packet.cmd); + + for(uint8_t i=0; ipacket.dir == MSPI_RX) { /* TODO: Jira ticket: NRFX-6877 Process received data */ } else if (packet->packet.dir == MSPI_TX) { - //TODO prepare_and_send_data(packet->packet); + prepare_and_send_data(packet->packet); } break; }