diff --git a/applications/sdp/mspi/src/hrt/hrt.c b/applications/sdp/mspi/src/hrt/hrt.c index 9c175e8913e2..5e435bfc4d7d 100644 --- a/applications/sdp/mspi/src/hrt/hrt.c +++ b/applications/sdp/mspi/src/hrt/hrt.c @@ -137,7 +137,7 @@ void hrt_write(hrt_xfer_t *hrt_xfer_params) } /* Enable CE */ - if (hrt_xfer_params->ce_polarity == MSPI_CE_ACTIVE_LOW) { + if (hrt_xfer_params->ce_polarity == NRFE_MSPI_POL_ACTIVE_LOW) { nrf_vpr_csr_vio_out_clear_set(BIT(hrt_xfer_params->ce_vio)); } else { nrf_vpr_csr_vio_out_or_set(BIT(hrt_xfer_params->ce_vio)); @@ -171,7 +171,7 @@ void hrt_write(hrt_xfer_t *hrt_xfer_params) /* Disable CE */ if (!hrt_xfer_params->ce_hold) { - if (hrt_xfer_params->ce_polarity == MSPI_CE_ACTIVE_LOW) { + if (hrt_xfer_params->ce_polarity == NRFE_MSPI_POL_ACTIVE_LOW) { nrf_vpr_csr_vio_out_or_set(BIT(hrt_xfer_params->ce_vio)); } else { nrf_vpr_csr_vio_out_clear_set(BIT(hrt_xfer_params->ce_vio)); diff --git a/applications/sdp/mspi/src/hrt/hrt.h b/applications/sdp/mspi/src/hrt/hrt.h index 5bee93dda762..257a10b91813 100644 --- a/applications/sdp/mspi/src/hrt/hrt.h +++ b/applications/sdp/mspi/src/hrt/hrt.h @@ -93,7 +93,7 @@ typedef struct { bool ce_hold; /** @brief Chip enable pin polarity in enabled state. */ - enum mspi_ce_polarity ce_polarity; + nrfe_mspi_polarity_t ce_polarity; /** @brief When true clock signal makes 1 transition less. * It is required for spi modes 1 and 3 due to hardware issue. diff --git a/applications/sdp/mspi/src/hrt/hrt.s b/applications/sdp/mspi/src/hrt/hrt.s index 6cfc1b95db80..528fff28b580 100644 --- a/applications/sdp/mspi/src/hrt/hrt.s +++ b/applications/sdp/mspi/src/hrt/hrt.s @@ -162,13 +162,13 @@ hrt_write: #APP csrw 3022, a5 #NO_APP - lbu a4,66(s0) - li a5,1 - sll a5,a5,a4 - lbu a4,68(s0) + lbu a5,66(s0) + li a4,1 + lbu a3,68(s0) + sll a5,a4,a5 slli a5,a5,16 srli a5,a5,16 - bne a4,zero,.L21 + bne a3,a4,.L21 #APP csrc 3008, a5 #NO_APP @@ -209,13 +209,13 @@ hrt_write: #NO_APP lbu a5,67(s0) bne a5,zero,.L13 - lbu a4,66(s0) - li a5,1 - sll a5,a5,a4 - lbu a4,68(s0) + lbu a5,66(s0) + li a4,1 + lbu a3,68(s0) + sll a5,a4,a5 slli a5,a5,16 srli a5,a5,16 - bne a4,zero,.L26 + bne a3,a4,.L26 #APP csrs 3008, a5 #NO_APP diff --git a/applications/sdp/mspi/src/main.c b/applications/sdp/mspi/src/main.c index 22a83417c6e7..44194ba8c79a 100644 --- a/applications/sdp/mspi/src/main.c +++ b/applications/sdp/mspi/src/main.c @@ -19,10 +19,6 @@ #include -#define CE_PINS_MAX 9 -#define DATA_PINS_MAX 8 -#define VIO_COUNT 11 - #define SUPPORTED_IO_MODES_COUNT 7 #define HRT_IRQ_PRIORITY 2 @@ -34,7 +30,7 @@ /* In OCTAL mode 4 bytes for address + 32 bytes for up to 32 dummy cycles*/ #define ADDR_AND_CYCLES_MAX_SIZE 36 -static const uint8_t pin_to_vio_map[VIO_COUNT] = { +static const uint8_t pin_to_vio_map[NRFE_MSPI_VIO_COUNT] = { 4, /* Physical pin 0 */ 0, /* Physical pin 1 */ 1, /* Physical pin 2 */ @@ -59,18 +55,27 @@ static const hrt_xfer_bus_widths_t io_modes[SUPPORTED_IO_MODES_COUNT] = { }; static volatile uint8_t ce_vios_count; -static volatile uint8_t ce_vios[CE_PINS_MAX]; +static volatile uint8_t ce_vios[NRFE_MSPI_CE_PINS_MAX]; static volatile uint8_t data_vios_count; -static volatile uint8_t data_vios[DATA_PINS_MAX]; -static volatile struct mspi_cfg nrfe_mspi_cfg; -static volatile struct mspi_dev_cfg nrfe_mspi_dev_cfg; -static volatile struct mspi_xfer nrfe_mspi_xfer; +static volatile uint8_t data_vios[NRFE_MSPI_DATA_PINS_MAX]; +static volatile nrfe_mspi_xfer_config_t nrfe_mspi_xfer_config; + static volatile hrt_xfer_t xfer_params; static volatile uint8_t address_and_dummy_cycles[ADDR_AND_CYCLES_MAX_SIZE]; static struct ipc_ept ep; static atomic_t ipc_atomic_sem = ATOMIC_INIT(0); +NRF_STATIC_INLINE void nrf_vpr_csr_vio_out_or_set(uint16_t value) +{ + nrf_csr_set_bits(VPRCSR_NORDIC_OUT, value); +} + +NRF_STATIC_INLINE void nrf_vpr_csr_vio_out_clear_set(uint16_t value) +{ + nrf_csr_clear_bits(VPRCSR_NORDIC_OUT, value); +} + static void adjust_tail(volatile hrt_xfer_data_t *xfer_data, uint16_t frame_width, uint32_t data_length) { if (data_length == 0) { @@ -150,36 +155,37 @@ static void configure_clock(enum mspi_cpp_mode cpp_mode) nrf_vpr_csr_vio_config_set(&vio_config); } -static void xfer_execute(struct mspi_xfer_packet xfer_packet) +static void xfer_execute(nrfe_mspi_xfer_packet_t *xfer_packet, uint8_t *buffer) { - NRFX_ASSERT(nrfe_mspi_dev_cfg.ce_num < ce_vios_count); - NRFX_ASSERT(nrfe_mspi_dev_cfg.io_mode < SUPPORTED_IO_MODES_COUNT); + NRFX_ASSERT(nrfe_mspi_xfer_config.ce_num < ce_vios_count); + NRFX_ASSERT(nrfe_mspi_xfer_config.io_mode < SUPPORTED_IO_MODES_COUNT); + NRFX_ASSERT(nrfe_mspi_xfer_config.ce_polarities[nrfe_mspi_xfer_config.ce_num] != NRFE_MSPI_POL_UNDEFINED); xfer_params.counter_value = 4; - xfer_params.ce_vio = ce_vios[nrfe_mspi_dev_cfg.ce_num]; - xfer_params.ce_hold = nrfe_mspi_xfer.hold_ce; - xfer_params.ce_polarity = nrfe_mspi_dev_cfg.ce_polarity; - xfer_params.bus_widths = io_modes[nrfe_mspi_dev_cfg.io_mode]; - + xfer_params.ce_vio = ce_vios[nrfe_mspi_xfer_config.ce_num]; + xfer_params.ce_hold = nrfe_mspi_xfer_config.hold_ce; + xfer_params.ce_polarity = nrfe_mspi_xfer_config.ce_polarities[nrfe_mspi_xfer_config.ce_num]; + xfer_params.bus_widths = io_modes[nrfe_mspi_xfer_config.io_mode]; + /* Fix position of command if command length is < BITS_IN_WORD, * so that leading zeros would not be printed instead of data bits. */ - xfer_packet.cmd = xfer_packet.cmd - << (BITS_IN_WORD - nrfe_mspi_xfer.cmd_length * BITS_IN_BYTE); + xfer_packet->command = xfer_packet->command + << (BITS_IN_WORD - nrfe_mspi_xfer_config.command_length * BITS_IN_BYTE); xfer_params.xfer_data[HRT_FE_COMMAND].vio_out_set = &nrf_vpr_csr_vio_out_buffered_reversed_word_set; - xfer_params.xfer_data[HRT_FE_COMMAND].data = (uint8_t *)&xfer_packet.cmd; + xfer_params.xfer_data[HRT_FE_COMMAND].data = (uint8_t *)&xfer_packet->command; xfer_params.xfer_data[HRT_FE_COMMAND].word_count = 0; adjust_tail(&xfer_params.xfer_data[HRT_FE_COMMAND], xfer_params.bus_widths.command, - nrfe_mspi_xfer.cmd_length * BITS_IN_BYTE); + nrfe_mspi_xfer_config.command_length * BITS_IN_BYTE); - for (uint8_t i = 0; i < nrfe_mspi_xfer.addr_length; i++) { - address_and_dummy_cycles[i] = *(((uint8_t *)&xfer_packet.address)+nrfe_mspi_xfer.addr_length-i-1); + for (uint8_t i = 0; i < nrfe_mspi_xfer_config.address_length; i++) { + address_and_dummy_cycles[i] = *(((uint8_t *)&xfer_packet->address)+nrfe_mspi_xfer_config.address_length-i-1); } - for (uint8_t i = nrfe_mspi_xfer.addr_length; i < ADDR_AND_CYCLES_MAX_SIZE; i++) { + for (uint8_t i = nrfe_mspi_xfer_config.address_length; i < ADDR_AND_CYCLES_MAX_SIZE; i++) { address_and_dummy_cycles[i] = 0; } @@ -189,15 +195,15 @@ static void xfer_execute(struct mspi_xfer_packet xfer_packet) adjust_tail(&xfer_params.xfer_data[HRT_FE_ADDRESS], xfer_params.bus_widths.address, - nrfe_mspi_xfer.addr_length * BITS_IN_BYTE + - nrfe_mspi_xfer.tx_dummy * xfer_params.bus_widths.address); + nrfe_mspi_xfer_config.address_length * BITS_IN_BYTE + + nrfe_mspi_xfer_config.tx_dummy * xfer_params.bus_widths.address); xfer_params.xfer_data[HRT_FE_DATA].vio_out_set = &nrf_vpr_csr_vio_out_buffered_reversed_byte_set; - xfer_params.xfer_data[HRT_FE_DATA].data = xfer_packet.data_buf; + xfer_params.xfer_data[HRT_FE_DATA].data = buffer; xfer_params.xfer_data[HRT_FE_DATA].word_count = 0; adjust_tail(&xfer_params.xfer_data[HRT_FE_DATA], - xfer_params.bus_widths.data, xfer_packet.num_bytes * BITS_IN_BYTE); + xfer_params.bus_widths.data, xfer_packet->num_bytes * BITS_IN_BYTE); nrf_vpr_clic_int_pending_set(NRF_VPRCLIC, VEVIF_IRQN(HRT_VEVIF_IDX_WRITE)); } @@ -215,7 +221,7 @@ static void config_pins(nrfe_mspi_pinctrl_soc_pin_t *pins_cfg) uint8_t pin_number = NRF_PIN_NUMBER_TO_PIN(psel); - NRFX_ASSERT(pin_number < VIO_COUNT) + NRFX_ASSERT(pin_number < NRFE_MSPI_VIO_COUNT) if ((fun >= NRF_FUN_SDP_MSPI_CS0) && (fun <= NRF_FUN_SDP_MSPI_CS4)) { @@ -244,7 +250,24 @@ static void config_pins(nrfe_mspi_pinctrl_soc_pin_t *pins_cfg) } } nrf_vpr_csr_vio_dir_set(xfer_params.tx_direction_mask); - nrf_vpr_csr_vio_out_set(VPRCSR_NORDIC_OUT_HIGH << pin_to_vio_map[NRFE_MSPI_CS0_PIN_NUMBER]); +} + +static void set_ce_pins() +{ + for(uint8_t i=0; (icfg; - break; - } - case NRFE_MSPI_CONFIG_DEV: { - nrfe_mspi_dev_cfg_t *cfg = (nrfe_mspi_dev_cfg_t *)data; - nrfe_mspi_dev_cfg = cfg->cfg; - configure_clock(nrfe_mspi_dev_cfg.cpp); - break; - } case NRFE_MSPI_CONFIG_XFER: { - nrfe_mspi_xfer_t *xfer = (nrfe_mspi_xfer_t *)data; - nrfe_mspi_xfer = xfer->xfer; + nrfe_mspi_xfer_config = *(nrfe_mspi_xfer_config_t *)data; + configure_clock(nrfe_mspi_xfer_config.cpp); + set_ce_pins(); break; } case NRFE_MSPI_TX: - case NRFE_MSPI_TXRX: { + nrfe_mspi_xfer_packet_t *packet = (nrfe_mspi_xfer_packet_t*)data; + xfer_execute(packet, (uint8_t*)((uint8_t*)data+sizeof(nrfe_mspi_xfer_packet_t))); + break; + case NRFE_MSPI_RX: { nrfe_mspi_xfer_packet_t *packet = (nrfe_mspi_xfer_packet_t *)data; - - if (packet->packet.dir == MSPI_RX) { - /* TODO: Process received data */ - } else if (packet->packet.dir == MSPI_TX) { - xfer_execute(packet->packet); - } break; } default: diff --git a/drivers/mspi/mspi_nrfe.c b/drivers/mspi/mspi_nrfe.c index bbf82f58ed68..a8fc472a59ec 100644 --- a/drivers/mspi/mspi_nrfe.c +++ b/drivers/mspi/mspi_nrfe.c @@ -83,6 +83,9 @@ static const struct mspi_nrfe_config dev_config = { .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0), }; +static nrfe_mspi_pinctrl_soc_pin_t mspi_pin_config; +static nrfe_mspi_xfer_config_t mspi_xfer_config; + static void ipc_recv_clbk(const void *data, size_t len); static void ep_bound(void *priv) @@ -131,22 +134,6 @@ static void ipc_recv_clbk(const void *data, size_t len) k_sem_give(&ipc_sem_cfg); #else atomic_set_bit(&ipc_atomic_sem, NRFE_MSPI_CONFIG_PINS); -#endif - break; - } - case NRFE_MSPI_CONFIG_CTRL: { -#if defined(CONFIG_MULTITHREADING) - k_sem_give(&ipc_sem_cfg); -#else - atomic_set_bit(&ipc_atomic_sem, NRFE_MSPI_CONFIG_CTRL); -#endif - break; - } - case NRFE_MSPI_CONFIG_DEV: { -#if defined(CONFIG_MULTITHREADING) - k_sem_give(&ipc_sem_cfg); -#else - atomic_set_bit(&ipc_atomic_sem, NRFE_MSPI_CONFIG_DEV); #endif break; } @@ -166,7 +153,7 @@ static void ipc_recv_clbk(const void *data, size_t len) #endif break; } - case NRFE_MSPI_TXRX: { + case NRFE_MSPI_RX: { if (len) { ipc_received = len - 1; ipc_receive_buffer = (uint8_t *)&response->data; @@ -174,7 +161,7 @@ static void ipc_recv_clbk(const void *data, size_t len) #if defined(CONFIG_MULTITHREADING) k_sem_give(&ipc_sem_xfer); #else - atomic_set_bit(&ipc_atomic_sem, NRFE_MSPI_TXRX); + atomic_set_bit(&ipc_atomic_sem, NRFE_MSPI_RX); #endif break; } @@ -197,7 +184,7 @@ static void ipc_recv_clbk(const void *data, size_t len) * @return 0 on success, -ENOMEM if there is no space in the buffer, * -ETIMEDOUT if the transfer timed out. */ -static int mspi_ipc_data_send(enum nrfe_mspi_opcode opcode, const void *data, size_t len) +static int mspi_ipc_data_send(nrfe_mspi_opcode_t opcode, const void *data, size_t len) { int rc; @@ -234,21 +221,19 @@ static int mspi_ipc_data_send(enum nrfe_mspi_opcode opcode, const void *data, si * * @return 0 on success, -ETIMEDOUT if the operation timed out. */ -static int nrfe_mspi_wait_for_response(enum nrfe_mspi_opcode opcode, uint32_t timeout) +static int nrfe_mspi_wait_for_response(nrfe_mspi_opcode_t opcode, uint32_t timeout) { #if defined(CONFIG_MULTITHREADING) int ret = 0; switch (opcode) { case NRFE_MSPI_CONFIG_PINS: - case NRFE_MSPI_CONFIG_CTRL: - case NRFE_MSPI_CONFIG_DEV: case NRFE_MSPI_CONFIG_XFER: { ret = k_sem_take(&ipc_sem_cfg, K_MSEC(timeout)); break; } case NRFE_MSPI_TX: - case NRFE_MSPI_TXRX: + case NRFE_MSPI_RX: ret = k_sem_take(&ipc_sem_xfer, K_MSEC(timeout)); break; default: @@ -281,28 +266,6 @@ static int nrfe_mspi_wait_for_response(enum nrfe_mspi_opcode opcode, uint32_t ti return 0; } -/** - * @brief Send a data struct to the FLPR core using the IPC service. - * - * The function sends a data structure to the FLPR core, - * inserting a byte at the beginning responsible for the opcode. - * - * @param opcode The NRFE MSPI opcode. - * @param data The data to send. - * @param len The length of the data to send. - * - * @return 0 on success, negative errno code on failure. - */ -static int send_with_opcode(enum nrfe_mspi_opcode opcode, const void *data, size_t len) -{ - uint8_t buffer[len + 1]; - - buffer[0] = (uint8_t)opcode; - memcpy(&buffer[1], data, len); - - return mspi_ipc_data_send(opcode, buffer, sizeof(buffer)); -} - /** * @brief Send a configuration struct to the FLPR core using the IPC service. * @@ -312,11 +275,11 @@ static int send_with_opcode(enum nrfe_mspi_opcode opcode, const void *data, size * * @return 0 on success, negative errno code on failure. */ -static int send_config(enum nrfe_mspi_opcode opcode, const void *config, size_t len) +static int send_config(nrfe_mspi_opcode_t opcode, const void *config, size_t len) { int rc; + rc = mspi_ipc_data_send(opcode, config, len); - rc = send_with_opcode(opcode, config, len); if (rc < 0) { LOG_ERR("%d: Configuration send failed: %d", __LINE__, rc); return rc; @@ -343,28 +306,25 @@ static int send_config(enum nrfe_mspi_opcode opcode, const void *config, size_t */ static int api_config(const struct mspi_dt_spec *spec) { - int ret; - const struct mspi_cfg *config = &spec->config; const struct mspi_nrfe_config *drv_cfg = spec->bus->config; - if (config->op_mode != MSPI_OP_MODE_CONTROLLER) { + if (spec->config.op_mode != MSPI_OP_MODE_CONTROLLER) { LOG_ERR("%u, only support MSPI controller mode.", __LINE__); return -ENOTSUP; } - if (config->dqs_support) { + if (spec->config.dqs_support) { LOG_ERR("%u, only support non-DQS mode.", __LINE__); return -ENOTSUP; } - if (config->max_freq > drv_cfg->mspicfg.max_freq) { + if (spec->config.max_freq > drv_cfg->mspicfg.max_freq) { LOG_ERR("%u, max_freq too large.", __LINE__); return -ENOTSUP; } /* Create pinout configuration */ uint8_t state_id; - nrfe_mspi_pinctrl_soc_pin_t pins_cfg; for (state_id = 0; state_id < drv_cfg->pcfg->state_cnt; state_id++) { if (drv_cfg->pcfg->states[state_id].id == PINCTRL_STATE_DEFAULT) { @@ -383,17 +343,15 @@ static int api_config(const struct mspi_dt_spec *spec) } for (uint8_t i = 0; i < drv_cfg->pcfg->states[state_id].pin_cnt; i++) { - pins_cfg.pin[i] = drv_cfg->pcfg->states[state_id].pins[i]; + mspi_pin_config.pin[i] = drv_cfg->pcfg->states[state_id].pins[i]; } + mspi_pin_config.opcode = NRFE_MSPI_CONFIG_PINS; - /* Send pinout configuration to FLPR */ - ret = send_config(NRFE_MSPI_CONFIG_PINS, (const void *)pins_cfg.pin, sizeof(pins_cfg)); - if (ret < 0) { - return ret; - } + mspi_xfer_config.duplex = spec->config.duplex; + memset(mspi_xfer_config.ce_polarities, NRFE_MSPI_POL_UNDEFINED, NRFE_MSPI_CE_PINS_MAX*sizeof(nrfe_mspi_polarity_t)); - /* Send controller configuration to FLPR */ - return send_config(NRFE_MSPI_CONFIG_CTRL, (const void *)config, sizeof(struct mspi_cfg)); + /* Send pinout configuration to FLPR */ + return send_config(NRFE_MSPI_CONFIG_PINS, (const void *)&mspi_pin_config, sizeof(nrfe_mspi_pinctrl_soc_pin_t)); } static int check_io_mode(enum mspi_io_mode io_mode) @@ -472,10 +430,17 @@ static int api_dev_config(const struct device *dev, const struct mspi_dev_id *de } } + mspi_xfer_config.ce_polarities[cfg->ce_num] = (cfg->ce_polarity == MSPI_CE_ACTIVE_LOW) ? NRFE_MSPI_POL_ACTIVE_LOW : NRFE_MSPI_POL_ACTIVE_HIGH; + mspi_xfer_config.ce_num = cfg->ce_num; + mspi_xfer_config.io_mode = cfg->io_mode; + mspi_xfer_config.cpp = cfg->cpp; + mspi_xfer_config.endian = cfg->endian; + mspi_xfer_config.freq = cfg->freq; + memcpy((void *)&drv_data->dev_cfg, (void *)cfg, sizeof(drv_data->dev_cfg)); drv_data->dev_id = *dev_id; - return send_config(NRFE_MSPI_CONFIG_DEV, (void *)cfg, sizeof(struct mspi_dev_cfg)); + return 0; } static int api_get_channel_status(const struct device *dev, uint8_t ch) @@ -498,21 +463,24 @@ static int api_get_channel_status(const struct device *dev, uint8_t ch) static int xfer_packet(struct mspi_xfer_packet *packet, uint32_t timeout) { int rc; - uint32_t struct_size = sizeof(struct mspi_xfer_packet); - uint32_t len = struct_size + packet->num_bytes + 1; - uint8_t buffer[len]; - enum nrfe_mspi_opcode opcode = (packet->dir == MSPI_RX) ? NRFE_MSPI_TXRX : NRFE_MSPI_TX; + nrfe_mspi_xfer_packet_t xfer_packet = { + .opcode = (packet->dir == MSPI_RX) ? NRFE_MSPI_RX : NRFE_MSPI_TX, + .command = packet->cmd, + .address = packet->address, + .num_bytes = packet->num_bytes, + }; - buffer[0] = (uint8_t)opcode; - memcpy((void *)&buffer[1], (void *)packet, struct_size); - memcpy((void *)(&buffer[1] + struct_size), (void *)packet->data_buf, packet->num_bytes); + uint32_t len = sizeof(nrfe_mspi_xfer_packet_t)+packet->num_bytes; + uint8_t buffer[len]; + memcpy((void *)buffer, (void *)&xfer_packet, sizeof(nrfe_mspi_xfer_packet_t)); + memcpy((void *)(buffer + sizeof(nrfe_mspi_xfer_packet_t)), (void *)packet->data_buf, packet->num_bytes); - rc = mspi_ipc_data_send(opcode, buffer, len); + rc = mspi_ipc_data_send(xfer_packet.opcode, buffer, len); if (rc < 0) { LOG_ERR("%d: Packet transfer error: %d", __LINE__, rc); } - rc = nrfe_mspi_wait_for_response(opcode, timeout); + rc = nrfe_mspi_wait_for_response(xfer_packet.opcode, timeout); if (rc < 0) { LOG_ERR("%d: FLPR Xfer response timeout: %d", __LINE__, rc); return rc; @@ -591,9 +559,16 @@ static int api_transceive(const struct device *dev, const struct mspi_dev_id *de return -EFAULT; } + mspi_xfer_config.opcode = NRFE_MSPI_CONFIG_XFER; + mspi_xfer_config.command_length = req->cmd_length; + mspi_xfer_config.address_length = req->addr_length; + mspi_xfer_config.hold_ce = req->hold_ce; + mspi_xfer_config.tx_dummy = req->tx_dummy; + mspi_xfer_config.rx_dummy = req->rx_dummy; + drv_data->xfer = *req; - rc = send_config(NRFE_MSPI_CONFIG_XFER, (void *)&drv_data->xfer, sizeof(struct mspi_xfer)); + rc = send_config(NRFE_MSPI_CONFIG_XFER, (void *)&mspi_xfer_config, sizeof(nrfe_mspi_xfer_config_t)); if (rc < 0) { LOG_ERR("Send xfer config error: %d", rc); return rc; diff --git a/include/drivers/mspi/nrfe_mspi.h b/include/drivers/mspi/nrfe_mspi.h index f404a42e1d8a..35a62f561cf0 100644 --- a/include/drivers/mspi/nrfe_mspi.h +++ b/include/drivers/mspi/nrfe_mspi.h @@ -16,6 +16,10 @@ extern "C" { #ifdef CONFIG_SOC_NRF54L15 +#define NRFE_MSPI_CE_PINS_MAX 5 +#define NRFE_MSPI_DATA_PINS_MAX 8 +#define NRFE_MSPI_VIO_COUNT 11 + #define NRFE_MSPI_PORT_NUMBER 2 /* Physical port number */ #define NRFE_MSPI_SCK_PIN_NUMBER 1 /* Physical pins number on port 2 */ #define NRFE_MSPI_DQ0_PIN_NUMBER 2 @@ -30,48 +34,55 @@ extern "C" { #endif /** @brief eMSPI opcodes. */ -enum nrfe_mspi_opcode { +typedef enum { NRFE_MSPI_EP_BOUNDED = 0, - NRFE_MSPI_CONFIG_PINS, - NRFE_MSPI_CONFIG_CTRL, /* struct mspi_cfg */ - NRFE_MSPI_CONFIG_DEV, /* struct mspi_dev_cfg */ - NRFE_MSPI_CONFIG_XFER, /* struct mspi_xfer */ - NRFE_MSPI_TX, - NRFE_MSPI_TXRX, + NRFE_MSPI_CONFIG_PINS, /*nrfe_mspi_pinctrl_soc_pin_t*/ + NRFE_MSPI_CONFIG_XFER, /*nrfe_mspi_xfer_config_t*/ + NRFE_MSPI_TX, /*nrfe_mspi_xfer_packet_t + data buffer at the end*/ + NRFE_MSPI_RX, NRFE_MSPI_WRONG_OPCODE, NRFE_MSPI_ALL_OPCODES = NRFE_MSPI_WRONG_OPCODE, -}; +} nrfe_mspi_opcode_t; -typedef struct __packed { - uint8_t opcode; /* nrfe_mspi_opcode */ +typedef enum { + NRFE_MSPI_POL_UNDEFINED = 0, + NRFE_MSPI_POL_ACTIVE_LOW, + NRFE_MSPI_POL_ACTIVE_HIGH, +} nrfe_mspi_polarity_t; + +typedef struct { + nrfe_mspi_opcode_t opcode; /* nrfe_mspi_opcode */ pinctrl_soc_pin_t pin[NRFE_MSPI_PINS_MAX]; } nrfe_mspi_pinctrl_soc_pin_t; +typedef struct { + nrfe_mspi_opcode_t opcode; /* nrfe_mspi_opcode */ + uint8_t command_length; + uint8_t address_length; + uint8_t ce_num; //vio number + enum mspi_duplex duplex; + enum mspi_io_mode io_mode; + enum mspi_cpp_mode cpp; + enum mspi_endian endian; + bool hold_ce; + nrfe_mspi_polarity_t ce_polarities[NRFE_MSPI_CE_PINS_MAX]; + uint16_t tx_dummy; + uint16_t rx_dummy; + uint32_t freq; +} nrfe_mspi_xfer_config_t; + +typedef struct { + nrfe_mspi_opcode_t opcode; /* nrfe_mspi_opcode */ + uint32_t command; + uint32_t address; + uint32_t num_bytes; +} nrfe_mspi_xfer_packet_t; + typedef struct __packed { uint8_t opcode; /* nrfe_mspi_opcode */ uint8_t data; } nrfe_mspi_flpr_response_t; -typedef struct __packed { - uint8_t opcode; - struct mspi_cfg cfg; -} nrfe_mspi_cfg_t; - -typedef struct __packed { - uint8_t opcode; - struct mspi_dev_cfg cfg; -} nrfe_mspi_dev_cfg_t; - -typedef struct __packed { - uint8_t opcode; - struct mspi_xfer xfer; -} nrfe_mspi_xfer_t; - -typedef struct __packed { - uint8_t opcode; - struct mspi_xfer_packet packet; -} nrfe_mspi_xfer_packet_t; - #ifdef __cplusplus } #endif