zed68k_def_val.txt

BOARD_PART:(string) DEFAULT_VALUE ()==CURRENT_VALUE (digilentinc.com:arty-a7-100:part0:1.0)
COMPXLIB.ACTIVEHDL_COMPILED_LIBRARY_DIR:(string) DEFAULT_VALUE (D:/code/zed-68k/zed68k.cache/compile_simlib/activehdl)==CURRENT_VALUE (D:/code/zed-68k/zed68k.cache/compile_simlib/activehdl)
COMPXLIB.FUNCSIM:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
COMPXLIB.IES_COMPILED_LIBRARY_DIR:(string) DEFAULT_VALUE (D:/code/zed-68k/zed68k.cache/compile_simlib/ies)==CURRENT_VALUE (D:/code/zed-68k/zed68k.cache/compile_simlib/ies)
COMPXLIB.MODELSIM_COMPILED_LIBRARY_DIR:(string) DEFAULT_VALUE (D:/code/zed-68k/zed68k.cache/compile_simlib/modelsim)==CURRENT_VALUE (D:/code/zed-68k/zed68k.cache/compile_simlib/modelsim)
COMPXLIB.OVERWRITE_LIBS:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
COMPXLIB.QUESTA_COMPILED_LIBRARY_DIR:(string) DEFAULT_VALUE (D:/code/zed-68k/zed68k.cache/compile_simlib/questa)==CURRENT_VALUE (D:/code/zed-68k/zed68k.cache/compile_simlib/questa)
COMPXLIB.RIVIERA_COMPILED_LIBRARY_DIR:(string) DEFAULT_VALUE (D:/code/zed-68k/zed68k.cache/compile_simlib/riviera)==CURRENT_VALUE (D:/code/zed-68k/zed68k.cache/compile_simlib/riviera)
COMPXLIB.TIMESIM:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
COMPXLIB.VCS_COMPILED_LIBRARY_DIR:(string) DEFAULT_VALUE (D:/code/zed-68k/zed68k.cache/compile_simlib/vcs)==CURRENT_VALUE (D:/code/zed-68k/zed68k.cache/compile_simlib/vcs)
COMPXLIB.XSIM_COMPILED_LIBRARY_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
CORECONTAINER.ENABLE:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
DEFAULT_LIB:(string) DEFAULT_VALUE ()==CURRENT_VALUE (xil_defaultlib)
ENABLE_OPTIONAL_RUNS_STA:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
ENABLE_VHDL_2008:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (1)
GENERATE_IP_UPGRADE_LOG:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
IP_CACHE_PERMISSIONS:(string*) DEFAULT_VALUE ()==CURRENT_VALUE (read write)
IP_INTERFACE_INFERENCE_PRIORITY:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
IP_OUTPUT_REPO:(string) DEFAULT_VALUE ()==CURRENT_VALUE (D:/code/zed-68k/zed68k.cache/ip)
IS_READONLY:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
LEGACY_IP_REPO_PATHS:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
MEM.ENABLE_MEMORY_MAP_GENERATION:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (1)
PLATFORM.BOARD_ID:(string) DEFAULT_VALUE ()==CURRENT_VALUE (Nexys4DDR)
PLATFORM.DEFAULT_OUTPUT_TYPE:(enum) DEFAULT_VALUE (undefined)==CURRENT_VALUE (sd_card)
PLATFORM.DESIGN_INTENT.DATACENTER:(enum) DEFAULT_VALUE (undefined)==CURRENT_VALUE (false)
PLATFORM.DESIGN_INTENT.EMBEDDED:(enum) DEFAULT_VALUE (undefined)==CURRENT_VALUE (true)
PLATFORM.DESIGN_INTENT.EXTERNAL_HOST:(enum) DEFAULT_VALUE (undefined)==CURRENT_VALUE (false)
PLATFORM.DESIGN_INTENT.SERVER_MANAGED:(enum) DEFAULT_VALUE (undefined)==CURRENT_VALUE (false)
PLATFORM.NAME:(string) DEFAULT_VALUE ()==CURRENT_VALUE (M68)
PLATFORM.ROM.DEBUG_TYPE:(int) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
PLATFORM.ROM.PROM_TYPE:(int) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
PLATFORM.SLRCONSTRAINTMODE:(int) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
PLATFORM.VERSION:(string) DEFAULT_VALUE (0.0)==CURRENT_VALUE (1.0)
PROJECT_TYPE:(enum) DEFAULT_VALUE (Default)==CURRENT_VALUE (Default)
PR_FLOW:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
SIM.CENTRAL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE (D:/code/zed-68k/zed68k.ip_user_files)
SIM.IP.AUTO_EXPORT_SCRIPTS:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (1)
SIM.USE_IP_COMPILED_LIBS:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
SIMULATOR.ACTIVEHDL_INSTALL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
SIMULATOR.IES_INSTALL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
SIMULATOR.MODELSIM_INSTALL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
SIMULATOR.QUESTA_INSTALL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
SIMULATOR.RIVIERA_INSTALL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
SIMULATOR.VCS_INSTALL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
SIMULATOR.XCELIUM_INSTALL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
SIMULATOR_LANGUAGE:(enum) DEFAULT_VALUE (Verilog)==CURRENT_VALUE (Mixed)
SOURCE_MGMT_MODE:(enum) DEFAULT_VALUE (All)==CURRENT_VALUE (All)
TARGET_LANGUAGE:(enum) DEFAULT_VALUE (Verilog)==CURRENT_VALUE (Verilog)
TARGET_SIMULATOR:(string) DEFAULT_VALUE (XSim)==CURRENT_VALUE (XSim)
TOOL_FLOW:(enum) DEFAULT_VALUE (Vivado)==CURRENT_VALUE (Vivado)
WEBTALK.ACTIVEHDL_EXPORT_SIM:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (317)
WEBTALK.IES_EXPORT_SIM:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (317)
WEBTALK.MODELSIM_EXPORT_SIM:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (317)
WEBTALK.QUESTA_EXPORT_SIM:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (317)
WEBTALK.RIVIERA_EXPORT_SIM:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (317)
WEBTALK.VCS_EXPORT_SIM:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (317)
WEBTALK.XSIM_EXPORT_SIM:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (318)
WEBTALK.XSIM_LAUNCH_SIM:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (1466)
XPM_LIBRARIES:(string*) DEFAULT_VALUE ()==CURRENT_VALUE (XPM_CDC XPM_FIFO XPM_MEMORY)
XSIM.ARRAY_DISPLAY_LIMIT:(string) DEFAULT_VALUE (1024)==CURRENT_VALUE (1024)
XSIM.RADIX:(enum) DEFAULT_VALUE (hex)==CURRENT_VALUE (hex)
XSIM.TIME_UNIT:(enum) DEFAULT_VALUE (ns)==CURRENT_VALUE (ns)
XSIM.TRACE_LIMIT:(string) DEFAULT_VALUE (65536)==CURRENT_VALUE (65536)
Uart_RX.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL)
Uart_RX.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
Uart_RX.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
Uart_RX.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
Uart_RX.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
Uart_RX.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
Uart_RX.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
Uart_RX.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
UART_CTL.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL)
UART_CTL.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
UART_CTL.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
UART_CTL.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
UART_CTL.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
UART_CTL.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
UART_CTL.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
UART_CTL.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
UART_TX.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL)
UART_TX.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
UART_TX.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
UART_TX.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
UART_TX.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
UART_TX.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
UART_TX.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
UART_TX.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
FC1002_MII.edn=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (EDIF)
FC1002_MII.edn=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
FC1002_MII.edn=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
FC1002_MII.edn=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
FC1002_MII.edn=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
FC1002_MII.edn=SCOPED_TO_CELLS (string*) :DEFAULT_VALUE ()==CURRENT_VALUE ()
FC1002_MII.edn=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation)==CURRENT_VALUE (synthesis implementation)
FC1002_MII.edn=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
FC1002_MII.edn=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
axis_rx_fifo.xci=GENERATE_FILES_FOR_REFERENCE (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (0)
axis_rx_fifo.xci=GENERATE_SYNTH_CHECKPOINT (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
axis_rx_fifo.xci=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
axis_rx_fifo.xci=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
axis_rx_fifo.xci=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
axis_rx_fifo.xci=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
axis_rx_fifo.xci=REGISTERED_WITH_MANAGER (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (1)
axis_rx_fifo.xci=SYNTH_CHECKPOINT_MODE (enum) :DEFAULT_VALUE (None)==CURRENT_VALUE (Singular)
axis_rx_fifo.xci=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
axis_rx_fifo.xci=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
axis_rx_fifo.xci=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
axis_rx_fifo.xci=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
axis_register.v=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (Verilog)
axis_register.v=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
axis_register.v=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
axis_register.v=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
axis_register.v=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
axis_register.v=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
axis_register.v=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
axis_register.v=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
axis_register.v=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
design_1_wrapper.v=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (Verilog)
design_1_wrapper.v=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
design_1_wrapper.v=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
design_1_wrapper.v=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
design_1_wrapper.v=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
design_1_wrapper.v=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
design_1_wrapper.v=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
design_1_wrapper.v=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
design_1_wrapper.v=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
main.v=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (Verilog)
main.v=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
main.v=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
main.v=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
main.v=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
main.v=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
main.v=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
main.v=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
main.v=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
memory_wrapper.v=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (Verilog)
memory_wrapper.v=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
memory_wrapper.v=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
memory_wrapper.v=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
memory_wrapper.v=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
memory_wrapper.v=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
memory_wrapper.v=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
memory_wrapper.v=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
memory_wrapper.v=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
serial_wrapper.v=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (Verilog)
serial_wrapper.v=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
serial_wrapper.v=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
serial_wrapper.v=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
serial_wrapper.v=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
serial_wrapper.v=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
serial_wrapper.v=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
serial_wrapper.v=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
serial_wrapper.v=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
SBCTextDisplayRGB.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL)
SBCTextDisplayRGB.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
SBCTextDisplayRGB.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
SBCTextDisplayRGB.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
SBCTextDisplayRGB.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
SBCTextDisplayRGB.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
SBCTextDisplayRGB.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
SBCTextDisplayRGB.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fpaddsub.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL)
fpaddsub.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fpaddsub.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
fpaddsub.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
fpaddsub.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
fpaddsub.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
fpaddsub.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fpaddsub.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fpdiv.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL)
fpdiv.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fpdiv.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
fpdiv.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
fpdiv.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
fpdiv.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
fpdiv.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fpdiv.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fpmult.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL)
fpmult.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fpmult.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
fpmult.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
fpmult.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
fpmult.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
fpmult.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fpmult.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fpsqrt.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL)
fpsqrt.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fpsqrt.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
fpsqrt.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
fpsqrt.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
fpsqrt.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
fpsqrt.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fpsqrt.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
i2c_master.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL)
i2c_master.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
i2c_master.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
i2c_master.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
i2c_master.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
i2c_master.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
i2c_master.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
i2c_master.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
timer.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL)
timer.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
timer.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
timer.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
timer.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
timer.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
timer.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
timer.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
interrupt_controller.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL 2008)
interrupt_controller.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
interrupt_controller.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
interrupt_controller.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
interrupt_controller.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
interrupt_controller.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
interrupt_controller.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
interrupt_controller.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
pmod_real_time_clock.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL 2008)
pmod_real_time_clock.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
pmod_real_time_clock.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
pmod_real_time_clock.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
pmod_real_time_clock.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
pmod_real_time_clock.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
pmod_real_time_clock.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
pmod_real_time_clock.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
TG68K_Pack.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL 2008)
TG68K_Pack.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
TG68K_Pack.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
TG68K_Pack.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
TG68K_Pack.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
TG68K_Pack.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
TG68K_Pack.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
TG68K_Pack.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
TG68KdotC_Kernel.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL 2008)
TG68KdotC_Kernel.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
TG68KdotC_Kernel.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
TG68KdotC_Kernel.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
TG68KdotC_Kernel.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
TG68KdotC_Kernel.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
TG68KdotC_Kernel.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
TG68KdotC_Kernel.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
TG68_minimal.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL 2008)
TG68_minimal.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
TG68_minimal.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
TG68_minimal.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
TG68_minimal.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
TG68_minimal.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
TG68_minimal.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
TG68_minimal.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
rom.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL 2008)
rom.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
rom.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
rom.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
rom.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
rom.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
rom.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
rom.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
ram.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL 2008)
ram.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
ram.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
ram.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
ram.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
ram.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
ram.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
ram.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
Microcomputer.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL 2008)
Microcomputer.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
Microcomputer.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
Microcomputer.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
Microcomputer.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
Microcomputer.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
Microcomputer.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
Microcomputer.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
TG68K_ALU.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL 2008)
TG68K_ALU.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
TG68K_ALU.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
TG68K_ALU.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
TG68K_ALU.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
TG68K_ALU.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
TG68K_ALU.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
TG68K_ALU.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
ethernet.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL 2008)
ethernet.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
ethernet.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
ethernet.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
ethernet.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
ethernet.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
ethernet.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
ethernet.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fpu_double.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL 2008)
fpu_double.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fpu_double.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
fpu_double.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
fpu_double.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
fpu_double.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
fpu_double.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fpu_double.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
spi_master.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL 2008)
spi_master.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
spi_master.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
spi_master.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
spi_master.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
spi_master.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis)
spi_master.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (0)
spi_master.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fram_control.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL 2008)
fram_control.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fram_control.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
fram_control.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
fram_control.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
fram_control.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis)
fram_control.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (0)
fram_control.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
sd_spi.vhdl=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL 2008)
sd_spi.vhdl=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
sd_spi.vhdl=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
sd_spi.vhdl=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
sd_spi.vhdl=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
sd_spi.vhdl=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
sd_spi.vhdl=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
sd_spi.vhdl=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
multicomp_wrapper.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL 2008)
multicomp_wrapper.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
multicomp_wrapper.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
multicomp_wrapper.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
multicomp_wrapper.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
multicomp_wrapper.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
multicomp_wrapper.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
multicomp_wrapper.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
cache.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL)
cache.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
cache.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
cache.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
cache.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
cache.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
cache.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
cache.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
utilities.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL)
utilities.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
utilities.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
utilities.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
utilities.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
utilities.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
utilities.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
utilities.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
mig_b.prj=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
mig_b.prj=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
mig_b.prj=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
mig_b.prj=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
mig_b.prj=SCOPED_TO_CELLS (string*) :DEFAULT_VALUE ()==CURRENT_VALUE (mig)
mig_b.prj=SCOPED_TO_REF (string) :DEFAULT_VALUE ()==CURRENT_VALUE ()
mig_b.prj=USED_IN (string*) :DEFAULT_VALUE (synthesis)==CURRENT_VALUE (synthesis)
mig_b.prj=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
mig_a.prj=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
mig_a.prj=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
mig_a.prj=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
mig_a.prj=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
mig_a.prj=SCOPED_TO_CELLS (string*) :DEFAULT_VALUE ()==CURRENT_VALUE (mig_7series_0)
mig_a.prj=SCOPED_TO_REF (string) :DEFAULT_VALUE ()==CURRENT_VALUE ()
mig_a.prj=USED_IN (string*) :DEFAULT_VALUE (synthesis)==CURRENT_VALUE (synthesis)
mig_a.prj=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
mig_b.prj=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
mig_b.prj=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
mig_b.prj=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
mig_b.prj=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
mig_b.prj=SCOPED_TO_CELLS (string*) :DEFAULT_VALUE ()==CURRENT_VALUE (mig_7series_0)
mig_b.prj=SCOPED_TO_REF (string) :DEFAULT_VALUE ()==CURRENT_VALUE ()
mig_b.prj=USED_IN (string*) :DEFAULT_VALUE (synthesis)==CURRENT_VALUE (synthesis)
mig_b.prj=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
mig_b.prj=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
mig_b.prj=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
mig_b.prj=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
mig_b.prj=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
mig_b.prj=SCOPED_TO_CELLS (string*) :DEFAULT_VALUE ()==CURRENT_VALUE (memory_mig_7series_0_2)
mig_b.prj=SCOPED_TO_REF (string) :DEFAULT_VALUE ()==CURRENT_VALUE ()
mig_b.prj=USED_IN (string*) :DEFAULT_VALUE (synthesis)==CURRENT_VALUE (synthesis)
mig_b.prj=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
DESIGN_MODE:(enum) DEFAULT_VALUE (RTL)==CURRENT_VALUE (RTL)
EDIF_EXTRA_SEARCH_PATHS:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
ELAB_LINK_DCPS:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
ELAB_LOAD_TIMING_CONSTRAINTS:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
GENERIC:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
INCLUDE_DIRS:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
LIB_MAP_FILE:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
LOOP_COUNT:(int) DEFAULT_VALUE (1000)==CURRENT_VALUE (1000)
NAME:(string) DEFAULT_VALUE (sources_1)==CURRENT_VALUE (sources_1)
TOP:(string) DEFAULT_VALUE ()==CURRENT_VALUE (multicomp_wrapper)
TOP_AUTO_SET:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (0)
VERILOG_DEFINE:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
VERILOG_UPPERCASE:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
VERILOG_VERSION:(enum) DEFAULT_VALUE (verilog_2001)==CURRENT_VALUE (verilog_2001)
VHDL_VERSION:(enum) DEFAULT_VALUE (vhdl_2k)==CURRENT_VALUE (vhdl_2k)
pll.xci=GENERATE_FILES_FOR_REFERENCE (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (0)
pll.xci=GENERATE_SYNTH_CHECKPOINT (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
pll.xci=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
pll.xci=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
pll.xci=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
pll.xci=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
pll.xci=REGISTERED_WITH_MANAGER (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (1)
pll.xci=SYNTH_CHECKPOINT_MODE (enum) :DEFAULT_VALUE (None)==CURRENT_VALUE (Singular)
pll.xci=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
pll.xci=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
pll.xci=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
pll.xci=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fp_mult.xci=GENERATE_FILES_FOR_REFERENCE (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (0)
fp_mult.xci=GENERATE_SYNTH_CHECKPOINT (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fp_mult.xci=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fp_mult.xci=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
fp_mult.xci=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
fp_mult.xci=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
fp_mult.xci=REGISTERED_WITH_MANAGER (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (1)
fp_mult.xci=SYNTH_CHECKPOINT_MODE (enum) :DEFAULT_VALUE (None)==CURRENT_VALUE (Singular)
fp_mult.xci=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
fp_mult.xci=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fp_mult.xci=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fp_mult.xci=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fp_div.xci=GENERATE_FILES_FOR_REFERENCE (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (0)
fp_div.xci=GENERATE_SYNTH_CHECKPOINT (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fp_div.xci=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fp_div.xci=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
fp_div.xci=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
fp_div.xci=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
fp_div.xci=REGISTERED_WITH_MANAGER (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (1)
fp_div.xci=SYNTH_CHECKPOINT_MODE (enum) :DEFAULT_VALUE (None)==CURRENT_VALUE (Singular)
fp_div.xci=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
fp_div.xci=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fp_div.xci=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fp_div.xci=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fp_addsub.xci=GENERATE_FILES_FOR_REFERENCE (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (0)
fp_addsub.xci=GENERATE_SYNTH_CHECKPOINT (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fp_addsub.xci=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fp_addsub.xci=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
fp_addsub.xci=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
fp_addsub.xci=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
fp_addsub.xci=REGISTERED_WITH_MANAGER (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (1)
fp_addsub.xci=SYNTH_CHECKPOINT_MODE (enum) :DEFAULT_VALUE (None)==CURRENT_VALUE (Singular)
fp_addsub.xci=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
fp_addsub.xci=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fp_addsub.xci=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fp_addsub.xci=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fp_sqrt.xci=GENERATE_FILES_FOR_REFERENCE (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (0)
fp_sqrt.xci=GENERATE_SYNTH_CHECKPOINT (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fp_sqrt.xci=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fp_sqrt.xci=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
fp_sqrt.xci=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
fp_sqrt.xci=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
fp_sqrt.xci=REGISTERED_WITH_MANAGER (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (1)
fp_sqrt.xci=SYNTH_CHECKPOINT_MODE (enum) :DEFAULT_VALUE (None)==CURRENT_VALUE (Singular)
fp_sqrt.xci=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
fp_sqrt.xci=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fp_sqrt.xci=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fp_sqrt.xci=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
master.xdc=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (XDC)
master.xdc=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
master.xdc=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
master.xdc=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
master.xdc=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
master.xdc=PROCESSING_ORDER (enum) :DEFAULT_VALUE (NORMAL)==CURRENT_VALUE (NORMAL)
master.xdc=SCOPED_TO_CELLS (string*) :DEFAULT_VALUE ()==CURRENT_VALUE ()
master.xdc=SCOPED_TO_REF (string) :DEFAULT_VALUE ()==CURRENT_VALUE ()
master.xdc=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation)==CURRENT_VALUE (synthesis implementation)
master.xdc=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
master.xdc=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
CONSTRS_TYPE:(enum) DEFAULT_VALUE (XDC)==CURRENT_VALUE (XDC)
NAME:(string) DEFAULT_VALUE (constrs_1)==CURRENT_VALUE (constrs_1)
TARGET_CONSTRS_FILE:(string) DEFAULT_VALUE ()==CURRENT_VALUE ($PSRCDIR/zed68k.srcs/constrs_1/imports/new/master.xdc)
TARGET_UCF:(string) DEFAULT_VALUE ()==CURRENT_VALUE ($PSRCDIR/zed68k.srcs/constrs_1/imports/new/master.xdc)
timer_tb.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL)
timer_tb.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
timer_tb.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
timer_tb.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
timer_tb.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
timer_tb.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
timer_tb.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
timer_tb.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
cache_tb.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL)
cache_tb.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
cache_tb.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
cache_tb.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
cache_tb.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
cache_tb.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
cache_tb.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
cache_tb.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fpu_double_TB.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL)
fpu_double_TB.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fpu_double_TB.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
fpu_double_TB.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
fpu_double_TB.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
fpu_double_TB.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
fpu_double_TB.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fpu_double_TB.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
ddr3_model_parameters.vh=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (Verilog Header)
ddr3_model_parameters.vh=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
ddr3_model_parameters.vh=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
ddr3_model_parameters.vh=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
ddr3_model_parameters.vh=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
ddr3_model_parameters.vh=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
ddr3_model_parameters.vh=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
ddr3_model_parameters.vh=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
ddr3_model.v=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (Verilog)
ddr3_model.v=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
ddr3_model.v=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
ddr3_model.v=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
ddr3_model.v=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
ddr3_model.v=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
ddr3_model.v=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
ddr3_model.v=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
ddr3_model.v=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
system_tb.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL)
system_tb.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
system_tb.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
system_tb.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
system_tb.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
system_tb.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
system_tb.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
system_tb.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
main_tb_behav.wcfg=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
main_tb_behav.wcfg=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
main_tb_behav.wcfg=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
main_tb_behav.wcfg=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
main_tb_behav.wcfg=USED_IN (string*) :DEFAULT_VALUE (simulation)==CURRENT_VALUE (simulation)
main_tb_behav.wcfg=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
revision.v=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (Verilog Header)
revision.v=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
revision.v=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
revision.v=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
revision.v=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
revision.v=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
revision.v=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
revision.v=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
io_def.vh=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (Verilog Header)
io_def.vh=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
io_def.vh=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
io_def.vh=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
io_def.vh=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
io_def.vh=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
io_def.vh=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
io_def.vh=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
1024Mb_ddr3_parameters.vh=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (Verilog Header)
1024Mb_ddr3_parameters.vh=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
1024Mb_ddr3_parameters.vh=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
1024Mb_ddr3_parameters.vh=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
1024Mb_ddr3_parameters.vh=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
1024Mb_ddr3_parameters.vh=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
1024Mb_ddr3_parameters.vh=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
1024Mb_ddr3_parameters.vh=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
subtest.vh=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (Verilog Header)
subtest.vh=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
subtest.vh=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
subtest.vh=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
subtest.vh=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
subtest.vh=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
subtest.vh=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
subtest.vh=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
ps2_tb.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL 2008)
ps2_tb.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
ps2_tb.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
ps2_tb.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
ps2_tb.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
ps2_tb.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
ps2_tb.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
ps2_tb.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
32BIT:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
GENERIC:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
HBS.CONFIGURE_DESIGN_FOR_HIER_ACCESS:(bool) DEFAULT_VALUE ()==CURRENT_VALUE (1)
INCLUDE_DIRS:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
INCREMENTAL:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
NAME:(string) DEFAULT_VALUE (sim_1)==CURRENT_VALUE (sim_1)
NL.CELL:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
NL.INCL_UNISIM_MODELS:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
NL.MODE:(string) DEFAULT_VALUE (timesim)==CURRENT_VALUE (funcsim)
NL.PROCESS_CORNER:(string) DEFAULT_VALUE (slow)==CURRENT_VALUE (slow)
NL.RENAME_TOP:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
NL.SDF_ANNO:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
NL.WRITE_ALL_OVERRIDES:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
SOURCE_SET:(string) DEFAULT_VALUE (sources_1)==CURRENT_VALUE (sources_1)
SYSTEMC_INCLUDE_DIRS:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
TOP:(string) DEFAULT_VALUE ()==CURRENT_VALUE (timer_tb)
TOP_AUTO_SET:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (0)
TOP_LIB:(string) DEFAULT_VALUE ()==CURRENT_VALUE (xil_defaultlib)
TRANSPORT_INT_DELAY:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
TRANSPORT_PATH_DELAY:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
VERILOG_DEFINE:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
VERILOG_UPPERCASE:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
XELAB.DLL:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
XSIM.COMPILE.TCL.PRE:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.COMPILE.XSC.MORE_OPTIONS:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.COMPILE.XVHDL.MORE_OPTIONS:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.COMPILE.XVHDL.NOSORT:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
XSIM.COMPILE.XVHDL.RELAX:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
XSIM.COMPILE.XVLOG.MORE_OPTIONS:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.COMPILE.XVLOG.NOSORT:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
XSIM.COMPILE.XVLOG.RELAX:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
XSIM.ELABORATE.DEBUG_LEVEL:(enum) DEFAULT_VALUE (typical)==CURRENT_VALUE (typical)
XSIM.ELABORATE.LOAD_GLBL:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
XSIM.ELABORATE.MT_LEVEL:(enum) DEFAULT_VALUE (auto)==CURRENT_VALUE (auto)
XSIM.ELABORATE.RANGECHECK:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
XSIM.ELABORATE.RELAX:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
XSIM.ELABORATE.SDF_DELAY:(enum) DEFAULT_VALUE (sdfmax)==CURRENT_VALUE (sdfmax)
XSIM.ELABORATE.SNAPSHOT:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.ELABORATE.XELAB.MORE_OPTIONS:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.ELABORATE.XSC.MORE_OPTIONS:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.SIMULATE.ADD_POSITIONAL:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
XSIM.SIMULATE.CUSTOM_TCL:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.SIMULATE.LOG_ALL_SIGNALS:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
XSIM.SIMULATE.NO_QUIT:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
XSIM.SIMULATE.RUNTIME:(string) DEFAULT_VALUE (1000ns)==CURRENT_VALUE (1000ns)
XSIM.SIMULATE.SAIF:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.SIMULATE.SAIF_ALL_SIGNALS:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
XSIM.SIMULATE.SAIF_SCOPE:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.SIMULATE.TCL.POST:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.SIMULATE.WDB:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.SIMULATE.XSIM.MORE_OPTIONS:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
multicomp_wrapper.dcp=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
multicomp_wrapper.dcp=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
multicomp_wrapper.dcp=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
multicomp_wrapper.dcp=NETLIST_ONLY (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (0)
multicomp_wrapper.dcp=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
multicomp_wrapper.dcp=SCOPED_TO_CELLS (string*) :DEFAULT_VALUE ()==CURRENT_VALUE ()
multicomp_wrapper.dcp=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation)==CURRENT_VALUE (synthesis implementation)
multicomp_wrapper.dcp=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
multicomp_wrapper.dcp=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
NAME:(string) DEFAULT_VALUE (utils_1)==CURRENT_VALUE (utils_1)
CONSTRSET:(string) DEFAULT_VALUE (constrs_1)==CURRENT_VALUE (constrs_1)
DESCRIPTION:(string) DEFAULT_VALUE (Vivado Synthesis Defaults)==CURRENT_VALUE (Vivado Synthesis Defaults)
FLOW:(string) DEFAULT_VALUE (Vivado Synthesis 2019)==CURRENT_VALUE (Vivado Synthesis 2019)
NAME:(string) DEFAULT_VALUE (synth_1)==CURRENT_VALUE (synth_1)
NEEDS_REFRESH:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
SRCSET:(string) DEFAULT_VALUE (sources_1)==CURRENT_VALUE (sources_1)
INCREMENTAL_CHECKPOINT:(file) DEFAULT_VALUE ()==CURRENT_VALUE ()
AUTO_INCREMENTAL_CHECKPOINT:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
RQS_FILES:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
INCREMENTAL_CHECKPOINT.MORE_OPTIONS:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
INCLUDE_IN_ARCHIVE:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
GEN_FULL_BITSTREAM:(unknown) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
WRITE_INCREMENTAL_SYNTH_CHECKPOINT:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
STRATEGY:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE (Vivado Synthesis Defaults)
STEPS.SYNTH_DESIGN.TCL.PRE:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.SYNTH_DESIGN.TCL.POST:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY:(unknown) DEFAULT_VALUE (rebuilt)==CURRENT_VALUE (rebuilt)
STEPS.SYNTH_DESIGN.ARGS.GATED_CLOCK_CONVERSION:(unknown) DEFAULT_VALUE (off)==CURRENT_VALUE (off)
STEPS.SYNTH_DESIGN.ARGS.BUFG:(unknown) DEFAULT_VALUE (12)==CURRENT_VALUE (12)
STEPS.SYNTH_DESIGN.ARGS.FANOUT_LIMIT:(unknown) DEFAULT_VALUE (10000)==CURRENT_VALUE (10000)
STEPS.SYNTH_DESIGN.ARGS.DIRECTIVE:(unknown) DEFAULT_VALUE (Default)==CURRENT_VALUE (Default)
STEPS.SYNTH_DESIGN.ARGS.RETIMING:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
STEPS.SYNTH_DESIGN.ARGS.FSM_EXTRACTION:(unknown) DEFAULT_VALUE (auto)==CURRENT_VALUE (auto)
STEPS.SYNTH_DESIGN.ARGS.KEEP_EQUIVALENT_REGISTERS:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
STEPS.SYNTH_DESIGN.ARGS.RESOURCE_SHARING:(unknown) DEFAULT_VALUE (auto)==CURRENT_VALUE (auto)
STEPS.SYNTH_DESIGN.ARGS.CONTROL_SET_OPT_THRESHOLD:(unknown) DEFAULT_VALUE (auto)==CURRENT_VALUE (auto)
STEPS.SYNTH_DESIGN.ARGS.NO_LC:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
STEPS.SYNTH_DESIGN.ARGS.NO_SRLEXTRACT:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
STEPS.SYNTH_DESIGN.ARGS.SHREG_MIN_SIZE:(unknown) DEFAULT_VALUE (3)==CURRENT_VALUE (3)
STEPS.SYNTH_DESIGN.ARGS.MAX_BRAM:(unknown) DEFAULT_VALUE (-1)==CURRENT_VALUE (-1)
STEPS.SYNTH_DESIGN.ARGS.MAX_URAM:(unknown) DEFAULT_VALUE (-1)==CURRENT_VALUE (-1)
STEPS.SYNTH_DESIGN.ARGS.MAX_DSP:(unknown) DEFAULT_VALUE (-1)==CURRENT_VALUE (-1)
STEPS.SYNTH_DESIGN.ARGS.MAX_BRAM_CASCADE_HEIGHT:(unknown) DEFAULT_VALUE (-1)==CURRENT_VALUE (-1)
STEPS.SYNTH_DESIGN.ARGS.MAX_URAM_CASCADE_HEIGHT:(unknown) DEFAULT_VALUE (-1)==CURRENT_VALUE (-1)
STEPS.SYNTH_DESIGN.ARGS.CASCADE_DSP:(unknown) DEFAULT_VALUE (auto)==CURRENT_VALUE (auto)
STEPS.SYNTH_DESIGN.ARGS.ASSERT:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
CONSTRSET:(string) DEFAULT_VALUE (constrs_1)==CURRENT_VALUE (constrs_1)
DESCRIPTION:(string) DEFAULT_VALUE (Default settings for Implementation.)==CURRENT_VALUE (Default settings for Implementation.)
FLOW:(string) DEFAULT_VALUE (Vivado Implementation 2019)==CURRENT_VALUE (Vivado Implementation 2019)
NAME:(string) DEFAULT_VALUE (impl_1)==CURRENT_VALUE (impl_1)
NEEDS_REFRESH:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
PR_CONFIGURATION:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
SRCSET:(string) DEFAULT_VALUE (sources_1)==CURRENT_VALUE (sources_1)
INCREMENTAL_CHECKPOINT:(file) DEFAULT_VALUE ()==CURRENT_VALUE ()
AUTO_INCREMENTAL_CHECKPOINT:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (1)
RQS_FILES:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
INCREMENTAL_CHECKPOINT.MORE_OPTIONS:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
INCLUDE_IN_ARCHIVE:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
GEN_FULL_BITSTREAM:(unknown) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
STRATEGY:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE (Vivado Implementation Defaults)
STEPS.INIT_DESIGN.TCL.PRE:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.INIT_DESIGN.TCL.POST:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.OPT_DESIGN.IS_ENABLED:(unknown) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
STEPS.OPT_DESIGN.TCL.PRE:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.OPT_DESIGN.TCL.POST:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.OPT_DESIGN.ARGS.VERBOSE:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
STEPS.OPT_DESIGN.ARGS.DIRECTIVE:(unknown) DEFAULT_VALUE (Default)==CURRENT_VALUE (Default)
STEPS.OPT_DESIGN.ARGS.MORE OPTIONS:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.POWER_OPT_DESIGN.IS_ENABLED:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
STEPS.POWER_OPT_DESIGN.TCL.PRE:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.POWER_OPT_DESIGN.TCL.POST:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.POWER_OPT_DESIGN.ARGS.MORE OPTIONS:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.PLACE_DESIGN.TCL.PRE:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.PLACE_DESIGN.TCL.POST:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.PLACE_DESIGN.ARGS.DIRECTIVE:(unknown) DEFAULT_VALUE (Default)==CURRENT_VALUE (Default)
STEPS.PLACE_DESIGN.ARGS.MORE OPTIONS:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.POST_PLACE_POWER_OPT_DESIGN.IS_ENABLED:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
STEPS.POST_PLACE_POWER_OPT_DESIGN.TCL.PRE:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.POST_PLACE_POWER_OPT_DESIGN.TCL.POST:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.POST_PLACE_POWER_OPT_DESIGN.ARGS.MORE OPTIONS:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.PHYS_OPT_DESIGN.IS_ENABLED:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (1)
STEPS.PHYS_OPT_DESIGN.TCL.PRE:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.PHYS_OPT_DESIGN.TCL.POST:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE:(unknown) DEFAULT_VALUE (Default)==CURRENT_VALUE (Default)
STEPS.PHYS_OPT_DESIGN.ARGS.MORE OPTIONS:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.ROUTE_DESIGN.TCL.PRE:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.ROUTE_DESIGN.TCL.POST:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE:(unknown) DEFAULT_VALUE (Default)==CURRENT_VALUE (Default)
STEPS.ROUTE_DESIGN.ARGS.MORE OPTIONS:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
STEPS.POST_ROUTE_PHYS_OPT_DESIGN.TCL.PRE:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.POST_ROUTE_PHYS_OPT_DESIGN.TCL.POST:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.DIRECTIVE:(unknown) DEFAULT_VALUE (Default)==CURRENT_VALUE (Default)
STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.MORE OPTIONS:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.WRITE_BITSTREAM.TCL.PRE:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.WRITE_BITSTREAM.TCL.POST:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.WRITE_BITSTREAM.ARGS.RAW_BITFILE:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
STEPS.WRITE_BITSTREAM.ARGS.MASK_FILE:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
STEPS.WRITE_BITSTREAM.ARGS.NO_BINARY_BITFILE:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
STEPS.WRITE_BITSTREAM.ARGS.BIN_FILE:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
STEPS.WRITE_BITSTREAM.ARGS.READBACK_FILE:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE (0)
STEPS.WRITE_BITSTREAM.ARGS.LOGIC_LOCATION_FILE:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
STEPS.WRITE_BITSTREAM.ARGS.VERBOSE:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE (0)
STEPS.WRITE_BITSTREAM.ARGS.MORE OPTIONS:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
CONSTRSET:(string) DEFAULT_VALUE (constrs_1)==CURRENT_VALUE (constrs_1)
DESCRIPTION:(string) DEFAULT_VALUE (Default settings for Implementation.)==CURRENT_VALUE (Default settings for Implementation.)
FLOW:(string) DEFAULT_VALUE (Vivado Implementation 2019)==CURRENT_VALUE (Vivado Implementation 2019)
NAME:(string) DEFAULT_VALUE (impl_1_nex)==CURRENT_VALUE (impl_1_nex)
NEEDS_REFRESH:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
PR_CONFIGURATION:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
SRCSET:(string) DEFAULT_VALUE (sources_1)==CURRENT_VALUE (sources_1)
INCREMENTAL_CHECKPOINT:(file) DEFAULT_VALUE ()==CURRENT_VALUE ()
AUTO_INCREMENTAL_CHECKPOINT:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
RQS_FILES:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
INCREMENTAL_CHECKPOINT.MORE_OPTIONS:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
INCLUDE_IN_ARCHIVE:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
GEN_FULL_BITSTREAM:(unknown) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
STRATEGY:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE (Vivado Implementation Defaults)
STEPS.INIT_DESIGN.TCL.PRE:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.INIT_DESIGN.TCL.POST:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.OPT_DESIGN.IS_ENABLED:(unknown) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
STEPS.OPT_DESIGN.TCL.PRE:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.OPT_DESIGN.TCL.POST:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.OPT_DESIGN.ARGS.VERBOSE:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
STEPS.OPT_DESIGN.ARGS.DIRECTIVE:(unknown) DEFAULT_VALUE (Default)==CURRENT_VALUE (Default)
STEPS.OPT_DESIGN.ARGS.MORE OPTIONS:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.POWER_OPT_DESIGN.IS_ENABLED:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
STEPS.POWER_OPT_DESIGN.TCL.PRE:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.POWER_OPT_DESIGN.TCL.POST:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.POWER_OPT_DESIGN.ARGS.MORE OPTIONS:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.PLACE_DESIGN.TCL.PRE:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.PLACE_DESIGN.TCL.POST:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.PLACE_DESIGN.ARGS.DIRECTIVE:(unknown) DEFAULT_VALUE (Default)==CURRENT_VALUE (Default)
STEPS.PLACE_DESIGN.ARGS.MORE OPTIONS:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.POST_PLACE_POWER_OPT_DESIGN.IS_ENABLED:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
STEPS.POST_PLACE_POWER_OPT_DESIGN.TCL.PRE:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.POST_PLACE_POWER_OPT_DESIGN.TCL.POST:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.POST_PLACE_POWER_OPT_DESIGN.ARGS.MORE OPTIONS:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.PHYS_OPT_DESIGN.IS_ENABLED:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (1)
STEPS.PHYS_OPT_DESIGN.TCL.PRE:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.PHYS_OPT_DESIGN.TCL.POST:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE:(unknown) DEFAULT_VALUE (Default)==CURRENT_VALUE (Default)
STEPS.PHYS_OPT_DESIGN.ARGS.MORE OPTIONS:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.ROUTE_DESIGN.TCL.PRE:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.ROUTE_DESIGN.TCL.POST:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
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STEPS.ROUTE_DESIGN.ARGS.MORE OPTIONS:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
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