MiniMips_BRAM.twr

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Release 14.7 Trace  (nt)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 3 -n
3 -fastpaths -xml MiniMips_BRAM.twx MiniMips_BRAM.ncd -o MiniMips_BRAM.twr
MiniMips_BRAM.pcf -ucf MiniMips.ucf

Design file:              MiniMips_BRAM.ncd
Physical constraint file: MiniMips_BRAM.pcf
Device,package,speed:     xc6slx16,csg324,C,-3 (PRODUCTION 1.23 2013-10-13)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk_global
------------+------------+------------+------------+------------+------------------+--------+
            |Max Setup to|  Process   |Max Hold to |  Process   |                  | Clock  |
Source      | clk (edge) |   Corner   | clk (edge) |   Corner   |Internal Clock(s) | Phase  |
------------+------------+------------+------------+------------+------------------+--------+
reset_global|    2.410(R)|      SLOW  |   -1.458(R)|      FAST  |clk_global_BUFGP  |   0.000|
------------+------------+------------+------------+------------+------------------+--------+

Clock clk_global to Pad
------------+-----------------+------------+-----------------+------------+------------------+--------+
            |Max (slowest) clk|  Process   |Min (fastest) clk|  Process   |                  | Clock  |
Destination |  (edge) to PAD  |   Corner   |  (edge) to PAD  |   Corner   |Internal Clock(s) | Phase  |
------------+-----------------+------------+-----------------+------------+------------------+--------+
en_n_o<0>   |         8.996(R)|      SLOW  |         4.714(R)|      FAST  |clk_global_BUFGP  |   0.000|
en_n_o<1>   |         9.219(R)|      SLOW  |         4.894(R)|      FAST  |clk_global_BUFGP  |   0.000|
en_n_o<2>   |         9.306(R)|      SLOW  |         4.911(R)|      FAST  |clk_global_BUFGP  |   0.000|
en_n_o<3>   |         9.204(R)|      SLOW  |         4.871(R)|      FAST  |clk_global_BUFGP  |   0.000|
------------+-----------------+------------+-----------------+------------+------------------+--------+

Clock to Setup on destination clock clk_global
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk_global     |    3.243|         |         |         |
---------------+---------+---------+---------+---------+


Analysis completed Wed May 21 12:33:03 2014 
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Trace Settings:
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Trace Settings 

Peak Memory Usage: 150 MB