@@ -551,11 +551,11 @@ def create_channel_handlers(vcd_manager, devices, ref_period,
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and desc ["class" ] in {"TTLOut" , "TTLInOut" }):
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channel = desc ["arguments" ]["channel" ]
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channel_handlers [channel ] = TTLHandler (vcd_manager , name )
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- if (desc ["module" ] == "artiq.coredevice.ttl"
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+ elif (desc ["module" ] == "artiq.coredevice.ttl"
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and desc ["class" ] == "TTLClockGen" ):
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channel = desc ["arguments" ]["channel" ]
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channel_handlers [channel ] = TTLClockGenHandler (vcd_manager , name , ref_period )
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- if (desc ["module" ] == "artiq.coredevice.ad9914"
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+ elif (desc ["module" ] == "artiq.coredevice.ad9914"
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and desc ["class" ] == "AD9914" ):
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dds_bus_channel = desc ["arguments" ]["bus_channel" ]
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dds_channel = desc ["arguments" ]["channel" ]
@@ -565,11 +565,29 @@ def create_channel_handlers(vcd_manager, devices, ref_period,
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dds_handler = DDSHandler (vcd_manager , dds_onehot_sel , dds_sysclk )
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channel_handlers [dds_bus_channel ] = dds_handler
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dds_handler .add_dds_channel (name , dds_channel )
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- if (desc ["module" ] == "artiq.coredevice.spi2" and
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+ elif (desc ["module" ] == "artiq.coredevice.spi2" and
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desc ["class" ] == "SPIMaster" ):
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channel = desc ["arguments" ]["channel" ]
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channel_handlers [channel ] = SPIMaster2Handler (
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vcd_manager , name )
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+ elif (
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+ "channel" in desc ["arguments" ].keys () and
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+ desc ["type" ] == "local" and
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+ "core" not in name .lower () and
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+ "core" not in desc ["class" ].lower ()
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+ ):
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+ channel = desc ["arguments" ]["channel" ]
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+ logger .info (
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+ "Adding Wishbone coreanalyzer channel (RTIO#%i): %s: %s" ,
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+ channel ,
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+ name ,
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+ desc ,
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+ )
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+ channel_handlers [channel ] = GenericWishboneHandler (
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+ vcd_manager ,
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+ name ,
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+ channel ,
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+ )
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return channel_handlers
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