diff --git a/hw/mcu/nordic/include/nrfx_glue.h b/hw/mcu/nordic/include/nrfx_glue.h index 6f42c2e1da..fa3df8a0ca 100644 --- a/hw/mcu/nordic/include/nrfx_glue.h +++ b/hw/mcu/nordic/include/nrfx_glue.h @@ -273,6 +273,18 @@ extern "C" { //------------------------------------------------------------------------------ +/** + * @brief Macro for invalidating cache lines associated with the specified buffer. + * + * @note Macro should be empty if data cache is disabled or not present. + * + * @param[in] p_buffer Pointer to the buffer. + * @param[in] size Size of the buffer. + */ +#define NRFY_CACHE_INV(p_buffer, size) (void)p_buffer; (void)size; + +//------------------------------------------------------------------------------ + /** @brief Bitmask that defines DPPI channels that are reserved for use outside of the nrfx library. */ #define NRFX_DPPI_CHANNELS_USED 0 diff --git a/hw/mcu/nordic/nrf5340/include/nrfx_config_nrf5340_application.h b/hw/mcu/nordic/nrf5340/include/nrfx_config_nrf5340_application.h index 7e4208581c..54c284bb63 100644 --- a/hw/mcu/nordic/nrf5340/include/nrfx_config_nrf5340_application.h +++ b/hw/mcu/nordic/nrf5340/include/nrfx_config_nrf5340_application.h @@ -1109,8 +1109,13 @@ * Boolean. Accepted values: 0 and 1. */ #ifndef NRFX_SPIM_ENABLED +#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_1_MASTER) || \ + MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_3_MASTER) || MYNEWT_VAL(SPI_4_MASTER) +#define NRFX_SPIM_ENABLED 1 +#else #define NRFX_SPIM_ENABLED 0 #endif +#endif /** * @brief NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY @@ -1151,7 +1156,7 @@ * Boolean. Accepted values: 0 and 1. */ #ifndef NRFX_SPIM0_ENABLED -#define NRFX_SPIM0_ENABLED 0 +#define NRFX_SPIM0_ENABLED 1 #endif /** @@ -1196,8 +1201,13 @@ * Boolean. Accepted values: 0 and 1. */ #ifndef NRFX_SPIS_ENABLED +#if MYNEWT_VAL(SPI_0_SLAVE) || MYNEWT_VAL(SPI_1_SLAVE) || \ + MYNEWT_VAL(SPI_2_SLAVE) || MYNEWT_VAL(SPI_3_SLAVE) +#define NRFX_SPIS_ENABLED 1 +#else #define NRFX_SPIS_ENABLED 0 #endif +#endif /** * @brief NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY @@ -1238,8 +1248,12 @@ * Boolean. Accepted values: 0 and 1. */ #ifndef NRFX_SPIS0_ENABLED +#if MYNEWT_VAL(SPI_0_SLAVE) +#define NRFX_SPIS0_ENABLED 1 +#else #define NRFX_SPIS0_ENABLED 0 #endif +#endif /** * @brief NRFX_SPIS1_ENABLED @@ -1247,8 +1261,12 @@ * Boolean. Accepted values: 0 and 1. */ #ifndef NRFX_SPIS1_ENABLED +#if MYNEWT_VAL(SPI_1_SLAVE) +#define NRFX_SPIS1_ENABLED 1 +#else #define NRFX_SPIS1_ENABLED 0 #endif +#endif /** * @brief NRFX_SPIS2_ENABLED @@ -1256,8 +1274,12 @@ * Boolean. Accepted values: 0 and 1. */ #ifndef NRFX_SPIS2_ENABLED +#if MYNEWT_VAL(SPI_2_SLAVE) +#define NRFX_SPIS2_ENABLED 1 +#else #define NRFX_SPIS2_ENABLED 0 #endif +#endif /** * @brief NRFX_SPIS3_ENABLED @@ -1265,8 +1287,12 @@ * Boolean. Accepted values: 0 and 1. */ #ifndef NRFX_SPIS3_ENABLED +#if MYNEWT_VAL(SPI_3_SLAVE) +#define NRFX_SPIS3_ENABLED 1 +#else #define NRFX_SPIS3_ENABLED 0 #endif +#endif /** * @brief NRFX_SYSTICK_ENABLED diff --git a/hw/mcu/nordic/nrf5340/src/hal_spi.c b/hw/mcu/nordic/nrf5340/src/hal_spi.c index caeab72e99..d0be1f4558 100644 --- a/hw/mcu/nordic/nrf5340/src/hal_spi.c +++ b/hw/mcu/nordic/nrf5340/src/hal_spi.c @@ -21,24 +21,20 @@ #include #include #include -#include #include #include #include #include #include +#include +#include +//TODO: ifdef dla innych nrfow #define SPIM_TXD_MAXCNT_MAX 0xffff -/* IRQ handler type */ -typedef void (*nrf5340_spi_irq_handler_t)(void); - /* The maximum number of SPI interfaces we will allow */ #define NRF5340_HAL_SPI_MAX (5) -/* Used to disable all interrupts */ -#define NRF_SPI_IRQ_DISABLE_ALL 0xffffffff - /* * Slave states * @@ -52,32 +48,29 @@ typedef void (*nrf5340_spi_irq_handler_t)(void); #define HAL_SPI_SLAVE_STATE_ACQ_SEM (1) #define HAL_SPI_SLAVE_STATE_READY (2) +struct txrx_cb_data { + hal_spi_txrx_cb func; + void *arg; +}; + struct nrf5340_hal_spi { uint8_t spi_type; - uint8_t spi_xfr_flag; /* Master only */ - uint8_t dummy_rx; /* Master only */ uint8_t slave_state; /* Slave only */ - uint16_t nhs_buflen; - uint16_t nhs_bytes_txd; - struct hal_spi_settings spi_cfg; /* Slave and master */ + uint8_t def_tx_val; - /* Pointer to HW registers */ - union { - NRF_SPIM_Type *spim; - NRF_SPIS_Type *spis; - } nhs_spi; - - /* IRQ number */ - IRQn_Type irq_num; + int8_t sck_pin; + int8_t mosi_pin; + int8_t miso_pin; + int8_t ss_pin; - /* Pointers to tx/rx buffers */ - uint8_t *nhs_txbuf; - uint8_t *nhs_rxbuf; + union { + nrfx_spim_t spim; + nrfx_spis_t spis; + } nrfx_spi; /* Callback and arguments */ - hal_spi_txrx_cb txrx_cb_func; - void *txrx_cb_arg; + struct txrx_cb_data cb_data; }; #if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE) @@ -135,197 +128,13 @@ static const struct nrf5340_hal_spi *nrf5340_hal_spis[NRF5340_HAL_SPI_MAX] = { goto err; \ } -#if (MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_3_MASTER) || MYNEWT_VAL(SPI_4_MASTER)) static void -nrf5340_irqm_handler(struct nrf5340_hal_spi *spi) -{ - NRF_SPIM_Type *spim; - uint16_t xfr_bytes; - uint16_t len; - - spim = spi->nhs_spi.spim; - if (spim->EVENTS_END) { - spim->EVENTS_END = 0; - - /* Should not occur but if no transfer just leave */ - if (spi->spi_xfr_flag == 0) { - return; - } - - /* Are there more bytes to send? */ - xfr_bytes = spim->TXD.AMOUNT; - spi->nhs_bytes_txd += xfr_bytes; - if (spi->nhs_bytes_txd < spi->nhs_buflen) { - spi->nhs_txbuf += xfr_bytes; - len = spi->nhs_buflen - spi->nhs_bytes_txd; - len = min(SPIM_TXD_MAXCNT_MAX, len); - spim->TXD.PTR = (uint32_t)spi->nhs_txbuf; - spim->TXD.MAXCNT = len; - - /* If no rxbuf, we need to set rxbuf and maxcnt to 1 */ - if (spi->nhs_rxbuf) { - spi->nhs_rxbuf += xfr_bytes; - spim->RXD.PTR = (uint32_t)spi->nhs_rxbuf; - spim->RXD.MAXCNT = len; - } - spim->TASKS_START = 1; - } else { - spi->spi_xfr_flag = 0; - spim->INTENCLR = SPIM_INTENSET_END_Msk; - if (spi->txrx_cb_func) { - spi->txrx_cb_func(spi->txrx_cb_arg, spi->nhs_buflen); - } - } - } -} -#endif - -#if (MYNEWT_VAL(SPI_0_SLAVE) || MYNEWT_VAL(SPI_1_SLAVE) || MYNEWT_VAL(SPI_2_SLAVE) || MYNEWT_VAL(SPI_3_SLAVE)) -static void -nrf5340_irqs_handler(struct nrf5340_hal_spi *spi) -{ - uint8_t xfr_len; - NRF_SPIS_Type *spis; - - spis = spi->nhs_spi.spis; - - /* Semaphore acquired event */ - if (spis->EVENTS_ACQUIRED) { - spis->EVENTS_ACQUIRED = 0; - - if (spi->slave_state == HAL_SPI_SLAVE_STATE_ACQ_SEM) { - if (spi->nhs_txbuf == NULL) { - spis->TXD.PTR = 0; - spis->TXD.MAXCNT = 0; - } else { - spis->TXD.PTR = (uint32_t)spi->nhs_txbuf; - spis->TXD.MAXCNT = spi->nhs_buflen; - } - - if (spi->nhs_rxbuf == NULL) { - spis->RXD.PTR = 0; - spis->RXD.MAXCNT = 0; - } else { - spis->RXD.PTR = (uint32_t)spi->nhs_rxbuf; - spis->RXD.MAXCNT = spi->nhs_buflen; - } - spis->TASKS_RELEASE = 1; - spi->slave_state = HAL_SPI_SLAVE_STATE_READY; - } - } - - /* SPI transaction complete */ - if (spis->EVENTS_END) { - spis->EVENTS_END = 0; - if (spi->slave_state == HAL_SPI_SLAVE_STATE_READY) { - if (spi->txrx_cb_func) { - /* Get transfer length */ - if (spi->nhs_txbuf == NULL) { - xfr_len = spis->RXD.AMOUNT; - } else { - xfr_len = spis->TXD.AMOUNT; - } - spi->txrx_cb_func(spi->txrx_cb_arg, xfr_len); - } - spi->slave_state = HAL_SPI_SLAVE_STATE_IDLE; - } - } - -} -#endif - -/* Interrupt handlers for SPI ports */ -#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE) -void -nrf5340_spi0_irq_handler(void) -{ - os_trace_isr_enter(); - if (nrf5340_hal_spi0.spi_type == HAL_SPI_TYPE_MASTER) { -#if MYNEWT_VAL(SPI_0_MASTER) - nrf5340_irqm_handler(&nrf5340_hal_spi0); -#endif - } else { -#if MYNEWT_VAL(SPI_0_SLAVE) - nrf5340_irqs_handler(&nrf5340_hal_spi0); -#endif - } - os_trace_isr_exit(); -} -#endif - -#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE) -void -nrf5340_spi1_irq_handler(void) -{ - os_trace_isr_enter(); - if (nrf5340_hal_spi1.spi_type == HAL_SPI_TYPE_MASTER) { -#if MYNEWT_VAL(SPI_1_MASTER) - nrf5340_irqm_handler(&nrf5340_hal_spi1); -#endif - } else { -#if MYNEWT_VAL(SPI_1_SLAVE) - nrf5340_irqs_handler(&nrf5340_hal_spi1); -#endif - } - os_trace_isr_exit(); -} -#endif - -#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE) -void -nrf5340_spi2_irq_handler(void) -{ - os_trace_isr_enter(); - if (nrf5340_hal_spi2.spi_type == HAL_SPI_TYPE_MASTER) { -#if MYNEWT_VAL(SPI_2_MASTER) - nrf5340_irqm_handler(&nrf5340_hal_spi2); -#endif - } else { -#if MYNEWT_VAL(SPI_2_SLAVE) - nrf5340_irqs_handler(&nrf5340_hal_spi2); -#endif - } - os_trace_isr_exit(); -} -#endif - -#if MYNEWT_VAL(SPI_3_MASTER) || MYNEWT_VAL(SPI_3_SLAVE) -void -nrf5340_spi3_irq_handler(void) +hal_spim_nrfx_handler(nrfx_spim_evt_t const *p_event, void *p_context) { - os_trace_isr_enter(); - if (nrf5340_hal_spi3.spi_type == HAL_SPI_TYPE_MASTER) { -#if MYNEWT_VAL(SPI_3_MASTER) - nrf5340_irqm_handler(&nrf5340_hal_spi3); -#endif - } else { -#if MYNEWT_VAL(SPI_3_SLAVE) - nrf5340_irqs_handler(&nrf5340_hal_spi3); -#endif - } - os_trace_isr_exit(); -} -#endif + struct txrx_cb_data *cb_arg = p_context; -#if MYNEWT_VAL(SPI_4_MASTER) -void -nrf5340_spi4_irq_handler(void) -{ - os_trace_isr_enter(); - if (nrf5340_hal_spi4.spi_type == HAL_SPI_TYPE_MASTER) { - nrf5340_irqm_handler(&nrf5340_hal_spi4); - } - os_trace_isr_exit(); -} -#endif - -static void -hal_spi_stop_transfer(NRF_SPIM_Type *spim) -{ - spim->TASKS_STOP = 1; - while (!spim->EVENTS_STOPPED) { - }; - spim->EVENTS_STOPPED = 0; + assert(cb_arg != NULL); + cb_arg->func(cb_arg->arg, p_event->xfer_desc.rx_length); } static int @@ -333,253 +142,125 @@ hal_spi_config_master(struct nrf5340_hal_spi *spi, struct hal_spi_settings *settings) { int rc; - uint32_t nrf_config; - uint32_t frequency; - NRF_SPIM_Type *spim; - NRF_GPIO_Type *port; - uint32_t pin; - - spim = spi->nhs_spi.spim; - memcpy(&spi->spi_cfg, settings, sizeof(*settings)); - - /* - * Configure SCK. NOTE: this is done here in the config API as the data - * mode is not set at init time so we do it here when we configure the SPI. - */ - pin = spim->PSEL.SCK & SPIM_PSEL_SCK_PIN_Msk; - if (spim->PSEL.SCK & SPIM_PSEL_SCK_PORT_Msk) { - port = NRF_P1; - } else { - port = NRF_P0; - } - - if (settings->data_mode <= HAL_SPI_MODE1) { - port->OUTCLR = (1UL << pin); - } else { - port->OUTSET = (1UL << pin); - } - port->PIN_CNF[pin] = - (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos) | - (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos); - - /* Only 8-bit word sizes supported. */ - rc = 0; - switch (settings->word_size) { - case HAL_SPI_WORD_SIZE_8BIT: - break; - default: - rc = EINVAL; - break; - } - - switch (settings->data_mode) { - case HAL_SPI_MODE0: - nrf_config = (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) | - (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos); - break; - case HAL_SPI_MODE1: - nrf_config = (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) | - (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos); - break; - case HAL_SPI_MODE2: - nrf_config = (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) | - (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos); - break; - case HAL_SPI_MODE3: - nrf_config = (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) | - (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos); - break; - default: - nrf_config = 0; - rc = EINVAL; - break; - } - - /* NOTE: msb first is 0 so no check done */ - if (settings->data_order == HAL_SPI_LSB_FIRST) { - nrf_config |= SPIM_CONFIG_ORDER_LsbFirst; - } - spim->CONFIG = nrf_config; + int frequency; + nrfx_spim_config_t spim_config; /* 16 and 32 MHz is only supported on SPI_4_MASTER */ #if defined(SPIM_FREQUENCY_FREQUENCY_M32) && MYNEWT_VAL(SPI_4_MASTER) if (settings->baudrate >= 32000 && spim == NRF_SPIM4) { - frequency = SPIM_FREQUENCY_FREQUENCY_M32; + frequency = 32000000; } else #endif #if defined(SPIM_FREQUENCY_FREQUENCY_M16) && MYNEWT_VAL(SPI_4_MASTER) if (settings->baudrate >= 16000 && spim == NRF_SPIM4) { - frequency = SPIM_FREQUENCY_FREQUENCY_M16; + frequency = 16000000; } else #endif if (settings->baudrate >= 8000) { - frequency = SPIM_FREQUENCY_FREQUENCY_M8; + frequency = 8000000; } else if (settings->baudrate >= 4000) { - frequency = SPIM_FREQUENCY_FREQUENCY_M4; + frequency = 4000000; } else if (settings->baudrate >= 2000) { - frequency = SPIM_FREQUENCY_FREQUENCY_M2; + frequency = 2000000; } else if (settings->baudrate >= 1000) { - frequency = SPIM_FREQUENCY_FREQUENCY_M1; + frequency = 1000000; } else if (settings->baudrate >= 500) { - frequency = SPIM_FREQUENCY_FREQUENCY_K500; + frequency = 500000; } else if (settings->baudrate >= 250) { - frequency = SPIM_FREQUENCY_FREQUENCY_K250; + frequency = 250000; } else if (settings->baudrate >= 125) { - frequency = SPIM_FREQUENCY_FREQUENCY_K125; + frequency = 125000; } else { frequency = 0; - rc = EINVAL; + return EINVAL; } - spim->FREQUENCY = frequency; - - return rc; -} - -static int -hal_spi_config_slave(struct nrf5340_hal_spi *spi, - struct hal_spi_settings *settings) -{ - int rc; - uint32_t nrf_config; - NRF_SPIS_Type *spis; - spis = spi->nhs_spi.spis; - - rc = 0; - switch (settings->data_mode) { - case HAL_SPI_MODE0: - nrf_config = (SPIS_CONFIG_CPOL_ActiveHigh << SPIS_CONFIG_CPOL_Pos) | - (SPIS_CONFIG_CPHA_Leading << SPIS_CONFIG_CPHA_Pos); - break; - case HAL_SPI_MODE1: - nrf_config = (SPIS_CONFIG_CPOL_ActiveHigh << SPIS_CONFIG_CPOL_Pos) | - (SPIS_CONFIG_CPHA_Trailing << SPIS_CONFIG_CPHA_Pos); - break; - case HAL_SPI_MODE2: - nrf_config = (SPIS_CONFIG_CPOL_ActiveLow << SPIS_CONFIG_CPOL_Pos) | - (SPIS_CONFIG_CPHA_Leading << SPIS_CONFIG_CPHA_Pos); - break; - case HAL_SPI_MODE3: - nrf_config = (SPIS_CONFIG_CPOL_ActiveLow << SPIS_CONFIG_CPOL_Pos) | - (SPIS_CONFIG_CPHA_Trailing << SPIS_CONFIG_CPHA_Pos); - break; - default: - nrf_config = 0; - rc = EINVAL; - break; + if (settings->word_size != HAL_SPI_WORD_SIZE_8BIT) { + return EINVAL; } - if (settings->data_order == HAL_SPI_LSB_FIRST) { - nrf_config |= SPIS_CONFIG_ORDER_LsbFirst; - } - spis->CONFIG = nrf_config; + spim_config.miso_pin = spi->miso_pin; + spim_config.mosi_pin = spi->mosi_pin; + spim_config.ss_pin = spi->ss_pin; + spim_config.sck_pin = spi->sck_pin; + spim_config.frequency = frequency; + spim_config.mode = settings->data_mode; + spim_config.bit_order = settings->data_order; + spim_config.miso_pull = NRF_GPIO_PIN_NOPULL; + spim_config.irq_priority = (1 << __NVIC_PRIO_BITS) - 1; + spim_config.skip_psel_cfg = false; + spim_config.skip_gpio_cfg = false; + spim_config.ss_active_high = false; - /* Only 8-bit word sizes supported. */ - switch (settings->word_size) { - case HAL_SPI_WORD_SIZE_8BIT: - break; - default: - rc = EINVAL; - break; + rc = nrfx_spim_init(&spi->nrfx_spi.spim, &spim_config, hal_spim_nrfx_handler, &spi->cb_data); + if (rc != NRFX_SUCCESS) { + return EINVAL; } - return rc; + return 0; } -static int -hal_spi_init_master(struct nrf5340_hal_spi *spi, - struct nrf5340_hal_spi_cfg *cfg, - nrf5340_spi_irq_handler_t handler) +#if MYNEWT_VAL(SPI_0_SLAVE) || MYNEWT_VAL(SPI_1_SLAVE) || \ + MYNEWT_VAL(SPI_2_SLAVE) +static void +hal_spis_nrfx_handler(nrfx_spis_evt_t const *p_event, void *p_context) { - NRF_SPIM_Type *spim; - NRF_GPIO_Type *port; - uint32_t pin; - - /* Configure MOSI */ - port = HAL_GPIO_PORT(cfg->mosi_pin); - pin = HAL_GPIO_INDEX(cfg->mosi_pin); - port->OUTCLR = (1UL << pin); - port->PIN_CNF[pin] = - ((uint32_t)GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos) | - ((uint32_t)GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos); - - /* Configure MISO */ - port = HAL_GPIO_PORT(cfg->miso_pin); - pin = HAL_GPIO_INDEX(cfg->miso_pin); - port->PIN_CNF[pin] = - ((uint32_t)GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) | - ((uint32_t)GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos); - - spim = (NRF_SPIM_Type *)spi->nhs_spi.spim; - spim->PSEL.SCK = cfg->sck_pin; - spim->PSEL.MOSI = cfg->mosi_pin; - spim->PSEL.MISO = cfg->miso_pin; - - spim->INTENCLR = NRF_SPI_IRQ_DISABLE_ALL; - NVIC_SetVector(spi->irq_num, (uint32_t)handler); - NVIC_SetPriority(spi->irq_num, (1 << __NVIC_PRIO_BITS) - 1); - NVIC_ClearPendingIRQ(spi->irq_num); - NVIC_EnableIRQ(spi->irq_num); + struct txrx_cb_data *cb_arg = p_context; + int len; + + assert(cb_arg != NULL); + if (p_event->evt_type == NRFX_SPIS_XFER_DONE) { + /* Driver only allows setting mutual len for both tx and rx. + * tx_amount == 0 means that tx_buffer was set to NULL and + * len value specified while calling hal_spi_txrx_noblock is stored + * in rx_amount. */ + if (p_event->tx_amount == 0) { + len = p_event->rx_amount; + } else { + len = p_event->tx_amount; + } - return 0; + cb_arg->func(cb_arg->arg, len); + } } +#endif static int -hal_spi_init_slave(struct nrf5340_hal_spi *spi, - struct nrf5340_hal_spi_cfg *cfg, - nrf5340_spi_irq_handler_t handler) +hal_spi_config_slave(struct nrf5340_hal_spi *spi, + struct hal_spi_settings *settings) { - NRF_SPIS_Type *spis; - NRF_GPIO_Type *port; - uint32_t pin; - - /* NOTE: making this pin an input is correct! See datasheet */ - port = HAL_GPIO_PORT(cfg->miso_pin); - pin = HAL_GPIO_INDEX(cfg->miso_pin); - port->PIN_CNF[pin] = - ((uint32_t)GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) | - ((uint32_t)GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos); - - port = HAL_GPIO_PORT(cfg->mosi_pin); - pin = HAL_GPIO_INDEX(cfg->mosi_pin); - port->PIN_CNF[pin] = - ((uint32_t)GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) | - ((uint32_t)GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos); - - port = HAL_GPIO_PORT(cfg->ss_pin); - pin = HAL_GPIO_INDEX(cfg->ss_pin); - port->PIN_CNF[pin] = - ((uint32_t)GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) | - ((uint32_t)GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) | - ((uint32_t)GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos); - - port = HAL_GPIO_PORT(cfg->sck_pin); - pin = HAL_GPIO_INDEX(cfg->sck_pin); - port->PIN_CNF[pin] = - ((uint32_t)GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) | - ((uint32_t)GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos); - - spis = (NRF_SPIS_Type *)spi->nhs_spi.spis; - spis->PSEL.SCK = cfg->sck_pin; - spis->PSEL.MOSI = cfg->mosi_pin; - spis->PSEL.MISO = cfg->miso_pin; - spis->PSEL.CSN = cfg->ss_pin; - - /* Disable interrupt and clear any interrupt events */ - spis->INTENCLR = SPIS_INTENSET_ACQUIRED_Msk | SPIS_INTENSET_END_Msk; - spis->EVENTS_END = 0; - spis->EVENTS_ACQUIRED = 0; - - /* Enable END_ACQUIRE shortcut. */ - spis->SHORTS = SPIS_SHORTS_END_ACQUIRE_Msk; - - /* Set interrupt vector and enable IRQ */ - NVIC_SetVector(spi->irq_num, (uint32_t)handler); - NVIC_SetPriority(spi->irq_num, (1 << __NVIC_PRIO_BITS) - 1); - NVIC_ClearPendingIRQ(spi->irq_num); - NVIC_EnableIRQ(spi->irq_num); +#if MYNEWT_VAL(SPI_0_SLAVE) || MYNEWT_VAL(SPI_1_SLAVE) || \ + MYNEWT_VAL(SPI_2_SLAVE) || MYNEWT_VAL(SPI_3_SLAVE) + int rc; + nrfx_spis_config_t spis_config; + /* Only 8-bit word sizes supported. */ + if (settings->word_size != HAL_SPI_WORD_SIZE_8BIT) { + return EINVAL; + } + + spis_config.miso_pin = spi->miso_pin; + spis_config.mosi_pin = spi->mosi_pin; + spis_config.sck_pin = spi->sck_pin; + spis_config.csn_pin = spi->ss_pin; + spis_config.mode = settings->data_mode; + spis_config.bit_order = settings->data_order; + spis_config.miso_drive = NRF_GPIO_PIN_S0S1; + spis_config.csn_pullup = NRF_GPIO_PIN_PULLUP; + spis_config.def = spi->def_tx_val; + spis_config.orc = spi->def_tx_val; + spis_config.irq_priority = (1 << __NVIC_PRIO_BITS) - 1; + spis_config.skip_gpio_cfg = false; + spis_config.skip_psel_cfg = false; + + rc = nrfx_spis_init(&spi->nrfx_spi.spis, &spis_config, hal_spis_nrfx_handler, &spi->cb_data); + if (rc != NRFX_SUCCESS) { + return EINVAL; + } return 0; +#else + return SYS_ENOTSUP; +#endif } /** @@ -598,7 +279,7 @@ hal_spi_init(int spi_num, void *cfg, uint8_t spi_type) { int rc; struct nrf5340_hal_spi *spi; - nrf5340_spi_irq_handler_t irq_handler; + struct nrf5340_hal_spi_cfg *pins; NRF5340_HAL_SPI_RESOLVE(spi_num, spi); @@ -612,21 +293,21 @@ hal_spi_init(int spi_num, void *cfg, uint8_t spi_type) goto err; } - irq_handler = NULL; spi->spi_type = spi_type; if (spi_num == 0) { #if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE) - spi->irq_num = SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn; - irq_handler = nrf5340_spi0_irq_handler; if (spi_type == HAL_SPI_TYPE_MASTER) { #if MYNEWT_VAL(SPI_0_MASTER) - spi->nhs_spi.spim = NRF_SPIM0_S; + spi->nrfx_spi.spim.p_reg = NRF_SPIM0_S; #else assert(0); #endif } else { #if MYNEWT_VAL(SPI_0_SLAVE) - spi->nhs_spi.spis = NRF_SPIS0_S; + + NVIC_SetVector(nrfx_get_irq_number(NRF_SPIS0_S), + (uint32_t)nrfx_spis_0_irq_handler); + spi->nrfx_spi.spis.p_reg = NRF_SPIS0_S; #else assert(0); #endif @@ -637,16 +318,15 @@ hal_spi_init(int spi_num, void *cfg, uint8_t spi_type) } else if (spi_num == 1) { #if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE) spi->irq_num = SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQn; - irq_handler = nrf5340_spi1_irq_handler; if (spi_type == HAL_SPI_TYPE_MASTER) { #if MYNEWT_VAL(SPI_1_MASTER) - spi->nhs_spi.spim = NRF_SPIM1_S; + spi->nrfx_spi.spim.p_reg = NRF_SPIM1_S; #else assert(0); #endif } else { #if MYNEWT_VAL(SPI_1_SLAVE) - spi->nhs_spi.spis = NRF_SPIS1_S; + spi->nrfx_spi.spis.p_reg = NRF_SPIS1_S; #else assert(0); #endif @@ -657,16 +337,15 @@ hal_spi_init(int spi_num, void *cfg, uint8_t spi_type) } else if (spi_num == 2) { #if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE) spi->irq_num = SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQn; - irq_handler = nrf5340_spi2_irq_handler; if (spi_type == HAL_SPI_TYPE_MASTER) { #if MYNEWT_VAL(SPI_2_MASTER) - spi->nhs_spi.spim = NRF_SPIM2_S; + spi->nrfx_spi.spim.p_reg = NRF_SPIM2_S; #else assert(0); #endif } else { #if MYNEWT_VAL(SPI_2_SLAVE) - spi->nhs_spi.spis = NRF_SPIS2_S; + spi->nrfx_spi.spis.p_reg = NRF_SPIS2_S; #else assert(0); #endif @@ -676,17 +355,15 @@ hal_spi_init(int spi_num, void *cfg, uint8_t spi_type) #endif } else if (spi_num == 3) { #if MYNEWT_VAL(SPI_3_MASTER) || MYNEWT_VAL(SPI_3_SLAVE) - spi->irq_num = SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQn; - irq_handler = nrf5340_spi3_irq_handler; if (spi_type == HAL_SPI_TYPE_MASTER) { #if MYNEWT_VAL(SPI_3_MASTER) - spi->nhs_spi.spim = NRF_SPIM2_S; + spi->nrfx_spi.spim.p_reg = NRF_SPIM2_S; #else assert(0); #endif } else { #if MYNEWT_VAL(SPI_3_SLAVE) - spi->nhs_spi.spis = NRF_SPIS2_S; + spi->nrfx_spi.spis.p_reg = NRF_SPIS2_S; #else assert(0); #endif @@ -696,10 +373,8 @@ hal_spi_init(int spi_num, void *cfg, uint8_t spi_type) #endif } else if (spi_num == 4) { #if MYNEWT_VAL(SPI_4_MASTER) - spi->irq_num = SPIM4_IRQn; - irq_handler = nrf5340_spi4_irq_handler; if (spi_type == HAL_SPI_TYPE_MASTER) { - spi->nhs_spi.spim = NRF_SPIM4_S; + spi->nrfx_spi.spim.p_reg = NRF_SPIM4_S; } else { assert(0); } @@ -715,13 +390,11 @@ hal_spi_init(int spi_num, void *cfg, uint8_t spi_type) goto err; } - if (spi_type == HAL_SPI_TYPE_MASTER) { - rc = hal_spi_init_master(spi, (struct nrf5340_hal_spi_cfg *)cfg, - irq_handler); - } else { - rc = hal_spi_init_slave(spi, (struct nrf5340_hal_spi_cfg *)cfg, - irq_handler); - } + pins = (struct nrf5340_hal_spi_cfg *)cfg; + spi->sck_pin = pins->sck_pin; + spi->ss_pin = pins->ss_pin; + spi->mosi_pin = pins->mosi_pin; + spi->miso_pin = pins->miso_pin; err: return (rc); @@ -758,17 +431,21 @@ hal_spi_config(int spi_num, struct hal_spi_settings *settings) { int rc; struct nrf5340_hal_spi *spi; - NRF_SPIM_Type *spim; NRF5340_HAL_SPI_RESOLVE(spi_num, spi); - /* - * This looks odd, but the ENABLE register is in the same location for - * SPIM and SPIS - */ - spim = spi->nhs_spi.spim; - if (spim->ENABLE != 0) { - return -1; + if (spi->spi_type == HAL_SPI_TYPE_MASTER) { + if (nrf_spim_enable_check(spi->nrfx_spi.spim.p_reg)) { + return -1; + } + } else { + if (nrf_spis_enable_check(spi->nrfx_spi.spis.p_reg)) { + return -1; + } + } + + if (settings->word_size != HAL_SPI_WORD_SIZE_8BIT) { + return EINVAL; } if (spi->spi_type == HAL_SPI_TYPE_MASTER) { @@ -777,6 +454,8 @@ hal_spi_config(int spi_num, struct hal_spi_settings *settings) rc = hal_spi_config_slave(spi, settings); } + hal_spi_disable(spi_num); + err: return (rc); } @@ -800,21 +479,21 @@ hal_spi_enable(int spi_num) NRF5340_HAL_SPI_RESOLVE(spi_num, spi); - if (spi->txrx_cb_func == NULL) { + if (spi->cb_data.func == NULL) { rc = EINVAL; goto err; } if (spi->spi_type == HAL_SPI_TYPE_MASTER) { - spim = spi->nhs_spi.spim; - spim->EVENTS_END = 0; - spim->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos); + spim = spi->nrfx_spi.spim.p_reg; + nrf_spim_event_clear(spim, NRF_SPIM_EVENT_END); + nrf_spim_enable(spim); } else { - spis = spi->nhs_spi.spis; - spis->EVENTS_END = 0; - spis->EVENTS_ACQUIRED = 0; - spis->INTENSET = SPIS_INTENSET_END_Msk | SPIS_INTENSET_ACQUIRED_Msk; - spis->ENABLE = (SPIS_ENABLE_ENABLE_Enabled << SPIS_ENABLE_ENABLE_Pos); + spis = spi->nrfx_spi.spis.p_reg; + nrf_spis_event_clear(spis, NRF_SPIS_EVENT_END); + nrf_spis_event_clear(spis, NRF_SPIS_EVENT_ACQUIRED); + nrf_spis_int_enable(spis, NRF_SPIS_INT_END_MASK | NRF_SPIS_INT_ACQUIRED_MASK); + nrf_spis_enable(spis); } rc = 0; @@ -835,40 +514,122 @@ hal_spi_disable(int spi_num) { int rc; NRF_SPIS_Type *spis; - NRF_SPIM_Type *spim; struct nrf5340_hal_spi *spi; NRF5340_HAL_SPI_RESOLVE(spi_num, spi); if (spi->spi_type == HAL_SPI_TYPE_MASTER) { - spim = spi->nhs_spi.spim; - spim->INTENCLR = NRF_SPI_IRQ_DISABLE_ALL; - - if (spi->spi_xfr_flag) { - hal_spi_stop_transfer(spim); - spi->spi_xfr_flag = 0; + if (nrfx_spim_init_check(&spi->nrfx_spi.spim)) { + nrfx_spim_abort(&spi->nrfx_spi.spim); } - spim->ENABLE = 0; } else { - spis = spi->nhs_spi.spis; - spis->INTENCLR = NRF_SPI_IRQ_DISABLE_ALL; - spis->EVENTS_END = 0; - spis->EVENTS_ACQUIRED = 0; - spis->ENABLE = 0; + spis = spi->nrfx_spi.spis.p_reg; + nrf_spis_int_disable(spis, NRF_SPIS_ALL_INTS_MASK); + nrf_spis_event_clear(spis, NRF_SPIS_EVENT_END); + nrf_spis_event_clear(spis, NRF_SPIS_EVENT_ACQUIRED); + nrf_spis_disable(spis); spi->slave_state = HAL_SPI_SLAVE_STATE_IDLE; } - spi->nhs_txbuf = NULL; - spi->nhs_rxbuf = NULL; - spi->nhs_buflen = 0; - spi->nhs_bytes_txd = 0; - rc = 0; err: return rc; } +/** + * Blocking call to send a value on the SPI. Returns the value received from the + * SPI slave. + * + * MASTER: Sends the value and returns the received value from the slave. + * SLAVE: Invalid API. Returns 0xFFFF + * + * @param spi_num Spi interface to use + * @param val Value to send + * + * @return uint16_t Value received on SPI interface from slave. Returns 0xFFFF + * if called when the SPI is configured to be a slave + */ +uint16_t hal_spi_tx_val(int spi_num, uint16_t val) +{ + int rc; + uint16_t txval; + uint16_t retval; + struct nrf5340_hal_spi *hal_spi; + + NRF5340_HAL_SPI_RESOLVE(spi_num, hal_spi); + + if (hal_spi->spi_type == HAL_SPI_TYPE_MASTER) { + txval = val; + rc = hal_spi_txrx(spi_num, &txval, &retval, 2); + if (rc) { + goto err; + } + } else { + retval = 0xFFFF; + } + + return retval; + + err: + return rc; +} + +int +hal_spi_txrx(int spi_num, void *txbuf, void *rxbuf, int len) +{ + int rc; + int nrfx_rxlen; + int nrfx_txlen; + nrfx_spim_t *spim; + struct nrf5340_hal_spi *hal_spi; + nrfx_spim_xfer_desc_t xfer_desc; + + rc = -1; + /* Must have txbuf or rxbuf */ + if ((txbuf == NULL) && (rxbuf == NULL)) { + goto err; + } + + if ((rxbuf != NULL && !nrfx_is_in_ram(rxbuf)) || + (txbuf != NULL && !nrfx_is_in_ram(txbuf))) { + goto err; + } + + if ((len == 0) || (len > SPIM_TXD_MAXCNT_MAX)) { + goto err; + } + + if (rxbuf == NULL) { + nrfx_rxlen = 0; + } else { + nrfx_rxlen = len; + } + if (txbuf == NULL) { + nrfx_txlen = 0; + } else { + nrfx_txlen = len; + } + + NRF5340_HAL_SPI_RESOLVE(spi_num, hal_spi); + + if (hal_spi->spi_type == HAL_SPI_TYPE_MASTER) { + spim = &hal_spi->nrfx_spi.spim; + + xfer_desc.p_tx_buffer = txbuf; + xfer_desc.p_rx_buffer = rxbuf; + xfer_desc.rx_length = nrfx_rxlen; + xfer_desc.tx_length = nrfx_txlen; + nrfx_spim_xfer(spim, &xfer_desc, NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER); + while (nrf_spim_event_check(spim->p_reg, NRF_SPIM_EVENT_END)) {}; + + return 0; + } + + err: + return rc; +} + /** * Sets the txrx callback (executed at interrupt context) when the * buffer is transferred by the master or the slave using the non-blocking API. @@ -888,28 +649,59 @@ int hal_spi_set_txrx_cb(int spi_num, hal_spi_txrx_cb txrx_cb, void *arg) { int rc; - NRF_SPIM_Type *spim; struct nrf5340_hal_spi *spi; NRF5340_HAL_SPI_RESOLVE(spi_num, spi); - /* - * This looks odd, but the ENABLE register is in the same location for - * SPIM and SPIS - */ - spim = spi->nhs_spi.spim; - if (spim->ENABLE != 0) { - rc = -1; + if (spi->spi_type == HAL_SPI_TYPE_MASTER) { + if (nrf_spim_enable_check(spi->nrfx_spi.spim.p_reg)) { + rc = -1; + goto err; + } } else { - spi->txrx_cb_func = txrx_cb; - spi->txrx_cb_arg = arg; - rc = 0; + if (nrf_spis_enable_check(spi->nrfx_spi.spis.p_reg)) { + rc = -1; + goto err; + } } + spi->cb_data.func = txrx_cb; + spi->cb_data.arg = arg; + rc = 0; err: return rc; } +static inline nrfx_err_t +hal_spis_txrx_noblock(nrfx_spis_t *spis, void *txbuf, int txlen, + void *rxbuf, int rxlen) +{ +#if MYNEWT_VAL(SPI_0_SLAVE) || MYNEWT_VAL(SPI_1_SLAVE) || \ + MYNEWT_VAL(SPI_2_SLAVE) || MYNEWT_VAL(SPI_3_SLAVE) + return nrfx_spis_buffers_set(spis, txbuf, txlen, rxbuf, rxlen); +#else + return ENOTSUP; +#endif +} + +static inline nrfx_err_t +hal_spim_txrx_noblock(nrfx_spim_t *spim, void *txbuf, int txlen, + void *rxbuf, int rxlen) +{ + nrfx_spim_xfer_desc_t xfer_desc; + +#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_1_MASTER) || \ + MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_3_MASTER) || MYNEWT_VAL(SPI_4_MASTER) + xfer_desc.p_tx_buffer = txbuf; + xfer_desc.p_rx_buffer = rxbuf; + xfer_desc.rx_length = rxlen; + xfer_desc.tx_length = txlen; + return nrfx_spim_xfer(spim, &xfer_desc, 0); +#else + return ENOTSUP; +#endif +} + /** * Non-blocking interface to send a buffer and store received values. Can be * used for both master and slave SPI types. The user must configure the @@ -946,72 +738,53 @@ int hal_spi_txrx_noblock(int spi_num, void *txbuf, void *rxbuf, int len) { int rc; - NRF_SPIM_Type *spim; + int nrfx_rxlen; + int nrfx_txlen; + nrfx_spim_t *spim; + nrfx_spis_t *spis; struct nrf5340_hal_spi *spi; rc = EINVAL; NRF5340_HAL_SPI_RESOLVE(spi_num, spi); - if ((spi->txrx_cb_func == NULL) || (len == 0) || !nrfx_is_in_ram(txbuf)) { + /* Must have txbuf or rxbuf */ + if ((txbuf == NULL) && (rxbuf == NULL)) { goto err; } - if (rxbuf != NULL && !nrfx_is_in_ram(rxbuf)) { + if ((rxbuf != NULL && !nrfx_is_in_ram(rxbuf)) || + (txbuf != NULL && !nrfx_is_in_ram(txbuf))) { goto err; } - if (spi->spi_type == HAL_SPI_TYPE_MASTER) { - /* Must have a txbuf for master! */ - if (txbuf == NULL) { - goto err; - } - - /* Not allowed if transfer in progress */ - if (spi->spi_xfr_flag) { - rc = -1; - goto err; - } - spim = spi->nhs_spi.spim; - - spim->INTENCLR = SPIM_INTENCLR_END_Msk; - spi->spi_xfr_flag = 1; - - /* Set internal data structure information */ - spi->nhs_bytes_txd = 0; - spi->nhs_buflen = len; - spi->nhs_txbuf = txbuf; - - len = min(SPIM_TXD_MAXCNT_MAX, len); - - /* Set chip registers */ - spim->TXD.PTR = (uint32_t)txbuf; - spim->TXD.MAXCNT = len; + if ((len == 0) || (len > SPIM_TXD_MAXCNT_MAX)) { + goto err; + } - /* If no rxbuf, we need to set rxbuf and maxcnt to 1 */ - spi->nhs_rxbuf = rxbuf; - if (rxbuf == NULL) { - spim->RXD.PTR = (uint32_t)&spi->dummy_rx; - spim->RXD.MAXCNT = 1; - } else { - spim->RXD.PTR = (uint32_t)rxbuf; - spim->RXD.MAXCNT = len; - } + if (spi->cb_data.func == NULL) { + goto err; + } - spim->EVENTS_END = 0; - spim->EVENTS_STOPPED = 0; - spim->TASKS_START = 1; - spim->INTENSET = SPIM_INTENSET_END_Msk; + if (rxbuf == NULL) { + nrfx_rxlen = 0; } else { - /* Must have txbuf or rxbuf */ - if ((txbuf == NULL) && (rxbuf == NULL)) { - goto err; - } + nrfx_rxlen = len; + } + if (txbuf == NULL) { + nrfx_txlen = 0; + } else { + nrfx_txlen = len; + } - /* XXX: what to do here? */ - if (len > 255) { + if (spi->spi_type == HAL_SPI_TYPE_MASTER) { + spim = &spi->nrfx_spi.spim; + + rc = hal_spim_txrx_noblock(spim, txbuf, nrfx_txlen, rxbuf, nrfx_rxlen); + if (rc != NRFX_SUCCESS) { + rc = -1; goto err; } - + } else { /* * Ready the slave for a transfer. Do not allow this to be called * if the slave has already been readied or is requesting the @@ -1021,12 +794,12 @@ hal_spi_txrx_noblock(int spi_num, void *txbuf, void *rxbuf, int len) rc = -1; goto err; } - - spi->nhs_rxbuf = rxbuf; - spi->nhs_txbuf = txbuf; - spi->nhs_buflen = len; - spi->slave_state = HAL_SPI_SLAVE_STATE_ACQ_SEM; - spi->nhs_spi.spis->TASKS_ACQUIRE = 1; + spis = &spi->nrfx_spi.spis; + rc = hal_spis_txrx_noblock(spis, txbuf, nrfx_txlen, rxbuf, nrfx_rxlen); + if (rc != NRFX_SUCCESS) { + rc = -1; + goto err; + } } return 0; @@ -1045,14 +818,15 @@ int hal_spi_slave_set_def_tx_val(int spi_num, uint16_t val) { int rc; - NRF_SPIS_Type *spis; + nrfx_spis_t *spis; struct nrf5340_hal_spi *spi; NRF5340_HAL_SPI_RESOLVE(spi_num, spi); - if (spi->spi_type == HAL_SPI_TYPE_SLAVE) { - spis = spi->nhs_spi.spis; - spis->DEF = (uint8_t)val; - spis->ORC = (uint8_t)val; + if (spi->spi_type == HAL_SPI_TYPE_SLAVE) { + spis = &spi->nrfx_spi.spis; + spi->def_tx_val = (uint8_t)val; + nrf_spis_orc_set(spis->p_reg, spi->def_tx_val); + nrf_spis_def_set(spis->p_reg, spi->def_tx_val); rc = 0; } else { rc = EINVAL; @@ -1075,30 +849,15 @@ int hal_spi_abort(int spi_num) { int rc; - NRF_SPIM_Type *spim; + nrfx_spim_t *spim; struct nrf5340_hal_spi *spi; NRF5340_HAL_SPI_RESOLVE(spi_num, spi); rc = 0; if (spi->spi_type == HAL_SPI_TYPE_MASTER) { - spim = spi->nhs_spi.spim; - if (spi->spi_xfr_flag) { - spim->INTENCLR = NRF_SPI_IRQ_DISABLE_ALL; - hal_spi_stop_transfer(spim); - spi->spi_xfr_flag = 0; - spim->INTENSET = SPIM_INTENSET_END_Msk; - } - } else { - /* Only way I can see doing this is to disable, then re-enable */ - rc = hal_spi_disable(spi_num); - if (rc) { - goto err; - } - rc = hal_spi_enable(spi_num); - if (rc) { - goto err; - } + spim = &spi->nrfx_spi.spim; + nrfx_spim_abort(spim); } err: diff --git a/hw/mcu/nordic/nrf5340/startup/src/arch/cortex_m33/gcc_startup_nrf5340.s b/hw/mcu/nordic/nrf5340/startup/src/arch/cortex_m33/gcc_startup_nrf5340.s index 9a45847c5c..256ae2fae1 100644 --- a/hw/mcu/nordic/nrf5340/startup/src/arch/cortex_m33/gcc_startup_nrf5340.s +++ b/hw/mcu/nordic/nrf5340/startup/src/arch/cortex_m33/gcc_startup_nrf5340.s @@ -21,6 +21,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. */ #include "syscfg/syscfg.h" +#include "nrf5340_application_name_change.h" .syntax unified .arch armv8-m.main