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There is almost always a 1-tick delay associated with a tristate buffer's state changing, but not always. Inputs that come from above never have any delay, nor does the uppermost/first of inputs coming from the left. This holds true whether it's one contiguous/solid row of tristate buffers, or separate ones with connected outputs - but multiple sets of tristate buffers that do not share an output behave independently.
Here's a simple demonstration, and here's a more in-depth exploration, along with an example of abusing this.
The text was updated successfully, but these errors were encountered:
There is almost always a 1-tick delay associated with a tristate buffer's state changing, but not always. Inputs that come from above never have any delay, nor does the uppermost/first of inputs coming from the left. This holds true whether it's one contiguous/solid row of tristate buffers, or separate ones with connected outputs - but multiple sets of tristate buffers that do not share an output behave independently.
Here's a simple demonstration, and here's a more in-depth exploration, along with an example of abusing this.
The text was updated successfully, but these errors were encountered: