diff --git a/docs/04_cv32a65x_design/source/parameters_cv32a65x.rst b/docs/04_cv32a65x_design/source/parameters_cv32a65x.rst index f49970bcf8..db048cd7f3 100644 --- a/docs/04_cv32a65x_design/source/parameters_cv32a65x.rst +++ b/docs/04_cv32a65x_design/source/parameters_cv32a65x.rst @@ -16,6 +16,14 @@ - description - Value + * - XLEN + - General Purpose Register Size (in bits) + - 32 + + * - FPGA_EN + - Is FPGA optimization of CV32A6 + - 0 + * - NrCommitPorts - Number of commit ports - 1 @@ -80,6 +88,10 @@ - Zcb RISC-V extension - 1 + * - RVZCMP + - Zcmp RISC-V extension + - 0 + * - XFVec - Non standard Vector Floating Point - 0 @@ -100,6 +112,10 @@ - User mode - 0 + * - NrScoreboardEntries + - Scoreboard length + - 4 + * - HaltAddress - Address to jump when halt request - 64'h800 @@ -195,3 +211,39 @@ * - AxiBurstWriteEn - AXI burst in write - 0 + + * - IcacheByteSize + - Instruction cache size (in bytes) + - 2048 + + * - IcacheSetAssoc + - Instruction cache associativity (number of ways) + - 2 + + * - IcacheLineWidth + - Instruction line width + - 128 + + * - DcacheByteSize + - Data cache size (in bytes) + - 32768 + + * - DcacheSetAssoc + - Data cache associativity (number of ways) + - 8 + + * - DcacheLineWidth + - Data line width + - 128 + + * - DataUserEn + - TODO + - 0 + + * - FetchUserWidth + - TODO + - 32 + + * - FetchUserEn + - TODO + - 0 diff --git a/docs/04_cv32a65x_design/source/port_alu.rst b/docs/04_cv32a65x_design/source/port_alu.rst index c6cea25699..6da09d56b7 100644 --- a/docs/04_cv32a65x_design/source/port_alu.rst +++ b/docs/04_cv32a65x_design/source/port_alu.rst @@ -40,7 +40,7 @@ - out - ALU result - ISSUE_STAGE - - riscv::xlen_t + - logic[CVA6Cfg.XLEN-1:0] * - ``alu_branch_res_o`` - out diff --git a/docs/04_cv32a65x_design/source/port_bht.rst b/docs/04_cv32a65x_design/source/port_bht.rst index 918ae6adfe..d4d01001da 100644 --- a/docs/04_cv32a65x_design/source/port_bht.rst +++ b/docs/04_cv32a65x_design/source/port_bht.rst @@ -34,7 +34,7 @@ - in - Virtual PC - CACHE - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] * - ``bht_update_i`` - in @@ -46,7 +46,7 @@ - out - Prediction from bht - FRONTEND - - ariane_pkg::bht_prediction_t[ariane_pkg::INSTR_PER_FETCH-1:0] + - ariane_pkg::bht_prediction_t[CVA6Cfg.INSTR_PER_FETCH-1:0] Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below diff --git a/docs/04_cv32a65x_design/source/port_branch_unit.rst b/docs/04_cv32a65x_design/source/port_branch_unit.rst index a1f7574a4f..b34d47860d 100644 --- a/docs/04_cv32a65x_design/source/port_branch_unit.rst +++ b/docs/04_cv32a65x_design/source/port_branch_unit.rst @@ -40,7 +40,7 @@ - in - Instruction PC - ISSUE_STAGE - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] * - ``is_compressed_instr_i`` - in @@ -70,7 +70,7 @@ - out - Brach unit result - ISSUE_STAGE - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] * - ``branch_predict_i`` - in diff --git a/docs/04_cv32a65x_design/source/port_btb.rst b/docs/04_cv32a65x_design/source/port_btb.rst index f40ecedce3..24111b7fee 100644 --- a/docs/04_cv32a65x_design/source/port_btb.rst +++ b/docs/04_cv32a65x_design/source/port_btb.rst @@ -34,7 +34,7 @@ - in - Virtual PC - CACHE - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] * - ``btb_update_i`` - in @@ -46,7 +46,7 @@ - out - BTB Prediction - FRONTEND - - btb_prediction_t[ariane_pkg::INSTR_PER_FETCH-1:0] + - btb_prediction_t[CVA6Cfg.INSTR_PER_FETCH-1:0] Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below diff --git a/docs/04_cv32a65x_design/source/port_commit_stage.rst b/docs/04_cv32a65x_design/source/port_commit_stage.rst index 496772fee9..debb281f76 100644 --- a/docs/04_cv32a65x_design/source/port_commit_stage.rst +++ b/docs/04_cv32a65x_design/source/port_commit_stage.rst @@ -60,6 +60,12 @@ - ISSUE_STAGE - logic[CVA6Cfg.NrCommitPorts-1:0] + * - ``commit_macro_ack_o`` + - out + - Acknowledge that we are indeed committing + - CSR_REGFILE + - logic[CVA6Cfg.NrCommitPorts-1:0] + * - ``waddr_o`` - out - Register file write address @@ -70,7 +76,7 @@ - out - Register file write data - ISSUE_STAGE - - logic[CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] + - logic[CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] * - ``we_gpr_o`` - out @@ -88,7 +94,7 @@ - out - TO_BE_COMPLETED - FRONTEND_CSR_REGFILE - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] * - ``csr_op_o`` - out @@ -100,13 +106,13 @@ - out - Data to write to CSR - CSR_REGFILE - - riscv::xlen_t + - logic[CVA6Cfg.XLEN-1:0] * - ``csr_rdata_i`` - in - Data to read from CSR - CSR_REGFILE - - riscv::xlen_t + - logic[CVA6Cfg.XLEN-1:0] * - ``csr_exception_i`` - in @@ -130,7 +136,7 @@ - out - Transaction id of first commit port - ID_STAGE - - logic[TRANS_ID_BITS-1:0] + - logic[CVA6Cfg.TRANS_ID_BITS-1:0] * - ``no_st_pending_i`` - in diff --git a/docs/04_cv32a65x_design/source/port_compressed_decoder.rst b/docs/04_cv32a65x_design/source/port_compressed_decoder.rst index 99d55c4ecd..4a5cdb30cf 100644 --- a/docs/04_cv32a65x_design/source/port_compressed_decoder.rst +++ b/docs/04_cv32a65x_design/source/port_compressed_decoder.rst @@ -36,6 +36,12 @@ - decoder - logic + * - ``is_macro_instr_o`` + - out + - Output instruction is macro + - decoder + - logic + * - ``is_compressed_o`` - out - Output instruction is compressed diff --git a/docs/04_cv32a65x_design/source/port_csr_buffer.rst b/docs/04_cv32a65x_design/source/port_csr_buffer.rst index c50d72cb1b..e83ad5e34a 100644 --- a/docs/04_cv32a65x_design/source/port_csr_buffer.rst +++ b/docs/04_cv32a65x_design/source/port_csr_buffer.rst @@ -58,7 +58,7 @@ - out - CSR buffer result - ISSUE_STAGE - - riscv::xlen_t + - logic[CVA6Cfg.XLEN-1:0] * - ``csr_commit_i`` - in diff --git a/docs/04_cv32a65x_design/source/port_csr_regfile.rst b/docs/04_cv32a65x_design/source/port_csr_regfile.rst index 7524f40392..3a6814396e 100644 --- a/docs/04_cv32a65x_design/source/port_csr_regfile.rst +++ b/docs/04_cv32a65x_design/source/port_csr_regfile.rst @@ -64,13 +64,13 @@ - in - Address from which to start booting, mtvec is set to the same address - SUBSYSTEM - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] * - ``hart_id_i`` - in - Hart id in a multicore environment (reflected in a CSR) - SUBSYSTEM - - logic[riscv::XLEN-1:0] + - logic[CVA6Cfg.XLEN-1:0] * - ``ex_i`` - in @@ -94,19 +94,19 @@ - in - Write data in - COMMIT_STAGE - - logic[riscv::XLEN-1:0] + - logic[CVA6Cfg.XLEN-1:0] * - ``csr_rdata_o`` - out - Read data out - COMMIT_STAGE - - logic[riscv::XLEN-1:0] + - logic[CVA6Cfg.XLEN-1:0] * - ``pc_i`` - in - PC of instruction accessing the CSR - COMMIT_STAGE - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] * - ``csr_exception_o`` - out @@ -118,7 +118,7 @@ - out - Output the exception PC to PC Gen, the correct CSR (mepc, sepc) is set accordingly - FRONTEND - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] * - ``eret_o`` - out @@ -130,7 +130,7 @@ - out - Output base of exception vector, correct CSR is output (mtvec, stvec) - FRONTEND - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] * - ``irq_ctrl_o`` - out diff --git a/docs/04_cv32a65x_design/source/port_cva6.rst b/docs/04_cv32a65x_design/source/port_cva6.rst index 7ea51ae6a9..60828c4d68 100644 --- a/docs/04_cv32a65x_design/source/port_cva6.rst +++ b/docs/04_cv32a65x_design/source/port_cva6.rst @@ -34,13 +34,13 @@ - in - Reset boot address - SUBSYSTEM - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] * - ``hart_id_i`` - in - Hard ID reflected as CSR - SUBSYSTEM - - logic[riscv::XLEN-1:0] + - logic[CVA6Cfg.XLEN-1:0] * - ``irq_i`` - in diff --git a/docs/04_cv32a65x_design/source/port_cva6_hpdcache_subsystem.rst b/docs/04_cv32a65x_design/source/port_cva6_hpdcache_subsystem.rst index 15fb0ca2e6..225dc34f64 100644 --- a/docs/04_cv32a65x_design/source/port_cva6_hpdcache_subsystem.rst +++ b/docs/04_cv32a65x_design/source/port_cva6_hpdcache_subsystem.rst @@ -58,25 +58,25 @@ - in - Input address translation request - EX_STAGE - - ariane_pkg::icache_areq_t + - icache_areq_t * - ``icache_areq_o`` - out - Output address translation request - EX_STAGE - - ariane_pkg::icache_arsp_t + - icache_arsp_t * - ``icache_dreq_i`` - in - Input data translation request - FRONTEND - - ariane_pkg::icache_dreq_t + - icache_dreq_t * - ``icache_dreq_o`` - out - Output data translation request - FRONTEND - - ariane_pkg::icache_drsp_t + - icache_drsp_t * - ``dcache_enable_i`` - in @@ -112,13 +112,13 @@ - in - Data cache input request ports - EX_STAGE - - ariane_pkg::dcache_req_i_t[NumPorts-1:0] + - dcache_req_i_t[NumPorts-1:0] * - ``dcache_req_ports_o`` - out - Data cache output request ports - EX_STAGE - - ariane_pkg::dcache_req_o_t[NumPorts-1:0] + - dcache_req_o_t[NumPorts-1:0] * - ``wbuffer_empty_o`` - out diff --git a/docs/04_cv32a65x_design/source/port_cvxif_fu.rst b/docs/04_cv32a65x_design/source/port_cvxif_fu.rst index 7d71c3e1c3..7e481a15a4 100644 --- a/docs/04_cv32a65x_design/source/port_cvxif_fu.rst +++ b/docs/04_cv32a65x_design/source/port_cvxif_fu.rst @@ -58,7 +58,7 @@ - out - CVXIF transaction ID - ISSUE_STAGE - - logic[TRANS_ID_BITS-1:0] + - logic[CVA6Cfg.TRANS_ID_BITS-1:0] * - ``x_exception_o`` - out @@ -70,7 +70,7 @@ - out - CVXIF FU result - ISSUE_STAGE - - riscv::xlen_t + - logic[CVA6Cfg.XLEN-1:0] * - ``x_valid_o`` - out diff --git a/docs/04_cv32a65x_design/source/port_decoder.rst b/docs/04_cv32a65x_design/source/port_decoder.rst index 30772b20af..27b12103d5 100644 --- a/docs/04_cv32a65x_design/source/port_decoder.rst +++ b/docs/04_cv32a65x_design/source/port_decoder.rst @@ -22,7 +22,7 @@ - in - PC from fetch stage - FRONTEND - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] * - ``is_compressed_i`` - in @@ -48,6 +48,24 @@ - FRONTEND - logic[31:0] + * - ``is_macro_instr_i`` + - in + - Is a macro instruction + - macro_decoder + - logic + + * - ``is_last_macro_instr_i`` + - in + - Is a last macro instruction + - macro_decoder + - logic + + * - ``is_double_rd_macro_instr_i`` + - in + - Is mvsa01/mva01s macro instruction + - macro_decoder + - logic + * - ``branch_predict_i`` - in - Is a branch predict instruction diff --git a/docs/04_cv32a65x_design/source/port_ex_stage.rst b/docs/04_cv32a65x_design/source/port_ex_stage.rst index 8799172d55..5fe790dcfd 100644 --- a/docs/04_cv32a65x_design/source/port_ex_stage.rst +++ b/docs/04_cv32a65x_design/source/port_ex_stage.rst @@ -40,13 +40,13 @@ - in - rs1 forwarding - ISSUE_STAGE - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] * - ``rs2_forwarding_i`` - in - rs2 forwarding - ISSUE_STAGE - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] * - ``fu_data_i`` - in @@ -58,7 +58,7 @@ - in - PC of the current instruction - ISSUE_STAGE - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] * - ``is_compressed_instr_i`` - in @@ -70,13 +70,13 @@ - out - Fixed Latency Unit result - ISSUE_STAGE - - riscv::xlen_t + - logic[CVA6Cfg.XLEN-1:0] * - ``flu_trans_id_o`` - out - ID of the scoreboard entry at which a=to write back - ISSUE_STAGE - - logic[TRANS_ID_BITS-1:0] + - logic[CVA6Cfg.TRANS_ID_BITS-1:0] * - ``flu_exception_o`` - out @@ -172,13 +172,13 @@ - out - Load result valid - ISSUE_STAGE - - riscv::xlen_t + - logic[CVA6Cfg.XLEN-1:0] * - ``load_trans_id_o`` - out - Load instruction ID - ISSUE_STAGE - - logic[TRANS_ID_BITS-1:0] + - logic[CVA6Cfg.TRANS_ID_BITS-1:0] * - ``load_exception_o`` - out @@ -196,13 +196,13 @@ - out - Store result - ISSUE_STAGE - - riscv::xlen_t + - logic[CVA6Cfg.XLEN-1:0] * - ``store_trans_id_o`` - out - Store instruction ID - ISSUE_STAGE - - logic[TRANS_ID_BITS-1:0] + - logic[CVA6Cfg.TRANS_ID_BITS-1:0] * - ``store_exception_o`` - out @@ -226,7 +226,7 @@ - in - Commit transaction ID - COMMIT_STAGE - - logic[TRANS_ID_BITS-1:0] + - logic[CVA6Cfg.TRANS_ID_BITS-1:0] * - ``no_st_pending_o`` - out @@ -256,7 +256,7 @@ - out - CVXIF transaction ID - ISSUE_STAGE - - logic[TRANS_ID_BITS-1:0] + - logic[CVA6Cfg.TRANS_ID_BITS-1:0] * - ``x_exception_o`` - out @@ -268,7 +268,7 @@ - out - CVXIF result - ISSUE_STAGE - - riscv::xlen_t + - logic[CVA6Cfg.XLEN-1:0] * - ``x_valid_o`` - out @@ -340,7 +340,7 @@ - in - Report the PMP addresses - CSR_REGFILE - - logic[15:0][riscv::PLEN-3:0] + - logic[15:0][CVA6Cfg.PLEN-3:0] Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below diff --git a/docs/04_cv32a65x_design/source/port_frontend.rst b/docs/04_cv32a65x_design/source/port_frontend.rst index 5bd70dcb48..a2a10c0681 100644 --- a/docs/04_cv32a65x_design/source/port_frontend.rst +++ b/docs/04_cv32a65x_design/source/port_frontend.rst @@ -34,7 +34,7 @@ - in - Next PC when reset - SUBSYSTEM - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] * - ``flush_i`` - in @@ -58,7 +58,7 @@ - in - COMMIT PC - COMMIT - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] * - ``ex_valid_i`` - in @@ -82,13 +82,13 @@ - in - Next PC when returning from exception - CSR - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] * - ``trap_vector_base_i`` - in - Next PC when jumping into exception - CSR - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] * - ``icache_dreq_o`` - out diff --git a/docs/04_cv32a65x_design/source/port_instr_queue.rst b/docs/04_cv32a65x_design/source/port_instr_queue.rst index 3b13a9369f..e43f04996a 100644 --- a/docs/04_cv32a65x_design/source/port_instr_queue.rst +++ b/docs/04_cv32a65x_design/source/port_instr_queue.rst @@ -40,19 +40,19 @@ - in - Instruction - instr_realign - - logic[ariane_pkg::INSTR_PER_FETCH-1:0][31:0] + - logic[CVA6Cfg.INSTR_PER_FETCH-1:0][31:0] * - ``addr_i`` - in - Instruction address - instr_realign - - logic[ariane_pkg::INSTR_PER_FETCH-1:0][riscv::VLEN-1:0] + - logic[CVA6Cfg.INSTR_PER_FETCH-1:0][CVA6Cfg.VLEN-1:0] * - ``valid_i`` - in - Instruction is valid - instr_realign - - logic[ariane_pkg::INSTR_PER_FETCH-1:0] + - logic[CVA6Cfg.INSTR_PER_FETCH-1:0] * - ``ready_o`` - out @@ -64,7 +64,7 @@ - out - Indicates instructions consummed, or popped by ID_STAGE - FRONTEND - - logic[ariane_pkg::INSTR_PER_FETCH-1:0] + - logic[CVA6Cfg.INSTR_PER_FETCH-1:0] * - ``exception_i`` - in @@ -76,19 +76,19 @@ - in - Exception address - CACHE - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] * - ``predict_address_i`` - in - Branch predict - FRONTEND - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] * - ``cf_type_i`` - in - Instruction predict address - FRONTEND - - ariane_pkg::cf_t[ariane_pkg::INSTR_PER_FETCH-1:0] + - ariane_pkg::cf_t[CVA6Cfg.INSTR_PER_FETCH-1:0] * - ``replay_o`` - out @@ -100,7 +100,7 @@ - out - Address at which to replay the fetch - FRONTEND - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] * - ``fetch_entry_o`` - out diff --git a/docs/04_cv32a65x_design/source/port_instr_realign.rst b/docs/04_cv32a65x_design/source/port_instr_realign.rst index 98f6014881..fef98d99e6 100644 --- a/docs/04_cv32a65x_design/source/port_instr_realign.rst +++ b/docs/04_cv32a65x_design/source/port_instr_realign.rst @@ -52,30 +52,30 @@ - in - 32-bit block address - CACHE - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] * - ``data_i`` - in - 32-bit block - CACHE - - logic[FETCH_WIDTH-1:0] + - logic[CVA6Cfg.FETCH_WIDTH-1:0] * - ``valid_o`` - out - instruction is valid - FRONTEND - - logic[INSTR_PER_FETCH-1:0] + - logic[CVA6Cfg.INSTR_PER_FETCH-1:0] * - ``addr_o`` - out - Instruction address - FRONTEND - - logic[INSTR_PER_FETCH-1:0][riscv::VLEN-1:0] + - logic[CVA6Cfg.INSTR_PER_FETCH-1:0][CVA6Cfg.VLEN-1:0] * - ``instr_o`` - out - Instruction - instr_scan&instr_queue - - logic[INSTR_PER_FETCH-1:0][31:0] + - logic[CVA6Cfg.INSTR_PER_FETCH-1:0][31:0] diff --git a/docs/04_cv32a65x_design/source/port_instr_scan.rst b/docs/04_cv32a65x_design/source/port_instr_scan.rst index f95e363e55..dbc877777e 100644 --- a/docs/04_cv32a65x_design/source/port_instr_scan.rst +++ b/docs/04_cv32a65x_design/source/port_instr_scan.rst @@ -58,7 +58,7 @@ - out - Instruction immediat - FRONTEND - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] * - ``rvc_branch_o`` - out @@ -100,6 +100,6 @@ - out - Instruction compressed immediat - FRONTEND - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] diff --git a/docs/04_cv32a65x_design/source/port_issue_read_operands.rst b/docs/04_cv32a65x_design/source/port_issue_read_operands.rst index 6c43aa94e0..3f7e916bd2 100644 --- a/docs/04_cv32a65x_design/source/port_issue_read_operands.rst +++ b/docs/04_cv32a65x_design/source/port_issue_read_operands.rst @@ -70,7 +70,7 @@ - in - rs1 operand - scoreboard - - riscv::xlen_t + - logic[CVA6Cfg.XLEN-1:0] * - ``rs1_valid_i`` - in @@ -88,7 +88,7 @@ - in - rs2 operand - scoreboard - - riscv::xlen_t + - logic[CVA6Cfg.XLEN-1:0] * - ``rs2_valid_i`` - in @@ -136,19 +136,19 @@ - out - Unregistered version of fu_data_o.operanda - TO_BE_COMPLETED - - riscv::xlen_t + - logic[CVA6Cfg.XLEN-1:0] * - ``rs2_forwarding_o`` - out - Unregistered version of fu_data_o.operandb - TO_BE_COMPLETED - - riscv::xlen_t + - logic[CVA6Cfg.XLEN-1:0] * - ``pc_o`` - out - Instruction pc - TO_BE_COMPLETED - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] * - ``is_compressed_instr_o`` - out @@ -232,7 +232,7 @@ - in - TO_BE_COMPLETED - TO_BE_COMPLETED - - logic[CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] + - logic[CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] * - ``we_gpr_i`` - in diff --git a/docs/04_cv32a65x_design/source/port_issue_stage.rst b/docs/04_cv32a65x_design/source/port_issue_stage.rst index 9de390d84b..f4904126ab 100644 --- a/docs/04_cv32a65x_design/source/port_issue_stage.rst +++ b/docs/04_cv32a65x_design/source/port_issue_stage.rst @@ -76,13 +76,13 @@ - out - rs1 forwarding - EX_STAGE - - [riscv::VLEN-1:0] + - [CVA6Cfg.VLEN-1:0] * - ``rs2_forwarding_o`` - out - rs2 forwarding - EX_STAGE - - [riscv::VLEN-1:0] + - [CVA6Cfg.VLEN-1:0] * - ``fu_data_o`` - out @@ -94,7 +94,7 @@ - out - Program Counter - EX_STAGE - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] * - ``is_compressed_instr_o`` - out @@ -178,7 +178,7 @@ - in - Transaction ID - EX_STAGE - - logic[CVA6Cfg.NrWbPorts-1:0][TRANS_ID_BITS-1:0] + - logic[CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] * - ``resolved_branch_i`` - in @@ -190,7 +190,7 @@ - in - TO_BE_COMPLETED - EX_STAGE - - logic[CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0] + - logic[CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.XLEN-1:0] * - ``ex_ex_i`` - in @@ -220,7 +220,7 @@ - in - TO_BE_COMPLETED - EX_STAGE - - logic[CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] + - logic[CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] * - ``we_gpr_i`` - in diff --git a/docs/04_cv32a65x_design/source/port_load_store_unit.rst b/docs/04_cv32a65x_design/source/port_load_store_unit.rst index fa85194602..f4f53ece2d 100644 --- a/docs/04_cv32a65x_design/source/port_load_store_unit.rst +++ b/docs/04_cv32a65x_design/source/port_load_store_unit.rst @@ -70,13 +70,13 @@ - out - Load transaction ID - ISSUE_STAGE - - logic[TRANS_ID_BITS-1:0] + - logic[CVA6Cfg.TRANS_ID_BITS-1:0] * - ``load_result_o`` - out - Load result - ISSUE_STAGE - - riscv::xlen_t + - logic[CVA6Cfg.XLEN-1:0] * - ``load_valid_o`` - out @@ -94,13 +94,13 @@ - out - Store transaction ID - ISSUE_STAGE - - logic[TRANS_ID_BITS-1:0] + - logic[CVA6Cfg.TRANS_ID_BITS-1:0] * - ``store_result_o`` - out - Store result - ISSUE_STAGE - - riscv::xlen_t + - logic[CVA6Cfg.XLEN-1:0] * - ``store_valid_o`` - out @@ -130,7 +130,7 @@ - in - Commit transaction ID - TO_BE_COMPLETED - - logic[TRANS_ID_BITS-1:0] + - logic[CVA6Cfg.TRANS_ID_BITS-1:0] * - ``icache_areq_i`` - in @@ -178,7 +178,7 @@ - in - PMP address - CSR_REGFILE - - logic[15:0][riscv::PLEN-3:0] + - logic[15:0][CVA6Cfg.PLEN-3:0] Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below diff --git a/docs/04_cv32a65x_design/source/port_load_unit.rst b/docs/04_cv32a65x_design/source/port_load_unit.rst index 1ba1466f22..046498f6f8 100644 --- a/docs/04_cv32a65x_design/source/port_load_unit.rst +++ b/docs/04_cv32a65x_design/source/port_load_unit.rst @@ -64,13 +64,13 @@ - out - Load transaction ID - TO_BE_COMPLETED - - logic[TRANS_ID_BITS-1:0] + - logic[CVA6Cfg.TRANS_ID_BITS-1:0] * - ``result_o`` - out - Load result - TO_BE_COMPLETED - - riscv::xlen_t + - logic[CVA6Cfg.XLEN-1:0] * - ``ex_o`` - out @@ -88,13 +88,13 @@ - out - Virtual address - TO_BE_COMPLETED - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] * - ``paddr_i`` - in - Physical address - TO_BE_COMPLETED - - logic[riscv::PLEN-1:0] + - logic[CVA6Cfg.PLEN-1:0] * - ``ex_i`` - in @@ -124,7 +124,7 @@ - in - TO_BE_COMPLETED - TO_BE_COMPLETED - - logic[TRANS_ID_BITS-1:0] + - logic[CVA6Cfg.TRANS_ID_BITS-1:0] * - ``req_port_i`` - in diff --git a/docs/04_cv32a65x_design/source/port_mult.rst b/docs/04_cv32a65x_design/source/port_mult.rst index 358e77dd7e..41e342d72f 100644 --- a/docs/04_cv32a65x_design/source/port_mult.rst +++ b/docs/04_cv32a65x_design/source/port_mult.rst @@ -52,7 +52,7 @@ - out - Mult result - ISSUE_STAGE - - riscv::xlen_t + - logic[CVA6Cfg.XLEN-1:0] * - ``mult_valid_o`` - out @@ -70,6 +70,6 @@ - out - Mult transaction ID - ISSUE_STAGE - - logic[TRANS_ID_BITS-1:0] + - logic[CVA6Cfg.TRANS_ID_BITS-1:0] diff --git a/docs/04_cv32a65x_design/source/port_multiplier.rst b/docs/04_cv32a65x_design/source/port_multiplier.rst index 77da9c48be..5dfca691c0 100644 --- a/docs/04_cv32a65x_design/source/port_multiplier.rst +++ b/docs/04_cv32a65x_design/source/port_multiplier.rst @@ -34,7 +34,7 @@ - in - Multiplier transaction ID - Mult - - logic[TRANS_ID_BITS-1:0] + - logic[CVA6Cfg.TRANS_ID_BITS-1:0] * - ``mult_valid_i`` - in @@ -52,19 +52,19 @@ - in - A operand - Mult - - riscv::xlen_t + - logic[CVA6Cfg.XLEN-1:0] * - ``operand_b_i`` - in - B operand - Mult - - riscv::xlen_t + - logic[CVA6Cfg.XLEN-1:0] * - ``result_o`` - out - Multiplier result - Mult - - riscv::xlen_t + - logic[CVA6Cfg.XLEN-1:0] * - ``mult_valid_o`` - out @@ -82,6 +82,6 @@ - out - Multiplier transaction ID - Mult - - logic[TRANS_ID_BITS-1:0] + - logic[CVA6Cfg.TRANS_ID_BITS-1:0] diff --git a/docs/04_cv32a65x_design/source/port_ras.rst b/docs/04_cv32a65x_design/source/port_ras.rst index 9298a5f638..f0bdb4d401 100644 --- a/docs/04_cv32a65x_design/source/port_ras.rst +++ b/docs/04_cv32a65x_design/source/port_ras.rst @@ -46,7 +46,7 @@ - in - Data to be pushed - FRONTEND - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] * - ``data_o`` - out diff --git a/docs/04_cv32a65x_design/source/port_scoreboard.rst b/docs/04_cv32a65x_design/source/port_scoreboard.rst index 80001913b3..0959761cbc 100644 --- a/docs/04_cv32a65x_design/source/port_scoreboard.rst +++ b/docs/04_cv32a65x_design/source/port_scoreboard.rst @@ -76,7 +76,7 @@ - out - rs1 operand - issue_read_operands - - riscv::xlen_t + - logic[CVA6Cfg.XLEN-1:0] * - ``rs1_valid_o`` - out @@ -94,7 +94,7 @@ - out - rs2 operand - issue_read_operands - - riscv::xlen_t + - logic[CVA6Cfg.XLEN-1:0] * - ``rs2_valid_o`` - out @@ -184,13 +184,13 @@ - in - Transaction ID at which to write the result back - TO_BE_COMPLETED - - logic[CVA6Cfg.NrWbPorts-1:0][ariane_pkg::TRANS_ID_BITS-1:0] + - logic[CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] * - ``wbdata_i`` - in - Results to write back - TO_BE_COMPLETED - - logic[CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0] + - logic[CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.XLEN-1:0] * - ``ex_i`` - in diff --git a/docs/04_cv32a65x_design/source/port_serdiv.rst b/docs/04_cv32a65x_design/source/port_serdiv.rst index 392f049392..467df2704a 100644 --- a/docs/04_cv32a65x_design/source/port_serdiv.rst +++ b/docs/04_cv32a65x_design/source/port_serdiv.rst @@ -34,7 +34,7 @@ - in - Serdiv translation ID - Mult - - logic[TRANS_ID_BITS-1:0] + - logic[CVA6Cfg.TRANS_ID_BITS-1:0] * - ``op_a_i`` - in @@ -88,7 +88,7 @@ - out - Serdiv transaction ID - Mult - - logic[TRANS_ID_BITS-1:0] + - logic[CVA6Cfg.TRANS_ID_BITS-1:0] * - ``res_o`` - out diff --git a/docs/04_cv32a65x_design/source/port_store_unit.rst b/docs/04_cv32a65x_design/source/port_store_unit.rst index 6bcbc5918c..1a94294930 100644 --- a/docs/04_cv32a65x_design/source/port_store_unit.rst +++ b/docs/04_cv32a65x_design/source/port_store_unit.rst @@ -94,13 +94,13 @@ - out - Transaction ID - ISSUE_STAGE - - logic[TRANS_ID_BITS-1:0] + - logic[CVA6Cfg.TRANS_ID_BITS-1:0] * - ``result_o`` - out - Store result - ISSUE_STAGE - - riscv::xlen_t + - logic[CVA6Cfg.XLEN-1:0] * - ``ex_o`` - out @@ -118,13 +118,13 @@ - out - Virtual address - TO_BE_COMPLETED - - logic[riscv::VLEN-1:0] + - logic[CVA6Cfg.VLEN-1:0] * - ``paddr_i`` - in - Physical address - TO_BE_COMPLETED - - logic[riscv::PLEN-1:0] + - logic[CVA6Cfg.PLEN-1:0] * - ``ex_i`` - in