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Hypervisor extension (openhwgroup#1938)
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Support 64bit H extension
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ninolomata authored Mar 21, 2024
1 parent 9ecdaa1 commit 86e1408
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Showing 44 changed files with 4,216 additions and 368 deletions.
20 changes: 20 additions & 0 deletions Bender.yml
Original file line number Diff line number Diff line change
Expand Up @@ -50,6 +50,26 @@ sources:
- core/mmu_sv39/ptw.sv
- core/cva6_accel_first_pass_decoder_stub.sv

- target: cv64a6_imafdch_sv39
files:
- core/include/cv64a6_imafdch_sv39_config_pkg.sv
- core/include/riscv_pkg.sv
- core/include/ariane_pkg.sv
- core/mmu_sv39x4/cva6_tlb_sv39x4.sv
- core/mmu_sv39x4/cva6_mmu_sv39x4.sv
- core/mmu_sv39x4/cva6_ptw_sv39x4.sv
- core/cva6_accel_first_pass_decoder_stub.sv

- target: cv64a6_imafdch_sv39_wb
files:
- core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv
- core/include/riscv_pkg.sv
- core/include/ariane_pkg.sv
- core/mmu_sv39x4/cva6_tlb_sv39x4.sv
- core/mmu_sv39x4/cva6_mmu_sv39x4.sv
- core/mmu_sv39x4/cva6_ptw_sv39x4.sv
- core/cva6_accel_first_pass_decoder_stub.sv

- target: cv32a6_imac_sv0
files:
- core/include/cv32a6_imac_sv0_config_pkg.sv
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3 changes: 3 additions & 0 deletions Flist.ariane
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Expand Up @@ -84,18 +84,21 @@ core/load_unit.sv
core/load_store_unit.sv
core/lsu_bypass.sv
core/mmu_sv39/mmu.sv
core/mmu_sv39x4/cva6_mmu_sv39x4.sv
core/mult.sv
core/multiplier.sv
core/serdiv.sv
core/perf_counters.sv
core/mmu_sv39/ptw.sv
core/mmu_sv39x4/ptw_sv39x4.sv
core/ariane_regfile_ff.sv
core/re_name.sv
core/scoreboard.sv
core/store_buffer.sv
core/amo_buffer.sv
core/store_unit.sv
core/mmu_sv39/tlb.sv
core/mmu_sv39x4/tlb_sv39x4.sv
core/commit_stage.sv
core/cache_subsystem/wt_dcache_ctrl.sv
core/cache_subsystem/wt_dcache_mem.sv
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16 changes: 16 additions & 0 deletions ci/build-hyp-riscv-tests.sh
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@@ -0,0 +1,16 @@
#!/bin/bash
set -e
ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
VERSION="920c1379cf6ca2374c6c5207dca425a933d8c7fd"

cd $ROOT/tmp

if [ -z ${NUM_JOBS} ]; then
NUM_JOBS=1
fi

[ -d $ROOT/tmp/riscv-hyp-tests ] || git clone https://github.com/ninolomata/riscv-hyp-tests
cd riscv-hyp-tests
git checkout $VERSION
git submodule update --init --recursive
make PLAT=cva6
5 changes: 5 additions & 0 deletions core/Flist.cva6
Original file line number Diff line number Diff line change
Expand Up @@ -189,6 +189,11 @@ ${CVA6_REPO_DIR}/core/mmu_sv39/mmu.sv
${CVA6_REPO_DIR}/core/mmu_sv39/ptw.sv
${CVA6_REPO_DIR}/core/mmu_sv39/tlb.sv

// MMU Sv39x4
${CVA6_REPO_DIR}/core/mmu_sv39x4/cva6_mmu_sv39x4.sv
${CVA6_REPO_DIR}/core/mmu_sv39x4/cva6_ptw_sv39x4.sv
${CVA6_REPO_DIR}/core/mmu_sv39x4/cva6_tlb_sv39x4.sv

// MMU Sv32
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_mmu_sv32.sv
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_ptw_sv32.sv
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27 changes: 17 additions & 10 deletions core/acc_dispatcher.sv
Original file line number Diff line number Diff line change
Expand Up @@ -297,22 +297,29 @@ module acc_dispatcher
logic acc_st_disp;

// Unpack the accelerator response
assign acc_trans_id_o = acc_resp_i.trans_id;
assign acc_result_o = acc_resp_i.result;
assign acc_valid_o = acc_resp_i.resp_valid;
assign acc_exception_o = '{cause: riscv::ILLEGAL_INSTR, tval : '0, valid: acc_resp_i.error};
assign acc_fflags_valid_o = acc_resp_i.fflags_valid;
assign acc_fflags_o = acc_resp_i.fflags;
assign acc_trans_id_o = acc_resp_i.trans_id;
assign acc_result_o = acc_resp_i.result;
assign acc_valid_o = acc_resp_i.resp_valid;
assign acc_exception_o = '{
cause: riscv::ILLEGAL_INSTR,
tval : '0,
tval2 : '0,
tinst : '0,
gva : '0,
valid: acc_resp_i.error
};
assign acc_fflags_valid_o = acc_resp_i.fflags_valid;
assign acc_fflags_o = acc_resp_i.fflags;
// Always ready to receive responses
assign acc_req_o.resp_ready = 1'b1;

// Signal dispatched load/store to issue stage
assign acc_ld_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_LOAD);
assign acc_st_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_STORE);
assign acc_ld_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_LOAD);
assign acc_st_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_STORE);

// Cache invalidation
assign inval_valid_o = acc_resp_i.inval_valid;
assign inval_addr_o = acc_resp_i.inval_addr;
assign inval_valid_o = acc_resp_i.inval_valid;
assign inval_addr_o = acc_resp_i.inval_addr;

/**************************
* Accelerator commit *
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5 changes: 5 additions & 0 deletions core/branch_unit.sv
Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,8 @@ module branch_unit #(
input logic clk_i,
// Asynchronous reset active low - SUBSYSTEM
input logic rst_ni,
// Virtualization mode state - CSR_REGFILE
input logic v_i,
// Debug mode state - CSR_REGFILE
input logic debug_mode_i,
// FU data needed to execute instruction - ISSUE_STAGE
Expand Down Expand Up @@ -115,6 +117,9 @@ module branch_unit #(
if (CVA6Cfg.TvalEn)
branch_exception_o.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{pc_i[CVA6Cfg.VLEN-1]}}, pc_i};
else branch_exception_o.tval = '0;
branch_exception_o.tval2 = {CVA6Cfg.GPLEN{1'b0}};
branch_exception_o.tinst = '0;
branch_exception_o.gva = CVA6Cfg.RVH ? v_i : 1'b0;
// Only throw instruction address misaligned exception if this is indeed a `taken` conditional branch or
// an unconditional jump
if (branch_valid_i && (target_address[0] || (!CVA6Cfg.RVC && target_address[1])) && jump_taken) begin
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39 changes: 38 additions & 1 deletion core/commit_stage.sv
Original file line number Diff line number Diff line change
Expand Up @@ -81,7 +81,9 @@ module commit_stage
// Request a pipeline flush - CONTROLLER
output logic flush_commit_o,
// Flush TLBs and pipeline - CONTROLLER
output logic sfence_vma_o
output logic sfence_vma_o,
output logic hfence_vvma_o,
output logic hfence_gvma_o
);

// ila_0 i_ila_commit (
Expand Down Expand Up @@ -142,6 +144,8 @@ module commit_stage
fence_i_o = 1'b0;
fence_o = 1'b0;
sfence_vma_o = 1'b0;
hfence_vvma_o = 1'b0;
hfence_gvma_o = 1'b0;
csr_write_fflags_o = 1'b0;
flush_commit_o = 1'b0;

Expand Down Expand Up @@ -212,6 +216,30 @@ module commit_stage
commit_ack_o[0] = no_st_pending_i;
end
// ------------------
// HFENCE.VVMA Logic
// ------------------
// hfence.vvma is idempotent so we can safely re-execute it after returning
// from interrupt service routine
// check if this instruction was a HFENCE_VVMA
if (CVA6Cfg.RVH && commit_instr_i[0].op == HFENCE_VVMA) begin
// no store pending so we can flush the TLBs and pipeline
hfence_vvma_o = no_st_pending_i;
// wait for the store buffer to drain until flushing the pipeline
commit_ack_o[0] = no_st_pending_i;
end
// ------------------
// HFENCE.GVMA Logic
// ------------------
// hfence.gvma is idempotent so we can safely re-execute it after returning
// from interrupt service routine
// check if this instruction was a HFENCE_GVMA
if (CVA6Cfg.RVH && commit_instr_i[0].op == HFENCE_GVMA) begin
// no store pending so we can flush the TLBs and pipeline
hfence_gvma_o = no_st_pending_i;
// wait for the store buffer to drain until flushing the pipeline
commit_ack_o[0] = no_st_pending_i;
end
// ------------------
// FENCE.I Logic
// ------------------
// fence.i is idempotent so we can safely re-execute it after returning
Expand Down Expand Up @@ -308,6 +336,10 @@ module commit_stage
exception_o.valid = 1'b0;
exception_o.cause = '0;
exception_o.tval = '0;
exception_o.tval2 = '0;
exception_o.tinst = '0;
exception_o.gva = 1'b0;

// we need a valid instruction in the commit stage
if (commit_instr_i[0].valid) begin
// ------------------------
Expand All @@ -319,6 +351,11 @@ module commit_stage
// the instruction bits from the ID stage. If a earlier exception happened we don't care
// as we will overwrite it anyway in the next IF bl
exception_o.tval = commit_instr_i[0].ex.tval;
if (CVA6Cfg.RVH) begin
exception_o.tinst = commit_instr_i[0].ex.tinst;
exception_o.tval2 = commit_instr_i[0].ex.tval2;
exception_o.gva = commit_instr_i[0].ex.gva;
end
end
// ------------------------
// Earlier Exceptions
Expand Down
37 changes: 36 additions & 1 deletion core/controller.sv
Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,8 @@ module controller
input logic clk_i,
// Asynchronous reset active low - SUBSYSTEM
input logic rst_ni,
// Virtualization mode - CSR_REGFILE
input logic v_i,
// Set PC om PC Gen - FRONTEND
output logic set_pc_commit_o,
// Flush the IF stage - FRONTEND
Expand All @@ -43,6 +45,8 @@ module controller
input logic flush_dcache_ack_i,
// Flush TLBs - EX_STAGE
output logic flush_tlb_o,
output logic flush_tlb_vvma_o,
output logic flush_tlb_gvma_o,
// Halt request from CSR (WFI instruction) - CSR_REGFILE
input logic halt_csr_i,
// Halt request from accelerator dispatcher - ACC_DISPATCHER
Expand All @@ -65,6 +69,8 @@ module controller
input logic fence_i,
// We got an instruction to flush the TLBs and pipeline - COMMIT_STAGE
input logic sfence_vma_i,
input logic hfence_vvma_i,
input logic hfence_gvma_i,
// Flush request from commit stage - COMMIT_STAGE
input logic flush_commit_i,
// Flush request from accelerator - ACC_DISPATCHER
Expand All @@ -88,6 +94,8 @@ module controller
flush_dcache = 1'b0;
flush_icache_o = 1'b0;
flush_tlb_o = 1'b0;
flush_tlb_vvma_o = 1'b0;
flush_tlb_gvma_o = 1'b0;
flush_bp_o = 1'b0;
// ------------
// Mis-predict
Expand Down Expand Up @@ -157,7 +165,34 @@ module controller
flush_id_o = 1'b1;
flush_ex_o = 1'b1;

flush_tlb_o = 1'b1;
if (CVA6Cfg.RVH && v_i) flush_tlb_vvma_o = 1'b1;
else flush_tlb_o = 1'b1;
end

// ---------------------------------
// HFENCE.VVMA
// ---------------------------------
if (CVA6Cfg.RVH && hfence_vvma_i) begin
set_pc_commit_o = 1'b1;
flush_if_o = 1'b1;
flush_unissued_instr_o = 1'b1;
flush_id_o = 1'b1;
flush_ex_o = 1'b1;

flush_tlb_vvma_o = 1'b1;
end

// ---------------------------------
// HFENCE.GVMA
// ---------------------------------
if (CVA6Cfg.RVH && hfence_gvma_i) begin
set_pc_commit_o = 1'b1;
flush_if_o = 1'b1;
flush_unissued_instr_o = 1'b1;
flush_id_o = 1'b1;
flush_ex_o = 1'b1;

flush_tlb_gvma_o = 1'b1;
end

// ---------------------------------
Expand Down
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