diff --git a/hw/ip/prim/rtl/prim_clock_meas.sv b/hw/ip/prim/rtl/prim_clock_meas.sv
index 45c0ec2ee4780..642fd23792af8 100644
--- a/hw/ip/prim/rtl/prim_clock_meas.sv
+++ b/hw/ip/prim/rtl/prim_clock_meas.sv
@@ -13,14 +13,12 @@
 `include "prim_assert.sv"
 
 module prim_clock_meas #(
-  // Maximum value of input clock counts over measurement period
+  // Maximum number of input clock counts over measurement period. Note that this is 1-based
+  // indexing (so a hardware counter would only count up to Cnt-1)
   parameter int Cnt = 16,
-  // Maximum value of reference clock counts over measurement period
-  parameter int RefCnt = 1,
   parameter bit ClkTimeOutChkEn = 1,
   parameter bit RefTimeOutChkEn = 1,
-  localparam int CntWidth = prim_util_pkg::vbits(Cnt),
-  localparam int RefCntWidth = prim_util_pkg::vbits(RefCnt)
+  localparam int CntWidth = prim_util_pkg::vbits(Cnt)
 ) (
   input clk_i,
   input rst_ni,
@@ -155,27 +153,10 @@ module prim_clock_meas #(
     .dst_pulse_o(valid_ref)
   );
 
-
-  if (RefCnt == 1) begin : gen_degenerate_case
-    // if reference count is one, cnt_ref is always 0.
-    // So there is no need to maintain a counter, and
-    // valid just becomes valid_ref
-    assign valid = valid_ref;
-  end else begin : gen_normal_case
-    logic [RefCntWidth-1:0] cnt_ref;
-    assign valid = valid_ref & (int'(cnt_ref) == RefCnt - 1);
-    always_ff @(posedge clk_i or negedge rst_ni) begin
-      if (!rst_ni) begin
-        cnt_ref <= '0;
-      end else if (!cnt_en && |cnt_ref) begin
-        cnt_ref <= '0;
-      end else if (cnt_en && valid) begin
-        cnt_ref <= '0;
-      end else if (cnt_en && valid_ref) begin
-        cnt_ref <= cnt_ref + 1'b1;
-      end
-    end
-  end
+  // There isn't really a reference counter (we just wait for the first edge on that clock). The
+  // valid signal is supposed to be saying that we have seen the synchronised version of the last
+  // edge we are waiting for, so it is always equal to valid_ref.
+  assign valid = valid_ref;
 
   logic cnt_ovfl;
   logic [CntWidth-1:0] cnt;
@@ -206,16 +187,13 @@ module prim_clock_meas #(
 
   localparam bit TimeOutChkEn = ClkTimeOutChkEn | RefTimeOutChkEn;
 
-  // determine ratio between
-  localparam int ClkRatio = Cnt / RefCnt;
-
   // maximum cdc latency from the perspective of the measured clock
   // 1 cycle to output request
   // 2 ref cycles for synchronization
   // 1 ref cycle to send ack
   // 2 cycles to sync ack
   // Double for margin
-  localparam int MaxClkCdcLatency = (1 + 2*ClkRatio + 1*ClkRatio + 2)*2;
+  localparam int MaxClkCdcLatency = (1 + 2 + 1 + 2)*2;
 
   // maximum cdc latency from the perspective of the reference clock
   // 1 ref cycle to output request
@@ -261,19 +239,11 @@ module prim_clock_meas #(
   // Assertions
   //////////////////////////
 
-  if (TimeOutChkEn) begin : gen_timeout_assert
-    // the measured clock must be faster than the reference clock
-    `ASSERT_INIT(ClkRatios_A, ClkRatio > 2)
-  end
-
-  // reference count has to be at least 1
-  `ASSERT_INIT(RefCntVal_A, RefCnt >= 1)
+  // We must be measuring at least two cycles on the input clock.
+  `ASSERT_INIT(CntMin_A, Cnt > 1)
 
   // if we've reached the max count, enable must be 0 next.
   // Otherwise the width of the counter is too small to accommodate the usecase
   `ASSERT(MaxWidth_A, (cnt == Cnt-1) |=> !cnt_en )
 
-
-
-
-endmodule // prim_clk_meas
+endmodule
diff --git a/hw/ip_templates/clkmgr/rtl/clkmgr.sv.tpl b/hw/ip_templates/clkmgr/rtl/clkmgr.sv.tpl
index 8d86bd825d3a0..5eca99c60f44d 100644
--- a/hw/ip_templates/clkmgr/rtl/clkmgr.sv.tpl
+++ b/hw/ip_templates/clkmgr/rtl/clkmgr.sv.tpl
@@ -398,8 +398,7 @@ rg_srcs = list(sorted({sig['src_name'] for sig
  sel_idx = f"Clk{Name.from_snake_case(src).as_camel_case()}Idx"
 %>
   clkmgr_meas_chk #(
-    .Cnt(${cnt}),
-    .RefCnt(1)
+    .Cnt(${cnt})
   ) u_${src}_meas (
     .clk_i,
     .rst_ni,
diff --git a/hw/ip_templates/clkmgr/rtl/clkmgr_meas_chk.sv b/hw/ip_templates/clkmgr/rtl/clkmgr_meas_chk.sv
index ea0bc8e92be6f..b98c21823af4b 100644
--- a/hw/ip_templates/clkmgr/rtl/clkmgr_meas_chk.sv
+++ b/hw/ip_templates/clkmgr/rtl/clkmgr_meas_chk.sv
@@ -9,8 +9,6 @@ module clkmgr_meas_chk
 #(
   // Maximum value of input clock counts over measurement period
   parameter int Cnt = 16,
-  // Maximum value of reference clock counts over measurement period
-  parameter int RefCnt = 1,
   localparam int CntWidth = prim_util_pkg::vbits(Cnt)
 ) (
   // the local operating clock
@@ -42,7 +40,6 @@ module clkmgr_meas_chk
 
   prim_clock_meas #(
     .Cnt(Cnt),
-    .RefCnt(RefCnt),
     .ClkTimeOutChkEn(1'b1),
     .RefTimeOutChkEn(1'b0)
   ) u_meas (
diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr.sv b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr.sv
index a5b001644fb34..c19df556d447b 100644
--- a/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr.sv
+++ b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr.sv
@@ -549,8 +549,7 @@
   end
 
   clkmgr_meas_chk #(
-    .Cnt(16),
-    .RefCnt(1)
+    .Cnt(16)
   ) u_io_div4_meas (
     .clk_i,
     .rst_ni,
@@ -576,8 +575,7 @@
 
 
   clkmgr_meas_chk #(
-    .Cnt(64),
-    .RefCnt(1)
+    .Cnt(64)
   ) u_main_meas (
     .clk_i,
     .rst_ni,
@@ -603,8 +601,7 @@
 
 
   clkmgr_meas_chk #(
-    .Cnt(64),
-    .RefCnt(1)
+    .Cnt(64)
   ) u_usb_meas (
     .clk_i,
     .rst_ni,
diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_meas_chk.sv b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_meas_chk.sv
index ea0bc8e92be6f..b98c21823af4b 100644
--- a/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_meas_chk.sv
+++ b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_meas_chk.sv
@@ -9,8 +9,6 @@ module clkmgr_meas_chk
 #(
   // Maximum value of input clock counts over measurement period
   parameter int Cnt = 16,
-  // Maximum value of reference clock counts over measurement period
-  parameter int RefCnt = 1,
   localparam int CntWidth = prim_util_pkg::vbits(Cnt)
 ) (
   // the local operating clock
@@ -42,7 +40,6 @@ module clkmgr_meas_chk
 
   prim_clock_meas #(
     .Cnt(Cnt),
-    .RefCnt(RefCnt),
     .ClkTimeOutChkEn(1'b1),
     .RefTimeOutChkEn(1'b0)
   ) u_meas (
diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr.sv b/hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr.sv
index 8fb4dc40d7623..7c23aec1cb1d7 100644
--- a/hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr.sv
+++ b/hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr.sv
@@ -559,8 +559,7 @@
   end
 
   clkmgr_meas_chk #(
-    .Cnt(1024),
-    .RefCnt(1)
+    .Cnt(1024)
   ) u_io_meas (
     .clk_i,
     .rst_ni,
@@ -586,8 +585,7 @@
 
 
   clkmgr_meas_chk #(
-    .Cnt(512),
-    .RefCnt(1)
+    .Cnt(512)
   ) u_io_div2_meas (
     .clk_i,
     .rst_ni,
@@ -613,8 +611,7 @@
 
 
   clkmgr_meas_chk #(
-    .Cnt(256),
-    .RefCnt(1)
+    .Cnt(256)
   ) u_io_div4_meas (
     .clk_i,
     .rst_ni,
@@ -640,8 +637,7 @@
 
 
   clkmgr_meas_chk #(
-    .Cnt(1024),
-    .RefCnt(1)
+    .Cnt(1024)
   ) u_main_meas (
     .clk_i,
     .rst_ni,
@@ -667,8 +663,7 @@
 
 
   clkmgr_meas_chk #(
-    .Cnt(512),
-    .RefCnt(1)
+    .Cnt(512)
   ) u_usb_meas (
     .clk_i,
     .rst_ni,
diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr_meas_chk.sv b/hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr_meas_chk.sv
index ea0bc8e92be6f..b98c21823af4b 100644
--- a/hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr_meas_chk.sv
+++ b/hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr_meas_chk.sv
@@ -9,8 +9,6 @@ module clkmgr_meas_chk
 #(
   // Maximum value of input clock counts over measurement period
   parameter int Cnt = 16,
-  // Maximum value of reference clock counts over measurement period
-  parameter int RefCnt = 1,
   localparam int CntWidth = prim_util_pkg::vbits(Cnt)
 ) (
   // the local operating clock
@@ -42,7 +40,6 @@ module clkmgr_meas_chk
 
   prim_clock_meas #(
     .Cnt(Cnt),
-    .RefCnt(RefCnt),
     .ClkTimeOutChkEn(1'b1),
     .RefTimeOutChkEn(1'b0)
   ) u_meas (
diff --git a/hw/top_englishbreakfast/ip_autogen/clkmgr/rtl/clkmgr.sv b/hw/top_englishbreakfast/ip_autogen/clkmgr/rtl/clkmgr.sv
index 81939ebc44c42..a25159ab9fce9 100644
--- a/hw/top_englishbreakfast/ip_autogen/clkmgr/rtl/clkmgr.sv
+++ b/hw/top_englishbreakfast/ip_autogen/clkmgr/rtl/clkmgr.sv
@@ -554,8 +554,7 @@
   end
 
   clkmgr_meas_chk #(
-    .Cnt(1024),
-    .RefCnt(1)
+    .Cnt(1024)
   ) u_io_meas (
     .clk_i,
     .rst_ni,
@@ -581,8 +580,7 @@
 
 
   clkmgr_meas_chk #(
-    .Cnt(256),
-    .RefCnt(1)
+    .Cnt(256)
   ) u_io_div4_meas (
     .clk_i,
     .rst_ni,
@@ -608,8 +606,7 @@
 
 
   clkmgr_meas_chk #(
-    .Cnt(1024),
-    .RefCnt(1)
+    .Cnt(1024)
   ) u_main_meas (
     .clk_i,
     .rst_ni,
@@ -635,8 +632,7 @@
 
 
   clkmgr_meas_chk #(
-    .Cnt(512),
-    .RefCnt(1)
+    .Cnt(512)
   ) u_usb_meas (
     .clk_i,
     .rst_ni,
diff --git a/hw/top_englishbreakfast/ip_autogen/clkmgr/rtl/clkmgr_meas_chk.sv b/hw/top_englishbreakfast/ip_autogen/clkmgr/rtl/clkmgr_meas_chk.sv
index ea0bc8e92be6f..b98c21823af4b 100644
--- a/hw/top_englishbreakfast/ip_autogen/clkmgr/rtl/clkmgr_meas_chk.sv
+++ b/hw/top_englishbreakfast/ip_autogen/clkmgr/rtl/clkmgr_meas_chk.sv
@@ -9,8 +9,6 @@ module clkmgr_meas_chk
 #(
   // Maximum value of input clock counts over measurement period
   parameter int Cnt = 16,
-  // Maximum value of reference clock counts over measurement period
-  parameter int RefCnt = 1,
   localparam int CntWidth = prim_util_pkg::vbits(Cnt)
 ) (
   // the local operating clock
@@ -42,7 +40,6 @@ module clkmgr_meas_chk
 
   prim_clock_meas #(
     .Cnt(Cnt),
-    .RefCnt(RefCnt),
     .ClkTimeOutChkEn(1'b1),
     .RefTimeOutChkEn(1'b0)
   ) u_meas (