From d695154211ecac2e9911ba8b2b777a4770f5f083 Mon Sep 17 00:00:00 2001 From: Pascal Nasahl Date: Thu, 2 Jan 2025 09:38:09 +0000 Subject: [PATCH 1/4] [sram_ctrl,dv] Update prim_subreg exclusions As recently two new registers (status_readback_error and status_sram_alert) were added, this commit adds two new cov exclusions that are already present for the other error registers. These exclusions are needed as the wr_data signal is directly tied to 1'b1. Furthermore, this commit adds a more detailed explanation why these exclusions are needed and moves them to the upper part of the file to indicate that they were manually added. Finally, these exclusions were added to a new file to cleary mark them as manually added. Signed-off-by: Pascal Nasahl --- hw/ip/sram_ctrl/dv/cov/sram_ctrl_cov_excl.el | 13 --------- .../dv/cov/sram_ctrl_manual_cov_excl.el | 27 +++++++++++++++++++ .../sram_ctrl/dv/sram_ctrl_base_sim_cfg.hjson | 1 + 3 files changed, 28 insertions(+), 13 deletions(-) create mode 100644 hw/ip/sram_ctrl/dv/cov/sram_ctrl_manual_cov_excl.el diff --git a/hw/ip/sram_ctrl/dv/cov/sram_ctrl_cov_excl.el b/hw/ip/sram_ctrl/dv/cov/sram_ctrl_cov_excl.el index bb9f5260a9405..7a158b0276c96 100644 --- a/hw/ip/sram_ctrl/dv/cov/sram_ctrl_cov_excl.el +++ b/hw/ip/sram_ctrl/dv/cov/sram_ctrl_cov_excl.el @@ -43,19 +43,6 @@ Block 1 "461445014" "assign rsp_intg = tl_i.d_user.rsp_intg;" ANNOTATION: "[UNR] all inputs are constant" Block 2 "2643129081" "assign data_intg = tl_i.d_user.data_intg;" -CHECKSUM: "281300783 1779845869" -INSTANCE: tb.dut.u_reg_regs.u_status_bus_integ_error.wr_en_data_arb -ANNOTATION: "[UNR] all inputs are constant" -Block 2 "1620753216" "assign wr_data = d;" -INSTANCE: tb.dut.u_reg_regs.u_status_init_error.wr_en_data_arb -ANNOTATION: "[UNR] all inputs are constant" -Block 2 "1620753216" "assign wr_data = d;" - -CHECKSUM: "281300783 1779845869" -INSTANCE: tb.dut.u_reg_regs.u_status_escalated.wr_en_data_arb -ANNOTATION: "[UNR] all inputs are constant" -Block 2 "1620753216" "assign wr_data = d;" - CHECKSUM: "1296247128 1854270750" INSTANCE: tb.dut ANNOTATION: "[UNSUPPORTED] ACK can't come without REQ" diff --git a/hw/ip/sram_ctrl/dv/cov/sram_ctrl_manual_cov_excl.el b/hw/ip/sram_ctrl/dv/cov/sram_ctrl_manual_cov_excl.el new file mode 100644 index 0000000000000..d96ab277a9f4f --- /dev/null +++ b/hw/ip/sram_ctrl/dv/cov/sram_ctrl_manual_cov_excl.el @@ -0,0 +1,27 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The following exclusions were manually added. + +// The reason for the following five exclusions are that "d" in "assign wr_data = d;" +// is driven by "hw2reg.status..d = 1'b1' inside the "sram_ctrl" module. +CHECKSUM: "2099741489 2073313596" +INSTANCE: tb.dut.u_reg_regs.u_status_bus_integ_error.wr_en_data_arb +ANNOTATION: "[UNR] all inputs are constant" +Block 2 "1620753216" "assign wr_data = d;" +INSTANCE: tb.dut.u_reg_regs.u_status_init_error.wr_en_data_arb +ANNOTATION: "[UNR] all inputs are constant" +Block 2 "1620753216" "assign wr_data = d;" +CHECKSUM: "2099741489 2073313596" +INSTANCE: tb.dut.u_reg_regs.u_status_escalated.wr_en_data_arb +ANNOTATION: "[UNR] all inputs are constant" +Block 2 "1620753216" "assign wr_data = d;" +CHECKSUM: "2099741489 2073313596" +INSTANCE: tb.dut.u_reg_regs.u_status_readback_error.wr_en_data_arb +ANNOTATION: "[UNR] all inputs are constant" +Block 2 "1620753216" "assign wr_data = d;" +CHECKSUM: "2099741489 2073313596" +INSTANCE: tb.dut.u_reg_regs.u_status_sram_alert.wr_en_data_arb +ANNOTATION: "[UNR] all inputs are constant" +Block 2 "1620753216" "assign wr_data = d;" diff --git a/hw/ip/sram_ctrl/dv/sram_ctrl_base_sim_cfg.hjson b/hw/ip/sram_ctrl/dv/sram_ctrl_base_sim_cfg.hjson index 7480d833b8898..e8479b2b87136 100644 --- a/hw/ip/sram_ctrl/dv/sram_ctrl_base_sim_cfg.hjson +++ b/hw/ip/sram_ctrl/dv/sram_ctrl_base_sim_cfg.hjson @@ -47,6 +47,7 @@ reseed: 50 vcs_cov_excl_files: ["{proj_root}/hw/ip/sram_ctrl/dv/cov/sram_ctrl_cov_excl.el", + "{proj_root}/hw/ip/sram_ctrl/dv/cov/sram_ctrl_manual_cov_excl.el", "{proj_root}/hw/ip/sram_ctrl/dv/cov/sram_ctrl_unr_excl.el"] // Need to override the default output directory From 5e42bb265a8c6a35cfb7fd51181171cdcd573c45 Mon Sep 17 00:00:00 2001 From: Pascal Nasahl Date: Thu, 2 Jan 2025 13:37:48 +0000 Subject: [PATCH 2/4] [sram_ctrl,dv] Add new exclusions for fifo_cnt As the depth of the FIFO is one, we can exclude a couple of uncovered conditions. Signed-off-by: Pascal Nasahl --- .../dv/cov/sram_ctrl_manual_cov_excl.el | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/hw/ip/sram_ctrl/dv/cov/sram_ctrl_manual_cov_excl.el b/hw/ip/sram_ctrl/dv/cov/sram_ctrl_manual_cov_excl.el index d96ab277a9f4f..91574c045f543 100644 --- a/hw/ip/sram_ctrl/dv/cov/sram_ctrl_manual_cov_excl.el +++ b/hw/ip/sram_ctrl/dv/cov/sram_ctrl_manual_cov_excl.el @@ -25,3 +25,23 @@ CHECKSUM: "2099741489 2073313596" INSTANCE: tb.dut.u_reg_regs.u_status_sram_alert.wr_en_data_arb ANNOTATION: "[UNR] all inputs are constant" Block 2 "1620753216" "assign wr_data = d;" + +// As the depth of this FIFO is 1, the following conditions cannot be met. +CHECKSUM: "3215070453 33318353" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo.gen_normal_fifo.u_fifo_cnt +Condition 1 "2532211833" "(incr_wptr_i & (wptr_o == 1'((Depth - 1)))) 1 -1" +Condition 7 "687544961" "(full_o ? (1'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o))))) 1 -1" +Condition 3 "2597027294" "(incr_rptr_i & (rptr_o == 1'((Depth - 1)))) 1 -1" +CHECKSUM: "3215070453 1827096802" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo.gen_normal_fifo.u_fifo_cnt +Branch 0 "721764659" "full_o" (0) "full_o 1,-" +Branch 0 "721764659" "full_o" (2) "full_o 0,0" +Branch 0 "721764659" "full_o" (1) "full_o 0,1" +CHECKSUM: "3215070453 3446030929" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo.gen_normal_fifo.u_fifo_cnt +Block 19 "4019242409" "wptr_wrap_cnt_q <= (wptr_wrap_cnt_q + {{(WrapPtrW - 1) {1'b0}}, 1'b1});" +Block 28 "1113085816" "rptr_wrap_cnt_q <= (rptr_wrap_cnt_q + {{(WrapPtrW - 1) {1'b0}}, 1'b1});" +CHECKSUM: "3215070453 1827096802" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo.gen_normal_fifo.u_fifo_cnt +Branch 1 "2417346495" "(!rst_ni)" (3) "(!rst_ni) 0,0,0,1" +Branch 2 "456961687" "(!rst_ni)" (3) "(!rst_ni) 0,0,0,1" From 279788991cc0b16d87b928159eca8be02543a134 Mon Sep 17 00:00:00 2001 From: Pascal Nasahl Date: Fri, 3 Jan 2025 08:36:38 +0000 Subject: [PATCH 3/4] [sram_ctrl,dv] Update unr_excl This commit manually updates an automatically generated coverage exclusion as it is outdated. In the next UNR run this can be overwritten but it helps for now to reach V3. Signed-off-by: Pascal Nasahl --- hw/ip/sram_ctrl/dv/cov/sram_ctrl_unr_excl.el | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/ip/sram_ctrl/dv/cov/sram_ctrl_unr_excl.el b/hw/ip/sram_ctrl/dv/cov/sram_ctrl_unr_excl.el index 163f824638867..86395d9f4973b 100644 --- a/hw/ip/sram_ctrl/dv/cov/sram_ctrl_unr_excl.el +++ b/hw/ip/sram_ctrl/dv/cov/sram_ctrl_unr_excl.el @@ -14,10 +14,10 @@ ANNOTATION: "VC_COV_UNR" Block 12 "398307645" "wptr_o <= (wptr_o + {{(Width - 1) {1'b0}}, 1'b1});" ANNOTATION: "VC_COV_UNR" Block 21 "2517571270" "rptr_o <= (rptr_o + {{(Width - 1) {1'b0}}, 1'b1});" -CHECKSUM: "4263908928 1069164873" +CHECKSUM: "2326541723 4103140726" INSTANCE: tb.dut.u_prim_ram_1p_scr ANNOTATION: "VC_COV_UNR" -Block 23 "264295034" "rdata_o[k] = rdata[k];" +Block 28 "16825046" "rdata_o[k] = rdata[k];" CHECKSUM: "4224194069 2881513198" INSTANCE: tb.dut.u_tlul_lc_gate ANNOTATION: "VC_COV_UNR" From 5436b8778ff021680cb140172f070b3e4f84358d Mon Sep 17 00:00:00 2001 From: Pascal Nasahl Date: Fri, 3 Jan 2025 09:09:49 +0000 Subject: [PATCH 4/4] [sram_ctrl,dv] Exclude default branch This commit excludes the default branch of the FSM inside the tlul_adapter_sram_byte module as we should not reach it under normal operational conditions. Signed-off-by: Pascal Nasahl --- hw/ip/sram_ctrl/dv/cov/sram_ctrl_manual_cov_excl.el | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/ip/sram_ctrl/dv/cov/sram_ctrl_manual_cov_excl.el b/hw/ip/sram_ctrl/dv/cov/sram_ctrl_manual_cov_excl.el index 91574c045f543..d3366571696c9 100644 --- a/hw/ip/sram_ctrl/dv/cov/sram_ctrl_manual_cov_excl.el +++ b/hw/ip/sram_ctrl/dv/cov/sram_ctrl_manual_cov_excl.el @@ -45,3 +45,12 @@ CHECKSUM: "3215070453 1827096802" INSTANCE: tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo.gen_normal_fifo.u_fifo_cnt Branch 1 "2417346495" "(!rst_ni)" (3) "(!rst_ni) 0,0,0,1" Branch 2 "456961687" "(!rst_ni)" (3) "(!rst_ni) 0,0,0,1" + +// Exclude the default branch of the FSM inside the tlul_sram_byte module as we +// should not reach it under normal conditions. +CHECKSUM: "432309571 1160560609" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_sram_byte +Branch 1 "2309313685" "gen_integ_handling.state_q" (46) "gen_integ_handling.state_q default,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +CHECKSUM: "432309571 1673264206" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_sram_byte +Block 86 "2943004802" "alert_o = 1'b1;"