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[doc] Fix links to rv_core_ibex
Signed-off-by: Robert Schilling <[email protected]>
1 parent bca5326 commit fe5c70a

27 files changed

+62
-38
lines changed

‎BLOCKFILE

+1-1
Original file line numberDiff line numberDiff line change
@@ -102,7 +102,6 @@ hw/top_earlgrey/data/otp/otp_ctrl_mmap.hjson
102102
hw/top_earlgrey/data/otp/otp_ctrl_img_test_unlocked1.hjson
103103
hw/top_earlgrey/data/otp/otp_ctrl_img_prod.hjson
104104
hw/top_earlgrey/data/otp/otp_ctrl_img_test_unlocked2.hjson
105-
hw/ip/rv_core_ibex/data/rv_core_ibex.hjson
106105
hw/ip/pwm/data/pwm.hjson
107106
hw/ip/aon_timer/data/aon_timer.hjson
108107

@@ -117,6 +116,7 @@ hw/top_earlgrey/ip_autogen/pwrmgr/data/pwrmgr.hjson
117116
hw/top_earlgrey/ip_autogen/rstmgr/data/rstmgr.hjson
118117
hw/top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson
119118
hw/top_earlgrey/ip_autogen/gpio/rtl/gpio.hjson
119+
hw/top_earlgrey/ip_autogen/rv_core_ibex/data/rv_core_ibex.hjson
120120

121121
hw/top_earlgrey/data/top_earlgrey.hjson
122122
hw/top_earlgrey/data/xbar_main.hjson

‎SUMMARY.md

+21-7
Original file line numberDiff line numberDiff line change
@@ -73,6 +73,13 @@
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- [Registers](./hw/top_earlgrey/ip/sensor_ctrl/doc/registers.md)
7474
- [Device Interface Functions](./sw/device/lib/dif/dif_sensor_ctrl.h)
7575
- [Checklist](./hw/top_earlgrey/ip/sensor_ctrl/doc/checklist.md)
76+
- [Ibex RISC-V Core Wrapper](./hw/top_earlgrey/ip_autogen/rv_core_ibex/README.md)
77+
- [Theory of Operation](./hw/top_earlgrey/ip_autogen/rv_core_ibex/doc/theory_of_operation.md)
78+
- [Design Verification](./hw/top_earlgrey/ip_autogen/rv_core_ibex/dv/README.md)
79+
- [Programmer's Guide](./hw/top_earlgrey/ip_autogen/rv_core_ibex/doc/programmers_guide.md)
80+
- [Hardware Interfaces](./hw/top_earlgrey/ip_autogen/rv_core_ibex/doc/interfaces.md)
81+
- [Registers](./hw/top_earlgrey/ip_autogen/rv_core_ibex/doc/registers.md)
82+
- [Checklist](./hw/top_earlgrey/ip_autogen/rv_core_ibex/doc/checklist.md)
7683
- [TL-UL Checklist](./hw/top_earlgrey/ip/xbar/doc/checklist.md)
7784
- [Pinmux Targets](./hw/top_earlgrey/ip_autogen/pinmux/doc/targets.md)
7885
- [ASIC Target Pinout and Pinmux Connectivity](./hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_asic.md)
@@ -106,15 +113,22 @@
106113
- [Registers](./hw/top_darjeeling/ip_autogen/gpio/doc/registers.md)
107114
- [Device Interface Functions](./sw/device/lib/dif/dif_gpio.h)
108115
- [Checklist](./hw/top_darjeeling/ip_autogen/gpio/doc/checklist.md)
116+
- [Ibex RISC-V Core Wrapper](./hw/top_darjeeling/ip_autogen/rv_core_ibex/README.md)
117+
- [Theory of Operation](./hw/top_darjeeling/ip_autogen/rv_core_ibex/doc/theory_of_operation.md)
118+
- [Design Verification](./hw/top_darjeeling/ip_autogen/rv_core_ibex/dv/README.md)
119+
- [Programmer's Guide](./hw/top_darjeeling/ip_autogen/rv_core_ibex/doc/programmers_guide.md)
120+
- [Hardware Interfaces](./hw/top_darjeeling/ip_autogen/rv_core_ibex/doc/interfaces.md)
121+
- [Registers](./hw/top_darjeeling/ip_autogen/rv_core_ibex/doc/registers.md)
122+
- [Checklist](./hw/top_darjeeling/ip_autogen/rv_core_ibex/doc/checklist.md)
109123

110124
- [Cores](./hw/doc/cores.md)
111-
- [Ibex RISC-V Core Wrapper](./hw/ip/rv_core_ibex/README.md)
112-
- [Theory of Operation](./hw/ip/rv_core_ibex/doc/theory_of_operation.md)
113-
- [Design Verification](./hw/ip/rv_core_ibex/dv/README.md)
114-
- [Programmer's Guide](./hw/ip/rv_core_ibex/doc/programmers_guide.md)
115-
- [Hardware Interfaces](./hw/ip/rv_core_ibex/doc/interfaces.md)
116-
- [Registers](./hw/ip/rv_core_ibex/doc/registers.md)
117-
- [Checklist](./hw/ip/rv_core_ibex/doc/checklist.md)
125+
- [Ibex RISC-V Core Wrapper](./hw/top_earlgrey/ip_autogen/rv_core_ibex/README.md)
126+
- [Theory of Operation](./hw/top_earlgrey/ip_autogen/rv_core_ibex/doc/theory_of_operation.md)
127+
- [Design Verification](./hw/top_earlgrey/ip_autogen/rv_core_ibex/dv/README.md)
128+
- [Programmer's Guide](./hw/top_earlgrey/ip_autogen/rv_core_ibex/doc/programmers_guide.md)
129+
- [Hardware Interfaces](./hw/top_earlgrey/ip_autogen/rv_core_ibex/doc/interfaces.md)
130+
- [Registers](./hw/top_earlgrey/ip_autogen/rv_core_ibex/doc/registers.md)
131+
- [Checklist](./hw/top_earlgrey/ip_autogen/rv_core_ibex/doc/checklist.md)
118132
- [OTBN](./hw/ip/otbn/README.md)
119133
- [Theory of Operation](./hw/ip/otbn/doc/theory_of_operation.md)
120134
- [Introduction to OTBN](./hw/ip/otbn/doc/otbn_intro.md)

‎hw/doc/cores.md

+1-1
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@@ -3,7 +3,7 @@
33
Cores in OpenTitan are processing units that can run programs.
44

55
Currently, there are two cores in OpenTitan:
6-
* [Ibex](../ip/rv_core_ibex/README.md) (RV32IMCB)
6+
* [Ibex](../top_earlgrey/ip_autogen/rv_core_ibex/README.md) (RV32IMCB)
77
* [OTBN](../ip/otbn/README.md) (programmable coprocessor for asymmetric cryptographic algorithms, 256-bit datapath)
88

99
Since cores are the interface between hardware and software, please also consult the [software resources](../../sw/README.md).

‎hw/dv/sv/sim_sram/README.md

+1-1
Original file line numberDiff line numberDiff line change
@@ -79,5 +79,5 @@ The disconnection must be made in the desired design block ONLY if `` `SYNTHESIS
7979
This module is instantiated in the testbench rather than in the design.
8080
Its inbound and outbound TL interfaces are then connected to the disconnected TL interface in the design by hierarchically referencing their paths.
8181

82-
This disconnection is currently done in `hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv`, which relies on `` `RV_CORE_IBEX_SIM_SRAM`` being defined.
82+
This disconnection is currently done in `hw/top_earlgrey/ip_autogen/rv_core_ibex/rtl/rv_core_ibex.sv`, which relies on `` `RV_CORE_IBEX_SIM_SRAM`` being defined.
8383
In UVM DV simulations, we do not disconnect anything - we use forces instead to make the connections.

‎hw/ip/BUILD

-1
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,6 @@ filegroup(
3333
"//hw/ip/prim_xilinx_ultrascale:rtl_files",
3434
"//hw/ip/pwm:rtl_files",
3535
"//hw/ip/rom_ctrl:rtl_files",
36-
"//hw/ip/rv_core_ibex:rtl_files",
3736
"//hw/ip/rv_dm:rtl_files",
3837
"//hw/ip/rv_timer:rtl_files",
3938
"//hw/ip/spi_device:rtl_files",

‎hw/ip/README.md

-2
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,6 @@
2323
| [`pattgen`] | Transmission of short time-dependent data patterns on two clock-parallel output channels |
2424
| [`pwm`] | Transmission of pulse-width modulated output signals with adjustable duty cycle |
2525
| [`rom_ctrl`] | Interfaces scrambled boot ROM with system bus and KMAC for initial health check after reset |
26-
| [`rv_core_ibex`] | Dual-core lockstep 32-bit RISC-V processor running application and control software |
2726
| [`rv_dm`] | Enables debug support for Ibex, access protected by life cycle |
2827
| [`rv_timer`] | Memory-mapped timer unit implementing RISC-V mtime and mtimecmp registers |
2928
| [`soc_dbg_ctrl`] | Control module to enable or disable debug access |
@@ -56,7 +55,6 @@
5655
[`pattgen`]: ./pattgen/README.md
5756
[`pwm`]: ./pwm/README.md
5857
[`rom_ctrl`]: ./rom_ctrl/README.md
59-
[`rv_core_ibex`]: ./rv_core_ibex/README.md
6058
[`rv_dm`]: ./rv_dm/README.md
6159
[`rv_timer`]: ./rv_timer/README.md
6260
[`soc_dbg_ctrl`]: ./soc_dbg_ctrl/README.md

‎hw/ip/aes/README.md

+2-2
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@@ -43,15 +43,15 @@ This AES unit targets medium performance (16 parallel S-Boxes, \~1 cycle per rou
4343
High-speed, single-cycle operation for high-bandwidth data streaming is not required.
4444

4545
Cipher modes other than ECB, CBC, CFB, OFB and CTR are beyond this version of the AES unit but might be supported in future versions.
46-
Galois/Counter Mode (GCM) can be implemented by leveraging [Ibex](../rv_core_ibex/README.md) for the GHASH operation as demonstrated in [OpenTitan's library of cryptographic implementations](https://github.com/lowRISC/opentitan/tree/master/sw/device/lib/crypto).
46+
Galois/Counter Mode (GCM) can be implemented by leveraging [Ibex](../../top_earlgrey/ip_autogen/rv_core_ibex/README.md) for the GHASH operation as demonstrated in [OpenTitan's library of cryptographic implementations](https://github.com/lowRISC/opentitan/tree/master/sw/device/lib/crypto).
4747

4848

4949
## Description
5050

5151
The AES unit is a cryptographic accelerator that accepts requests from the processor to encrypt or decrypt 16B blocks of data.
5252
It supports AES-128/192/256 in Electronic Codebook (ECB) mode, Cipher Block Chaining (CBC) mode, Cipher Feedback (CFB) mode (fixed data segment size of 128 bits, i.e., CFB-128), Output Feedback (OFB) mode and Counter (CTR) mode.
5353
For more information on these cipher modes, refer to [Recommendation for Block Cipher Modes of Operation](https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-38a.pdf).
54-
Galois/Counter Mode (GCM) can be implemented using [Ibex](../rv_core_ibex/README.md) for the GHASH operation as demonstrated in the [OpenTitan Cryptography Library](../../../doc/security/cryptolib/README.md).
54+
Galois/Counter Mode (GCM) can be implemented using [Ibex](../../top_earlgrey/ip_autogen/rv_core_ibex/README.md) for the GHASH operation as demonstrated in the [OpenTitan Cryptography Library](../../../doc/security/cryptolib/README.md).
5555
To improve the performance of GCM, instructions of the [RISC-V Bit-Manipulation Extension of Ibex](https://ibex-core.readthedocs.io/en/latest/03_reference/instruction_decode_execute.html#arithmetic-logic-unit-alu) can be leveraged.
5656
In particular, carry-less multiply instructions can help to speed up the GHASH operation.
5757
For details on GCM, refer to [Recommendation for Block Cipher Modes of Operation: Galois/Counter Mode (GCM) and GMAC](https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-38d.pdf).

‎hw/ip_templates/rstmgr/doc/theory_of_operation.md.tpl

+1-1
Original file line numberDiff line numberDiff line change
@@ -306,7 +306,7 @@ Set [`ALERT_INFO_CTRL.INDEX`](registers.md#alert_info_ctrl) to the desired segme
306306
The CPU information register contains the value of the CPU state prior to a triggered reset.
307307
Since this information differs in length between system implementation, the information register only displays 32-bits at a time.
308308

309-
For more details on the CPU dump details, please see [crash dump](../../../../ip/rv_core_ibex/README.md#crash-dump-collection).
309+
For more details on the CPU dump details, please see [crash dump](../../rv_core_ibex/README.md#crash-dump-collection).
310310

311311
The [`CPU_INFO_ATTR`](registers.md#cpu_info_attr) register indicates how many 32-bit data segments must be read.
312312
Software then simply needs to write in [`CPU_INFO_CTRL.INDEX`](registers.md#cpu_info_ctrl) which segment it wishes and then read out the [`CPU_INFO`](registers.md#cpu_info) register.

‎hw/top_darjeeling/formal/top_darjeeling_fpv_sec_cm_cfgs.hjson

+1-1
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@@ -181,7 +181,7 @@
181181
{
182182
name: rv_core_ibex_sec_cm
183183
dut: rv_core_ibex
184-
fusesoc_core: lowrisc:dv:top_darjeeling_rv_core_ibex_sva
184+
fusesoc_core: lowrisc:darjeeling_dv:rv_core_ibex_sva
185185
import_cfgs: ["{proj_root}/hw/formal/tools/dvsim/common_fpv_cfg.hjson"]
186186
rel_path: "hw/ip/otbn/{sub_flow}/{tool}"
187187
stopats: ["*if_stage_i.pc_mismatch_alert_o",

‎hw/top_darjeeling/ip_autogen/rstmgr/doc/theory_of_operation.md

+1-1
Original file line numberDiff line numberDiff line change
@@ -304,7 +304,7 @@ Set [`ALERT_INFO_CTRL.INDEX`](registers.md#alert_info_ctrl) to the desired segme
304304
The CPU information register contains the value of the CPU state prior to a triggered reset.
305305
Since this information differs in length between system implementation, the information register only displays 32-bits at a time.
306306

307-
For more details on the CPU dump details, please see [crash dump](../../../../ip/rv_core_ibex/README.md#crash-dump-collection).
307+
For more details on the CPU dump details, please see [crash dump](../../rv_core_ibex/README.md#crash-dump-collection).
308308

309309
The [`CPU_INFO_ATTR`](registers.md#cpu_info_attr) register indicates how many 32-bit data segments must be read.
310310
Software then simply needs to write in [`CPU_INFO_CTRL.INDEX`](registers.md#cpu_info_ctrl) which segment it wishes and then read out the [`CPU_INFO`](registers.md#cpu_info) register.

‎hw/top_darjeeling/lint/top_darjeeling_lint_cfgs.hjson

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@@ -197,9 +197,15 @@
197197
]
198198
},
199199
{ name: rv_core_ibex
200-
fusesoc_core: lowrisc:ip:rv_core_ibex
201-
import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
202-
rel_path: "hw/ip/rv_core_ibex/lint/{tool}"
200+
fusesoc_core: lowrisc:darjeeling_ip:rv_core_ibex
201+
import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"],
202+
rel_path: "hw/top_darjeeling/ip_autogen/rv_core_ibex/lint/{tool}",
203+
overrides: [
204+
{
205+
name: design_level
206+
value: "top"
207+
}
208+
]
203209
},
204210
{ name: rv_dm
205211
fusesoc_core: lowrisc:ip:rv_dm

‎hw/top_darjeeling/sw/autogen/top_darjeeling_memory.ld

+1-1
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,6 @@ _rom1_chip_info_start = _rom1_chip_info_end - _chip_info_size;
5959
* large enough to cover the .crt section.
6060
*
6161
* NOTE: This value must match the size of the RX region in
62-
* hw/ip/rv_core_ibex/rtl/ibex_pmp_reset.svh.
62+
* hw/darjeeling/rtl/ibex_pmp_reset_pkg.sv.
6363
*/
6464
_epmp_reset_rx_size = 2048;

‎hw/top_earlgrey/formal/top_earlgrey_fpv_sec_cm_cfgs.hjson

+1-1
Original file line numberDiff line numberDiff line change
@@ -190,7 +190,7 @@
190190
{
191191
name: rv_core_ibex_sec_cm
192192
dut: rv_core_ibex
193-
fusesoc_core: lowrisc:dv:rv_core_ibex_sva
193+
fusesoc_core: lowrisc:earlgrey_dv:rv_core_ibex_sva
194194
import_cfgs: ["{proj_root}/hw/formal/tools/dvsim/common_fpv_cfg.hjson"]
195195
rel_path: "hw/ip/otbn/{sub_flow}/{tool}"
196196
stopats: ["*if_stage_i.pc_mismatch_alert_o",

‎hw/top_earlgrey/ip/BUILD

+1
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@@ -20,6 +20,7 @@ filegroup(
2020
"//hw/top_earlgrey/ip_autogen/pinmux:rtl_files",
2121
"//hw/top_earlgrey/ip_autogen/pwrmgr:rtl_files",
2222
"//hw/top_earlgrey/ip_autogen/rstmgr:rtl_files",
23+
"//hw/top_earlgrey/ip_autogen/rv_core_ibex:rtl_files",
2324
"//hw/top_earlgrey/ip_autogen/rv_plic:rtl_files",
2425
],
2526
)

‎hw/top_earlgrey/ip_autogen/rstmgr/doc/theory_of_operation.md

+1-1
Original file line numberDiff line numberDiff line change
@@ -304,7 +304,7 @@ Set [`ALERT_INFO_CTRL.INDEX`](registers.md#alert_info_ctrl) to the desired segme
304304
The CPU information register contains the value of the CPU state prior to a triggered reset.
305305
Since this information differs in length between system implementation, the information register only displays 32-bits at a time.
306306

307-
For more details on the CPU dump details, please see [crash dump](../../../../ip/rv_core_ibex/README.md#crash-dump-collection).
307+
For more details on the CPU dump details, please see [crash dump](../../rv_core_ibex/README.md#crash-dump-collection).
308308

309309
The [`CPU_INFO_ATTR`](registers.md#cpu_info_attr) register indicates how many 32-bit data segments must be read.
310310
Software then simply needs to write in [`CPU_INFO_CTRL.INDEX`](registers.md#cpu_info_ctrl) which segment it wishes and then read out the [`CPU_INFO`](registers.md#cpu_info) register.

‎hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson

+9-3
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@@ -213,9 +213,15 @@
213213
]
214214
},
215215
{ name: rv_core_ibex
216-
fusesoc_core: lowrisc:ip:rv_core_ibex
217-
import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
218-
rel_path: "hw/ip/rv_core_ibex/lint/{tool}"
216+
fusesoc_core: lowrisc:earlgrey_ip:rv_core_ibex
217+
import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"],
218+
rel_path: "hw/top_earlgrey/ip_autogen/rv_core_ibex/lint/{tool}",
219+
overrides: [
220+
{
221+
name: design_level
222+
value: "top"
223+
}
224+
]
219225
},
220226
{ name: rv_dm
221227
fusesoc_core: lowrisc:ip:rv_dm

‎hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld

+1-1
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@@ -55,6 +55,6 @@ _rom_chip_info_start = _rom_chip_info_end - _chip_info_size;
5555
* large enough to cover the .crt section.
5656
*
5757
* NOTE: This value must match the size of the RX region in
58-
* hw/ip/rv_core_ibex/rtl/ibex_pmp_reset.svh.
58+
* hw/earlgrey/rtl/ibex_pmp_reset_pkg.sv.
5959
*/
6060
_epmp_reset_rx_size = 2048;

‎hw/top_earlgrey/syn/top_earlgrey_batch_syn_cfg.hjson

+1-1
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@@ -18,7 +18,7 @@
1818
"{proj_root}/hw/ip/kmac/syn/kmac_syn_cfg.hjson",
1919
"{proj_root}/hw/ip/lc_ctrl/syn/lc_ctrl_syn_cfg.hjson",
2020
"{proj_root}/hw/ip/otbn/syn/otbn_syn_cfg.hjson",
21-
"{proj_root}/hw/ip/rv_core_ibex/syn/rv_core_ibex_syn_cfg.hjson",
21+
"{proj_root}/hw/top_earlgrey/ip_autogen/rv_core_ibex/syn/rv_core_ibex_syn_cfg.hjson",
2222
"{proj_root}/hw/top_earlgrey/ip_autogen/otp_ctrl/syn/otp_ctrl_syn_cfg.hjson",
2323
// Top-level synthesis flows.
2424
// TODO: align Verilator and ASIC versions.

‎hw/top_earlgrey/syn/top_earlgrey_gtech_batch_syn_cfg.hjson

+1-1
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@
1919
"{proj_root}/hw/ip/kmac/syn/kmac_gtech_syn_cfg.hjson",
2020
"{proj_root}/hw/ip/lc_ctrl/syn/lc_ctrl_gtech_syn_cfg.hjson",
2121
"{proj_root}/hw/ip/otbn/syn/otbn_gtech_syn_cfg.hjson",
22-
"{proj_root}/hw/ip/rv_core_ibex/syn/rv_core_ibex_gtech_syn_cfg.hjson",
22+
"{proj_root}/hw/top_earlgrey/ip_autogen/rv_core_ibex/syn/rv_core_ibex_gtech_syn_cfg.hjson",
2323
"{proj_root}/hw/top_earlgrey/ip_autogen/otp_ctrl/syn/otp_ctrl_gtech_syn_cfg.hjson",
2424
// Top-level GTECH synthesis flows.
2525
// TODO: align Verilator and ASIC versions.

‎hw/top_englishbreakfast/ip_autogen/rstmgr/doc/theory_of_operation.md

+1-1
Original file line numberDiff line numberDiff line change
@@ -299,7 +299,7 @@ Set [`ALERT_INFO_CTRL.INDEX`](registers.md#alert_info_ctrl) to the desired segme
299299
The CPU information register contains the value of the CPU state prior to a triggered reset.
300300
Since this information differs in length between system implementation, the information register only displays 32-bits at a time.
301301

302-
For more details on the CPU dump details, please see [crash dump](../../../../ip/rv_core_ibex/README.md#crash-dump-collection).
302+
For more details on the CPU dump details, please see [crash dump](../../rv_core_ibex/README.md#crash-dump-collection).
303303

304304
The [`CPU_INFO_ATTR`](registers.md#cpu_info_attr) register indicates how many 32-bit data segments must be read.
305305
Software then simply needs to write in [`CPU_INFO_CTRL.INDEX`](registers.md#cpu_info_ctrl) which segment it wishes and then read out the [`CPU_INFO`](registers.md#cpu_info) register.

‎hw/top_englishbreakfast/sw/autogen/top_englishbreakfast_memory.ld

+1-1
Original file line numberDiff line numberDiff line change
@@ -54,6 +54,6 @@ _rom_chip_info_start = _rom_chip_info_end - _chip_info_size;
5454
* large enough to cover the .crt section.
5555
*
5656
* NOTE: This value must match the size of the RX region in
57-
* hw/ip/rv_core_ibex/rtl/ibex_pmp_reset.svh.
57+
* hw/englishbreakfast/rtl/ibex_pmp_reset_pkg.sv.
5858
*/
5959
_epmp_reset_rx_size = 2048;

‎sw/device/lib/dif/dif_rv_core_ibex.md

+1-1
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# Rv core ibex DIF Checklist
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This checklist is for [Development Stage](../../../../doc/project_governance/development_stages.md) transitions for the [Rv core ibex DIF](../../../../hw/ip/rv_core_ibex/README.md).
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This checklist is for [Development Stage](../../../../doc/project_governance/development_stages.md) transitions for the [Rv core ibex DIF](../../../../hw/top_earlgrey/ip_autogen/rv_core_ibex/README.md).
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All checklist items refer to the content in the [Checklist](../../../../doc/project_governance/checklist/README.md).
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<h2>DIF Checklist</h2>

‎sw/device/tests/rv_core_ibex_epmp_test.c

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* Sets up the execution area of Machine Mode.
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*
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* This configuration adjusts the existing configuration from the
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* [reset PMP configuration](/hw/ip/rv_core_ibex/rtl/ibex_pmp_reset.svh)
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* [reset PMP configuration](/hw/top_{}/ip_autogen/rtl/ibex_pmp_reset_pkg.sv)
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* and [SRAM loader](/sw/host/opentitanlib/src/test_utils/load_sram_program.rs).
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*
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* These changes are needed before mseccfg.MML is enabled,

‎sw/host/opentitanlib/src/test_utils/load_sram_program.rs

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/// [0]: https://opentitan.org/book/sw/device/silicon_creator/rom/doc/memory_protection.html
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/// [1]: https://github.com/lowRISC/opentitan/issues/14978
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/// [2]: https://riscv.org/wp-content/uploads/2019/03/riscv-debug-release.pdf
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/// [3]: https://github.com/lowRISC/opentitan/blob/master/hw/ip/rv_core_ibex/rtl/ibex_pmp_reset.svh
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/// [3]: https://github.com/lowRISC/opentitan/blob/master/hw/top_earlgrey/rtl/ibex_pmp_reset_pkg.sv
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pub fn prepare_epmp(jtag: &mut dyn Jtag) -> Result<()> {
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// Setup ePMP for SRAM execution.
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log::info!("Configure ePMP for SRAM execution.");

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