diff --git a/hw/ip_templates/ac_range_check/data/ac_range_check.hjson.tpl b/hw/ip_templates/ac_range_check/data/ac_range_check.hjson.tpl index dfadec41b3507..311abe339dee7 100644 --- a/hw/ip_templates/ac_range_check/data/ac_range_check.hjson.tpl +++ b/hw/ip_templates/ac_range_check/data/ac_range_check.hjson.tpl @@ -112,6 +112,46 @@ import math ] regwidth: "32" registers: [ + { name: "ALERT_STATUS" + desc: "Status of hardware alerts." + swaccess: "ro" + hwaccess: "hwo" + fields: [ + { bits: "0" + name: "SHADOWED_UPDATE_ERR" + resval: "0" + swaccess: "rc" + desc: '''Update error of a shadowed register. + This is a recoverable error caused by SW misbehavior. + This field gets cleared by a SW read. + ''' + } + { bits: "1" + name: "SHADOWED_STORAGE_ERR" + resval: "0" + desc: '''Storage error of a shadowed register. + This is a fatal error. + Once set, this field remains set until this HW IP block gets reset. + ''' + } + { bits: "2" + name: "REG_INTG_ERR" + resval: "0" + desc: '''Integrity error in the register interface. + This is a fatal error. + Once set, this field remains set until this HW IP block gets reset. + ''' + } + { bits: "3" + name: "COUNTER_ERR" + resval: "0" + desc: '''Integrity error in a counter. + This is a fatal error. + Once set, this field remains set until this HW IP block gets reset. + ''' + } + ] + } { name: "LOG_CONFIG" desc: "" swaccess: "rw" diff --git a/hw/ip_templates/ac_range_check/rtl/ac_range_check.sv.tpl b/hw/ip_templates/ac_range_check/rtl/ac_range_check.sv.tpl index 32848624f9362..d3a200b6d0df0 100644 --- a/hw/ip_templates/ac_range_check/rtl/ac_range_check.sv.tpl +++ b/hw/ip_templates/ac_range_check/rtl/ac_range_check.sv.tpl @@ -94,6 +94,15 @@ module ${module_instance_name} ); end + assign hw2reg.alert_status.shadowed_storage_err.d = 1'b1; + assign hw2reg.alert_status.shadowed_storage_err.de = shadowed_storage_err; + assign hw2reg.alert_status.shadowed_update_err.d = 1'b1; + assign hw2reg.alert_status.shadowed_update_err.de = shadowed_update_err; + assign hw2reg.alert_status.reg_intg_err.d = 1'b1; + assign hw2reg.alert_status.reg_intg_err.de = reg_intg_error; + assign hw2reg.alert_status.counter_err.d = 1'b1; + assign hw2reg.alert_status.counter_err.de = deny_cnt_error; + ////////////////////////////////////////////////////////////////////////////// // Range Check Logic ////////////////////////////////////////////////////////////////////////////// diff --git a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson index 22946308e07f8..63b70995ef1f9 100644 --- a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson +++ b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson @@ -9885,6 +9885,7 @@ INTR_ENABLE: 2 INTR_TEST: 2 ALERT_TEST: 2 + ALERT_STATUS: 2 LOG_CONFIG: 2 LOG_STATUS: 2 LOG_ADDRESS: 2 diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/data/ac_range_check.hjson b/hw/top_darjeeling/ip_autogen/ac_range_check/data/ac_range_check.hjson index 3c5ea8105b2ac..f1c53c05f4fcb 100644 --- a/hw/top_darjeeling/ip_autogen/ac_range_check/data/ac_range_check.hjson +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/data/ac_range_check.hjson @@ -109,6 +109,46 @@ ] regwidth: "32" registers: [ + { name: "ALERT_STATUS" + desc: "Status of hardware alerts." + swaccess: "ro" + hwaccess: "hwo" + fields: [ + { bits: "0" + name: "SHADOWED_UPDATE_ERR" + resval: "0" + swaccess: "rc" + desc: '''Update error of a shadowed register. + This is a recoverable error caused by SW misbehavior. + This field gets cleared by a SW read. + ''' + } + { bits: "1" + name: "SHADOWED_STORAGE_ERR" + resval: "0" + desc: '''Storage error of a shadowed register. + This is a fatal error. + Once set, this field remains set until this HW IP block gets reset. + ''' + } + { bits: "2" + name: "REG_INTG_ERR" + resval: "0" + desc: '''Integrity error in the register interface. + This is a fatal error. + Once set, this field remains set until this HW IP block gets reset. + ''' + } + { bits: "3" + name: "COUNTER_ERR" + resval: "0" + desc: '''Integrity error in a counter. + This is a fatal error. + Once set, this field remains set until this HW IP block gets reset. + ''' + } + ] + } { name: "LOG_CONFIG" desc: "" swaccess: "rw" diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/doc/registers.md b/hw/top_darjeeling/ip_autogen/ac_range_check/doc/registers.md index 941842f760d6e..e1f425b406443 100644 --- a/hw/top_darjeeling/ip_autogen/ac_range_check/doc/registers.md +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/doc/registers.md @@ -9,169 +9,170 @@ | ac_range_check.[`INTR_ENABLE`](#intr_enable) | 0x4 | 4 | Interrupt Enable Register | | ac_range_check.[`INTR_TEST`](#intr_test) | 0x8 | 4 | Interrupt Test Register | | ac_range_check.[`ALERT_TEST`](#alert_test) | 0xc | 4 | Alert Test Register | -| ac_range_check.[`LOG_CONFIG`](#log_config) | 0x10 | 4 | | -| ac_range_check.[`LOG_STATUS`](#log_status) | 0x14 | 4 | The LOG_STATUS register stores the number of denied accesses and gives more detailed diagnostics to the first denied request. | -| ac_range_check.[`LOG_ADDRESS`](#log_address) | 0x18 | 4 | First denied request address (if logging is enabled) gets written into that register. | -| ac_range_check.[`RANGE_REGWEN_0`](#range_regwen) | 0x1c | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_1`](#range_regwen) | 0x20 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_2`](#range_regwen) | 0x24 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_3`](#range_regwen) | 0x28 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_4`](#range_regwen) | 0x2c | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_5`](#range_regwen) | 0x30 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_6`](#range_regwen) | 0x34 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_7`](#range_regwen) | 0x38 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_8`](#range_regwen) | 0x3c | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_9`](#range_regwen) | 0x40 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_10`](#range_regwen) | 0x44 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_11`](#range_regwen) | 0x48 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_12`](#range_regwen) | 0x4c | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_13`](#range_regwen) | 0x50 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_14`](#range_regwen) | 0x54 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_15`](#range_regwen) | 0x58 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_16`](#range_regwen) | 0x5c | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_17`](#range_regwen) | 0x60 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_18`](#range_regwen) | 0x64 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_19`](#range_regwen) | 0x68 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_20`](#range_regwen) | 0x6c | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_21`](#range_regwen) | 0x70 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_22`](#range_regwen) | 0x74 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_23`](#range_regwen) | 0x78 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_24`](#range_regwen) | 0x7c | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_25`](#range_regwen) | 0x80 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_26`](#range_regwen) | 0x84 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_27`](#range_regwen) | 0x88 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_28`](#range_regwen) | 0x8c | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_29`](#range_regwen) | 0x90 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_30`](#range_regwen) | 0x94 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_REGWEN_31`](#range_regwen) | 0x98 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | -| ac_range_check.[`RANGE_BASE_0`](#range_base) | 0x9c | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_1`](#range_base) | 0xa0 | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_2`](#range_base) | 0xa4 | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_3`](#range_base) | 0xa8 | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_4`](#range_base) | 0xac | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_5`](#range_base) | 0xb0 | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_6`](#range_base) | 0xb4 | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_7`](#range_base) | 0xb8 | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_8`](#range_base) | 0xbc | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_9`](#range_base) | 0xc0 | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_10`](#range_base) | 0xc4 | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_11`](#range_base) | 0xc8 | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_12`](#range_base) | 0xcc | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_13`](#range_base) | 0xd0 | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_14`](#range_base) | 0xd4 | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_15`](#range_base) | 0xd8 | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_16`](#range_base) | 0xdc | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_17`](#range_base) | 0xe0 | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_18`](#range_base) | 0xe4 | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_19`](#range_base) | 0xe8 | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_20`](#range_base) | 0xec | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_21`](#range_base) | 0xf0 | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_22`](#range_base) | 0xf4 | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_23`](#range_base) | 0xf8 | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_24`](#range_base) | 0xfc | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_25`](#range_base) | 0x100 | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_26`](#range_base) | 0x104 | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_27`](#range_base) | 0x108 | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_28`](#range_base) | 0x10c | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_29`](#range_base) | 0x110 | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_30`](#range_base) | 0x114 | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_BASE_31`](#range_base) | 0x118 | 4 | Base address for the range check. | -| ac_range_check.[`RANGE_LIMIT_0`](#range_limit) | 0x11c | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_1`](#range_limit) | 0x120 | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_2`](#range_limit) | 0x124 | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_3`](#range_limit) | 0x128 | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_4`](#range_limit) | 0x12c | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_5`](#range_limit) | 0x130 | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_6`](#range_limit) | 0x134 | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_7`](#range_limit) | 0x138 | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_8`](#range_limit) | 0x13c | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_9`](#range_limit) | 0x140 | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_10`](#range_limit) | 0x144 | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_11`](#range_limit) | 0x148 | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_12`](#range_limit) | 0x14c | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_13`](#range_limit) | 0x150 | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_14`](#range_limit) | 0x154 | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_15`](#range_limit) | 0x158 | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_16`](#range_limit) | 0x15c | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_17`](#range_limit) | 0x160 | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_18`](#range_limit) | 0x164 | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_19`](#range_limit) | 0x168 | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_20`](#range_limit) | 0x16c | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_21`](#range_limit) | 0x170 | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_22`](#range_limit) | 0x174 | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_23`](#range_limit) | 0x178 | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_24`](#range_limit) | 0x17c | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_25`](#range_limit) | 0x180 | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_26`](#range_limit) | 0x184 | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_27`](#range_limit) | 0x188 | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_28`](#range_limit) | 0x18c | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_29`](#range_limit) | 0x190 | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_30`](#range_limit) | 0x194 | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_LIMIT_31`](#range_limit) | 0x198 | 4 | The (exclusive) limit address register used for the address matching. | -| ac_range_check.[`RANGE_PERM_0`](#range_perm) | 0x19c | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_1`](#range_perm) | 0x1a0 | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_2`](#range_perm) | 0x1a4 | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_3`](#range_perm) | 0x1a8 | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_4`](#range_perm) | 0x1ac | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_5`](#range_perm) | 0x1b0 | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_6`](#range_perm) | 0x1b4 | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_7`](#range_perm) | 0x1b8 | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_8`](#range_perm) | 0x1bc | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_9`](#range_perm) | 0x1c0 | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_10`](#range_perm) | 0x1c4 | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_11`](#range_perm) | 0x1c8 | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_12`](#range_perm) | 0x1cc | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_13`](#range_perm) | 0x1d0 | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_14`](#range_perm) | 0x1d4 | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_15`](#range_perm) | 0x1d8 | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_16`](#range_perm) | 0x1dc | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_17`](#range_perm) | 0x1e0 | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_18`](#range_perm) | 0x1e4 | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_19`](#range_perm) | 0x1e8 | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_20`](#range_perm) | 0x1ec | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_21`](#range_perm) | 0x1f0 | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_22`](#range_perm) | 0x1f4 | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_23`](#range_perm) | 0x1f8 | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_24`](#range_perm) | 0x1fc | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_25`](#range_perm) | 0x200 | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_26`](#range_perm) | 0x204 | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_27`](#range_perm) | 0x208 | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_28`](#range_perm) | 0x20c | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_29`](#range_perm) | 0x210 | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_30`](#range_perm) | 0x214 | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_PERM_31`](#range_perm) | 0x218 | 4 | Permission configuration of the range. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_0`](#range_racl_policy_shadowed) | 0x21c | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_1`](#range_racl_policy_shadowed) | 0x220 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_2`](#range_racl_policy_shadowed) | 0x224 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_3`](#range_racl_policy_shadowed) | 0x228 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_4`](#range_racl_policy_shadowed) | 0x22c | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_5`](#range_racl_policy_shadowed) | 0x230 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_6`](#range_racl_policy_shadowed) | 0x234 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_7`](#range_racl_policy_shadowed) | 0x238 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_8`](#range_racl_policy_shadowed) | 0x23c | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_9`](#range_racl_policy_shadowed) | 0x240 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_10`](#range_racl_policy_shadowed) | 0x244 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_11`](#range_racl_policy_shadowed) | 0x248 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_12`](#range_racl_policy_shadowed) | 0x24c | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_13`](#range_racl_policy_shadowed) | 0x250 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_14`](#range_racl_policy_shadowed) | 0x254 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_15`](#range_racl_policy_shadowed) | 0x258 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_16`](#range_racl_policy_shadowed) | 0x25c | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_17`](#range_racl_policy_shadowed) | 0x260 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_18`](#range_racl_policy_shadowed) | 0x264 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_19`](#range_racl_policy_shadowed) | 0x268 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_20`](#range_racl_policy_shadowed) | 0x26c | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_21`](#range_racl_policy_shadowed) | 0x270 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_22`](#range_racl_policy_shadowed) | 0x274 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_23`](#range_racl_policy_shadowed) | 0x278 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_24`](#range_racl_policy_shadowed) | 0x27c | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_25`](#range_racl_policy_shadowed) | 0x280 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_26`](#range_racl_policy_shadowed) | 0x284 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_27`](#range_racl_policy_shadowed) | 0x288 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_28`](#range_racl_policy_shadowed) | 0x28c | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_29`](#range_racl_policy_shadowed) | 0x290 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_30`](#range_racl_policy_shadowed) | 0x294 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | -| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_31`](#range_racl_policy_shadowed) | 0x298 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`ALERT_STATUS`](#alert_status) | 0x10 | 4 | Status of hardware alerts. | +| ac_range_check.[`LOG_CONFIG`](#log_config) | 0x14 | 4 | | +| ac_range_check.[`LOG_STATUS`](#log_status) | 0x18 | 4 | The LOG_STATUS register stores the number of denied accesses and gives more detailed diagnostics to the first denied request. | +| ac_range_check.[`LOG_ADDRESS`](#log_address) | 0x1c | 4 | First denied request address (if logging is enabled) gets written into that register. | +| ac_range_check.[`RANGE_REGWEN_0`](#range_regwen) | 0x20 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_1`](#range_regwen) | 0x24 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_2`](#range_regwen) | 0x28 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_3`](#range_regwen) | 0x2c | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_4`](#range_regwen) | 0x30 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_5`](#range_regwen) | 0x34 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_6`](#range_regwen) | 0x38 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_7`](#range_regwen) | 0x3c | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_8`](#range_regwen) | 0x40 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_9`](#range_regwen) | 0x44 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_10`](#range_regwen) | 0x48 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_11`](#range_regwen) | 0x4c | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_12`](#range_regwen) | 0x50 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_13`](#range_regwen) | 0x54 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_14`](#range_regwen) | 0x58 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_15`](#range_regwen) | 0x5c | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_16`](#range_regwen) | 0x60 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_17`](#range_regwen) | 0x64 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_18`](#range_regwen) | 0x68 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_19`](#range_regwen) | 0x6c | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_20`](#range_regwen) | 0x70 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_21`](#range_regwen) | 0x74 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_22`](#range_regwen) | 0x78 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_23`](#range_regwen) | 0x7c | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_24`](#range_regwen) | 0x80 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_25`](#range_regwen) | 0x84 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_26`](#range_regwen) | 0x88 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_27`](#range_regwen) | 0x8c | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_28`](#range_regwen) | 0x90 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_29`](#range_regwen) | 0x94 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_30`](#range_regwen) | 0x98 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_31`](#range_regwen) | 0x9c | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_PERM_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_BASE_0`](#range_base) | 0xa0 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_1`](#range_base) | 0xa4 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_2`](#range_base) | 0xa8 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_3`](#range_base) | 0xac | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_4`](#range_base) | 0xb0 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_5`](#range_base) | 0xb4 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_6`](#range_base) | 0xb8 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_7`](#range_base) | 0xbc | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_8`](#range_base) | 0xc0 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_9`](#range_base) | 0xc4 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_10`](#range_base) | 0xc8 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_11`](#range_base) | 0xcc | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_12`](#range_base) | 0xd0 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_13`](#range_base) | 0xd4 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_14`](#range_base) | 0xd8 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_15`](#range_base) | 0xdc | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_16`](#range_base) | 0xe0 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_17`](#range_base) | 0xe4 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_18`](#range_base) | 0xe8 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_19`](#range_base) | 0xec | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_20`](#range_base) | 0xf0 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_21`](#range_base) | 0xf4 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_22`](#range_base) | 0xf8 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_23`](#range_base) | 0xfc | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_24`](#range_base) | 0x100 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_25`](#range_base) | 0x104 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_26`](#range_base) | 0x108 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_27`](#range_base) | 0x10c | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_28`](#range_base) | 0x110 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_29`](#range_base) | 0x114 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_30`](#range_base) | 0x118 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_31`](#range_base) | 0x11c | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_LIMIT_0`](#range_limit) | 0x120 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_1`](#range_limit) | 0x124 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_2`](#range_limit) | 0x128 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_3`](#range_limit) | 0x12c | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_4`](#range_limit) | 0x130 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_5`](#range_limit) | 0x134 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_6`](#range_limit) | 0x138 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_7`](#range_limit) | 0x13c | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_8`](#range_limit) | 0x140 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_9`](#range_limit) | 0x144 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_10`](#range_limit) | 0x148 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_11`](#range_limit) | 0x14c | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_12`](#range_limit) | 0x150 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_13`](#range_limit) | 0x154 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_14`](#range_limit) | 0x158 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_15`](#range_limit) | 0x15c | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_16`](#range_limit) | 0x160 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_17`](#range_limit) | 0x164 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_18`](#range_limit) | 0x168 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_19`](#range_limit) | 0x16c | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_20`](#range_limit) | 0x170 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_21`](#range_limit) | 0x174 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_22`](#range_limit) | 0x178 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_23`](#range_limit) | 0x17c | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_24`](#range_limit) | 0x180 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_25`](#range_limit) | 0x184 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_26`](#range_limit) | 0x188 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_27`](#range_limit) | 0x18c | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_28`](#range_limit) | 0x190 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_29`](#range_limit) | 0x194 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_30`](#range_limit) | 0x198 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_31`](#range_limit) | 0x19c | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_PERM_0`](#range_perm) | 0x1a0 | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_1`](#range_perm) | 0x1a4 | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_2`](#range_perm) | 0x1a8 | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_3`](#range_perm) | 0x1ac | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_4`](#range_perm) | 0x1b0 | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_5`](#range_perm) | 0x1b4 | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_6`](#range_perm) | 0x1b8 | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_7`](#range_perm) | 0x1bc | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_8`](#range_perm) | 0x1c0 | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_9`](#range_perm) | 0x1c4 | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_10`](#range_perm) | 0x1c8 | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_11`](#range_perm) | 0x1cc | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_12`](#range_perm) | 0x1d0 | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_13`](#range_perm) | 0x1d4 | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_14`](#range_perm) | 0x1d8 | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_15`](#range_perm) | 0x1dc | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_16`](#range_perm) | 0x1e0 | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_17`](#range_perm) | 0x1e4 | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_18`](#range_perm) | 0x1e8 | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_19`](#range_perm) | 0x1ec | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_20`](#range_perm) | 0x1f0 | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_21`](#range_perm) | 0x1f4 | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_22`](#range_perm) | 0x1f8 | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_23`](#range_perm) | 0x1fc | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_24`](#range_perm) | 0x200 | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_25`](#range_perm) | 0x204 | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_26`](#range_perm) | 0x208 | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_27`](#range_perm) | 0x20c | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_28`](#range_perm) | 0x210 | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_29`](#range_perm) | 0x214 | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_30`](#range_perm) | 0x218 | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_PERM_31`](#range_perm) | 0x21c | 4 | Permission configuration of the range. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_0`](#range_racl_policy_shadowed) | 0x220 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_1`](#range_racl_policy_shadowed) | 0x224 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_2`](#range_racl_policy_shadowed) | 0x228 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_3`](#range_racl_policy_shadowed) | 0x22c | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_4`](#range_racl_policy_shadowed) | 0x230 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_5`](#range_racl_policy_shadowed) | 0x234 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_6`](#range_racl_policy_shadowed) | 0x238 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_7`](#range_racl_policy_shadowed) | 0x23c | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_8`](#range_racl_policy_shadowed) | 0x240 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_9`](#range_racl_policy_shadowed) | 0x244 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_10`](#range_racl_policy_shadowed) | 0x248 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_11`](#range_racl_policy_shadowed) | 0x24c | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_12`](#range_racl_policy_shadowed) | 0x250 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_13`](#range_racl_policy_shadowed) | 0x254 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_14`](#range_racl_policy_shadowed) | 0x258 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_15`](#range_racl_policy_shadowed) | 0x25c | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_16`](#range_racl_policy_shadowed) | 0x260 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_17`](#range_racl_policy_shadowed) | 0x264 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_18`](#range_racl_policy_shadowed) | 0x268 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_19`](#range_racl_policy_shadowed) | 0x26c | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_20`](#range_racl_policy_shadowed) | 0x270 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_21`](#range_racl_policy_shadowed) | 0x274 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_22`](#range_racl_policy_shadowed) | 0x278 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_23`](#range_racl_policy_shadowed) | 0x27c | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_24`](#range_racl_policy_shadowed) | 0x280 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_25`](#range_racl_policy_shadowed) | 0x284 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_26`](#range_racl_policy_shadowed) | 0x288 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_27`](#range_racl_policy_shadowed) | 0x28c | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_28`](#range_racl_policy_shadowed) | 0x290 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_29`](#range_racl_policy_shadowed) | 0x294 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_30`](#range_racl_policy_shadowed) | 0x298 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_31`](#range_racl_policy_shadowed) | 0x29c | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | ## INTR_STATE Interrupt State Register @@ -242,9 +243,29 @@ Alert Test Register | 1 | wo | 0x0 | fatal_fault | Write 1 to trigger one alert event of this kind. | | 0 | wo | 0x0 | recov_ctrl_update_err | Write 1 to trigger one alert event of this kind. | +## ALERT_STATUS +Status of hardware alerts. +- Offset: `0x10` +- Reset default: `0x0` +- Reset mask: `0xf` + +### Fields + +```wavejson +{"reg": [{"name": "SHADOWED_UPDATE_ERR", "bits": 1, "attr": ["rc"], "rotate": -90}, {"name": "SHADOWED_STORAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "REG_INTG_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "COUNTER_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:---------------------|:--------------------------------------------------------------------------------------------------------------------------------------| +| 31:4 | | | | Reserved | +| 3 | ro | 0x0 | COUNTER_ERR | Integrity error in a counter. This is a fatal error. Once set, this field remains set until this HW IP block gets reset. | +| 2 | ro | 0x0 | REG_INTG_ERR | Integrity error in the register interface. This is a fatal error. Once set, this field remains set until this HW IP block gets reset. | +| 1 | ro | 0x0 | SHADOWED_STORAGE_ERR | Storage error of a shadowed register. This is a fatal error. Once set, this field remains set until this HW IP block gets reset. | +| 0 | rc | 0x0 | SHADOWED_UPDATE_ERR | Update error of a shadowed register. This is a recoverable error caused by SW misbehavior. This field gets cleared by a SW read. | + ## LOG_CONFIG -- Offset: `0x10` +- Offset: `0x14` - Reset default: `0x0` - Reset mask: `0x3ff` @@ -264,7 +285,7 @@ Alert Test Register ## LOG_STATUS The LOG_STATUS register stores the number of denied accesses and gives more detailed diagnostics to the first denied request. All fields of LOG_STATUS (other than deny_cnt) are only valid if deny_cnt > 0. -- Offset: `0x14` +- Offset: `0x18` - Reset default: `0x0` - Reset mask: `0xfffffff` @@ -290,7 +311,7 @@ All fields of LOG_STATUS (other than deny_cnt) are only valid if deny_cnt > 0. ## LOG_ADDRESS First denied request address (if logging is enabled) gets written into that register. -- Offset: `0x18` +- Offset: `0x1c` - Reset default: `0x0` - Reset mask: `0xffffffff` @@ -314,38 +335,38 @@ When cleared to Mubi4::False, the corresponding range configuration registers ar | Name | Offset | |:----------------|:---------| -| RANGE_REGWEN_0 | 0x1c | -| RANGE_REGWEN_1 | 0x20 | -| RANGE_REGWEN_2 | 0x24 | -| RANGE_REGWEN_3 | 0x28 | -| RANGE_REGWEN_4 | 0x2c | -| RANGE_REGWEN_5 | 0x30 | -| RANGE_REGWEN_6 | 0x34 | -| RANGE_REGWEN_7 | 0x38 | -| RANGE_REGWEN_8 | 0x3c | -| RANGE_REGWEN_9 | 0x40 | -| RANGE_REGWEN_10 | 0x44 | -| RANGE_REGWEN_11 | 0x48 | -| RANGE_REGWEN_12 | 0x4c | -| RANGE_REGWEN_13 | 0x50 | -| RANGE_REGWEN_14 | 0x54 | -| RANGE_REGWEN_15 | 0x58 | -| RANGE_REGWEN_16 | 0x5c | -| RANGE_REGWEN_17 | 0x60 | -| RANGE_REGWEN_18 | 0x64 | -| RANGE_REGWEN_19 | 0x68 | -| RANGE_REGWEN_20 | 0x6c | -| RANGE_REGWEN_21 | 0x70 | -| RANGE_REGWEN_22 | 0x74 | -| RANGE_REGWEN_23 | 0x78 | -| RANGE_REGWEN_24 | 0x7c | -| RANGE_REGWEN_25 | 0x80 | -| RANGE_REGWEN_26 | 0x84 | -| RANGE_REGWEN_27 | 0x88 | -| RANGE_REGWEN_28 | 0x8c | -| RANGE_REGWEN_29 | 0x90 | -| RANGE_REGWEN_30 | 0x94 | -| RANGE_REGWEN_31 | 0x98 | +| RANGE_REGWEN_0 | 0x20 | +| RANGE_REGWEN_1 | 0x24 | +| RANGE_REGWEN_2 | 0x28 | +| RANGE_REGWEN_3 | 0x2c | +| RANGE_REGWEN_4 | 0x30 | +| RANGE_REGWEN_5 | 0x34 | +| RANGE_REGWEN_6 | 0x38 | +| RANGE_REGWEN_7 | 0x3c | +| RANGE_REGWEN_8 | 0x40 | +| RANGE_REGWEN_9 | 0x44 | +| RANGE_REGWEN_10 | 0x48 | +| RANGE_REGWEN_11 | 0x4c | +| RANGE_REGWEN_12 | 0x50 | +| RANGE_REGWEN_13 | 0x54 | +| RANGE_REGWEN_14 | 0x58 | +| RANGE_REGWEN_15 | 0x5c | +| RANGE_REGWEN_16 | 0x60 | +| RANGE_REGWEN_17 | 0x64 | +| RANGE_REGWEN_18 | 0x68 | +| RANGE_REGWEN_19 | 0x6c | +| RANGE_REGWEN_20 | 0x70 | +| RANGE_REGWEN_21 | 0x74 | +| RANGE_REGWEN_22 | 0x78 | +| RANGE_REGWEN_23 | 0x7c | +| RANGE_REGWEN_24 | 0x80 | +| RANGE_REGWEN_25 | 0x84 | +| RANGE_REGWEN_26 | 0x88 | +| RANGE_REGWEN_27 | 0x8c | +| RANGE_REGWEN_28 | 0x90 | +| RANGE_REGWEN_29 | 0x94 | +| RANGE_REGWEN_30 | 0x98 | +| RANGE_REGWEN_31 | 0x9c | ### Fields @@ -372,38 +393,38 @@ Therefore, the lowest 2 bits of the 32-bit base and limit registers are tied to | Name | Offset | |:--------------|:---------| -| RANGE_BASE_0 | 0x9c | -| RANGE_BASE_1 | 0xa0 | -| RANGE_BASE_2 | 0xa4 | -| RANGE_BASE_3 | 0xa8 | -| RANGE_BASE_4 | 0xac | -| RANGE_BASE_5 | 0xb0 | -| RANGE_BASE_6 | 0xb4 | -| RANGE_BASE_7 | 0xb8 | -| RANGE_BASE_8 | 0xbc | -| RANGE_BASE_9 | 0xc0 | -| RANGE_BASE_10 | 0xc4 | -| RANGE_BASE_11 | 0xc8 | -| RANGE_BASE_12 | 0xcc | -| RANGE_BASE_13 | 0xd0 | -| RANGE_BASE_14 | 0xd4 | -| RANGE_BASE_15 | 0xd8 | -| RANGE_BASE_16 | 0xdc | -| RANGE_BASE_17 | 0xe0 | -| RANGE_BASE_18 | 0xe4 | -| RANGE_BASE_19 | 0xe8 | -| RANGE_BASE_20 | 0xec | -| RANGE_BASE_21 | 0xf0 | -| RANGE_BASE_22 | 0xf4 | -| RANGE_BASE_23 | 0xf8 | -| RANGE_BASE_24 | 0xfc | -| RANGE_BASE_25 | 0x100 | -| RANGE_BASE_26 | 0x104 | -| RANGE_BASE_27 | 0x108 | -| RANGE_BASE_28 | 0x10c | -| RANGE_BASE_29 | 0x110 | -| RANGE_BASE_30 | 0x114 | -| RANGE_BASE_31 | 0x118 | +| RANGE_BASE_0 | 0xa0 | +| RANGE_BASE_1 | 0xa4 | +| RANGE_BASE_2 | 0xa8 | +| RANGE_BASE_3 | 0xac | +| RANGE_BASE_4 | 0xb0 | +| RANGE_BASE_5 | 0xb4 | +| RANGE_BASE_6 | 0xb8 | +| RANGE_BASE_7 | 0xbc | +| RANGE_BASE_8 | 0xc0 | +| RANGE_BASE_9 | 0xc4 | +| RANGE_BASE_10 | 0xc8 | +| RANGE_BASE_11 | 0xcc | +| RANGE_BASE_12 | 0xd0 | +| RANGE_BASE_13 | 0xd4 | +| RANGE_BASE_14 | 0xd8 | +| RANGE_BASE_15 | 0xdc | +| RANGE_BASE_16 | 0xe0 | +| RANGE_BASE_17 | 0xe4 | +| RANGE_BASE_18 | 0xe8 | +| RANGE_BASE_19 | 0xec | +| RANGE_BASE_20 | 0xf0 | +| RANGE_BASE_21 | 0xf4 | +| RANGE_BASE_22 | 0xf8 | +| RANGE_BASE_23 | 0xfc | +| RANGE_BASE_24 | 0x100 | +| RANGE_BASE_25 | 0x104 | +| RANGE_BASE_26 | 0x108 | +| RANGE_BASE_27 | 0x10c | +| RANGE_BASE_28 | 0x110 | +| RANGE_BASE_29 | 0x114 | +| RANGE_BASE_30 | 0x118 | +| RANGE_BASE_31 | 0x11c | ### Fields @@ -427,38 +448,38 @@ The (exclusive) limit address register used for the address matching. | Name | Offset | |:---------------|:---------| -| RANGE_LIMIT_0 | 0x11c | -| RANGE_LIMIT_1 | 0x120 | -| RANGE_LIMIT_2 | 0x124 | -| RANGE_LIMIT_3 | 0x128 | -| RANGE_LIMIT_4 | 0x12c | -| RANGE_LIMIT_5 | 0x130 | -| RANGE_LIMIT_6 | 0x134 | -| RANGE_LIMIT_7 | 0x138 | -| RANGE_LIMIT_8 | 0x13c | -| RANGE_LIMIT_9 | 0x140 | -| RANGE_LIMIT_10 | 0x144 | -| RANGE_LIMIT_11 | 0x148 | -| RANGE_LIMIT_12 | 0x14c | -| RANGE_LIMIT_13 | 0x150 | -| RANGE_LIMIT_14 | 0x154 | -| RANGE_LIMIT_15 | 0x158 | -| RANGE_LIMIT_16 | 0x15c | -| RANGE_LIMIT_17 | 0x160 | -| RANGE_LIMIT_18 | 0x164 | -| RANGE_LIMIT_19 | 0x168 | -| RANGE_LIMIT_20 | 0x16c | -| RANGE_LIMIT_21 | 0x170 | -| RANGE_LIMIT_22 | 0x174 | -| RANGE_LIMIT_23 | 0x178 | -| RANGE_LIMIT_24 | 0x17c | -| RANGE_LIMIT_25 | 0x180 | -| RANGE_LIMIT_26 | 0x184 | -| RANGE_LIMIT_27 | 0x188 | -| RANGE_LIMIT_28 | 0x18c | -| RANGE_LIMIT_29 | 0x190 | -| RANGE_LIMIT_30 | 0x194 | -| RANGE_LIMIT_31 | 0x198 | +| RANGE_LIMIT_0 | 0x120 | +| RANGE_LIMIT_1 | 0x124 | +| RANGE_LIMIT_2 | 0x128 | +| RANGE_LIMIT_3 | 0x12c | +| RANGE_LIMIT_4 | 0x130 | +| RANGE_LIMIT_5 | 0x134 | +| RANGE_LIMIT_6 | 0x138 | +| RANGE_LIMIT_7 | 0x13c | +| RANGE_LIMIT_8 | 0x140 | +| RANGE_LIMIT_9 | 0x144 | +| RANGE_LIMIT_10 | 0x148 | +| RANGE_LIMIT_11 | 0x14c | +| RANGE_LIMIT_12 | 0x150 | +| RANGE_LIMIT_13 | 0x154 | +| RANGE_LIMIT_14 | 0x158 | +| RANGE_LIMIT_15 | 0x15c | +| RANGE_LIMIT_16 | 0x160 | +| RANGE_LIMIT_17 | 0x164 | +| RANGE_LIMIT_18 | 0x168 | +| RANGE_LIMIT_19 | 0x16c | +| RANGE_LIMIT_20 | 0x170 | +| RANGE_LIMIT_21 | 0x174 | +| RANGE_LIMIT_22 | 0x178 | +| RANGE_LIMIT_23 | 0x17c | +| RANGE_LIMIT_24 | 0x180 | +| RANGE_LIMIT_25 | 0x184 | +| RANGE_LIMIT_26 | 0x188 | +| RANGE_LIMIT_27 | 0x18c | +| RANGE_LIMIT_28 | 0x190 | +| RANGE_LIMIT_29 | 0x194 | +| RANGE_LIMIT_30 | 0x198 | +| RANGE_LIMIT_31 | 0x19c | ### Fields @@ -484,38 +505,38 @@ If it is not enabled, the range is not considered during the range check. | Name | Offset | |:--------------|:---------| -| RANGE_PERM_0 | 0x19c | -| RANGE_PERM_1 | 0x1a0 | -| RANGE_PERM_2 | 0x1a4 | -| RANGE_PERM_3 | 0x1a8 | -| RANGE_PERM_4 | 0x1ac | -| RANGE_PERM_5 | 0x1b0 | -| RANGE_PERM_6 | 0x1b4 | -| RANGE_PERM_7 | 0x1b8 | -| RANGE_PERM_8 | 0x1bc | -| RANGE_PERM_9 | 0x1c0 | -| RANGE_PERM_10 | 0x1c4 | -| RANGE_PERM_11 | 0x1c8 | -| RANGE_PERM_12 | 0x1cc | -| RANGE_PERM_13 | 0x1d0 | -| RANGE_PERM_14 | 0x1d4 | -| RANGE_PERM_15 | 0x1d8 | -| RANGE_PERM_16 | 0x1dc | -| RANGE_PERM_17 | 0x1e0 | -| RANGE_PERM_18 | 0x1e4 | -| RANGE_PERM_19 | 0x1e8 | -| RANGE_PERM_20 | 0x1ec | -| RANGE_PERM_21 | 0x1f0 | -| RANGE_PERM_22 | 0x1f4 | -| RANGE_PERM_23 | 0x1f8 | -| RANGE_PERM_24 | 0x1fc | -| RANGE_PERM_25 | 0x200 | -| RANGE_PERM_26 | 0x204 | -| RANGE_PERM_27 | 0x208 | -| RANGE_PERM_28 | 0x20c | -| RANGE_PERM_29 | 0x210 | -| RANGE_PERM_30 | 0x214 | -| RANGE_PERM_31 | 0x218 | +| RANGE_PERM_0 | 0x1a0 | +| RANGE_PERM_1 | 0x1a4 | +| RANGE_PERM_2 | 0x1a8 | +| RANGE_PERM_3 | 0x1ac | +| RANGE_PERM_4 | 0x1b0 | +| RANGE_PERM_5 | 0x1b4 | +| RANGE_PERM_6 | 0x1b8 | +| RANGE_PERM_7 | 0x1bc | +| RANGE_PERM_8 | 0x1c0 | +| RANGE_PERM_9 | 0x1c4 | +| RANGE_PERM_10 | 0x1c8 | +| RANGE_PERM_11 | 0x1cc | +| RANGE_PERM_12 | 0x1d0 | +| RANGE_PERM_13 | 0x1d4 | +| RANGE_PERM_14 | 0x1d8 | +| RANGE_PERM_15 | 0x1dc | +| RANGE_PERM_16 | 0x1e0 | +| RANGE_PERM_17 | 0x1e4 | +| RANGE_PERM_18 | 0x1e8 | +| RANGE_PERM_19 | 0x1ec | +| RANGE_PERM_20 | 0x1f0 | +| RANGE_PERM_21 | 0x1f4 | +| RANGE_PERM_22 | 0x1f8 | +| RANGE_PERM_23 | 0x1fc | +| RANGE_PERM_24 | 0x200 | +| RANGE_PERM_25 | 0x204 | +| RANGE_PERM_26 | 0x208 | +| RANGE_PERM_27 | 0x20c | +| RANGE_PERM_28 | 0x210 | +| RANGE_PERM_29 | 0x214 | +| RANGE_PERM_30 | 0x218 | +| RANGE_PERM_31 | 0x21c | ### Fields @@ -545,38 +566,38 @@ This register is protected against fault attacks by using a shadow register impl | Name | Offset | |:------------------------------|:---------| -| RANGE_RACL_POLICY_SHADOWED_0 | 0x21c | -| RANGE_RACL_POLICY_SHADOWED_1 | 0x220 | -| RANGE_RACL_POLICY_SHADOWED_2 | 0x224 | -| RANGE_RACL_POLICY_SHADOWED_3 | 0x228 | -| RANGE_RACL_POLICY_SHADOWED_4 | 0x22c | -| RANGE_RACL_POLICY_SHADOWED_5 | 0x230 | -| RANGE_RACL_POLICY_SHADOWED_6 | 0x234 | -| RANGE_RACL_POLICY_SHADOWED_7 | 0x238 | -| RANGE_RACL_POLICY_SHADOWED_8 | 0x23c | -| RANGE_RACL_POLICY_SHADOWED_9 | 0x240 | -| RANGE_RACL_POLICY_SHADOWED_10 | 0x244 | -| RANGE_RACL_POLICY_SHADOWED_11 | 0x248 | -| RANGE_RACL_POLICY_SHADOWED_12 | 0x24c | -| RANGE_RACL_POLICY_SHADOWED_13 | 0x250 | -| RANGE_RACL_POLICY_SHADOWED_14 | 0x254 | -| RANGE_RACL_POLICY_SHADOWED_15 | 0x258 | -| RANGE_RACL_POLICY_SHADOWED_16 | 0x25c | -| RANGE_RACL_POLICY_SHADOWED_17 | 0x260 | -| RANGE_RACL_POLICY_SHADOWED_18 | 0x264 | -| RANGE_RACL_POLICY_SHADOWED_19 | 0x268 | -| RANGE_RACL_POLICY_SHADOWED_20 | 0x26c | -| RANGE_RACL_POLICY_SHADOWED_21 | 0x270 | -| RANGE_RACL_POLICY_SHADOWED_22 | 0x274 | -| RANGE_RACL_POLICY_SHADOWED_23 | 0x278 | -| RANGE_RACL_POLICY_SHADOWED_24 | 0x27c | -| RANGE_RACL_POLICY_SHADOWED_25 | 0x280 | -| RANGE_RACL_POLICY_SHADOWED_26 | 0x284 | -| RANGE_RACL_POLICY_SHADOWED_27 | 0x288 | -| RANGE_RACL_POLICY_SHADOWED_28 | 0x28c | -| RANGE_RACL_POLICY_SHADOWED_29 | 0x290 | -| RANGE_RACL_POLICY_SHADOWED_30 | 0x294 | -| RANGE_RACL_POLICY_SHADOWED_31 | 0x298 | +| RANGE_RACL_POLICY_SHADOWED_0 | 0x220 | +| RANGE_RACL_POLICY_SHADOWED_1 | 0x224 | +| RANGE_RACL_POLICY_SHADOWED_2 | 0x228 | +| RANGE_RACL_POLICY_SHADOWED_3 | 0x22c | +| RANGE_RACL_POLICY_SHADOWED_4 | 0x230 | +| RANGE_RACL_POLICY_SHADOWED_5 | 0x234 | +| RANGE_RACL_POLICY_SHADOWED_6 | 0x238 | +| RANGE_RACL_POLICY_SHADOWED_7 | 0x23c | +| RANGE_RACL_POLICY_SHADOWED_8 | 0x240 | +| RANGE_RACL_POLICY_SHADOWED_9 | 0x244 | +| RANGE_RACL_POLICY_SHADOWED_10 | 0x248 | +| RANGE_RACL_POLICY_SHADOWED_11 | 0x24c | +| RANGE_RACL_POLICY_SHADOWED_12 | 0x250 | +| RANGE_RACL_POLICY_SHADOWED_13 | 0x254 | +| RANGE_RACL_POLICY_SHADOWED_14 | 0x258 | +| RANGE_RACL_POLICY_SHADOWED_15 | 0x25c | +| RANGE_RACL_POLICY_SHADOWED_16 | 0x260 | +| RANGE_RACL_POLICY_SHADOWED_17 | 0x264 | +| RANGE_RACL_POLICY_SHADOWED_18 | 0x268 | +| RANGE_RACL_POLICY_SHADOWED_19 | 0x26c | +| RANGE_RACL_POLICY_SHADOWED_20 | 0x270 | +| RANGE_RACL_POLICY_SHADOWED_21 | 0x274 | +| RANGE_RACL_POLICY_SHADOWED_22 | 0x278 | +| RANGE_RACL_POLICY_SHADOWED_23 | 0x27c | +| RANGE_RACL_POLICY_SHADOWED_24 | 0x280 | +| RANGE_RACL_POLICY_SHADOWED_25 | 0x284 | +| RANGE_RACL_POLICY_SHADOWED_26 | 0x288 | +| RANGE_RACL_POLICY_SHADOWED_27 | 0x28c | +| RANGE_RACL_POLICY_SHADOWED_28 | 0x290 | +| RANGE_RACL_POLICY_SHADOWED_29 | 0x294 | +| RANGE_RACL_POLICY_SHADOWED_30 | 0x298 | +| RANGE_RACL_POLICY_SHADOWED_31 | 0x29c | ### Fields diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/rtl/ac_range_check.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/rtl/ac_range_check.sv index 6fca322adffe3..16d1e57992fd6 100644 --- a/hw/top_darjeeling/ip_autogen/ac_range_check/rtl/ac_range_check.sv +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/rtl/ac_range_check.sv @@ -94,6 +94,15 @@ module ac_range_check ); end + assign hw2reg.alert_status.shadowed_storage_err.d = 1'b1; + assign hw2reg.alert_status.shadowed_storage_err.de = shadowed_storage_err; + assign hw2reg.alert_status.shadowed_update_err.d = 1'b1; + assign hw2reg.alert_status.shadowed_update_err.de = shadowed_update_err; + assign hw2reg.alert_status.reg_intg_err.d = 1'b1; + assign hw2reg.alert_status.reg_intg_err.de = reg_intg_error; + assign hw2reg.alert_status.counter_err.d = 1'b1; + assign hw2reg.alert_status.counter_err.de = deny_cnt_error; + ////////////////////////////////////////////////////////////////////////////// // Range Check Logic ////////////////////////////////////////////////////////////////////////////// diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/rtl/ac_range_check_reg_pkg.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/rtl/ac_range_check_reg_pkg.sv index 7d0efef4e8e5f..924ce270588b7 100644 --- a/hw/top_darjeeling/ip_autogen/ac_range_check/rtl/ac_range_check_reg_pkg.sv +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/rtl/ac_range_check_reg_pkg.sv @@ -15,7 +15,7 @@ package ac_range_check_reg_pkg; parameter int BlockAw = 10; // Number of registers for every interface - parameter int NumRegs = 167; + parameter int NumRegs = 168; //////////////////////////// // Typedefs for registers // @@ -98,6 +98,25 @@ package ac_range_check_reg_pkg; logic de; } ac_range_check_hw2reg_intr_state_reg_t; + typedef struct packed { + struct packed { + logic d; + logic de; + } shadowed_update_err; + struct packed { + logic d; + logic de; + } shadowed_storage_err; + struct packed { + logic d; + logic de; + } reg_intg_err; + struct packed { + logic d; + logic de; + } counter_err; + } ac_range_check_hw2reg_alert_status_reg_t; + typedef struct packed { struct packed { logic [7:0] d; @@ -162,7 +181,8 @@ package ac_range_check_reg_pkg; // HW -> register type typedef struct packed { - ac_range_check_hw2reg_intr_state_reg_t intr_state; // [72:71] + ac_range_check_hw2reg_intr_state_reg_t intr_state; // [80:79] + ac_range_check_hw2reg_alert_status_reg_t alert_status; // [78:71] ac_range_check_hw2reg_log_status_reg_t log_status; // [70:33] ac_range_check_hw2reg_log_address_reg_t log_address; // [32:0] } ac_range_check_hw2reg_t; @@ -172,169 +192,170 @@ package ac_range_check_reg_pkg; parameter logic [BlockAw-1:0] AC_RANGE_CHECK_INTR_ENABLE_OFFSET = 10'h 4; parameter logic [BlockAw-1:0] AC_RANGE_CHECK_INTR_TEST_OFFSET = 10'h 8; parameter logic [BlockAw-1:0] AC_RANGE_CHECK_ALERT_TEST_OFFSET = 10'h c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_LOG_CONFIG_OFFSET = 10'h 10; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_LOG_STATUS_OFFSET = 10'h 14; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_LOG_ADDRESS_OFFSET = 10'h 18; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_0_OFFSET = 10'h 1c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_1_OFFSET = 10'h 20; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_2_OFFSET = 10'h 24; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_3_OFFSET = 10'h 28; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_4_OFFSET = 10'h 2c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_5_OFFSET = 10'h 30; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_6_OFFSET = 10'h 34; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_7_OFFSET = 10'h 38; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_8_OFFSET = 10'h 3c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_9_OFFSET = 10'h 40; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_10_OFFSET = 10'h 44; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_11_OFFSET = 10'h 48; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_12_OFFSET = 10'h 4c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_13_OFFSET = 10'h 50; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_14_OFFSET = 10'h 54; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_15_OFFSET = 10'h 58; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_16_OFFSET = 10'h 5c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_17_OFFSET = 10'h 60; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_18_OFFSET = 10'h 64; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_19_OFFSET = 10'h 68; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_20_OFFSET = 10'h 6c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_21_OFFSET = 10'h 70; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_22_OFFSET = 10'h 74; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_23_OFFSET = 10'h 78; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_24_OFFSET = 10'h 7c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_25_OFFSET = 10'h 80; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_26_OFFSET = 10'h 84; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_27_OFFSET = 10'h 88; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_28_OFFSET = 10'h 8c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_29_OFFSET = 10'h 90; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_30_OFFSET = 10'h 94; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_31_OFFSET = 10'h 98; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_0_OFFSET = 10'h 9c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_1_OFFSET = 10'h a0; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_2_OFFSET = 10'h a4; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_3_OFFSET = 10'h a8; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_4_OFFSET = 10'h ac; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_5_OFFSET = 10'h b0; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_6_OFFSET = 10'h b4; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_7_OFFSET = 10'h b8; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_8_OFFSET = 10'h bc; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_9_OFFSET = 10'h c0; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_10_OFFSET = 10'h c4; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_11_OFFSET = 10'h c8; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_12_OFFSET = 10'h cc; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_13_OFFSET = 10'h d0; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_14_OFFSET = 10'h d4; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_15_OFFSET = 10'h d8; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_16_OFFSET = 10'h dc; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_17_OFFSET = 10'h e0; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_18_OFFSET = 10'h e4; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_19_OFFSET = 10'h e8; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_20_OFFSET = 10'h ec; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_21_OFFSET = 10'h f0; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_22_OFFSET = 10'h f4; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_23_OFFSET = 10'h f8; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_24_OFFSET = 10'h fc; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_25_OFFSET = 10'h 100; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_26_OFFSET = 10'h 104; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_27_OFFSET = 10'h 108; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_28_OFFSET = 10'h 10c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_29_OFFSET = 10'h 110; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_30_OFFSET = 10'h 114; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_31_OFFSET = 10'h 118; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_0_OFFSET = 10'h 11c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_1_OFFSET = 10'h 120; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_2_OFFSET = 10'h 124; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_3_OFFSET = 10'h 128; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_4_OFFSET = 10'h 12c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_5_OFFSET = 10'h 130; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_6_OFFSET = 10'h 134; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_7_OFFSET = 10'h 138; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_8_OFFSET = 10'h 13c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_9_OFFSET = 10'h 140; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_10_OFFSET = 10'h 144; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_11_OFFSET = 10'h 148; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_12_OFFSET = 10'h 14c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_13_OFFSET = 10'h 150; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_14_OFFSET = 10'h 154; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_15_OFFSET = 10'h 158; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_16_OFFSET = 10'h 15c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_17_OFFSET = 10'h 160; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_18_OFFSET = 10'h 164; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_19_OFFSET = 10'h 168; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_20_OFFSET = 10'h 16c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_21_OFFSET = 10'h 170; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_22_OFFSET = 10'h 174; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_23_OFFSET = 10'h 178; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_24_OFFSET = 10'h 17c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_25_OFFSET = 10'h 180; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_26_OFFSET = 10'h 184; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_27_OFFSET = 10'h 188; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_28_OFFSET = 10'h 18c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_29_OFFSET = 10'h 190; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_30_OFFSET = 10'h 194; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_31_OFFSET = 10'h 198; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_0_OFFSET = 10'h 19c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_1_OFFSET = 10'h 1a0; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_2_OFFSET = 10'h 1a4; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_3_OFFSET = 10'h 1a8; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_4_OFFSET = 10'h 1ac; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_5_OFFSET = 10'h 1b0; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_6_OFFSET = 10'h 1b4; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_7_OFFSET = 10'h 1b8; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_8_OFFSET = 10'h 1bc; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_9_OFFSET = 10'h 1c0; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_10_OFFSET = 10'h 1c4; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_11_OFFSET = 10'h 1c8; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_12_OFFSET = 10'h 1cc; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_13_OFFSET = 10'h 1d0; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_14_OFFSET = 10'h 1d4; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_15_OFFSET = 10'h 1d8; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_16_OFFSET = 10'h 1dc; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_17_OFFSET = 10'h 1e0; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_18_OFFSET = 10'h 1e4; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_19_OFFSET = 10'h 1e8; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_20_OFFSET = 10'h 1ec; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_21_OFFSET = 10'h 1f0; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_22_OFFSET = 10'h 1f4; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_23_OFFSET = 10'h 1f8; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_24_OFFSET = 10'h 1fc; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_25_OFFSET = 10'h 200; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_26_OFFSET = 10'h 204; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_27_OFFSET = 10'h 208; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_28_OFFSET = 10'h 20c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_29_OFFSET = 10'h 210; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_30_OFFSET = 10'h 214; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_31_OFFSET = 10'h 218; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_0_OFFSET = 10'h 21c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_1_OFFSET = 10'h 220; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_2_OFFSET = 10'h 224; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_3_OFFSET = 10'h 228; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_4_OFFSET = 10'h 22c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_5_OFFSET = 10'h 230; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_6_OFFSET = 10'h 234; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_7_OFFSET = 10'h 238; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_8_OFFSET = 10'h 23c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_9_OFFSET = 10'h 240; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_10_OFFSET = 10'h 244; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_11_OFFSET = 10'h 248; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_12_OFFSET = 10'h 24c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_13_OFFSET = 10'h 250; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_14_OFFSET = 10'h 254; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_15_OFFSET = 10'h 258; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_16_OFFSET = 10'h 25c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_17_OFFSET = 10'h 260; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_18_OFFSET = 10'h 264; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_19_OFFSET = 10'h 268; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_20_OFFSET = 10'h 26c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_21_OFFSET = 10'h 270; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_22_OFFSET = 10'h 274; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_23_OFFSET = 10'h 278; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_24_OFFSET = 10'h 27c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_25_OFFSET = 10'h 280; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_26_OFFSET = 10'h 284; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_27_OFFSET = 10'h 288; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_28_OFFSET = 10'h 28c; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_29_OFFSET = 10'h 290; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_30_OFFSET = 10'h 294; - parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_31_OFFSET = 10'h 298; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_ALERT_STATUS_OFFSET = 10'h 10; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_LOG_CONFIG_OFFSET = 10'h 14; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_LOG_STATUS_OFFSET = 10'h 18; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_LOG_ADDRESS_OFFSET = 10'h 1c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_0_OFFSET = 10'h 20; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_1_OFFSET = 10'h 24; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_2_OFFSET = 10'h 28; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_3_OFFSET = 10'h 2c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_4_OFFSET = 10'h 30; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_5_OFFSET = 10'h 34; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_6_OFFSET = 10'h 38; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_7_OFFSET = 10'h 3c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_8_OFFSET = 10'h 40; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_9_OFFSET = 10'h 44; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_10_OFFSET = 10'h 48; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_11_OFFSET = 10'h 4c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_12_OFFSET = 10'h 50; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_13_OFFSET = 10'h 54; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_14_OFFSET = 10'h 58; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_15_OFFSET = 10'h 5c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_16_OFFSET = 10'h 60; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_17_OFFSET = 10'h 64; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_18_OFFSET = 10'h 68; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_19_OFFSET = 10'h 6c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_20_OFFSET = 10'h 70; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_21_OFFSET = 10'h 74; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_22_OFFSET = 10'h 78; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_23_OFFSET = 10'h 7c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_24_OFFSET = 10'h 80; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_25_OFFSET = 10'h 84; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_26_OFFSET = 10'h 88; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_27_OFFSET = 10'h 8c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_28_OFFSET = 10'h 90; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_29_OFFSET = 10'h 94; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_30_OFFSET = 10'h 98; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_31_OFFSET = 10'h 9c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_0_OFFSET = 10'h a0; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_1_OFFSET = 10'h a4; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_2_OFFSET = 10'h a8; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_3_OFFSET = 10'h ac; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_4_OFFSET = 10'h b0; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_5_OFFSET = 10'h b4; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_6_OFFSET = 10'h b8; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_7_OFFSET = 10'h bc; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_8_OFFSET = 10'h c0; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_9_OFFSET = 10'h c4; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_10_OFFSET = 10'h c8; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_11_OFFSET = 10'h cc; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_12_OFFSET = 10'h d0; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_13_OFFSET = 10'h d4; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_14_OFFSET = 10'h d8; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_15_OFFSET = 10'h dc; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_16_OFFSET = 10'h e0; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_17_OFFSET = 10'h e4; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_18_OFFSET = 10'h e8; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_19_OFFSET = 10'h ec; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_20_OFFSET = 10'h f0; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_21_OFFSET = 10'h f4; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_22_OFFSET = 10'h f8; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_23_OFFSET = 10'h fc; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_24_OFFSET = 10'h 100; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_25_OFFSET = 10'h 104; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_26_OFFSET = 10'h 108; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_27_OFFSET = 10'h 10c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_28_OFFSET = 10'h 110; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_29_OFFSET = 10'h 114; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_30_OFFSET = 10'h 118; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_31_OFFSET = 10'h 11c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_0_OFFSET = 10'h 120; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_1_OFFSET = 10'h 124; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_2_OFFSET = 10'h 128; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_3_OFFSET = 10'h 12c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_4_OFFSET = 10'h 130; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_5_OFFSET = 10'h 134; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_6_OFFSET = 10'h 138; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_7_OFFSET = 10'h 13c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_8_OFFSET = 10'h 140; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_9_OFFSET = 10'h 144; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_10_OFFSET = 10'h 148; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_11_OFFSET = 10'h 14c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_12_OFFSET = 10'h 150; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_13_OFFSET = 10'h 154; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_14_OFFSET = 10'h 158; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_15_OFFSET = 10'h 15c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_16_OFFSET = 10'h 160; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_17_OFFSET = 10'h 164; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_18_OFFSET = 10'h 168; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_19_OFFSET = 10'h 16c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_20_OFFSET = 10'h 170; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_21_OFFSET = 10'h 174; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_22_OFFSET = 10'h 178; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_23_OFFSET = 10'h 17c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_24_OFFSET = 10'h 180; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_25_OFFSET = 10'h 184; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_26_OFFSET = 10'h 188; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_27_OFFSET = 10'h 18c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_28_OFFSET = 10'h 190; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_29_OFFSET = 10'h 194; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_30_OFFSET = 10'h 198; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_31_OFFSET = 10'h 19c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_0_OFFSET = 10'h 1a0; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_1_OFFSET = 10'h 1a4; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_2_OFFSET = 10'h 1a8; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_3_OFFSET = 10'h 1ac; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_4_OFFSET = 10'h 1b0; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_5_OFFSET = 10'h 1b4; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_6_OFFSET = 10'h 1b8; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_7_OFFSET = 10'h 1bc; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_8_OFFSET = 10'h 1c0; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_9_OFFSET = 10'h 1c4; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_10_OFFSET = 10'h 1c8; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_11_OFFSET = 10'h 1cc; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_12_OFFSET = 10'h 1d0; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_13_OFFSET = 10'h 1d4; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_14_OFFSET = 10'h 1d8; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_15_OFFSET = 10'h 1dc; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_16_OFFSET = 10'h 1e0; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_17_OFFSET = 10'h 1e4; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_18_OFFSET = 10'h 1e8; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_19_OFFSET = 10'h 1ec; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_20_OFFSET = 10'h 1f0; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_21_OFFSET = 10'h 1f4; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_22_OFFSET = 10'h 1f8; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_23_OFFSET = 10'h 1fc; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_24_OFFSET = 10'h 200; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_25_OFFSET = 10'h 204; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_26_OFFSET = 10'h 208; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_27_OFFSET = 10'h 20c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_28_OFFSET = 10'h 210; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_29_OFFSET = 10'h 214; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_30_OFFSET = 10'h 218; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_PERM_31_OFFSET = 10'h 21c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_0_OFFSET = 10'h 220; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_1_OFFSET = 10'h 224; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_2_OFFSET = 10'h 228; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_3_OFFSET = 10'h 22c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_4_OFFSET = 10'h 230; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_5_OFFSET = 10'h 234; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_6_OFFSET = 10'h 238; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_7_OFFSET = 10'h 23c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_8_OFFSET = 10'h 240; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_9_OFFSET = 10'h 244; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_10_OFFSET = 10'h 248; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_11_OFFSET = 10'h 24c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_12_OFFSET = 10'h 250; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_13_OFFSET = 10'h 254; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_14_OFFSET = 10'h 258; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_15_OFFSET = 10'h 25c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_16_OFFSET = 10'h 260; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_17_OFFSET = 10'h 264; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_18_OFFSET = 10'h 268; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_19_OFFSET = 10'h 26c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_20_OFFSET = 10'h 270; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_21_OFFSET = 10'h 274; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_22_OFFSET = 10'h 278; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_23_OFFSET = 10'h 27c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_24_OFFSET = 10'h 280; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_25_OFFSET = 10'h 284; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_26_OFFSET = 10'h 288; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_27_OFFSET = 10'h 28c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_28_OFFSET = 10'h 290; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_29_OFFSET = 10'h 294; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_30_OFFSET = 10'h 298; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_31_OFFSET = 10'h 29c; // Reset values for hwext registers and their fields parameter logic [0:0] AC_RANGE_CHECK_INTR_TEST_RESVAL = 1'h 0; @@ -349,6 +370,7 @@ package ac_range_check_reg_pkg; AC_RANGE_CHECK_INTR_ENABLE, AC_RANGE_CHECK_INTR_TEST, AC_RANGE_CHECK_ALERT_TEST, + AC_RANGE_CHECK_ALERT_STATUS, AC_RANGE_CHECK_LOG_CONFIG, AC_RANGE_CHECK_LOG_STATUS, AC_RANGE_CHECK_LOG_ADDRESS, @@ -515,174 +537,175 @@ package ac_range_check_reg_pkg; } ac_range_check_id_e; // Register width information to check illegal writes - parameter logic [3:0] AC_RANGE_CHECK_PERMIT [167] = '{ + parameter logic [3:0] AC_RANGE_CHECK_PERMIT [168] = '{ 4'b 0001, // index[ 0] AC_RANGE_CHECK_INTR_STATE 4'b 0001, // index[ 1] AC_RANGE_CHECK_INTR_ENABLE 4'b 0001, // index[ 2] AC_RANGE_CHECK_INTR_TEST 4'b 0001, // index[ 3] AC_RANGE_CHECK_ALERT_TEST - 4'b 0011, // index[ 4] AC_RANGE_CHECK_LOG_CONFIG - 4'b 1111, // index[ 5] AC_RANGE_CHECK_LOG_STATUS - 4'b 1111, // index[ 6] AC_RANGE_CHECK_LOG_ADDRESS - 4'b 0001, // index[ 7] AC_RANGE_CHECK_RANGE_REGWEN_0 - 4'b 0001, // index[ 8] AC_RANGE_CHECK_RANGE_REGWEN_1 - 4'b 0001, // index[ 9] AC_RANGE_CHECK_RANGE_REGWEN_2 - 4'b 0001, // index[ 10] AC_RANGE_CHECK_RANGE_REGWEN_3 - 4'b 0001, // index[ 11] AC_RANGE_CHECK_RANGE_REGWEN_4 - 4'b 0001, // index[ 12] AC_RANGE_CHECK_RANGE_REGWEN_5 - 4'b 0001, // index[ 13] AC_RANGE_CHECK_RANGE_REGWEN_6 - 4'b 0001, // index[ 14] AC_RANGE_CHECK_RANGE_REGWEN_7 - 4'b 0001, // index[ 15] AC_RANGE_CHECK_RANGE_REGWEN_8 - 4'b 0001, // index[ 16] AC_RANGE_CHECK_RANGE_REGWEN_9 - 4'b 0001, // index[ 17] AC_RANGE_CHECK_RANGE_REGWEN_10 - 4'b 0001, // index[ 18] AC_RANGE_CHECK_RANGE_REGWEN_11 - 4'b 0001, // index[ 19] AC_RANGE_CHECK_RANGE_REGWEN_12 - 4'b 0001, // index[ 20] AC_RANGE_CHECK_RANGE_REGWEN_13 - 4'b 0001, // index[ 21] AC_RANGE_CHECK_RANGE_REGWEN_14 - 4'b 0001, // index[ 22] AC_RANGE_CHECK_RANGE_REGWEN_15 - 4'b 0001, // index[ 23] AC_RANGE_CHECK_RANGE_REGWEN_16 - 4'b 0001, // index[ 24] AC_RANGE_CHECK_RANGE_REGWEN_17 - 4'b 0001, // index[ 25] AC_RANGE_CHECK_RANGE_REGWEN_18 - 4'b 0001, // index[ 26] AC_RANGE_CHECK_RANGE_REGWEN_19 - 4'b 0001, // index[ 27] AC_RANGE_CHECK_RANGE_REGWEN_20 - 4'b 0001, // index[ 28] AC_RANGE_CHECK_RANGE_REGWEN_21 - 4'b 0001, // index[ 29] AC_RANGE_CHECK_RANGE_REGWEN_22 - 4'b 0001, // index[ 30] AC_RANGE_CHECK_RANGE_REGWEN_23 - 4'b 0001, // index[ 31] AC_RANGE_CHECK_RANGE_REGWEN_24 - 4'b 0001, // index[ 32] AC_RANGE_CHECK_RANGE_REGWEN_25 - 4'b 0001, // index[ 33] AC_RANGE_CHECK_RANGE_REGWEN_26 - 4'b 0001, // index[ 34] AC_RANGE_CHECK_RANGE_REGWEN_27 - 4'b 0001, // index[ 35] AC_RANGE_CHECK_RANGE_REGWEN_28 - 4'b 0001, // index[ 36] AC_RANGE_CHECK_RANGE_REGWEN_29 - 4'b 0001, // index[ 37] AC_RANGE_CHECK_RANGE_REGWEN_30 - 4'b 0001, // index[ 38] AC_RANGE_CHECK_RANGE_REGWEN_31 - 4'b 1111, // index[ 39] AC_RANGE_CHECK_RANGE_BASE_0 - 4'b 1111, // index[ 40] AC_RANGE_CHECK_RANGE_BASE_1 - 4'b 1111, // index[ 41] AC_RANGE_CHECK_RANGE_BASE_2 - 4'b 1111, // index[ 42] AC_RANGE_CHECK_RANGE_BASE_3 - 4'b 1111, // index[ 43] AC_RANGE_CHECK_RANGE_BASE_4 - 4'b 1111, // index[ 44] AC_RANGE_CHECK_RANGE_BASE_5 - 4'b 1111, // index[ 45] AC_RANGE_CHECK_RANGE_BASE_6 - 4'b 1111, // index[ 46] AC_RANGE_CHECK_RANGE_BASE_7 - 4'b 1111, // index[ 47] AC_RANGE_CHECK_RANGE_BASE_8 - 4'b 1111, // index[ 48] AC_RANGE_CHECK_RANGE_BASE_9 - 4'b 1111, // index[ 49] AC_RANGE_CHECK_RANGE_BASE_10 - 4'b 1111, // index[ 50] AC_RANGE_CHECK_RANGE_BASE_11 - 4'b 1111, // index[ 51] AC_RANGE_CHECK_RANGE_BASE_12 - 4'b 1111, // index[ 52] AC_RANGE_CHECK_RANGE_BASE_13 - 4'b 1111, // index[ 53] AC_RANGE_CHECK_RANGE_BASE_14 - 4'b 1111, // index[ 54] AC_RANGE_CHECK_RANGE_BASE_15 - 4'b 1111, // index[ 55] AC_RANGE_CHECK_RANGE_BASE_16 - 4'b 1111, // index[ 56] AC_RANGE_CHECK_RANGE_BASE_17 - 4'b 1111, // index[ 57] AC_RANGE_CHECK_RANGE_BASE_18 - 4'b 1111, // index[ 58] AC_RANGE_CHECK_RANGE_BASE_19 - 4'b 1111, // index[ 59] AC_RANGE_CHECK_RANGE_BASE_20 - 4'b 1111, // index[ 60] AC_RANGE_CHECK_RANGE_BASE_21 - 4'b 1111, // index[ 61] AC_RANGE_CHECK_RANGE_BASE_22 - 4'b 1111, // index[ 62] AC_RANGE_CHECK_RANGE_BASE_23 - 4'b 1111, // index[ 63] AC_RANGE_CHECK_RANGE_BASE_24 - 4'b 1111, // index[ 64] AC_RANGE_CHECK_RANGE_BASE_25 - 4'b 1111, // index[ 65] AC_RANGE_CHECK_RANGE_BASE_26 - 4'b 1111, // index[ 66] AC_RANGE_CHECK_RANGE_BASE_27 - 4'b 1111, // index[ 67] AC_RANGE_CHECK_RANGE_BASE_28 - 4'b 1111, // index[ 68] AC_RANGE_CHECK_RANGE_BASE_29 - 4'b 1111, // index[ 69] AC_RANGE_CHECK_RANGE_BASE_30 - 4'b 1111, // index[ 70] AC_RANGE_CHECK_RANGE_BASE_31 - 4'b 1111, // index[ 71] AC_RANGE_CHECK_RANGE_LIMIT_0 - 4'b 1111, // index[ 72] AC_RANGE_CHECK_RANGE_LIMIT_1 - 4'b 1111, // index[ 73] AC_RANGE_CHECK_RANGE_LIMIT_2 - 4'b 1111, // index[ 74] AC_RANGE_CHECK_RANGE_LIMIT_3 - 4'b 1111, // index[ 75] AC_RANGE_CHECK_RANGE_LIMIT_4 - 4'b 1111, // index[ 76] AC_RANGE_CHECK_RANGE_LIMIT_5 - 4'b 1111, // index[ 77] AC_RANGE_CHECK_RANGE_LIMIT_6 - 4'b 1111, // index[ 78] AC_RANGE_CHECK_RANGE_LIMIT_7 - 4'b 1111, // index[ 79] AC_RANGE_CHECK_RANGE_LIMIT_8 - 4'b 1111, // index[ 80] AC_RANGE_CHECK_RANGE_LIMIT_9 - 4'b 1111, // index[ 81] AC_RANGE_CHECK_RANGE_LIMIT_10 - 4'b 1111, // index[ 82] AC_RANGE_CHECK_RANGE_LIMIT_11 - 4'b 1111, // index[ 83] AC_RANGE_CHECK_RANGE_LIMIT_12 - 4'b 1111, // index[ 84] AC_RANGE_CHECK_RANGE_LIMIT_13 - 4'b 1111, // index[ 85] AC_RANGE_CHECK_RANGE_LIMIT_14 - 4'b 1111, // index[ 86] AC_RANGE_CHECK_RANGE_LIMIT_15 - 4'b 1111, // index[ 87] AC_RANGE_CHECK_RANGE_LIMIT_16 - 4'b 1111, // index[ 88] AC_RANGE_CHECK_RANGE_LIMIT_17 - 4'b 1111, // index[ 89] AC_RANGE_CHECK_RANGE_LIMIT_18 - 4'b 1111, // index[ 90] AC_RANGE_CHECK_RANGE_LIMIT_19 - 4'b 1111, // index[ 91] AC_RANGE_CHECK_RANGE_LIMIT_20 - 4'b 1111, // index[ 92] AC_RANGE_CHECK_RANGE_LIMIT_21 - 4'b 1111, // index[ 93] AC_RANGE_CHECK_RANGE_LIMIT_22 - 4'b 1111, // index[ 94] AC_RANGE_CHECK_RANGE_LIMIT_23 - 4'b 1111, // index[ 95] AC_RANGE_CHECK_RANGE_LIMIT_24 - 4'b 1111, // index[ 96] AC_RANGE_CHECK_RANGE_LIMIT_25 - 4'b 1111, // index[ 97] AC_RANGE_CHECK_RANGE_LIMIT_26 - 4'b 1111, // index[ 98] AC_RANGE_CHECK_RANGE_LIMIT_27 - 4'b 1111, // index[ 99] AC_RANGE_CHECK_RANGE_LIMIT_28 - 4'b 1111, // index[100] AC_RANGE_CHECK_RANGE_LIMIT_29 - 4'b 1111, // index[101] AC_RANGE_CHECK_RANGE_LIMIT_30 - 4'b 1111, // index[102] AC_RANGE_CHECK_RANGE_LIMIT_31 - 4'b 0111, // index[103] AC_RANGE_CHECK_RANGE_PERM_0 - 4'b 0111, // index[104] AC_RANGE_CHECK_RANGE_PERM_1 - 4'b 0111, // index[105] AC_RANGE_CHECK_RANGE_PERM_2 - 4'b 0111, // index[106] AC_RANGE_CHECK_RANGE_PERM_3 - 4'b 0111, // index[107] AC_RANGE_CHECK_RANGE_PERM_4 - 4'b 0111, // index[108] AC_RANGE_CHECK_RANGE_PERM_5 - 4'b 0111, // index[109] AC_RANGE_CHECK_RANGE_PERM_6 - 4'b 0111, // index[110] AC_RANGE_CHECK_RANGE_PERM_7 - 4'b 0111, // index[111] AC_RANGE_CHECK_RANGE_PERM_8 - 4'b 0111, // index[112] AC_RANGE_CHECK_RANGE_PERM_9 - 4'b 0111, // index[113] AC_RANGE_CHECK_RANGE_PERM_10 - 4'b 0111, // index[114] AC_RANGE_CHECK_RANGE_PERM_11 - 4'b 0111, // index[115] AC_RANGE_CHECK_RANGE_PERM_12 - 4'b 0111, // index[116] AC_RANGE_CHECK_RANGE_PERM_13 - 4'b 0111, // index[117] AC_RANGE_CHECK_RANGE_PERM_14 - 4'b 0111, // index[118] AC_RANGE_CHECK_RANGE_PERM_15 - 4'b 0111, // index[119] AC_RANGE_CHECK_RANGE_PERM_16 - 4'b 0111, // index[120] AC_RANGE_CHECK_RANGE_PERM_17 - 4'b 0111, // index[121] AC_RANGE_CHECK_RANGE_PERM_18 - 4'b 0111, // index[122] AC_RANGE_CHECK_RANGE_PERM_19 - 4'b 0111, // index[123] AC_RANGE_CHECK_RANGE_PERM_20 - 4'b 0111, // index[124] AC_RANGE_CHECK_RANGE_PERM_21 - 4'b 0111, // index[125] AC_RANGE_CHECK_RANGE_PERM_22 - 4'b 0111, // index[126] AC_RANGE_CHECK_RANGE_PERM_23 - 4'b 0111, // index[127] AC_RANGE_CHECK_RANGE_PERM_24 - 4'b 0111, // index[128] AC_RANGE_CHECK_RANGE_PERM_25 - 4'b 0111, // index[129] AC_RANGE_CHECK_RANGE_PERM_26 - 4'b 0111, // index[130] AC_RANGE_CHECK_RANGE_PERM_27 - 4'b 0111, // index[131] AC_RANGE_CHECK_RANGE_PERM_28 - 4'b 0111, // index[132] AC_RANGE_CHECK_RANGE_PERM_29 - 4'b 0111, // index[133] AC_RANGE_CHECK_RANGE_PERM_30 - 4'b 0111, // index[134] AC_RANGE_CHECK_RANGE_PERM_31 - 4'b 1111, // index[135] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_0 - 4'b 1111, // index[136] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_1 - 4'b 1111, // index[137] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_2 - 4'b 1111, // index[138] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_3 - 4'b 1111, // index[139] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_4 - 4'b 1111, // index[140] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_5 - 4'b 1111, // index[141] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_6 - 4'b 1111, // index[142] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_7 - 4'b 1111, // index[143] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_8 - 4'b 1111, // index[144] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_9 - 4'b 1111, // index[145] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_10 - 4'b 1111, // index[146] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_11 - 4'b 1111, // index[147] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_12 - 4'b 1111, // index[148] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_13 - 4'b 1111, // index[149] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_14 - 4'b 1111, // index[150] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_15 - 4'b 1111, // index[151] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_16 - 4'b 1111, // index[152] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_17 - 4'b 1111, // index[153] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_18 - 4'b 1111, // index[154] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_19 - 4'b 1111, // index[155] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_20 - 4'b 1111, // index[156] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_21 - 4'b 1111, // index[157] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_22 - 4'b 1111, // index[158] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_23 - 4'b 1111, // index[159] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_24 - 4'b 1111, // index[160] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_25 - 4'b 1111, // index[161] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_26 - 4'b 1111, // index[162] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_27 - 4'b 1111, // index[163] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_28 - 4'b 1111, // index[164] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_29 - 4'b 1111, // index[165] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_30 - 4'b 1111 // index[166] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_31 + 4'b 0001, // index[ 4] AC_RANGE_CHECK_ALERT_STATUS + 4'b 0011, // index[ 5] AC_RANGE_CHECK_LOG_CONFIG + 4'b 1111, // index[ 6] AC_RANGE_CHECK_LOG_STATUS + 4'b 1111, // index[ 7] AC_RANGE_CHECK_LOG_ADDRESS + 4'b 0001, // index[ 8] AC_RANGE_CHECK_RANGE_REGWEN_0 + 4'b 0001, // index[ 9] AC_RANGE_CHECK_RANGE_REGWEN_1 + 4'b 0001, // index[ 10] AC_RANGE_CHECK_RANGE_REGWEN_2 + 4'b 0001, // index[ 11] AC_RANGE_CHECK_RANGE_REGWEN_3 + 4'b 0001, // index[ 12] AC_RANGE_CHECK_RANGE_REGWEN_4 + 4'b 0001, // index[ 13] AC_RANGE_CHECK_RANGE_REGWEN_5 + 4'b 0001, // index[ 14] AC_RANGE_CHECK_RANGE_REGWEN_6 + 4'b 0001, // index[ 15] AC_RANGE_CHECK_RANGE_REGWEN_7 + 4'b 0001, // index[ 16] AC_RANGE_CHECK_RANGE_REGWEN_8 + 4'b 0001, // index[ 17] AC_RANGE_CHECK_RANGE_REGWEN_9 + 4'b 0001, // index[ 18] AC_RANGE_CHECK_RANGE_REGWEN_10 + 4'b 0001, // index[ 19] AC_RANGE_CHECK_RANGE_REGWEN_11 + 4'b 0001, // index[ 20] AC_RANGE_CHECK_RANGE_REGWEN_12 + 4'b 0001, // index[ 21] AC_RANGE_CHECK_RANGE_REGWEN_13 + 4'b 0001, // index[ 22] AC_RANGE_CHECK_RANGE_REGWEN_14 + 4'b 0001, // index[ 23] AC_RANGE_CHECK_RANGE_REGWEN_15 + 4'b 0001, // index[ 24] AC_RANGE_CHECK_RANGE_REGWEN_16 + 4'b 0001, // index[ 25] AC_RANGE_CHECK_RANGE_REGWEN_17 + 4'b 0001, // index[ 26] AC_RANGE_CHECK_RANGE_REGWEN_18 + 4'b 0001, // index[ 27] AC_RANGE_CHECK_RANGE_REGWEN_19 + 4'b 0001, // index[ 28] AC_RANGE_CHECK_RANGE_REGWEN_20 + 4'b 0001, // index[ 29] AC_RANGE_CHECK_RANGE_REGWEN_21 + 4'b 0001, // index[ 30] AC_RANGE_CHECK_RANGE_REGWEN_22 + 4'b 0001, // index[ 31] AC_RANGE_CHECK_RANGE_REGWEN_23 + 4'b 0001, // index[ 32] AC_RANGE_CHECK_RANGE_REGWEN_24 + 4'b 0001, // index[ 33] AC_RANGE_CHECK_RANGE_REGWEN_25 + 4'b 0001, // index[ 34] AC_RANGE_CHECK_RANGE_REGWEN_26 + 4'b 0001, // index[ 35] AC_RANGE_CHECK_RANGE_REGWEN_27 + 4'b 0001, // index[ 36] AC_RANGE_CHECK_RANGE_REGWEN_28 + 4'b 0001, // index[ 37] AC_RANGE_CHECK_RANGE_REGWEN_29 + 4'b 0001, // index[ 38] AC_RANGE_CHECK_RANGE_REGWEN_30 + 4'b 0001, // index[ 39] AC_RANGE_CHECK_RANGE_REGWEN_31 + 4'b 1111, // index[ 40] AC_RANGE_CHECK_RANGE_BASE_0 + 4'b 1111, // index[ 41] AC_RANGE_CHECK_RANGE_BASE_1 + 4'b 1111, // index[ 42] AC_RANGE_CHECK_RANGE_BASE_2 + 4'b 1111, // index[ 43] AC_RANGE_CHECK_RANGE_BASE_3 + 4'b 1111, // index[ 44] AC_RANGE_CHECK_RANGE_BASE_4 + 4'b 1111, // index[ 45] AC_RANGE_CHECK_RANGE_BASE_5 + 4'b 1111, // index[ 46] AC_RANGE_CHECK_RANGE_BASE_6 + 4'b 1111, // index[ 47] AC_RANGE_CHECK_RANGE_BASE_7 + 4'b 1111, // index[ 48] AC_RANGE_CHECK_RANGE_BASE_8 + 4'b 1111, // index[ 49] AC_RANGE_CHECK_RANGE_BASE_9 + 4'b 1111, // index[ 50] AC_RANGE_CHECK_RANGE_BASE_10 + 4'b 1111, // index[ 51] AC_RANGE_CHECK_RANGE_BASE_11 + 4'b 1111, // index[ 52] AC_RANGE_CHECK_RANGE_BASE_12 + 4'b 1111, // index[ 53] AC_RANGE_CHECK_RANGE_BASE_13 + 4'b 1111, // index[ 54] AC_RANGE_CHECK_RANGE_BASE_14 + 4'b 1111, // index[ 55] AC_RANGE_CHECK_RANGE_BASE_15 + 4'b 1111, // index[ 56] AC_RANGE_CHECK_RANGE_BASE_16 + 4'b 1111, // index[ 57] AC_RANGE_CHECK_RANGE_BASE_17 + 4'b 1111, // index[ 58] AC_RANGE_CHECK_RANGE_BASE_18 + 4'b 1111, // index[ 59] AC_RANGE_CHECK_RANGE_BASE_19 + 4'b 1111, // index[ 60] AC_RANGE_CHECK_RANGE_BASE_20 + 4'b 1111, // index[ 61] AC_RANGE_CHECK_RANGE_BASE_21 + 4'b 1111, // index[ 62] AC_RANGE_CHECK_RANGE_BASE_22 + 4'b 1111, // index[ 63] AC_RANGE_CHECK_RANGE_BASE_23 + 4'b 1111, // index[ 64] AC_RANGE_CHECK_RANGE_BASE_24 + 4'b 1111, // index[ 65] AC_RANGE_CHECK_RANGE_BASE_25 + 4'b 1111, // index[ 66] AC_RANGE_CHECK_RANGE_BASE_26 + 4'b 1111, // index[ 67] AC_RANGE_CHECK_RANGE_BASE_27 + 4'b 1111, // index[ 68] AC_RANGE_CHECK_RANGE_BASE_28 + 4'b 1111, // index[ 69] AC_RANGE_CHECK_RANGE_BASE_29 + 4'b 1111, // index[ 70] AC_RANGE_CHECK_RANGE_BASE_30 + 4'b 1111, // index[ 71] AC_RANGE_CHECK_RANGE_BASE_31 + 4'b 1111, // index[ 72] AC_RANGE_CHECK_RANGE_LIMIT_0 + 4'b 1111, // index[ 73] AC_RANGE_CHECK_RANGE_LIMIT_1 + 4'b 1111, // index[ 74] AC_RANGE_CHECK_RANGE_LIMIT_2 + 4'b 1111, // index[ 75] AC_RANGE_CHECK_RANGE_LIMIT_3 + 4'b 1111, // index[ 76] AC_RANGE_CHECK_RANGE_LIMIT_4 + 4'b 1111, // index[ 77] AC_RANGE_CHECK_RANGE_LIMIT_5 + 4'b 1111, // index[ 78] AC_RANGE_CHECK_RANGE_LIMIT_6 + 4'b 1111, // index[ 79] AC_RANGE_CHECK_RANGE_LIMIT_7 + 4'b 1111, // index[ 80] AC_RANGE_CHECK_RANGE_LIMIT_8 + 4'b 1111, // index[ 81] AC_RANGE_CHECK_RANGE_LIMIT_9 + 4'b 1111, // index[ 82] AC_RANGE_CHECK_RANGE_LIMIT_10 + 4'b 1111, // index[ 83] AC_RANGE_CHECK_RANGE_LIMIT_11 + 4'b 1111, // index[ 84] AC_RANGE_CHECK_RANGE_LIMIT_12 + 4'b 1111, // index[ 85] AC_RANGE_CHECK_RANGE_LIMIT_13 + 4'b 1111, // index[ 86] AC_RANGE_CHECK_RANGE_LIMIT_14 + 4'b 1111, // index[ 87] AC_RANGE_CHECK_RANGE_LIMIT_15 + 4'b 1111, // index[ 88] AC_RANGE_CHECK_RANGE_LIMIT_16 + 4'b 1111, // index[ 89] AC_RANGE_CHECK_RANGE_LIMIT_17 + 4'b 1111, // index[ 90] AC_RANGE_CHECK_RANGE_LIMIT_18 + 4'b 1111, // index[ 91] AC_RANGE_CHECK_RANGE_LIMIT_19 + 4'b 1111, // index[ 92] AC_RANGE_CHECK_RANGE_LIMIT_20 + 4'b 1111, // index[ 93] AC_RANGE_CHECK_RANGE_LIMIT_21 + 4'b 1111, // index[ 94] AC_RANGE_CHECK_RANGE_LIMIT_22 + 4'b 1111, // index[ 95] AC_RANGE_CHECK_RANGE_LIMIT_23 + 4'b 1111, // index[ 96] AC_RANGE_CHECK_RANGE_LIMIT_24 + 4'b 1111, // index[ 97] AC_RANGE_CHECK_RANGE_LIMIT_25 + 4'b 1111, // index[ 98] AC_RANGE_CHECK_RANGE_LIMIT_26 + 4'b 1111, // index[ 99] AC_RANGE_CHECK_RANGE_LIMIT_27 + 4'b 1111, // index[100] AC_RANGE_CHECK_RANGE_LIMIT_28 + 4'b 1111, // index[101] AC_RANGE_CHECK_RANGE_LIMIT_29 + 4'b 1111, // index[102] AC_RANGE_CHECK_RANGE_LIMIT_30 + 4'b 1111, // index[103] AC_RANGE_CHECK_RANGE_LIMIT_31 + 4'b 0111, // index[104] AC_RANGE_CHECK_RANGE_PERM_0 + 4'b 0111, // index[105] AC_RANGE_CHECK_RANGE_PERM_1 + 4'b 0111, // index[106] AC_RANGE_CHECK_RANGE_PERM_2 + 4'b 0111, // index[107] AC_RANGE_CHECK_RANGE_PERM_3 + 4'b 0111, // index[108] AC_RANGE_CHECK_RANGE_PERM_4 + 4'b 0111, // index[109] AC_RANGE_CHECK_RANGE_PERM_5 + 4'b 0111, // index[110] AC_RANGE_CHECK_RANGE_PERM_6 + 4'b 0111, // index[111] AC_RANGE_CHECK_RANGE_PERM_7 + 4'b 0111, // index[112] AC_RANGE_CHECK_RANGE_PERM_8 + 4'b 0111, // index[113] AC_RANGE_CHECK_RANGE_PERM_9 + 4'b 0111, // index[114] AC_RANGE_CHECK_RANGE_PERM_10 + 4'b 0111, // index[115] AC_RANGE_CHECK_RANGE_PERM_11 + 4'b 0111, // index[116] AC_RANGE_CHECK_RANGE_PERM_12 + 4'b 0111, // index[117] AC_RANGE_CHECK_RANGE_PERM_13 + 4'b 0111, // index[118] AC_RANGE_CHECK_RANGE_PERM_14 + 4'b 0111, // index[119] AC_RANGE_CHECK_RANGE_PERM_15 + 4'b 0111, // index[120] AC_RANGE_CHECK_RANGE_PERM_16 + 4'b 0111, // index[121] AC_RANGE_CHECK_RANGE_PERM_17 + 4'b 0111, // index[122] AC_RANGE_CHECK_RANGE_PERM_18 + 4'b 0111, // index[123] AC_RANGE_CHECK_RANGE_PERM_19 + 4'b 0111, // index[124] AC_RANGE_CHECK_RANGE_PERM_20 + 4'b 0111, // index[125] AC_RANGE_CHECK_RANGE_PERM_21 + 4'b 0111, // index[126] AC_RANGE_CHECK_RANGE_PERM_22 + 4'b 0111, // index[127] AC_RANGE_CHECK_RANGE_PERM_23 + 4'b 0111, // index[128] AC_RANGE_CHECK_RANGE_PERM_24 + 4'b 0111, // index[129] AC_RANGE_CHECK_RANGE_PERM_25 + 4'b 0111, // index[130] AC_RANGE_CHECK_RANGE_PERM_26 + 4'b 0111, // index[131] AC_RANGE_CHECK_RANGE_PERM_27 + 4'b 0111, // index[132] AC_RANGE_CHECK_RANGE_PERM_28 + 4'b 0111, // index[133] AC_RANGE_CHECK_RANGE_PERM_29 + 4'b 0111, // index[134] AC_RANGE_CHECK_RANGE_PERM_30 + 4'b 0111, // index[135] AC_RANGE_CHECK_RANGE_PERM_31 + 4'b 1111, // index[136] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_0 + 4'b 1111, // index[137] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_1 + 4'b 1111, // index[138] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_2 + 4'b 1111, // index[139] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_3 + 4'b 1111, // index[140] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_4 + 4'b 1111, // index[141] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_5 + 4'b 1111, // index[142] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_6 + 4'b 1111, // index[143] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_7 + 4'b 1111, // index[144] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_8 + 4'b 1111, // index[145] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_9 + 4'b 1111, // index[146] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_10 + 4'b 1111, // index[147] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_11 + 4'b 1111, // index[148] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_12 + 4'b 1111, // index[149] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_13 + 4'b 1111, // index[150] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_14 + 4'b 1111, // index[151] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_15 + 4'b 1111, // index[152] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_16 + 4'b 1111, // index[153] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_17 + 4'b 1111, // index[154] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_18 + 4'b 1111, // index[155] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_19 + 4'b 1111, // index[156] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_20 + 4'b 1111, // index[157] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_21 + 4'b 1111, // index[158] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_22 + 4'b 1111, // index[159] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_23 + 4'b 1111, // index[160] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_24 + 4'b 1111, // index[161] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_25 + 4'b 1111, // index[162] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_26 + 4'b 1111, // index[163] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_27 + 4'b 1111, // index[164] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_28 + 4'b 1111, // index[165] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_29 + 4'b 1111, // index[166] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_30 + 4'b 1111 // index[167] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_31 }; endpackage diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/rtl/ac_range_check_reg_top.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/rtl/ac_range_check_reg_top.sv index 73a8ca6731991..ebf8ccd4e6ac8 100644 --- a/hw/top_darjeeling/ip_autogen/ac_range_check/rtl/ac_range_check_reg_top.sv +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/rtl/ac_range_check_reg_top.sv @@ -66,9 +66,9 @@ module ac_range_check_reg_top // also check for spurious write enables logic reg_we_err; - logic [166:0] reg_we_check; + logic [167:0] reg_we_check; prim_reg_we_check #( - .OneHotWidth(167) + .OneHotWidth(168) ) u_prim_reg_we_check ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -147,6 +147,12 @@ module ac_range_check_reg_top logic alert_test_we; logic alert_test_recov_ctrl_update_err_wd; logic alert_test_fatal_fault_wd; + logic alert_status_re; + logic alert_status_shadowed_update_err_qs; + logic alert_status_shadowed_update_err_wd; + logic alert_status_shadowed_storage_err_qs; + logic alert_status_reg_intg_err_qs; + logic alert_status_counter_err_qs; logic log_config_we; logic log_config_log_enable_qs; logic log_config_log_enable_wd; @@ -1240,6 +1246,116 @@ module ac_range_check_reg_top assign reg2hw.alert_test.fatal_fault.qe = alert_test_qe; + // R[alert_status]: V(False) + // F[shadowed_update_err]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRC), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_status_shadowed_update_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_status_re), + .wd (alert_status_shadowed_update_err_wd), + + // from internal hardware + .de (hw2reg.alert_status.shadowed_update_err.de), + .d (hw2reg.alert_status.shadowed_update_err.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (alert_status_shadowed_update_err_qs) + ); + + // F[shadowed_storage_err]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_status_shadowed_storage_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.alert_status.shadowed_storage_err.de), + .d (hw2reg.alert_status.shadowed_storage_err.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (alert_status_shadowed_storage_err_qs) + ); + + // F[reg_intg_err]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_status_reg_intg_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.alert_status.reg_intg_err.de), + .d (hw2reg.alert_status.reg_intg_err.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (alert_status_reg_intg_err_qs) + ); + + // F[counter_err]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_status_counter_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.alert_status.counter_err.de), + .d (hw2reg.alert_status.counter_err.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (alert_status_counter_err_qs) + ); + + // R[log_config]: V(False) logic log_config_qe; logic [2:0] log_config_flds_we; @@ -11876,12 +11992,12 @@ module ac_range_check_reg_top - logic [166:0] addr_hit; + logic [167:0] addr_hit; top_racl_pkg::racl_role_vec_t racl_role_vec; top_racl_pkg::racl_role_t racl_role; - logic [166:0] racl_addr_hit_read; - logic [166:0] racl_addr_hit_write; + logic [167:0] racl_addr_hit_read; + logic [167:0] racl_addr_hit_write; if (EnableRacl) begin : gen_racl_role_logic // Retrieve RACL role from user bits and one-hot encode that for the comparison bitmap @@ -11907,172 +12023,173 @@ module ac_range_check_reg_top addr_hit[ 1] = (reg_addr == AC_RANGE_CHECK_INTR_ENABLE_OFFSET); addr_hit[ 2] = (reg_addr == AC_RANGE_CHECK_INTR_TEST_OFFSET); addr_hit[ 3] = (reg_addr == AC_RANGE_CHECK_ALERT_TEST_OFFSET); - addr_hit[ 4] = (reg_addr == AC_RANGE_CHECK_LOG_CONFIG_OFFSET); - addr_hit[ 5] = (reg_addr == AC_RANGE_CHECK_LOG_STATUS_OFFSET); - addr_hit[ 6] = (reg_addr == AC_RANGE_CHECK_LOG_ADDRESS_OFFSET); - addr_hit[ 7] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_0_OFFSET); - addr_hit[ 8] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_1_OFFSET); - addr_hit[ 9] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_2_OFFSET); - addr_hit[ 10] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_3_OFFSET); - addr_hit[ 11] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_4_OFFSET); - addr_hit[ 12] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_5_OFFSET); - addr_hit[ 13] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_6_OFFSET); - addr_hit[ 14] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_7_OFFSET); - addr_hit[ 15] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_8_OFFSET); - addr_hit[ 16] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_9_OFFSET); - addr_hit[ 17] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_10_OFFSET); - addr_hit[ 18] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_11_OFFSET); - addr_hit[ 19] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_12_OFFSET); - addr_hit[ 20] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_13_OFFSET); - addr_hit[ 21] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_14_OFFSET); - addr_hit[ 22] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_15_OFFSET); - addr_hit[ 23] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_16_OFFSET); - addr_hit[ 24] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_17_OFFSET); - addr_hit[ 25] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_18_OFFSET); - addr_hit[ 26] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_19_OFFSET); - addr_hit[ 27] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_20_OFFSET); - addr_hit[ 28] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_21_OFFSET); - addr_hit[ 29] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_22_OFFSET); - addr_hit[ 30] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_23_OFFSET); - addr_hit[ 31] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_24_OFFSET); - addr_hit[ 32] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_25_OFFSET); - addr_hit[ 33] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_26_OFFSET); - addr_hit[ 34] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_27_OFFSET); - addr_hit[ 35] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_28_OFFSET); - addr_hit[ 36] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_29_OFFSET); - addr_hit[ 37] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_30_OFFSET); - addr_hit[ 38] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_31_OFFSET); - addr_hit[ 39] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_0_OFFSET); - addr_hit[ 40] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_1_OFFSET); - addr_hit[ 41] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_2_OFFSET); - addr_hit[ 42] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_3_OFFSET); - addr_hit[ 43] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_4_OFFSET); - addr_hit[ 44] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_5_OFFSET); - addr_hit[ 45] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_6_OFFSET); - addr_hit[ 46] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_7_OFFSET); - addr_hit[ 47] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_8_OFFSET); - addr_hit[ 48] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_9_OFFSET); - addr_hit[ 49] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_10_OFFSET); - addr_hit[ 50] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_11_OFFSET); - addr_hit[ 51] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_12_OFFSET); - addr_hit[ 52] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_13_OFFSET); - addr_hit[ 53] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_14_OFFSET); - addr_hit[ 54] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_15_OFFSET); - addr_hit[ 55] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_16_OFFSET); - addr_hit[ 56] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_17_OFFSET); - addr_hit[ 57] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_18_OFFSET); - addr_hit[ 58] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_19_OFFSET); - addr_hit[ 59] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_20_OFFSET); - addr_hit[ 60] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_21_OFFSET); - addr_hit[ 61] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_22_OFFSET); - addr_hit[ 62] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_23_OFFSET); - addr_hit[ 63] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_24_OFFSET); - addr_hit[ 64] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_25_OFFSET); - addr_hit[ 65] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_26_OFFSET); - addr_hit[ 66] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_27_OFFSET); - addr_hit[ 67] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_28_OFFSET); - addr_hit[ 68] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_29_OFFSET); - addr_hit[ 69] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_30_OFFSET); - addr_hit[ 70] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_31_OFFSET); - addr_hit[ 71] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_0_OFFSET); - addr_hit[ 72] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_1_OFFSET); - addr_hit[ 73] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_2_OFFSET); - addr_hit[ 74] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_3_OFFSET); - addr_hit[ 75] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_4_OFFSET); - addr_hit[ 76] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_5_OFFSET); - addr_hit[ 77] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_6_OFFSET); - addr_hit[ 78] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_7_OFFSET); - addr_hit[ 79] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_8_OFFSET); - addr_hit[ 80] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_9_OFFSET); - addr_hit[ 81] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_10_OFFSET); - addr_hit[ 82] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_11_OFFSET); - addr_hit[ 83] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_12_OFFSET); - addr_hit[ 84] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_13_OFFSET); - addr_hit[ 85] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_14_OFFSET); - addr_hit[ 86] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_15_OFFSET); - addr_hit[ 87] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_16_OFFSET); - addr_hit[ 88] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_17_OFFSET); - addr_hit[ 89] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_18_OFFSET); - addr_hit[ 90] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_19_OFFSET); - addr_hit[ 91] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_20_OFFSET); - addr_hit[ 92] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_21_OFFSET); - addr_hit[ 93] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_22_OFFSET); - addr_hit[ 94] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_23_OFFSET); - addr_hit[ 95] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_24_OFFSET); - addr_hit[ 96] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_25_OFFSET); - addr_hit[ 97] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_26_OFFSET); - addr_hit[ 98] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_27_OFFSET); - addr_hit[ 99] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_28_OFFSET); - addr_hit[100] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_29_OFFSET); - addr_hit[101] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_30_OFFSET); - addr_hit[102] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_31_OFFSET); - addr_hit[103] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_0_OFFSET); - addr_hit[104] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_1_OFFSET); - addr_hit[105] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_2_OFFSET); - addr_hit[106] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_3_OFFSET); - addr_hit[107] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_4_OFFSET); - addr_hit[108] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_5_OFFSET); - addr_hit[109] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_6_OFFSET); - addr_hit[110] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_7_OFFSET); - addr_hit[111] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_8_OFFSET); - addr_hit[112] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_9_OFFSET); - addr_hit[113] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_10_OFFSET); - addr_hit[114] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_11_OFFSET); - addr_hit[115] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_12_OFFSET); - addr_hit[116] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_13_OFFSET); - addr_hit[117] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_14_OFFSET); - addr_hit[118] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_15_OFFSET); - addr_hit[119] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_16_OFFSET); - addr_hit[120] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_17_OFFSET); - addr_hit[121] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_18_OFFSET); - addr_hit[122] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_19_OFFSET); - addr_hit[123] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_20_OFFSET); - addr_hit[124] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_21_OFFSET); - addr_hit[125] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_22_OFFSET); - addr_hit[126] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_23_OFFSET); - addr_hit[127] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_24_OFFSET); - addr_hit[128] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_25_OFFSET); - addr_hit[129] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_26_OFFSET); - addr_hit[130] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_27_OFFSET); - addr_hit[131] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_28_OFFSET); - addr_hit[132] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_29_OFFSET); - addr_hit[133] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_30_OFFSET); - addr_hit[134] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_31_OFFSET); - addr_hit[135] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_0_OFFSET); - addr_hit[136] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_1_OFFSET); - addr_hit[137] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_2_OFFSET); - addr_hit[138] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_3_OFFSET); - addr_hit[139] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_4_OFFSET); - addr_hit[140] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_5_OFFSET); - addr_hit[141] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_6_OFFSET); - addr_hit[142] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_7_OFFSET); - addr_hit[143] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_8_OFFSET); - addr_hit[144] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_9_OFFSET); - addr_hit[145] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_10_OFFSET); - addr_hit[146] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_11_OFFSET); - addr_hit[147] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_12_OFFSET); - addr_hit[148] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_13_OFFSET); - addr_hit[149] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_14_OFFSET); - addr_hit[150] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_15_OFFSET); - addr_hit[151] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_16_OFFSET); - addr_hit[152] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_17_OFFSET); - addr_hit[153] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_18_OFFSET); - addr_hit[154] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_19_OFFSET); - addr_hit[155] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_20_OFFSET); - addr_hit[156] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_21_OFFSET); - addr_hit[157] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_22_OFFSET); - addr_hit[158] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_23_OFFSET); - addr_hit[159] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_24_OFFSET); - addr_hit[160] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_25_OFFSET); - addr_hit[161] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_26_OFFSET); - addr_hit[162] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_27_OFFSET); - addr_hit[163] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_28_OFFSET); - addr_hit[164] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_29_OFFSET); - addr_hit[165] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_30_OFFSET); - addr_hit[166] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_31_OFFSET); + addr_hit[ 4] = (reg_addr == AC_RANGE_CHECK_ALERT_STATUS_OFFSET); + addr_hit[ 5] = (reg_addr == AC_RANGE_CHECK_LOG_CONFIG_OFFSET); + addr_hit[ 6] = (reg_addr == AC_RANGE_CHECK_LOG_STATUS_OFFSET); + addr_hit[ 7] = (reg_addr == AC_RANGE_CHECK_LOG_ADDRESS_OFFSET); + addr_hit[ 8] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_0_OFFSET); + addr_hit[ 9] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_1_OFFSET); + addr_hit[ 10] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_2_OFFSET); + addr_hit[ 11] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_3_OFFSET); + addr_hit[ 12] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_4_OFFSET); + addr_hit[ 13] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_5_OFFSET); + addr_hit[ 14] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_6_OFFSET); + addr_hit[ 15] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_7_OFFSET); + addr_hit[ 16] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_8_OFFSET); + addr_hit[ 17] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_9_OFFSET); + addr_hit[ 18] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_10_OFFSET); + addr_hit[ 19] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_11_OFFSET); + addr_hit[ 20] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_12_OFFSET); + addr_hit[ 21] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_13_OFFSET); + addr_hit[ 22] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_14_OFFSET); + addr_hit[ 23] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_15_OFFSET); + addr_hit[ 24] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_16_OFFSET); + addr_hit[ 25] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_17_OFFSET); + addr_hit[ 26] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_18_OFFSET); + addr_hit[ 27] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_19_OFFSET); + addr_hit[ 28] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_20_OFFSET); + addr_hit[ 29] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_21_OFFSET); + addr_hit[ 30] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_22_OFFSET); + addr_hit[ 31] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_23_OFFSET); + addr_hit[ 32] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_24_OFFSET); + addr_hit[ 33] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_25_OFFSET); + addr_hit[ 34] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_26_OFFSET); + addr_hit[ 35] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_27_OFFSET); + addr_hit[ 36] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_28_OFFSET); + addr_hit[ 37] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_29_OFFSET); + addr_hit[ 38] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_30_OFFSET); + addr_hit[ 39] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_31_OFFSET); + addr_hit[ 40] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_0_OFFSET); + addr_hit[ 41] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_1_OFFSET); + addr_hit[ 42] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_2_OFFSET); + addr_hit[ 43] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_3_OFFSET); + addr_hit[ 44] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_4_OFFSET); + addr_hit[ 45] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_5_OFFSET); + addr_hit[ 46] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_6_OFFSET); + addr_hit[ 47] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_7_OFFSET); + addr_hit[ 48] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_8_OFFSET); + addr_hit[ 49] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_9_OFFSET); + addr_hit[ 50] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_10_OFFSET); + addr_hit[ 51] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_11_OFFSET); + addr_hit[ 52] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_12_OFFSET); + addr_hit[ 53] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_13_OFFSET); + addr_hit[ 54] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_14_OFFSET); + addr_hit[ 55] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_15_OFFSET); + addr_hit[ 56] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_16_OFFSET); + addr_hit[ 57] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_17_OFFSET); + addr_hit[ 58] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_18_OFFSET); + addr_hit[ 59] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_19_OFFSET); + addr_hit[ 60] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_20_OFFSET); + addr_hit[ 61] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_21_OFFSET); + addr_hit[ 62] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_22_OFFSET); + addr_hit[ 63] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_23_OFFSET); + addr_hit[ 64] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_24_OFFSET); + addr_hit[ 65] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_25_OFFSET); + addr_hit[ 66] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_26_OFFSET); + addr_hit[ 67] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_27_OFFSET); + addr_hit[ 68] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_28_OFFSET); + addr_hit[ 69] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_29_OFFSET); + addr_hit[ 70] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_30_OFFSET); + addr_hit[ 71] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_31_OFFSET); + addr_hit[ 72] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_0_OFFSET); + addr_hit[ 73] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_1_OFFSET); + addr_hit[ 74] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_2_OFFSET); + addr_hit[ 75] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_3_OFFSET); + addr_hit[ 76] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_4_OFFSET); + addr_hit[ 77] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_5_OFFSET); + addr_hit[ 78] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_6_OFFSET); + addr_hit[ 79] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_7_OFFSET); + addr_hit[ 80] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_8_OFFSET); + addr_hit[ 81] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_9_OFFSET); + addr_hit[ 82] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_10_OFFSET); + addr_hit[ 83] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_11_OFFSET); + addr_hit[ 84] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_12_OFFSET); + addr_hit[ 85] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_13_OFFSET); + addr_hit[ 86] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_14_OFFSET); + addr_hit[ 87] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_15_OFFSET); + addr_hit[ 88] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_16_OFFSET); + addr_hit[ 89] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_17_OFFSET); + addr_hit[ 90] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_18_OFFSET); + addr_hit[ 91] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_19_OFFSET); + addr_hit[ 92] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_20_OFFSET); + addr_hit[ 93] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_21_OFFSET); + addr_hit[ 94] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_22_OFFSET); + addr_hit[ 95] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_23_OFFSET); + addr_hit[ 96] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_24_OFFSET); + addr_hit[ 97] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_25_OFFSET); + addr_hit[ 98] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_26_OFFSET); + addr_hit[ 99] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_27_OFFSET); + addr_hit[100] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_28_OFFSET); + addr_hit[101] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_29_OFFSET); + addr_hit[102] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_30_OFFSET); + addr_hit[103] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_31_OFFSET); + addr_hit[104] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_0_OFFSET); + addr_hit[105] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_1_OFFSET); + addr_hit[106] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_2_OFFSET); + addr_hit[107] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_3_OFFSET); + addr_hit[108] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_4_OFFSET); + addr_hit[109] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_5_OFFSET); + addr_hit[110] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_6_OFFSET); + addr_hit[111] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_7_OFFSET); + addr_hit[112] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_8_OFFSET); + addr_hit[113] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_9_OFFSET); + addr_hit[114] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_10_OFFSET); + addr_hit[115] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_11_OFFSET); + addr_hit[116] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_12_OFFSET); + addr_hit[117] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_13_OFFSET); + addr_hit[118] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_14_OFFSET); + addr_hit[119] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_15_OFFSET); + addr_hit[120] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_16_OFFSET); + addr_hit[121] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_17_OFFSET); + addr_hit[122] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_18_OFFSET); + addr_hit[123] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_19_OFFSET); + addr_hit[124] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_20_OFFSET); + addr_hit[125] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_21_OFFSET); + addr_hit[126] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_22_OFFSET); + addr_hit[127] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_23_OFFSET); + addr_hit[128] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_24_OFFSET); + addr_hit[129] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_25_OFFSET); + addr_hit[130] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_26_OFFSET); + addr_hit[131] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_27_OFFSET); + addr_hit[132] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_28_OFFSET); + addr_hit[133] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_29_OFFSET); + addr_hit[134] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_30_OFFSET); + addr_hit[135] = (reg_addr == AC_RANGE_CHECK_RANGE_PERM_31_OFFSET); + addr_hit[136] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_0_OFFSET); + addr_hit[137] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_1_OFFSET); + addr_hit[138] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_2_OFFSET); + addr_hit[139] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_3_OFFSET); + addr_hit[140] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_4_OFFSET); + addr_hit[141] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_5_OFFSET); + addr_hit[142] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_6_OFFSET); + addr_hit[143] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_7_OFFSET); + addr_hit[144] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_8_OFFSET); + addr_hit[145] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_9_OFFSET); + addr_hit[146] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_10_OFFSET); + addr_hit[147] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_11_OFFSET); + addr_hit[148] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_12_OFFSET); + addr_hit[149] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_13_OFFSET); + addr_hit[150] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_14_OFFSET); + addr_hit[151] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_15_OFFSET); + addr_hit[152] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_16_OFFSET); + addr_hit[153] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_17_OFFSET); + addr_hit[154] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_18_OFFSET); + addr_hit[155] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_19_OFFSET); + addr_hit[156] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_20_OFFSET); + addr_hit[157] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_21_OFFSET); + addr_hit[158] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_22_OFFSET); + addr_hit[159] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_23_OFFSET); + addr_hit[160] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_24_OFFSET); + addr_hit[161] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_25_OFFSET); + addr_hit[162] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_26_OFFSET); + addr_hit[163] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_27_OFFSET); + addr_hit[164] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_28_OFFSET); + addr_hit[165] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_29_OFFSET); + addr_hit[166] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_30_OFFSET); + addr_hit[167] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_31_OFFSET); if (EnableRacl) begin : gen_racl_hit - for (int unsigned slice_idx = 0; slice_idx < 167; slice_idx++) begin + for (int unsigned slice_idx = 0; slice_idx < 168; slice_idx++) begin racl_addr_hit_read[slice_idx] = addr_hit[slice_idx] & (|(racl_policies_i[RaclPolicySelVec[slice_idx]].read_perm & racl_role_vec)); @@ -12270,7 +12387,8 @@ module ac_range_check_reg_top (racl_addr_hit_write[163] & (|(AC_RANGE_CHECK_PERMIT[163] & ~reg_be))) | (racl_addr_hit_write[164] & (|(AC_RANGE_CHECK_PERMIT[164] & ~reg_be))) | (racl_addr_hit_write[165] & (|(AC_RANGE_CHECK_PERMIT[165] & ~reg_be))) | - (racl_addr_hit_write[166] & (|(AC_RANGE_CHECK_PERMIT[166] & ~reg_be))))); + (racl_addr_hit_write[166] & (|(AC_RANGE_CHECK_PERMIT[166] & ~reg_be))) | + (racl_addr_hit_write[167] & (|(AC_RANGE_CHECK_PERMIT[167] & ~reg_be))))); end // Generate write-enables @@ -12288,302 +12406,305 @@ module ac_range_check_reg_top assign alert_test_recov_ctrl_update_err_wd = reg_wdata[0]; assign alert_test_fatal_fault_wd = reg_wdata[1]; - assign log_config_we = racl_addr_hit_write[4] & reg_we & !reg_error; + assign alert_status_re = racl_addr_hit_read[4] & reg_re & !reg_error; + + assign alert_status_shadowed_update_err_wd = '1; + assign log_config_we = racl_addr_hit_write[5] & reg_we & !reg_error; assign log_config_log_enable_wd = reg_wdata[0]; assign log_config_log_clear_wd = reg_wdata[1]; assign log_config_deny_cnt_threshold_wd = reg_wdata[9:2]; - assign range_regwen_0_we = racl_addr_hit_write[7] & reg_we & !reg_error; + assign range_regwen_0_we = racl_addr_hit_write[8] & reg_we & !reg_error; assign range_regwen_0_wd = reg_wdata[3:0]; - assign range_regwen_1_we = racl_addr_hit_write[8] & reg_we & !reg_error; + assign range_regwen_1_we = racl_addr_hit_write[9] & reg_we & !reg_error; assign range_regwen_1_wd = reg_wdata[3:0]; - assign range_regwen_2_we = racl_addr_hit_write[9] & reg_we & !reg_error; + assign range_regwen_2_we = racl_addr_hit_write[10] & reg_we & !reg_error; assign range_regwen_2_wd = reg_wdata[3:0]; - assign range_regwen_3_we = racl_addr_hit_write[10] & reg_we & !reg_error; + assign range_regwen_3_we = racl_addr_hit_write[11] & reg_we & !reg_error; assign range_regwen_3_wd = reg_wdata[3:0]; - assign range_regwen_4_we = racl_addr_hit_write[11] & reg_we & !reg_error; + assign range_regwen_4_we = racl_addr_hit_write[12] & reg_we & !reg_error; assign range_regwen_4_wd = reg_wdata[3:0]; - assign range_regwen_5_we = racl_addr_hit_write[12] & reg_we & !reg_error; + assign range_regwen_5_we = racl_addr_hit_write[13] & reg_we & !reg_error; assign range_regwen_5_wd = reg_wdata[3:0]; - assign range_regwen_6_we = racl_addr_hit_write[13] & reg_we & !reg_error; + assign range_regwen_6_we = racl_addr_hit_write[14] & reg_we & !reg_error; assign range_regwen_6_wd = reg_wdata[3:0]; - assign range_regwen_7_we = racl_addr_hit_write[14] & reg_we & !reg_error; + assign range_regwen_7_we = racl_addr_hit_write[15] & reg_we & !reg_error; assign range_regwen_7_wd = reg_wdata[3:0]; - assign range_regwen_8_we = racl_addr_hit_write[15] & reg_we & !reg_error; + assign range_regwen_8_we = racl_addr_hit_write[16] & reg_we & !reg_error; assign range_regwen_8_wd = reg_wdata[3:0]; - assign range_regwen_9_we = racl_addr_hit_write[16] & reg_we & !reg_error; + assign range_regwen_9_we = racl_addr_hit_write[17] & reg_we & !reg_error; assign range_regwen_9_wd = reg_wdata[3:0]; - assign range_regwen_10_we = racl_addr_hit_write[17] & reg_we & !reg_error; + assign range_regwen_10_we = racl_addr_hit_write[18] & reg_we & !reg_error; assign range_regwen_10_wd = reg_wdata[3:0]; - assign range_regwen_11_we = racl_addr_hit_write[18] & reg_we & !reg_error; + assign range_regwen_11_we = racl_addr_hit_write[19] & reg_we & !reg_error; assign range_regwen_11_wd = reg_wdata[3:0]; - assign range_regwen_12_we = racl_addr_hit_write[19] & reg_we & !reg_error; + assign range_regwen_12_we = racl_addr_hit_write[20] & reg_we & !reg_error; assign range_regwen_12_wd = reg_wdata[3:0]; - assign range_regwen_13_we = racl_addr_hit_write[20] & reg_we & !reg_error; + assign range_regwen_13_we = racl_addr_hit_write[21] & reg_we & !reg_error; assign range_regwen_13_wd = reg_wdata[3:0]; - assign range_regwen_14_we = racl_addr_hit_write[21] & reg_we & !reg_error; + assign range_regwen_14_we = racl_addr_hit_write[22] & reg_we & !reg_error; assign range_regwen_14_wd = reg_wdata[3:0]; - assign range_regwen_15_we = racl_addr_hit_write[22] & reg_we & !reg_error; + assign range_regwen_15_we = racl_addr_hit_write[23] & reg_we & !reg_error; assign range_regwen_15_wd = reg_wdata[3:0]; - assign range_regwen_16_we = racl_addr_hit_write[23] & reg_we & !reg_error; + assign range_regwen_16_we = racl_addr_hit_write[24] & reg_we & !reg_error; assign range_regwen_16_wd = reg_wdata[3:0]; - assign range_regwen_17_we = racl_addr_hit_write[24] & reg_we & !reg_error; + assign range_regwen_17_we = racl_addr_hit_write[25] & reg_we & !reg_error; assign range_regwen_17_wd = reg_wdata[3:0]; - assign range_regwen_18_we = racl_addr_hit_write[25] & reg_we & !reg_error; + assign range_regwen_18_we = racl_addr_hit_write[26] & reg_we & !reg_error; assign range_regwen_18_wd = reg_wdata[3:0]; - assign range_regwen_19_we = racl_addr_hit_write[26] & reg_we & !reg_error; + assign range_regwen_19_we = racl_addr_hit_write[27] & reg_we & !reg_error; assign range_regwen_19_wd = reg_wdata[3:0]; - assign range_regwen_20_we = racl_addr_hit_write[27] & reg_we & !reg_error; + assign range_regwen_20_we = racl_addr_hit_write[28] & reg_we & !reg_error; assign range_regwen_20_wd = reg_wdata[3:0]; - assign range_regwen_21_we = racl_addr_hit_write[28] & reg_we & !reg_error; + assign range_regwen_21_we = racl_addr_hit_write[29] & reg_we & !reg_error; assign range_regwen_21_wd = reg_wdata[3:0]; - assign range_regwen_22_we = racl_addr_hit_write[29] & reg_we & !reg_error; + assign range_regwen_22_we = racl_addr_hit_write[30] & reg_we & !reg_error; assign range_regwen_22_wd = reg_wdata[3:0]; - assign range_regwen_23_we = racl_addr_hit_write[30] & reg_we & !reg_error; + assign range_regwen_23_we = racl_addr_hit_write[31] & reg_we & !reg_error; assign range_regwen_23_wd = reg_wdata[3:0]; - assign range_regwen_24_we = racl_addr_hit_write[31] & reg_we & !reg_error; + assign range_regwen_24_we = racl_addr_hit_write[32] & reg_we & !reg_error; assign range_regwen_24_wd = reg_wdata[3:0]; - assign range_regwen_25_we = racl_addr_hit_write[32] & reg_we & !reg_error; + assign range_regwen_25_we = racl_addr_hit_write[33] & reg_we & !reg_error; assign range_regwen_25_wd = reg_wdata[3:0]; - assign range_regwen_26_we = racl_addr_hit_write[33] & reg_we & !reg_error; + assign range_regwen_26_we = racl_addr_hit_write[34] & reg_we & !reg_error; assign range_regwen_26_wd = reg_wdata[3:0]; - assign range_regwen_27_we = racl_addr_hit_write[34] & reg_we & !reg_error; + assign range_regwen_27_we = racl_addr_hit_write[35] & reg_we & !reg_error; assign range_regwen_27_wd = reg_wdata[3:0]; - assign range_regwen_28_we = racl_addr_hit_write[35] & reg_we & !reg_error; + assign range_regwen_28_we = racl_addr_hit_write[36] & reg_we & !reg_error; assign range_regwen_28_wd = reg_wdata[3:0]; - assign range_regwen_29_we = racl_addr_hit_write[36] & reg_we & !reg_error; + assign range_regwen_29_we = racl_addr_hit_write[37] & reg_we & !reg_error; assign range_regwen_29_wd = reg_wdata[3:0]; - assign range_regwen_30_we = racl_addr_hit_write[37] & reg_we & !reg_error; + assign range_regwen_30_we = racl_addr_hit_write[38] & reg_we & !reg_error; assign range_regwen_30_wd = reg_wdata[3:0]; - assign range_regwen_31_we = racl_addr_hit_write[38] & reg_we & !reg_error; + assign range_regwen_31_we = racl_addr_hit_write[39] & reg_we & !reg_error; assign range_regwen_31_wd = reg_wdata[3:0]; - assign range_base_0_we = racl_addr_hit_write[39] & reg_we & !reg_error; + assign range_base_0_we = racl_addr_hit_write[40] & reg_we & !reg_error; assign range_base_0_wd = reg_wdata[31:2]; - assign range_base_1_we = racl_addr_hit_write[40] & reg_we & !reg_error; + assign range_base_1_we = racl_addr_hit_write[41] & reg_we & !reg_error; assign range_base_1_wd = reg_wdata[31:2]; - assign range_base_2_we = racl_addr_hit_write[41] & reg_we & !reg_error; + assign range_base_2_we = racl_addr_hit_write[42] & reg_we & !reg_error; assign range_base_2_wd = reg_wdata[31:2]; - assign range_base_3_we = racl_addr_hit_write[42] & reg_we & !reg_error; + assign range_base_3_we = racl_addr_hit_write[43] & reg_we & !reg_error; assign range_base_3_wd = reg_wdata[31:2]; - assign range_base_4_we = racl_addr_hit_write[43] & reg_we & !reg_error; + assign range_base_4_we = racl_addr_hit_write[44] & reg_we & !reg_error; assign range_base_4_wd = reg_wdata[31:2]; - assign range_base_5_we = racl_addr_hit_write[44] & reg_we & !reg_error; + assign range_base_5_we = racl_addr_hit_write[45] & reg_we & !reg_error; assign range_base_5_wd = reg_wdata[31:2]; - assign range_base_6_we = racl_addr_hit_write[45] & reg_we & !reg_error; + assign range_base_6_we = racl_addr_hit_write[46] & reg_we & !reg_error; assign range_base_6_wd = reg_wdata[31:2]; - assign range_base_7_we = racl_addr_hit_write[46] & reg_we & !reg_error; + assign range_base_7_we = racl_addr_hit_write[47] & reg_we & !reg_error; assign range_base_7_wd = reg_wdata[31:2]; - assign range_base_8_we = racl_addr_hit_write[47] & reg_we & !reg_error; + assign range_base_8_we = racl_addr_hit_write[48] & reg_we & !reg_error; assign range_base_8_wd = reg_wdata[31:2]; - assign range_base_9_we = racl_addr_hit_write[48] & reg_we & !reg_error; + assign range_base_9_we = racl_addr_hit_write[49] & reg_we & !reg_error; assign range_base_9_wd = reg_wdata[31:2]; - assign range_base_10_we = racl_addr_hit_write[49] & reg_we & !reg_error; + assign range_base_10_we = racl_addr_hit_write[50] & reg_we & !reg_error; assign range_base_10_wd = reg_wdata[31:2]; - assign range_base_11_we = racl_addr_hit_write[50] & reg_we & !reg_error; + assign range_base_11_we = racl_addr_hit_write[51] & reg_we & !reg_error; assign range_base_11_wd = reg_wdata[31:2]; - assign range_base_12_we = racl_addr_hit_write[51] & reg_we & !reg_error; + assign range_base_12_we = racl_addr_hit_write[52] & reg_we & !reg_error; assign range_base_12_wd = reg_wdata[31:2]; - assign range_base_13_we = racl_addr_hit_write[52] & reg_we & !reg_error; + assign range_base_13_we = racl_addr_hit_write[53] & reg_we & !reg_error; assign range_base_13_wd = reg_wdata[31:2]; - assign range_base_14_we = racl_addr_hit_write[53] & reg_we & !reg_error; + assign range_base_14_we = racl_addr_hit_write[54] & reg_we & !reg_error; assign range_base_14_wd = reg_wdata[31:2]; - assign range_base_15_we = racl_addr_hit_write[54] & reg_we & !reg_error; + assign range_base_15_we = racl_addr_hit_write[55] & reg_we & !reg_error; assign range_base_15_wd = reg_wdata[31:2]; - assign range_base_16_we = racl_addr_hit_write[55] & reg_we & !reg_error; + assign range_base_16_we = racl_addr_hit_write[56] & reg_we & !reg_error; assign range_base_16_wd = reg_wdata[31:2]; - assign range_base_17_we = racl_addr_hit_write[56] & reg_we & !reg_error; + assign range_base_17_we = racl_addr_hit_write[57] & reg_we & !reg_error; assign range_base_17_wd = reg_wdata[31:2]; - assign range_base_18_we = racl_addr_hit_write[57] & reg_we & !reg_error; + assign range_base_18_we = racl_addr_hit_write[58] & reg_we & !reg_error; assign range_base_18_wd = reg_wdata[31:2]; - assign range_base_19_we = racl_addr_hit_write[58] & reg_we & !reg_error; + assign range_base_19_we = racl_addr_hit_write[59] & reg_we & !reg_error; assign range_base_19_wd = reg_wdata[31:2]; - assign range_base_20_we = racl_addr_hit_write[59] & reg_we & !reg_error; + assign range_base_20_we = racl_addr_hit_write[60] & reg_we & !reg_error; assign range_base_20_wd = reg_wdata[31:2]; - assign range_base_21_we = racl_addr_hit_write[60] & reg_we & !reg_error; + assign range_base_21_we = racl_addr_hit_write[61] & reg_we & !reg_error; assign range_base_21_wd = reg_wdata[31:2]; - assign range_base_22_we = racl_addr_hit_write[61] & reg_we & !reg_error; + assign range_base_22_we = racl_addr_hit_write[62] & reg_we & !reg_error; assign range_base_22_wd = reg_wdata[31:2]; - assign range_base_23_we = racl_addr_hit_write[62] & reg_we & !reg_error; + assign range_base_23_we = racl_addr_hit_write[63] & reg_we & !reg_error; assign range_base_23_wd = reg_wdata[31:2]; - assign range_base_24_we = racl_addr_hit_write[63] & reg_we & !reg_error; + assign range_base_24_we = racl_addr_hit_write[64] & reg_we & !reg_error; assign range_base_24_wd = reg_wdata[31:2]; - assign range_base_25_we = racl_addr_hit_write[64] & reg_we & !reg_error; + assign range_base_25_we = racl_addr_hit_write[65] & reg_we & !reg_error; assign range_base_25_wd = reg_wdata[31:2]; - assign range_base_26_we = racl_addr_hit_write[65] & reg_we & !reg_error; + assign range_base_26_we = racl_addr_hit_write[66] & reg_we & !reg_error; assign range_base_26_wd = reg_wdata[31:2]; - assign range_base_27_we = racl_addr_hit_write[66] & reg_we & !reg_error; + assign range_base_27_we = racl_addr_hit_write[67] & reg_we & !reg_error; assign range_base_27_wd = reg_wdata[31:2]; - assign range_base_28_we = racl_addr_hit_write[67] & reg_we & !reg_error; + assign range_base_28_we = racl_addr_hit_write[68] & reg_we & !reg_error; assign range_base_28_wd = reg_wdata[31:2]; - assign range_base_29_we = racl_addr_hit_write[68] & reg_we & !reg_error; + assign range_base_29_we = racl_addr_hit_write[69] & reg_we & !reg_error; assign range_base_29_wd = reg_wdata[31:2]; - assign range_base_30_we = racl_addr_hit_write[69] & reg_we & !reg_error; + assign range_base_30_we = racl_addr_hit_write[70] & reg_we & !reg_error; assign range_base_30_wd = reg_wdata[31:2]; - assign range_base_31_we = racl_addr_hit_write[70] & reg_we & !reg_error; + assign range_base_31_we = racl_addr_hit_write[71] & reg_we & !reg_error; assign range_base_31_wd = reg_wdata[31:2]; - assign range_limit_0_we = racl_addr_hit_write[71] & reg_we & !reg_error; + assign range_limit_0_we = racl_addr_hit_write[72] & reg_we & !reg_error; assign range_limit_0_wd = reg_wdata[31:2]; - assign range_limit_1_we = racl_addr_hit_write[72] & reg_we & !reg_error; + assign range_limit_1_we = racl_addr_hit_write[73] & reg_we & !reg_error; assign range_limit_1_wd = reg_wdata[31:2]; - assign range_limit_2_we = racl_addr_hit_write[73] & reg_we & !reg_error; + assign range_limit_2_we = racl_addr_hit_write[74] & reg_we & !reg_error; assign range_limit_2_wd = reg_wdata[31:2]; - assign range_limit_3_we = racl_addr_hit_write[74] & reg_we & !reg_error; + assign range_limit_3_we = racl_addr_hit_write[75] & reg_we & !reg_error; assign range_limit_3_wd = reg_wdata[31:2]; - assign range_limit_4_we = racl_addr_hit_write[75] & reg_we & !reg_error; + assign range_limit_4_we = racl_addr_hit_write[76] & reg_we & !reg_error; assign range_limit_4_wd = reg_wdata[31:2]; - assign range_limit_5_we = racl_addr_hit_write[76] & reg_we & !reg_error; + assign range_limit_5_we = racl_addr_hit_write[77] & reg_we & !reg_error; assign range_limit_5_wd = reg_wdata[31:2]; - assign range_limit_6_we = racl_addr_hit_write[77] & reg_we & !reg_error; + assign range_limit_6_we = racl_addr_hit_write[78] & reg_we & !reg_error; assign range_limit_6_wd = reg_wdata[31:2]; - assign range_limit_7_we = racl_addr_hit_write[78] & reg_we & !reg_error; + assign range_limit_7_we = racl_addr_hit_write[79] & reg_we & !reg_error; assign range_limit_7_wd = reg_wdata[31:2]; - assign range_limit_8_we = racl_addr_hit_write[79] & reg_we & !reg_error; + assign range_limit_8_we = racl_addr_hit_write[80] & reg_we & !reg_error; assign range_limit_8_wd = reg_wdata[31:2]; - assign range_limit_9_we = racl_addr_hit_write[80] & reg_we & !reg_error; + assign range_limit_9_we = racl_addr_hit_write[81] & reg_we & !reg_error; assign range_limit_9_wd = reg_wdata[31:2]; - assign range_limit_10_we = racl_addr_hit_write[81] & reg_we & !reg_error; + assign range_limit_10_we = racl_addr_hit_write[82] & reg_we & !reg_error; assign range_limit_10_wd = reg_wdata[31:2]; - assign range_limit_11_we = racl_addr_hit_write[82] & reg_we & !reg_error; + assign range_limit_11_we = racl_addr_hit_write[83] & reg_we & !reg_error; assign range_limit_11_wd = reg_wdata[31:2]; - assign range_limit_12_we = racl_addr_hit_write[83] & reg_we & !reg_error; + assign range_limit_12_we = racl_addr_hit_write[84] & reg_we & !reg_error; assign range_limit_12_wd = reg_wdata[31:2]; - assign range_limit_13_we = racl_addr_hit_write[84] & reg_we & !reg_error; + assign range_limit_13_we = racl_addr_hit_write[85] & reg_we & !reg_error; assign range_limit_13_wd = reg_wdata[31:2]; - assign range_limit_14_we = racl_addr_hit_write[85] & reg_we & !reg_error; + assign range_limit_14_we = racl_addr_hit_write[86] & reg_we & !reg_error; assign range_limit_14_wd = reg_wdata[31:2]; - assign range_limit_15_we = racl_addr_hit_write[86] & reg_we & !reg_error; + assign range_limit_15_we = racl_addr_hit_write[87] & reg_we & !reg_error; assign range_limit_15_wd = reg_wdata[31:2]; - assign range_limit_16_we = racl_addr_hit_write[87] & reg_we & !reg_error; + assign range_limit_16_we = racl_addr_hit_write[88] & reg_we & !reg_error; assign range_limit_16_wd = reg_wdata[31:2]; - assign range_limit_17_we = racl_addr_hit_write[88] & reg_we & !reg_error; + assign range_limit_17_we = racl_addr_hit_write[89] & reg_we & !reg_error; assign range_limit_17_wd = reg_wdata[31:2]; - assign range_limit_18_we = racl_addr_hit_write[89] & reg_we & !reg_error; + assign range_limit_18_we = racl_addr_hit_write[90] & reg_we & !reg_error; assign range_limit_18_wd = reg_wdata[31:2]; - assign range_limit_19_we = racl_addr_hit_write[90] & reg_we & !reg_error; + assign range_limit_19_we = racl_addr_hit_write[91] & reg_we & !reg_error; assign range_limit_19_wd = reg_wdata[31:2]; - assign range_limit_20_we = racl_addr_hit_write[91] & reg_we & !reg_error; + assign range_limit_20_we = racl_addr_hit_write[92] & reg_we & !reg_error; assign range_limit_20_wd = reg_wdata[31:2]; - assign range_limit_21_we = racl_addr_hit_write[92] & reg_we & !reg_error; + assign range_limit_21_we = racl_addr_hit_write[93] & reg_we & !reg_error; assign range_limit_21_wd = reg_wdata[31:2]; - assign range_limit_22_we = racl_addr_hit_write[93] & reg_we & !reg_error; + assign range_limit_22_we = racl_addr_hit_write[94] & reg_we & !reg_error; assign range_limit_22_wd = reg_wdata[31:2]; - assign range_limit_23_we = racl_addr_hit_write[94] & reg_we & !reg_error; + assign range_limit_23_we = racl_addr_hit_write[95] & reg_we & !reg_error; assign range_limit_23_wd = reg_wdata[31:2]; - assign range_limit_24_we = racl_addr_hit_write[95] & reg_we & !reg_error; + assign range_limit_24_we = racl_addr_hit_write[96] & reg_we & !reg_error; assign range_limit_24_wd = reg_wdata[31:2]; - assign range_limit_25_we = racl_addr_hit_write[96] & reg_we & !reg_error; + assign range_limit_25_we = racl_addr_hit_write[97] & reg_we & !reg_error; assign range_limit_25_wd = reg_wdata[31:2]; - assign range_limit_26_we = racl_addr_hit_write[97] & reg_we & !reg_error; + assign range_limit_26_we = racl_addr_hit_write[98] & reg_we & !reg_error; assign range_limit_26_wd = reg_wdata[31:2]; - assign range_limit_27_we = racl_addr_hit_write[98] & reg_we & !reg_error; + assign range_limit_27_we = racl_addr_hit_write[99] & reg_we & !reg_error; assign range_limit_27_wd = reg_wdata[31:2]; - assign range_limit_28_we = racl_addr_hit_write[99] & reg_we & !reg_error; + assign range_limit_28_we = racl_addr_hit_write[100] & reg_we & !reg_error; assign range_limit_28_wd = reg_wdata[31:2]; - assign range_limit_29_we = racl_addr_hit_write[100] & reg_we & !reg_error; + assign range_limit_29_we = racl_addr_hit_write[101] & reg_we & !reg_error; assign range_limit_29_wd = reg_wdata[31:2]; - assign range_limit_30_we = racl_addr_hit_write[101] & reg_we & !reg_error; + assign range_limit_30_we = racl_addr_hit_write[102] & reg_we & !reg_error; assign range_limit_30_wd = reg_wdata[31:2]; - assign range_limit_31_we = racl_addr_hit_write[102] & reg_we & !reg_error; + assign range_limit_31_we = racl_addr_hit_write[103] & reg_we & !reg_error; assign range_limit_31_wd = reg_wdata[31:2]; - assign range_perm_0_we = racl_addr_hit_write[103] & reg_we & !reg_error; + assign range_perm_0_we = racl_addr_hit_write[104] & reg_we & !reg_error; assign range_perm_0_enable_0_wd = reg_wdata[3:0]; @@ -12594,7 +12715,7 @@ module ac_range_check_reg_top assign range_perm_0_execute_access_0_wd = reg_wdata[15:12]; assign range_perm_0_log_denied_access_0_wd = reg_wdata[19:16]; - assign range_perm_1_we = racl_addr_hit_write[104] & reg_we & !reg_error; + assign range_perm_1_we = racl_addr_hit_write[105] & reg_we & !reg_error; assign range_perm_1_enable_1_wd = reg_wdata[3:0]; @@ -12605,7 +12726,7 @@ module ac_range_check_reg_top assign range_perm_1_execute_access_1_wd = reg_wdata[15:12]; assign range_perm_1_log_denied_access_1_wd = reg_wdata[19:16]; - assign range_perm_2_we = racl_addr_hit_write[105] & reg_we & !reg_error; + assign range_perm_2_we = racl_addr_hit_write[106] & reg_we & !reg_error; assign range_perm_2_enable_2_wd = reg_wdata[3:0]; @@ -12616,7 +12737,7 @@ module ac_range_check_reg_top assign range_perm_2_execute_access_2_wd = reg_wdata[15:12]; assign range_perm_2_log_denied_access_2_wd = reg_wdata[19:16]; - assign range_perm_3_we = racl_addr_hit_write[106] & reg_we & !reg_error; + assign range_perm_3_we = racl_addr_hit_write[107] & reg_we & !reg_error; assign range_perm_3_enable_3_wd = reg_wdata[3:0]; @@ -12627,7 +12748,7 @@ module ac_range_check_reg_top assign range_perm_3_execute_access_3_wd = reg_wdata[15:12]; assign range_perm_3_log_denied_access_3_wd = reg_wdata[19:16]; - assign range_perm_4_we = racl_addr_hit_write[107] & reg_we & !reg_error; + assign range_perm_4_we = racl_addr_hit_write[108] & reg_we & !reg_error; assign range_perm_4_enable_4_wd = reg_wdata[3:0]; @@ -12638,7 +12759,7 @@ module ac_range_check_reg_top assign range_perm_4_execute_access_4_wd = reg_wdata[15:12]; assign range_perm_4_log_denied_access_4_wd = reg_wdata[19:16]; - assign range_perm_5_we = racl_addr_hit_write[108] & reg_we & !reg_error; + assign range_perm_5_we = racl_addr_hit_write[109] & reg_we & !reg_error; assign range_perm_5_enable_5_wd = reg_wdata[3:0]; @@ -12649,7 +12770,7 @@ module ac_range_check_reg_top assign range_perm_5_execute_access_5_wd = reg_wdata[15:12]; assign range_perm_5_log_denied_access_5_wd = reg_wdata[19:16]; - assign range_perm_6_we = racl_addr_hit_write[109] & reg_we & !reg_error; + assign range_perm_6_we = racl_addr_hit_write[110] & reg_we & !reg_error; assign range_perm_6_enable_6_wd = reg_wdata[3:0]; @@ -12660,7 +12781,7 @@ module ac_range_check_reg_top assign range_perm_6_execute_access_6_wd = reg_wdata[15:12]; assign range_perm_6_log_denied_access_6_wd = reg_wdata[19:16]; - assign range_perm_7_we = racl_addr_hit_write[110] & reg_we & !reg_error; + assign range_perm_7_we = racl_addr_hit_write[111] & reg_we & !reg_error; assign range_perm_7_enable_7_wd = reg_wdata[3:0]; @@ -12671,7 +12792,7 @@ module ac_range_check_reg_top assign range_perm_7_execute_access_7_wd = reg_wdata[15:12]; assign range_perm_7_log_denied_access_7_wd = reg_wdata[19:16]; - assign range_perm_8_we = racl_addr_hit_write[111] & reg_we & !reg_error; + assign range_perm_8_we = racl_addr_hit_write[112] & reg_we & !reg_error; assign range_perm_8_enable_8_wd = reg_wdata[3:0]; @@ -12682,7 +12803,7 @@ module ac_range_check_reg_top assign range_perm_8_execute_access_8_wd = reg_wdata[15:12]; assign range_perm_8_log_denied_access_8_wd = reg_wdata[19:16]; - assign range_perm_9_we = racl_addr_hit_write[112] & reg_we & !reg_error; + assign range_perm_9_we = racl_addr_hit_write[113] & reg_we & !reg_error; assign range_perm_9_enable_9_wd = reg_wdata[3:0]; @@ -12693,7 +12814,7 @@ module ac_range_check_reg_top assign range_perm_9_execute_access_9_wd = reg_wdata[15:12]; assign range_perm_9_log_denied_access_9_wd = reg_wdata[19:16]; - assign range_perm_10_we = racl_addr_hit_write[113] & reg_we & !reg_error; + assign range_perm_10_we = racl_addr_hit_write[114] & reg_we & !reg_error; assign range_perm_10_enable_10_wd = reg_wdata[3:0]; @@ -12704,7 +12825,7 @@ module ac_range_check_reg_top assign range_perm_10_execute_access_10_wd = reg_wdata[15:12]; assign range_perm_10_log_denied_access_10_wd = reg_wdata[19:16]; - assign range_perm_11_we = racl_addr_hit_write[114] & reg_we & !reg_error; + assign range_perm_11_we = racl_addr_hit_write[115] & reg_we & !reg_error; assign range_perm_11_enable_11_wd = reg_wdata[3:0]; @@ -12715,7 +12836,7 @@ module ac_range_check_reg_top assign range_perm_11_execute_access_11_wd = reg_wdata[15:12]; assign range_perm_11_log_denied_access_11_wd = reg_wdata[19:16]; - assign range_perm_12_we = racl_addr_hit_write[115] & reg_we & !reg_error; + assign range_perm_12_we = racl_addr_hit_write[116] & reg_we & !reg_error; assign range_perm_12_enable_12_wd = reg_wdata[3:0]; @@ -12726,7 +12847,7 @@ module ac_range_check_reg_top assign range_perm_12_execute_access_12_wd = reg_wdata[15:12]; assign range_perm_12_log_denied_access_12_wd = reg_wdata[19:16]; - assign range_perm_13_we = racl_addr_hit_write[116] & reg_we & !reg_error; + assign range_perm_13_we = racl_addr_hit_write[117] & reg_we & !reg_error; assign range_perm_13_enable_13_wd = reg_wdata[3:0]; @@ -12737,7 +12858,7 @@ module ac_range_check_reg_top assign range_perm_13_execute_access_13_wd = reg_wdata[15:12]; assign range_perm_13_log_denied_access_13_wd = reg_wdata[19:16]; - assign range_perm_14_we = racl_addr_hit_write[117] & reg_we & !reg_error; + assign range_perm_14_we = racl_addr_hit_write[118] & reg_we & !reg_error; assign range_perm_14_enable_14_wd = reg_wdata[3:0]; @@ -12748,7 +12869,7 @@ module ac_range_check_reg_top assign range_perm_14_execute_access_14_wd = reg_wdata[15:12]; assign range_perm_14_log_denied_access_14_wd = reg_wdata[19:16]; - assign range_perm_15_we = racl_addr_hit_write[118] & reg_we & !reg_error; + assign range_perm_15_we = racl_addr_hit_write[119] & reg_we & !reg_error; assign range_perm_15_enable_15_wd = reg_wdata[3:0]; @@ -12759,7 +12880,7 @@ module ac_range_check_reg_top assign range_perm_15_execute_access_15_wd = reg_wdata[15:12]; assign range_perm_15_log_denied_access_15_wd = reg_wdata[19:16]; - assign range_perm_16_we = racl_addr_hit_write[119] & reg_we & !reg_error; + assign range_perm_16_we = racl_addr_hit_write[120] & reg_we & !reg_error; assign range_perm_16_enable_16_wd = reg_wdata[3:0]; @@ -12770,7 +12891,7 @@ module ac_range_check_reg_top assign range_perm_16_execute_access_16_wd = reg_wdata[15:12]; assign range_perm_16_log_denied_access_16_wd = reg_wdata[19:16]; - assign range_perm_17_we = racl_addr_hit_write[120] & reg_we & !reg_error; + assign range_perm_17_we = racl_addr_hit_write[121] & reg_we & !reg_error; assign range_perm_17_enable_17_wd = reg_wdata[3:0]; @@ -12781,7 +12902,7 @@ module ac_range_check_reg_top assign range_perm_17_execute_access_17_wd = reg_wdata[15:12]; assign range_perm_17_log_denied_access_17_wd = reg_wdata[19:16]; - assign range_perm_18_we = racl_addr_hit_write[121] & reg_we & !reg_error; + assign range_perm_18_we = racl_addr_hit_write[122] & reg_we & !reg_error; assign range_perm_18_enable_18_wd = reg_wdata[3:0]; @@ -12792,7 +12913,7 @@ module ac_range_check_reg_top assign range_perm_18_execute_access_18_wd = reg_wdata[15:12]; assign range_perm_18_log_denied_access_18_wd = reg_wdata[19:16]; - assign range_perm_19_we = racl_addr_hit_write[122] & reg_we & !reg_error; + assign range_perm_19_we = racl_addr_hit_write[123] & reg_we & !reg_error; assign range_perm_19_enable_19_wd = reg_wdata[3:0]; @@ -12803,7 +12924,7 @@ module ac_range_check_reg_top assign range_perm_19_execute_access_19_wd = reg_wdata[15:12]; assign range_perm_19_log_denied_access_19_wd = reg_wdata[19:16]; - assign range_perm_20_we = racl_addr_hit_write[123] & reg_we & !reg_error; + assign range_perm_20_we = racl_addr_hit_write[124] & reg_we & !reg_error; assign range_perm_20_enable_20_wd = reg_wdata[3:0]; @@ -12814,7 +12935,7 @@ module ac_range_check_reg_top assign range_perm_20_execute_access_20_wd = reg_wdata[15:12]; assign range_perm_20_log_denied_access_20_wd = reg_wdata[19:16]; - assign range_perm_21_we = racl_addr_hit_write[124] & reg_we & !reg_error; + assign range_perm_21_we = racl_addr_hit_write[125] & reg_we & !reg_error; assign range_perm_21_enable_21_wd = reg_wdata[3:0]; @@ -12825,7 +12946,7 @@ module ac_range_check_reg_top assign range_perm_21_execute_access_21_wd = reg_wdata[15:12]; assign range_perm_21_log_denied_access_21_wd = reg_wdata[19:16]; - assign range_perm_22_we = racl_addr_hit_write[125] & reg_we & !reg_error; + assign range_perm_22_we = racl_addr_hit_write[126] & reg_we & !reg_error; assign range_perm_22_enable_22_wd = reg_wdata[3:0]; @@ -12836,7 +12957,7 @@ module ac_range_check_reg_top assign range_perm_22_execute_access_22_wd = reg_wdata[15:12]; assign range_perm_22_log_denied_access_22_wd = reg_wdata[19:16]; - assign range_perm_23_we = racl_addr_hit_write[126] & reg_we & !reg_error; + assign range_perm_23_we = racl_addr_hit_write[127] & reg_we & !reg_error; assign range_perm_23_enable_23_wd = reg_wdata[3:0]; @@ -12847,7 +12968,7 @@ module ac_range_check_reg_top assign range_perm_23_execute_access_23_wd = reg_wdata[15:12]; assign range_perm_23_log_denied_access_23_wd = reg_wdata[19:16]; - assign range_perm_24_we = racl_addr_hit_write[127] & reg_we & !reg_error; + assign range_perm_24_we = racl_addr_hit_write[128] & reg_we & !reg_error; assign range_perm_24_enable_24_wd = reg_wdata[3:0]; @@ -12858,7 +12979,7 @@ module ac_range_check_reg_top assign range_perm_24_execute_access_24_wd = reg_wdata[15:12]; assign range_perm_24_log_denied_access_24_wd = reg_wdata[19:16]; - assign range_perm_25_we = racl_addr_hit_write[128] & reg_we & !reg_error; + assign range_perm_25_we = racl_addr_hit_write[129] & reg_we & !reg_error; assign range_perm_25_enable_25_wd = reg_wdata[3:0]; @@ -12869,7 +12990,7 @@ module ac_range_check_reg_top assign range_perm_25_execute_access_25_wd = reg_wdata[15:12]; assign range_perm_25_log_denied_access_25_wd = reg_wdata[19:16]; - assign range_perm_26_we = racl_addr_hit_write[129] & reg_we & !reg_error; + assign range_perm_26_we = racl_addr_hit_write[130] & reg_we & !reg_error; assign range_perm_26_enable_26_wd = reg_wdata[3:0]; @@ -12880,7 +13001,7 @@ module ac_range_check_reg_top assign range_perm_26_execute_access_26_wd = reg_wdata[15:12]; assign range_perm_26_log_denied_access_26_wd = reg_wdata[19:16]; - assign range_perm_27_we = racl_addr_hit_write[130] & reg_we & !reg_error; + assign range_perm_27_we = racl_addr_hit_write[131] & reg_we & !reg_error; assign range_perm_27_enable_27_wd = reg_wdata[3:0]; @@ -12891,7 +13012,7 @@ module ac_range_check_reg_top assign range_perm_27_execute_access_27_wd = reg_wdata[15:12]; assign range_perm_27_log_denied_access_27_wd = reg_wdata[19:16]; - assign range_perm_28_we = racl_addr_hit_write[131] & reg_we & !reg_error; + assign range_perm_28_we = racl_addr_hit_write[132] & reg_we & !reg_error; assign range_perm_28_enable_28_wd = reg_wdata[3:0]; @@ -12902,7 +13023,7 @@ module ac_range_check_reg_top assign range_perm_28_execute_access_28_wd = reg_wdata[15:12]; assign range_perm_28_log_denied_access_28_wd = reg_wdata[19:16]; - assign range_perm_29_we = racl_addr_hit_write[132] & reg_we & !reg_error; + assign range_perm_29_we = racl_addr_hit_write[133] & reg_we & !reg_error; assign range_perm_29_enable_29_wd = reg_wdata[3:0]; @@ -12913,7 +13034,7 @@ module ac_range_check_reg_top assign range_perm_29_execute_access_29_wd = reg_wdata[15:12]; assign range_perm_29_log_denied_access_29_wd = reg_wdata[19:16]; - assign range_perm_30_we = racl_addr_hit_write[133] & reg_we & !reg_error; + assign range_perm_30_we = racl_addr_hit_write[134] & reg_we & !reg_error; assign range_perm_30_enable_30_wd = reg_wdata[3:0]; @@ -12924,7 +13045,7 @@ module ac_range_check_reg_top assign range_perm_30_execute_access_30_wd = reg_wdata[15:12]; assign range_perm_30_log_denied_access_30_wd = reg_wdata[19:16]; - assign range_perm_31_we = racl_addr_hit_write[134] & reg_we & !reg_error; + assign range_perm_31_we = racl_addr_hit_write[135] & reg_we & !reg_error; assign range_perm_31_enable_31_wd = reg_wdata[3:0]; @@ -12935,194 +13056,194 @@ module ac_range_check_reg_top assign range_perm_31_execute_access_31_wd = reg_wdata[15:12]; assign range_perm_31_log_denied_access_31_wd = reg_wdata[19:16]; - assign range_racl_policy_shadowed_0_re = racl_addr_hit_read[135] & reg_re & !reg_error; - assign range_racl_policy_shadowed_0_we = racl_addr_hit_write[135] & reg_we & !reg_error; + assign range_racl_policy_shadowed_0_re = racl_addr_hit_read[136] & reg_re & !reg_error; + assign range_racl_policy_shadowed_0_we = racl_addr_hit_write[136] & reg_we & !reg_error; assign range_racl_policy_shadowed_0_read_perm_0_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_0_write_perm_0_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_1_re = racl_addr_hit_read[136] & reg_re & !reg_error; - assign range_racl_policy_shadowed_1_we = racl_addr_hit_write[136] & reg_we & !reg_error; + assign range_racl_policy_shadowed_1_re = racl_addr_hit_read[137] & reg_re & !reg_error; + assign range_racl_policy_shadowed_1_we = racl_addr_hit_write[137] & reg_we & !reg_error; assign range_racl_policy_shadowed_1_read_perm_1_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_1_write_perm_1_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_2_re = racl_addr_hit_read[137] & reg_re & !reg_error; - assign range_racl_policy_shadowed_2_we = racl_addr_hit_write[137] & reg_we & !reg_error; + assign range_racl_policy_shadowed_2_re = racl_addr_hit_read[138] & reg_re & !reg_error; + assign range_racl_policy_shadowed_2_we = racl_addr_hit_write[138] & reg_we & !reg_error; assign range_racl_policy_shadowed_2_read_perm_2_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_2_write_perm_2_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_3_re = racl_addr_hit_read[138] & reg_re & !reg_error; - assign range_racl_policy_shadowed_3_we = racl_addr_hit_write[138] & reg_we & !reg_error; + assign range_racl_policy_shadowed_3_re = racl_addr_hit_read[139] & reg_re & !reg_error; + assign range_racl_policy_shadowed_3_we = racl_addr_hit_write[139] & reg_we & !reg_error; assign range_racl_policy_shadowed_3_read_perm_3_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_3_write_perm_3_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_4_re = racl_addr_hit_read[139] & reg_re & !reg_error; - assign range_racl_policy_shadowed_4_we = racl_addr_hit_write[139] & reg_we & !reg_error; + assign range_racl_policy_shadowed_4_re = racl_addr_hit_read[140] & reg_re & !reg_error; + assign range_racl_policy_shadowed_4_we = racl_addr_hit_write[140] & reg_we & !reg_error; assign range_racl_policy_shadowed_4_read_perm_4_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_4_write_perm_4_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_5_re = racl_addr_hit_read[140] & reg_re & !reg_error; - assign range_racl_policy_shadowed_5_we = racl_addr_hit_write[140] & reg_we & !reg_error; + assign range_racl_policy_shadowed_5_re = racl_addr_hit_read[141] & reg_re & !reg_error; + assign range_racl_policy_shadowed_5_we = racl_addr_hit_write[141] & reg_we & !reg_error; assign range_racl_policy_shadowed_5_read_perm_5_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_5_write_perm_5_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_6_re = racl_addr_hit_read[141] & reg_re & !reg_error; - assign range_racl_policy_shadowed_6_we = racl_addr_hit_write[141] & reg_we & !reg_error; + assign range_racl_policy_shadowed_6_re = racl_addr_hit_read[142] & reg_re & !reg_error; + assign range_racl_policy_shadowed_6_we = racl_addr_hit_write[142] & reg_we & !reg_error; assign range_racl_policy_shadowed_6_read_perm_6_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_6_write_perm_6_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_7_re = racl_addr_hit_read[142] & reg_re & !reg_error; - assign range_racl_policy_shadowed_7_we = racl_addr_hit_write[142] & reg_we & !reg_error; + assign range_racl_policy_shadowed_7_re = racl_addr_hit_read[143] & reg_re & !reg_error; + assign range_racl_policy_shadowed_7_we = racl_addr_hit_write[143] & reg_we & !reg_error; assign range_racl_policy_shadowed_7_read_perm_7_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_7_write_perm_7_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_8_re = racl_addr_hit_read[143] & reg_re & !reg_error; - assign range_racl_policy_shadowed_8_we = racl_addr_hit_write[143] & reg_we & !reg_error; + assign range_racl_policy_shadowed_8_re = racl_addr_hit_read[144] & reg_re & !reg_error; + assign range_racl_policy_shadowed_8_we = racl_addr_hit_write[144] & reg_we & !reg_error; assign range_racl_policy_shadowed_8_read_perm_8_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_8_write_perm_8_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_9_re = racl_addr_hit_read[144] & reg_re & !reg_error; - assign range_racl_policy_shadowed_9_we = racl_addr_hit_write[144] & reg_we & !reg_error; + assign range_racl_policy_shadowed_9_re = racl_addr_hit_read[145] & reg_re & !reg_error; + assign range_racl_policy_shadowed_9_we = racl_addr_hit_write[145] & reg_we & !reg_error; assign range_racl_policy_shadowed_9_read_perm_9_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_9_write_perm_9_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_10_re = racl_addr_hit_read[145] & reg_re & !reg_error; - assign range_racl_policy_shadowed_10_we = racl_addr_hit_write[145] & reg_we & !reg_error; + assign range_racl_policy_shadowed_10_re = racl_addr_hit_read[146] & reg_re & !reg_error; + assign range_racl_policy_shadowed_10_we = racl_addr_hit_write[146] & reg_we & !reg_error; assign range_racl_policy_shadowed_10_read_perm_10_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_10_write_perm_10_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_11_re = racl_addr_hit_read[146] & reg_re & !reg_error; - assign range_racl_policy_shadowed_11_we = racl_addr_hit_write[146] & reg_we & !reg_error; + assign range_racl_policy_shadowed_11_re = racl_addr_hit_read[147] & reg_re & !reg_error; + assign range_racl_policy_shadowed_11_we = racl_addr_hit_write[147] & reg_we & !reg_error; assign range_racl_policy_shadowed_11_read_perm_11_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_11_write_perm_11_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_12_re = racl_addr_hit_read[147] & reg_re & !reg_error; - assign range_racl_policy_shadowed_12_we = racl_addr_hit_write[147] & reg_we & !reg_error; + assign range_racl_policy_shadowed_12_re = racl_addr_hit_read[148] & reg_re & !reg_error; + assign range_racl_policy_shadowed_12_we = racl_addr_hit_write[148] & reg_we & !reg_error; assign range_racl_policy_shadowed_12_read_perm_12_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_12_write_perm_12_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_13_re = racl_addr_hit_read[148] & reg_re & !reg_error; - assign range_racl_policy_shadowed_13_we = racl_addr_hit_write[148] & reg_we & !reg_error; + assign range_racl_policy_shadowed_13_re = racl_addr_hit_read[149] & reg_re & !reg_error; + assign range_racl_policy_shadowed_13_we = racl_addr_hit_write[149] & reg_we & !reg_error; assign range_racl_policy_shadowed_13_read_perm_13_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_13_write_perm_13_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_14_re = racl_addr_hit_read[149] & reg_re & !reg_error; - assign range_racl_policy_shadowed_14_we = racl_addr_hit_write[149] & reg_we & !reg_error; + assign range_racl_policy_shadowed_14_re = racl_addr_hit_read[150] & reg_re & !reg_error; + assign range_racl_policy_shadowed_14_we = racl_addr_hit_write[150] & reg_we & !reg_error; assign range_racl_policy_shadowed_14_read_perm_14_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_14_write_perm_14_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_15_re = racl_addr_hit_read[150] & reg_re & !reg_error; - assign range_racl_policy_shadowed_15_we = racl_addr_hit_write[150] & reg_we & !reg_error; + assign range_racl_policy_shadowed_15_re = racl_addr_hit_read[151] & reg_re & !reg_error; + assign range_racl_policy_shadowed_15_we = racl_addr_hit_write[151] & reg_we & !reg_error; assign range_racl_policy_shadowed_15_read_perm_15_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_15_write_perm_15_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_16_re = racl_addr_hit_read[151] & reg_re & !reg_error; - assign range_racl_policy_shadowed_16_we = racl_addr_hit_write[151] & reg_we & !reg_error; + assign range_racl_policy_shadowed_16_re = racl_addr_hit_read[152] & reg_re & !reg_error; + assign range_racl_policy_shadowed_16_we = racl_addr_hit_write[152] & reg_we & !reg_error; assign range_racl_policy_shadowed_16_read_perm_16_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_16_write_perm_16_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_17_re = racl_addr_hit_read[152] & reg_re & !reg_error; - assign range_racl_policy_shadowed_17_we = racl_addr_hit_write[152] & reg_we & !reg_error; + assign range_racl_policy_shadowed_17_re = racl_addr_hit_read[153] & reg_re & !reg_error; + assign range_racl_policy_shadowed_17_we = racl_addr_hit_write[153] & reg_we & !reg_error; assign range_racl_policy_shadowed_17_read_perm_17_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_17_write_perm_17_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_18_re = racl_addr_hit_read[153] & reg_re & !reg_error; - assign range_racl_policy_shadowed_18_we = racl_addr_hit_write[153] & reg_we & !reg_error; + assign range_racl_policy_shadowed_18_re = racl_addr_hit_read[154] & reg_re & !reg_error; + assign range_racl_policy_shadowed_18_we = racl_addr_hit_write[154] & reg_we & !reg_error; assign range_racl_policy_shadowed_18_read_perm_18_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_18_write_perm_18_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_19_re = racl_addr_hit_read[154] & reg_re & !reg_error; - assign range_racl_policy_shadowed_19_we = racl_addr_hit_write[154] & reg_we & !reg_error; + assign range_racl_policy_shadowed_19_re = racl_addr_hit_read[155] & reg_re & !reg_error; + assign range_racl_policy_shadowed_19_we = racl_addr_hit_write[155] & reg_we & !reg_error; assign range_racl_policy_shadowed_19_read_perm_19_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_19_write_perm_19_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_20_re = racl_addr_hit_read[155] & reg_re & !reg_error; - assign range_racl_policy_shadowed_20_we = racl_addr_hit_write[155] & reg_we & !reg_error; + assign range_racl_policy_shadowed_20_re = racl_addr_hit_read[156] & reg_re & !reg_error; + assign range_racl_policy_shadowed_20_we = racl_addr_hit_write[156] & reg_we & !reg_error; assign range_racl_policy_shadowed_20_read_perm_20_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_20_write_perm_20_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_21_re = racl_addr_hit_read[156] & reg_re & !reg_error; - assign range_racl_policy_shadowed_21_we = racl_addr_hit_write[156] & reg_we & !reg_error; + assign range_racl_policy_shadowed_21_re = racl_addr_hit_read[157] & reg_re & !reg_error; + assign range_racl_policy_shadowed_21_we = racl_addr_hit_write[157] & reg_we & !reg_error; assign range_racl_policy_shadowed_21_read_perm_21_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_21_write_perm_21_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_22_re = racl_addr_hit_read[157] & reg_re & !reg_error; - assign range_racl_policy_shadowed_22_we = racl_addr_hit_write[157] & reg_we & !reg_error; + assign range_racl_policy_shadowed_22_re = racl_addr_hit_read[158] & reg_re & !reg_error; + assign range_racl_policy_shadowed_22_we = racl_addr_hit_write[158] & reg_we & !reg_error; assign range_racl_policy_shadowed_22_read_perm_22_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_22_write_perm_22_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_23_re = racl_addr_hit_read[158] & reg_re & !reg_error; - assign range_racl_policy_shadowed_23_we = racl_addr_hit_write[158] & reg_we & !reg_error; + assign range_racl_policy_shadowed_23_re = racl_addr_hit_read[159] & reg_re & !reg_error; + assign range_racl_policy_shadowed_23_we = racl_addr_hit_write[159] & reg_we & !reg_error; assign range_racl_policy_shadowed_23_read_perm_23_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_23_write_perm_23_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_24_re = racl_addr_hit_read[159] & reg_re & !reg_error; - assign range_racl_policy_shadowed_24_we = racl_addr_hit_write[159] & reg_we & !reg_error; + assign range_racl_policy_shadowed_24_re = racl_addr_hit_read[160] & reg_re & !reg_error; + assign range_racl_policy_shadowed_24_we = racl_addr_hit_write[160] & reg_we & !reg_error; assign range_racl_policy_shadowed_24_read_perm_24_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_24_write_perm_24_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_25_re = racl_addr_hit_read[160] & reg_re & !reg_error; - assign range_racl_policy_shadowed_25_we = racl_addr_hit_write[160] & reg_we & !reg_error; + assign range_racl_policy_shadowed_25_re = racl_addr_hit_read[161] & reg_re & !reg_error; + assign range_racl_policy_shadowed_25_we = racl_addr_hit_write[161] & reg_we & !reg_error; assign range_racl_policy_shadowed_25_read_perm_25_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_25_write_perm_25_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_26_re = racl_addr_hit_read[161] & reg_re & !reg_error; - assign range_racl_policy_shadowed_26_we = racl_addr_hit_write[161] & reg_we & !reg_error; + assign range_racl_policy_shadowed_26_re = racl_addr_hit_read[162] & reg_re & !reg_error; + assign range_racl_policy_shadowed_26_we = racl_addr_hit_write[162] & reg_we & !reg_error; assign range_racl_policy_shadowed_26_read_perm_26_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_26_write_perm_26_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_27_re = racl_addr_hit_read[162] & reg_re & !reg_error; - assign range_racl_policy_shadowed_27_we = racl_addr_hit_write[162] & reg_we & !reg_error; + assign range_racl_policy_shadowed_27_re = racl_addr_hit_read[163] & reg_re & !reg_error; + assign range_racl_policy_shadowed_27_we = racl_addr_hit_write[163] & reg_we & !reg_error; assign range_racl_policy_shadowed_27_read_perm_27_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_27_write_perm_27_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_28_re = racl_addr_hit_read[163] & reg_re & !reg_error; - assign range_racl_policy_shadowed_28_we = racl_addr_hit_write[163] & reg_we & !reg_error; + assign range_racl_policy_shadowed_28_re = racl_addr_hit_read[164] & reg_re & !reg_error; + assign range_racl_policy_shadowed_28_we = racl_addr_hit_write[164] & reg_we & !reg_error; assign range_racl_policy_shadowed_28_read_perm_28_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_28_write_perm_28_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_29_re = racl_addr_hit_read[164] & reg_re & !reg_error; - assign range_racl_policy_shadowed_29_we = racl_addr_hit_write[164] & reg_we & !reg_error; + assign range_racl_policy_shadowed_29_re = racl_addr_hit_read[165] & reg_re & !reg_error; + assign range_racl_policy_shadowed_29_we = racl_addr_hit_write[165] & reg_we & !reg_error; assign range_racl_policy_shadowed_29_read_perm_29_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_29_write_perm_29_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_30_re = racl_addr_hit_read[165] & reg_re & !reg_error; - assign range_racl_policy_shadowed_30_we = racl_addr_hit_write[165] & reg_we & !reg_error; + assign range_racl_policy_shadowed_30_re = racl_addr_hit_read[166] & reg_re & !reg_error; + assign range_racl_policy_shadowed_30_we = racl_addr_hit_write[166] & reg_we & !reg_error; assign range_racl_policy_shadowed_30_read_perm_30_wd = reg_wdata[15:0]; assign range_racl_policy_shadowed_30_write_perm_30_wd = reg_wdata[31:16]; - assign range_racl_policy_shadowed_31_re = racl_addr_hit_read[166] & reg_re & !reg_error; - assign range_racl_policy_shadowed_31_we = racl_addr_hit_write[166] & reg_we & !reg_error; + assign range_racl_policy_shadowed_31_re = racl_addr_hit_read[167] & reg_re & !reg_error; + assign range_racl_policy_shadowed_31_we = racl_addr_hit_write[167] & reg_we & !reg_error; assign range_racl_policy_shadowed_31_read_perm_31_wd = reg_wdata[15:0]; @@ -13135,169 +13256,170 @@ module ac_range_check_reg_top reg_we_check[1] = intr_enable_we; reg_we_check[2] = intr_test_we; reg_we_check[3] = alert_test_we; - reg_we_check[4] = log_config_we; - reg_we_check[5] = 1'b0; + reg_we_check[4] = 1'b0; + reg_we_check[5] = log_config_we; reg_we_check[6] = 1'b0; - reg_we_check[7] = range_regwen_0_we; - reg_we_check[8] = range_regwen_1_we; - reg_we_check[9] = range_regwen_2_we; - reg_we_check[10] = range_regwen_3_we; - reg_we_check[11] = range_regwen_4_we; - reg_we_check[12] = range_regwen_5_we; - reg_we_check[13] = range_regwen_6_we; - reg_we_check[14] = range_regwen_7_we; - reg_we_check[15] = range_regwen_8_we; - reg_we_check[16] = range_regwen_9_we; - reg_we_check[17] = range_regwen_10_we; - reg_we_check[18] = range_regwen_11_we; - reg_we_check[19] = range_regwen_12_we; - reg_we_check[20] = range_regwen_13_we; - reg_we_check[21] = range_regwen_14_we; - reg_we_check[22] = range_regwen_15_we; - reg_we_check[23] = range_regwen_16_we; - reg_we_check[24] = range_regwen_17_we; - reg_we_check[25] = range_regwen_18_we; - reg_we_check[26] = range_regwen_19_we; - reg_we_check[27] = range_regwen_20_we; - reg_we_check[28] = range_regwen_21_we; - reg_we_check[29] = range_regwen_22_we; - reg_we_check[30] = range_regwen_23_we; - reg_we_check[31] = range_regwen_24_we; - reg_we_check[32] = range_regwen_25_we; - reg_we_check[33] = range_regwen_26_we; - reg_we_check[34] = range_regwen_27_we; - reg_we_check[35] = range_regwen_28_we; - reg_we_check[36] = range_regwen_29_we; - reg_we_check[37] = range_regwen_30_we; - reg_we_check[38] = range_regwen_31_we; - reg_we_check[39] = range_base_0_gated_we; - reg_we_check[40] = range_base_1_gated_we; - reg_we_check[41] = range_base_2_gated_we; - reg_we_check[42] = range_base_3_gated_we; - reg_we_check[43] = range_base_4_gated_we; - reg_we_check[44] = range_base_5_gated_we; - reg_we_check[45] = range_base_6_gated_we; - reg_we_check[46] = range_base_7_gated_we; - reg_we_check[47] = range_base_8_gated_we; - reg_we_check[48] = range_base_9_gated_we; - reg_we_check[49] = range_base_10_gated_we; - reg_we_check[50] = range_base_11_gated_we; - reg_we_check[51] = range_base_12_gated_we; - reg_we_check[52] = range_base_13_gated_we; - reg_we_check[53] = range_base_14_gated_we; - reg_we_check[54] = range_base_15_gated_we; - reg_we_check[55] = range_base_16_gated_we; - reg_we_check[56] = range_base_17_gated_we; - reg_we_check[57] = range_base_18_gated_we; - reg_we_check[58] = range_base_19_gated_we; - reg_we_check[59] = range_base_20_gated_we; - reg_we_check[60] = range_base_21_gated_we; - reg_we_check[61] = range_base_22_gated_we; - reg_we_check[62] = range_base_23_gated_we; - reg_we_check[63] = range_base_24_gated_we; - reg_we_check[64] = range_base_25_gated_we; - reg_we_check[65] = range_base_26_gated_we; - reg_we_check[66] = range_base_27_gated_we; - reg_we_check[67] = range_base_28_gated_we; - reg_we_check[68] = range_base_29_gated_we; - reg_we_check[69] = range_base_30_gated_we; - reg_we_check[70] = range_base_31_gated_we; - reg_we_check[71] = range_limit_0_gated_we; - reg_we_check[72] = range_limit_1_gated_we; - reg_we_check[73] = range_limit_2_gated_we; - reg_we_check[74] = range_limit_3_gated_we; - reg_we_check[75] = range_limit_4_gated_we; - reg_we_check[76] = range_limit_5_gated_we; - reg_we_check[77] = range_limit_6_gated_we; - reg_we_check[78] = range_limit_7_gated_we; - reg_we_check[79] = range_limit_8_gated_we; - reg_we_check[80] = range_limit_9_gated_we; - reg_we_check[81] = range_limit_10_gated_we; - reg_we_check[82] = range_limit_11_gated_we; - reg_we_check[83] = range_limit_12_gated_we; - reg_we_check[84] = range_limit_13_gated_we; - reg_we_check[85] = range_limit_14_gated_we; - reg_we_check[86] = range_limit_15_gated_we; - reg_we_check[87] = range_limit_16_gated_we; - reg_we_check[88] = range_limit_17_gated_we; - reg_we_check[89] = range_limit_18_gated_we; - reg_we_check[90] = range_limit_19_gated_we; - reg_we_check[91] = range_limit_20_gated_we; - reg_we_check[92] = range_limit_21_gated_we; - reg_we_check[93] = range_limit_22_gated_we; - reg_we_check[94] = range_limit_23_gated_we; - reg_we_check[95] = range_limit_24_gated_we; - reg_we_check[96] = range_limit_25_gated_we; - reg_we_check[97] = range_limit_26_gated_we; - reg_we_check[98] = range_limit_27_gated_we; - reg_we_check[99] = range_limit_28_gated_we; - reg_we_check[100] = range_limit_29_gated_we; - reg_we_check[101] = range_limit_30_gated_we; - reg_we_check[102] = range_limit_31_gated_we; - reg_we_check[103] = range_perm_0_gated_we; - reg_we_check[104] = range_perm_1_gated_we; - reg_we_check[105] = range_perm_2_gated_we; - reg_we_check[106] = range_perm_3_gated_we; - reg_we_check[107] = range_perm_4_gated_we; - reg_we_check[108] = range_perm_5_gated_we; - reg_we_check[109] = range_perm_6_gated_we; - reg_we_check[110] = range_perm_7_gated_we; - reg_we_check[111] = range_perm_8_gated_we; - reg_we_check[112] = range_perm_9_gated_we; - reg_we_check[113] = range_perm_10_gated_we; - reg_we_check[114] = range_perm_11_gated_we; - reg_we_check[115] = range_perm_12_gated_we; - reg_we_check[116] = range_perm_13_gated_we; - reg_we_check[117] = range_perm_14_gated_we; - reg_we_check[118] = range_perm_15_gated_we; - reg_we_check[119] = range_perm_16_gated_we; - reg_we_check[120] = range_perm_17_gated_we; - reg_we_check[121] = range_perm_18_gated_we; - reg_we_check[122] = range_perm_19_gated_we; - reg_we_check[123] = range_perm_20_gated_we; - reg_we_check[124] = range_perm_21_gated_we; - reg_we_check[125] = range_perm_22_gated_we; - reg_we_check[126] = range_perm_23_gated_we; - reg_we_check[127] = range_perm_24_gated_we; - reg_we_check[128] = range_perm_25_gated_we; - reg_we_check[129] = range_perm_26_gated_we; - reg_we_check[130] = range_perm_27_gated_we; - reg_we_check[131] = range_perm_28_gated_we; - reg_we_check[132] = range_perm_29_gated_we; - reg_we_check[133] = range_perm_30_gated_we; - reg_we_check[134] = range_perm_31_gated_we; - reg_we_check[135] = range_racl_policy_shadowed_0_gated_we; - reg_we_check[136] = range_racl_policy_shadowed_1_gated_we; - reg_we_check[137] = range_racl_policy_shadowed_2_gated_we; - reg_we_check[138] = range_racl_policy_shadowed_3_gated_we; - reg_we_check[139] = range_racl_policy_shadowed_4_gated_we; - reg_we_check[140] = range_racl_policy_shadowed_5_gated_we; - reg_we_check[141] = range_racl_policy_shadowed_6_gated_we; - reg_we_check[142] = range_racl_policy_shadowed_7_gated_we; - reg_we_check[143] = range_racl_policy_shadowed_8_gated_we; - reg_we_check[144] = range_racl_policy_shadowed_9_gated_we; - reg_we_check[145] = range_racl_policy_shadowed_10_gated_we; - reg_we_check[146] = range_racl_policy_shadowed_11_gated_we; - reg_we_check[147] = range_racl_policy_shadowed_12_gated_we; - reg_we_check[148] = range_racl_policy_shadowed_13_gated_we; - reg_we_check[149] = range_racl_policy_shadowed_14_gated_we; - reg_we_check[150] = range_racl_policy_shadowed_15_gated_we; - reg_we_check[151] = range_racl_policy_shadowed_16_gated_we; - reg_we_check[152] = range_racl_policy_shadowed_17_gated_we; - reg_we_check[153] = range_racl_policy_shadowed_18_gated_we; - reg_we_check[154] = range_racl_policy_shadowed_19_gated_we; - reg_we_check[155] = range_racl_policy_shadowed_20_gated_we; - reg_we_check[156] = range_racl_policy_shadowed_21_gated_we; - reg_we_check[157] = range_racl_policy_shadowed_22_gated_we; - reg_we_check[158] = range_racl_policy_shadowed_23_gated_we; - reg_we_check[159] = range_racl_policy_shadowed_24_gated_we; - reg_we_check[160] = range_racl_policy_shadowed_25_gated_we; - reg_we_check[161] = range_racl_policy_shadowed_26_gated_we; - reg_we_check[162] = range_racl_policy_shadowed_27_gated_we; - reg_we_check[163] = range_racl_policy_shadowed_28_gated_we; - reg_we_check[164] = range_racl_policy_shadowed_29_gated_we; - reg_we_check[165] = range_racl_policy_shadowed_30_gated_we; - reg_we_check[166] = range_racl_policy_shadowed_31_gated_we; + reg_we_check[7] = 1'b0; + reg_we_check[8] = range_regwen_0_we; + reg_we_check[9] = range_regwen_1_we; + reg_we_check[10] = range_regwen_2_we; + reg_we_check[11] = range_regwen_3_we; + reg_we_check[12] = range_regwen_4_we; + reg_we_check[13] = range_regwen_5_we; + reg_we_check[14] = range_regwen_6_we; + reg_we_check[15] = range_regwen_7_we; + reg_we_check[16] = range_regwen_8_we; + reg_we_check[17] = range_regwen_9_we; + reg_we_check[18] = range_regwen_10_we; + reg_we_check[19] = range_regwen_11_we; + reg_we_check[20] = range_regwen_12_we; + reg_we_check[21] = range_regwen_13_we; + reg_we_check[22] = range_regwen_14_we; + reg_we_check[23] = range_regwen_15_we; + reg_we_check[24] = range_regwen_16_we; + reg_we_check[25] = range_regwen_17_we; + reg_we_check[26] = range_regwen_18_we; + reg_we_check[27] = range_regwen_19_we; + reg_we_check[28] = range_regwen_20_we; + reg_we_check[29] = range_regwen_21_we; + reg_we_check[30] = range_regwen_22_we; + reg_we_check[31] = range_regwen_23_we; + reg_we_check[32] = range_regwen_24_we; + reg_we_check[33] = range_regwen_25_we; + reg_we_check[34] = range_regwen_26_we; + reg_we_check[35] = range_regwen_27_we; + reg_we_check[36] = range_regwen_28_we; + reg_we_check[37] = range_regwen_29_we; + reg_we_check[38] = range_regwen_30_we; + reg_we_check[39] = range_regwen_31_we; + reg_we_check[40] = range_base_0_gated_we; + reg_we_check[41] = range_base_1_gated_we; + reg_we_check[42] = range_base_2_gated_we; + reg_we_check[43] = range_base_3_gated_we; + reg_we_check[44] = range_base_4_gated_we; + reg_we_check[45] = range_base_5_gated_we; + reg_we_check[46] = range_base_6_gated_we; + reg_we_check[47] = range_base_7_gated_we; + reg_we_check[48] = range_base_8_gated_we; + reg_we_check[49] = range_base_9_gated_we; + reg_we_check[50] = range_base_10_gated_we; + reg_we_check[51] = range_base_11_gated_we; + reg_we_check[52] = range_base_12_gated_we; + reg_we_check[53] = range_base_13_gated_we; + reg_we_check[54] = range_base_14_gated_we; + reg_we_check[55] = range_base_15_gated_we; + reg_we_check[56] = range_base_16_gated_we; + reg_we_check[57] = range_base_17_gated_we; + reg_we_check[58] = range_base_18_gated_we; + reg_we_check[59] = range_base_19_gated_we; + reg_we_check[60] = range_base_20_gated_we; + reg_we_check[61] = range_base_21_gated_we; + reg_we_check[62] = range_base_22_gated_we; + reg_we_check[63] = range_base_23_gated_we; + reg_we_check[64] = range_base_24_gated_we; + reg_we_check[65] = range_base_25_gated_we; + reg_we_check[66] = range_base_26_gated_we; + reg_we_check[67] = range_base_27_gated_we; + reg_we_check[68] = range_base_28_gated_we; + reg_we_check[69] = range_base_29_gated_we; + reg_we_check[70] = range_base_30_gated_we; + reg_we_check[71] = range_base_31_gated_we; + reg_we_check[72] = range_limit_0_gated_we; + reg_we_check[73] = range_limit_1_gated_we; + reg_we_check[74] = range_limit_2_gated_we; + reg_we_check[75] = range_limit_3_gated_we; + reg_we_check[76] = range_limit_4_gated_we; + reg_we_check[77] = range_limit_5_gated_we; + reg_we_check[78] = range_limit_6_gated_we; + reg_we_check[79] = range_limit_7_gated_we; + reg_we_check[80] = range_limit_8_gated_we; + reg_we_check[81] = range_limit_9_gated_we; + reg_we_check[82] = range_limit_10_gated_we; + reg_we_check[83] = range_limit_11_gated_we; + reg_we_check[84] = range_limit_12_gated_we; + reg_we_check[85] = range_limit_13_gated_we; + reg_we_check[86] = range_limit_14_gated_we; + reg_we_check[87] = range_limit_15_gated_we; + reg_we_check[88] = range_limit_16_gated_we; + reg_we_check[89] = range_limit_17_gated_we; + reg_we_check[90] = range_limit_18_gated_we; + reg_we_check[91] = range_limit_19_gated_we; + reg_we_check[92] = range_limit_20_gated_we; + reg_we_check[93] = range_limit_21_gated_we; + reg_we_check[94] = range_limit_22_gated_we; + reg_we_check[95] = range_limit_23_gated_we; + reg_we_check[96] = range_limit_24_gated_we; + reg_we_check[97] = range_limit_25_gated_we; + reg_we_check[98] = range_limit_26_gated_we; + reg_we_check[99] = range_limit_27_gated_we; + reg_we_check[100] = range_limit_28_gated_we; + reg_we_check[101] = range_limit_29_gated_we; + reg_we_check[102] = range_limit_30_gated_we; + reg_we_check[103] = range_limit_31_gated_we; + reg_we_check[104] = range_perm_0_gated_we; + reg_we_check[105] = range_perm_1_gated_we; + reg_we_check[106] = range_perm_2_gated_we; + reg_we_check[107] = range_perm_3_gated_we; + reg_we_check[108] = range_perm_4_gated_we; + reg_we_check[109] = range_perm_5_gated_we; + reg_we_check[110] = range_perm_6_gated_we; + reg_we_check[111] = range_perm_7_gated_we; + reg_we_check[112] = range_perm_8_gated_we; + reg_we_check[113] = range_perm_9_gated_we; + reg_we_check[114] = range_perm_10_gated_we; + reg_we_check[115] = range_perm_11_gated_we; + reg_we_check[116] = range_perm_12_gated_we; + reg_we_check[117] = range_perm_13_gated_we; + reg_we_check[118] = range_perm_14_gated_we; + reg_we_check[119] = range_perm_15_gated_we; + reg_we_check[120] = range_perm_16_gated_we; + reg_we_check[121] = range_perm_17_gated_we; + reg_we_check[122] = range_perm_18_gated_we; + reg_we_check[123] = range_perm_19_gated_we; + reg_we_check[124] = range_perm_20_gated_we; + reg_we_check[125] = range_perm_21_gated_we; + reg_we_check[126] = range_perm_22_gated_we; + reg_we_check[127] = range_perm_23_gated_we; + reg_we_check[128] = range_perm_24_gated_we; + reg_we_check[129] = range_perm_25_gated_we; + reg_we_check[130] = range_perm_26_gated_we; + reg_we_check[131] = range_perm_27_gated_we; + reg_we_check[132] = range_perm_28_gated_we; + reg_we_check[133] = range_perm_29_gated_we; + reg_we_check[134] = range_perm_30_gated_we; + reg_we_check[135] = range_perm_31_gated_we; + reg_we_check[136] = range_racl_policy_shadowed_0_gated_we; + reg_we_check[137] = range_racl_policy_shadowed_1_gated_we; + reg_we_check[138] = range_racl_policy_shadowed_2_gated_we; + reg_we_check[139] = range_racl_policy_shadowed_3_gated_we; + reg_we_check[140] = range_racl_policy_shadowed_4_gated_we; + reg_we_check[141] = range_racl_policy_shadowed_5_gated_we; + reg_we_check[142] = range_racl_policy_shadowed_6_gated_we; + reg_we_check[143] = range_racl_policy_shadowed_7_gated_we; + reg_we_check[144] = range_racl_policy_shadowed_8_gated_we; + reg_we_check[145] = range_racl_policy_shadowed_9_gated_we; + reg_we_check[146] = range_racl_policy_shadowed_10_gated_we; + reg_we_check[147] = range_racl_policy_shadowed_11_gated_we; + reg_we_check[148] = range_racl_policy_shadowed_12_gated_we; + reg_we_check[149] = range_racl_policy_shadowed_13_gated_we; + reg_we_check[150] = range_racl_policy_shadowed_14_gated_we; + reg_we_check[151] = range_racl_policy_shadowed_15_gated_we; + reg_we_check[152] = range_racl_policy_shadowed_16_gated_we; + reg_we_check[153] = range_racl_policy_shadowed_17_gated_we; + reg_we_check[154] = range_racl_policy_shadowed_18_gated_we; + reg_we_check[155] = range_racl_policy_shadowed_19_gated_we; + reg_we_check[156] = range_racl_policy_shadowed_20_gated_we; + reg_we_check[157] = range_racl_policy_shadowed_21_gated_we; + reg_we_check[158] = range_racl_policy_shadowed_22_gated_we; + reg_we_check[159] = range_racl_policy_shadowed_23_gated_we; + reg_we_check[160] = range_racl_policy_shadowed_24_gated_we; + reg_we_check[161] = range_racl_policy_shadowed_25_gated_we; + reg_we_check[162] = range_racl_policy_shadowed_26_gated_we; + reg_we_check[163] = range_racl_policy_shadowed_27_gated_we; + reg_we_check[164] = range_racl_policy_shadowed_28_gated_we; + reg_we_check[165] = range_racl_policy_shadowed_29_gated_we; + reg_we_check[166] = range_racl_policy_shadowed_30_gated_we; + reg_we_check[167] = range_racl_policy_shadowed_31_gated_we; end // Read data return @@ -13322,12 +13444,19 @@ module ac_range_check_reg_top end racl_addr_hit_read[4]: begin + reg_rdata_next[0] = alert_status_shadowed_update_err_qs; + reg_rdata_next[1] = alert_status_shadowed_storage_err_qs; + reg_rdata_next[2] = alert_status_reg_intg_err_qs; + reg_rdata_next[3] = alert_status_counter_err_qs; + end + + racl_addr_hit_read[5]: begin reg_rdata_next[0] = log_config_log_enable_qs; reg_rdata_next[1] = log_config_log_clear_qs; reg_rdata_next[9:2] = log_config_deny_cnt_threshold_qs; end - racl_addr_hit_read[5]: begin + racl_addr_hit_read[6]: begin reg_rdata_next[7:0] = log_status_deny_cnt_qs; reg_rdata_next[8] = log_status_denied_read_access_qs; reg_rdata_next[9] = log_status_denied_write_access_qs; @@ -13340,395 +13469,395 @@ module ac_range_check_reg_top reg_rdata_next[27:23] = log_status_deny_range_index_qs; end - racl_addr_hit_read[6]: begin + racl_addr_hit_read[7]: begin reg_rdata_next[31:0] = log_address_qs; end - racl_addr_hit_read[7]: begin + racl_addr_hit_read[8]: begin reg_rdata_next[3:0] = range_regwen_0_qs; end - racl_addr_hit_read[8]: begin + racl_addr_hit_read[9]: begin reg_rdata_next[3:0] = range_regwen_1_qs; end - racl_addr_hit_read[9]: begin + racl_addr_hit_read[10]: begin reg_rdata_next[3:0] = range_regwen_2_qs; end - racl_addr_hit_read[10]: begin + racl_addr_hit_read[11]: begin reg_rdata_next[3:0] = range_regwen_3_qs; end - racl_addr_hit_read[11]: begin + racl_addr_hit_read[12]: begin reg_rdata_next[3:0] = range_regwen_4_qs; end - racl_addr_hit_read[12]: begin + racl_addr_hit_read[13]: begin reg_rdata_next[3:0] = range_regwen_5_qs; end - racl_addr_hit_read[13]: begin + racl_addr_hit_read[14]: begin reg_rdata_next[3:0] = range_regwen_6_qs; end - racl_addr_hit_read[14]: begin + racl_addr_hit_read[15]: begin reg_rdata_next[3:0] = range_regwen_7_qs; end - racl_addr_hit_read[15]: begin + racl_addr_hit_read[16]: begin reg_rdata_next[3:0] = range_regwen_8_qs; end - racl_addr_hit_read[16]: begin + racl_addr_hit_read[17]: begin reg_rdata_next[3:0] = range_regwen_9_qs; end - racl_addr_hit_read[17]: begin + racl_addr_hit_read[18]: begin reg_rdata_next[3:0] = range_regwen_10_qs; end - racl_addr_hit_read[18]: begin + racl_addr_hit_read[19]: begin reg_rdata_next[3:0] = range_regwen_11_qs; end - racl_addr_hit_read[19]: begin + racl_addr_hit_read[20]: begin reg_rdata_next[3:0] = range_regwen_12_qs; end - racl_addr_hit_read[20]: begin + racl_addr_hit_read[21]: begin reg_rdata_next[3:0] = range_regwen_13_qs; end - racl_addr_hit_read[21]: begin + racl_addr_hit_read[22]: begin reg_rdata_next[3:0] = range_regwen_14_qs; end - racl_addr_hit_read[22]: begin + racl_addr_hit_read[23]: begin reg_rdata_next[3:0] = range_regwen_15_qs; end - racl_addr_hit_read[23]: begin + racl_addr_hit_read[24]: begin reg_rdata_next[3:0] = range_regwen_16_qs; end - racl_addr_hit_read[24]: begin + racl_addr_hit_read[25]: begin reg_rdata_next[3:0] = range_regwen_17_qs; end - racl_addr_hit_read[25]: begin + racl_addr_hit_read[26]: begin reg_rdata_next[3:0] = range_regwen_18_qs; end - racl_addr_hit_read[26]: begin + racl_addr_hit_read[27]: begin reg_rdata_next[3:0] = range_regwen_19_qs; end - racl_addr_hit_read[27]: begin + racl_addr_hit_read[28]: begin reg_rdata_next[3:0] = range_regwen_20_qs; end - racl_addr_hit_read[28]: begin + racl_addr_hit_read[29]: begin reg_rdata_next[3:0] = range_regwen_21_qs; end - racl_addr_hit_read[29]: begin + racl_addr_hit_read[30]: begin reg_rdata_next[3:0] = range_regwen_22_qs; end - racl_addr_hit_read[30]: begin + racl_addr_hit_read[31]: begin reg_rdata_next[3:0] = range_regwen_23_qs; end - racl_addr_hit_read[31]: begin + racl_addr_hit_read[32]: begin reg_rdata_next[3:0] = range_regwen_24_qs; end - racl_addr_hit_read[32]: begin + racl_addr_hit_read[33]: begin reg_rdata_next[3:0] = range_regwen_25_qs; end - racl_addr_hit_read[33]: begin + racl_addr_hit_read[34]: begin reg_rdata_next[3:0] = range_regwen_26_qs; end - racl_addr_hit_read[34]: begin + racl_addr_hit_read[35]: begin reg_rdata_next[3:0] = range_regwen_27_qs; end - racl_addr_hit_read[35]: begin + racl_addr_hit_read[36]: begin reg_rdata_next[3:0] = range_regwen_28_qs; end - racl_addr_hit_read[36]: begin + racl_addr_hit_read[37]: begin reg_rdata_next[3:0] = range_regwen_29_qs; end - racl_addr_hit_read[37]: begin + racl_addr_hit_read[38]: begin reg_rdata_next[3:0] = range_regwen_30_qs; end - racl_addr_hit_read[38]: begin + racl_addr_hit_read[39]: begin reg_rdata_next[3:0] = range_regwen_31_qs; end - racl_addr_hit_read[39]: begin + racl_addr_hit_read[40]: begin reg_rdata_next[31:2] = range_base_0_qs; end - racl_addr_hit_read[40]: begin + racl_addr_hit_read[41]: begin reg_rdata_next[31:2] = range_base_1_qs; end - racl_addr_hit_read[41]: begin + racl_addr_hit_read[42]: begin reg_rdata_next[31:2] = range_base_2_qs; end - racl_addr_hit_read[42]: begin + racl_addr_hit_read[43]: begin reg_rdata_next[31:2] = range_base_3_qs; end - racl_addr_hit_read[43]: begin + racl_addr_hit_read[44]: begin reg_rdata_next[31:2] = range_base_4_qs; end - racl_addr_hit_read[44]: begin + racl_addr_hit_read[45]: begin reg_rdata_next[31:2] = range_base_5_qs; end - racl_addr_hit_read[45]: begin + racl_addr_hit_read[46]: begin reg_rdata_next[31:2] = range_base_6_qs; end - racl_addr_hit_read[46]: begin + racl_addr_hit_read[47]: begin reg_rdata_next[31:2] = range_base_7_qs; end - racl_addr_hit_read[47]: begin + racl_addr_hit_read[48]: begin reg_rdata_next[31:2] = range_base_8_qs; end - racl_addr_hit_read[48]: begin + racl_addr_hit_read[49]: begin reg_rdata_next[31:2] = range_base_9_qs; end - racl_addr_hit_read[49]: begin + racl_addr_hit_read[50]: begin reg_rdata_next[31:2] = range_base_10_qs; end - racl_addr_hit_read[50]: begin + racl_addr_hit_read[51]: begin reg_rdata_next[31:2] = range_base_11_qs; end - racl_addr_hit_read[51]: begin + racl_addr_hit_read[52]: begin reg_rdata_next[31:2] = range_base_12_qs; end - racl_addr_hit_read[52]: begin + racl_addr_hit_read[53]: begin reg_rdata_next[31:2] = range_base_13_qs; end - racl_addr_hit_read[53]: begin + racl_addr_hit_read[54]: begin reg_rdata_next[31:2] = range_base_14_qs; end - racl_addr_hit_read[54]: begin + racl_addr_hit_read[55]: begin reg_rdata_next[31:2] = range_base_15_qs; end - racl_addr_hit_read[55]: begin + racl_addr_hit_read[56]: begin reg_rdata_next[31:2] = range_base_16_qs; end - racl_addr_hit_read[56]: begin + racl_addr_hit_read[57]: begin reg_rdata_next[31:2] = range_base_17_qs; end - racl_addr_hit_read[57]: begin + racl_addr_hit_read[58]: begin reg_rdata_next[31:2] = range_base_18_qs; end - racl_addr_hit_read[58]: begin + racl_addr_hit_read[59]: begin reg_rdata_next[31:2] = range_base_19_qs; end - racl_addr_hit_read[59]: begin + racl_addr_hit_read[60]: begin reg_rdata_next[31:2] = range_base_20_qs; end - racl_addr_hit_read[60]: begin + racl_addr_hit_read[61]: begin reg_rdata_next[31:2] = range_base_21_qs; end - racl_addr_hit_read[61]: begin + racl_addr_hit_read[62]: begin reg_rdata_next[31:2] = range_base_22_qs; end - racl_addr_hit_read[62]: begin + racl_addr_hit_read[63]: begin reg_rdata_next[31:2] = range_base_23_qs; end - racl_addr_hit_read[63]: begin + racl_addr_hit_read[64]: begin reg_rdata_next[31:2] = range_base_24_qs; end - racl_addr_hit_read[64]: begin + racl_addr_hit_read[65]: begin reg_rdata_next[31:2] = range_base_25_qs; end - racl_addr_hit_read[65]: begin + racl_addr_hit_read[66]: begin reg_rdata_next[31:2] = range_base_26_qs; end - racl_addr_hit_read[66]: begin + racl_addr_hit_read[67]: begin reg_rdata_next[31:2] = range_base_27_qs; end - racl_addr_hit_read[67]: begin + racl_addr_hit_read[68]: begin reg_rdata_next[31:2] = range_base_28_qs; end - racl_addr_hit_read[68]: begin + racl_addr_hit_read[69]: begin reg_rdata_next[31:2] = range_base_29_qs; end - racl_addr_hit_read[69]: begin + racl_addr_hit_read[70]: begin reg_rdata_next[31:2] = range_base_30_qs; end - racl_addr_hit_read[70]: begin + racl_addr_hit_read[71]: begin reg_rdata_next[31:2] = range_base_31_qs; end - racl_addr_hit_read[71]: begin + racl_addr_hit_read[72]: begin reg_rdata_next[31:2] = range_limit_0_qs; end - racl_addr_hit_read[72]: begin + racl_addr_hit_read[73]: begin reg_rdata_next[31:2] = range_limit_1_qs; end - racl_addr_hit_read[73]: begin + racl_addr_hit_read[74]: begin reg_rdata_next[31:2] = range_limit_2_qs; end - racl_addr_hit_read[74]: begin + racl_addr_hit_read[75]: begin reg_rdata_next[31:2] = range_limit_3_qs; end - racl_addr_hit_read[75]: begin + racl_addr_hit_read[76]: begin reg_rdata_next[31:2] = range_limit_4_qs; end - racl_addr_hit_read[76]: begin + racl_addr_hit_read[77]: begin reg_rdata_next[31:2] = range_limit_5_qs; end - racl_addr_hit_read[77]: begin + racl_addr_hit_read[78]: begin reg_rdata_next[31:2] = range_limit_6_qs; end - racl_addr_hit_read[78]: begin + racl_addr_hit_read[79]: begin reg_rdata_next[31:2] = range_limit_7_qs; end - racl_addr_hit_read[79]: begin + racl_addr_hit_read[80]: begin reg_rdata_next[31:2] = range_limit_8_qs; end - racl_addr_hit_read[80]: begin + racl_addr_hit_read[81]: begin reg_rdata_next[31:2] = range_limit_9_qs; end - racl_addr_hit_read[81]: begin + racl_addr_hit_read[82]: begin reg_rdata_next[31:2] = range_limit_10_qs; end - racl_addr_hit_read[82]: begin + racl_addr_hit_read[83]: begin reg_rdata_next[31:2] = range_limit_11_qs; end - racl_addr_hit_read[83]: begin + racl_addr_hit_read[84]: begin reg_rdata_next[31:2] = range_limit_12_qs; end - racl_addr_hit_read[84]: begin + racl_addr_hit_read[85]: begin reg_rdata_next[31:2] = range_limit_13_qs; end - racl_addr_hit_read[85]: begin + racl_addr_hit_read[86]: begin reg_rdata_next[31:2] = range_limit_14_qs; end - racl_addr_hit_read[86]: begin + racl_addr_hit_read[87]: begin reg_rdata_next[31:2] = range_limit_15_qs; end - racl_addr_hit_read[87]: begin + racl_addr_hit_read[88]: begin reg_rdata_next[31:2] = range_limit_16_qs; end - racl_addr_hit_read[88]: begin + racl_addr_hit_read[89]: begin reg_rdata_next[31:2] = range_limit_17_qs; end - racl_addr_hit_read[89]: begin + racl_addr_hit_read[90]: begin reg_rdata_next[31:2] = range_limit_18_qs; end - racl_addr_hit_read[90]: begin + racl_addr_hit_read[91]: begin reg_rdata_next[31:2] = range_limit_19_qs; end - racl_addr_hit_read[91]: begin + racl_addr_hit_read[92]: begin reg_rdata_next[31:2] = range_limit_20_qs; end - racl_addr_hit_read[92]: begin + racl_addr_hit_read[93]: begin reg_rdata_next[31:2] = range_limit_21_qs; end - racl_addr_hit_read[93]: begin + racl_addr_hit_read[94]: begin reg_rdata_next[31:2] = range_limit_22_qs; end - racl_addr_hit_read[94]: begin + racl_addr_hit_read[95]: begin reg_rdata_next[31:2] = range_limit_23_qs; end - racl_addr_hit_read[95]: begin + racl_addr_hit_read[96]: begin reg_rdata_next[31:2] = range_limit_24_qs; end - racl_addr_hit_read[96]: begin + racl_addr_hit_read[97]: begin reg_rdata_next[31:2] = range_limit_25_qs; end - racl_addr_hit_read[97]: begin + racl_addr_hit_read[98]: begin reg_rdata_next[31:2] = range_limit_26_qs; end - racl_addr_hit_read[98]: begin + racl_addr_hit_read[99]: begin reg_rdata_next[31:2] = range_limit_27_qs; end - racl_addr_hit_read[99]: begin + racl_addr_hit_read[100]: begin reg_rdata_next[31:2] = range_limit_28_qs; end - racl_addr_hit_read[100]: begin + racl_addr_hit_read[101]: begin reg_rdata_next[31:2] = range_limit_29_qs; end - racl_addr_hit_read[101]: begin + racl_addr_hit_read[102]: begin reg_rdata_next[31:2] = range_limit_30_qs; end - racl_addr_hit_read[102]: begin + racl_addr_hit_read[103]: begin reg_rdata_next[31:2] = range_limit_31_qs; end - racl_addr_hit_read[103]: begin + racl_addr_hit_read[104]: begin reg_rdata_next[3:0] = range_perm_0_enable_0_qs; reg_rdata_next[7:4] = range_perm_0_read_access_0_qs; reg_rdata_next[11:8] = range_perm_0_write_access_0_qs; @@ -13736,7 +13865,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_0_log_denied_access_0_qs; end - racl_addr_hit_read[104]: begin + racl_addr_hit_read[105]: begin reg_rdata_next[3:0] = range_perm_1_enable_1_qs; reg_rdata_next[7:4] = range_perm_1_read_access_1_qs; reg_rdata_next[11:8] = range_perm_1_write_access_1_qs; @@ -13744,7 +13873,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_1_log_denied_access_1_qs; end - racl_addr_hit_read[105]: begin + racl_addr_hit_read[106]: begin reg_rdata_next[3:0] = range_perm_2_enable_2_qs; reg_rdata_next[7:4] = range_perm_2_read_access_2_qs; reg_rdata_next[11:8] = range_perm_2_write_access_2_qs; @@ -13752,7 +13881,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_2_log_denied_access_2_qs; end - racl_addr_hit_read[106]: begin + racl_addr_hit_read[107]: begin reg_rdata_next[3:0] = range_perm_3_enable_3_qs; reg_rdata_next[7:4] = range_perm_3_read_access_3_qs; reg_rdata_next[11:8] = range_perm_3_write_access_3_qs; @@ -13760,7 +13889,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_3_log_denied_access_3_qs; end - racl_addr_hit_read[107]: begin + racl_addr_hit_read[108]: begin reg_rdata_next[3:0] = range_perm_4_enable_4_qs; reg_rdata_next[7:4] = range_perm_4_read_access_4_qs; reg_rdata_next[11:8] = range_perm_4_write_access_4_qs; @@ -13768,7 +13897,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_4_log_denied_access_4_qs; end - racl_addr_hit_read[108]: begin + racl_addr_hit_read[109]: begin reg_rdata_next[3:0] = range_perm_5_enable_5_qs; reg_rdata_next[7:4] = range_perm_5_read_access_5_qs; reg_rdata_next[11:8] = range_perm_5_write_access_5_qs; @@ -13776,7 +13905,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_5_log_denied_access_5_qs; end - racl_addr_hit_read[109]: begin + racl_addr_hit_read[110]: begin reg_rdata_next[3:0] = range_perm_6_enable_6_qs; reg_rdata_next[7:4] = range_perm_6_read_access_6_qs; reg_rdata_next[11:8] = range_perm_6_write_access_6_qs; @@ -13784,7 +13913,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_6_log_denied_access_6_qs; end - racl_addr_hit_read[110]: begin + racl_addr_hit_read[111]: begin reg_rdata_next[3:0] = range_perm_7_enable_7_qs; reg_rdata_next[7:4] = range_perm_7_read_access_7_qs; reg_rdata_next[11:8] = range_perm_7_write_access_7_qs; @@ -13792,7 +13921,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_7_log_denied_access_7_qs; end - racl_addr_hit_read[111]: begin + racl_addr_hit_read[112]: begin reg_rdata_next[3:0] = range_perm_8_enable_8_qs; reg_rdata_next[7:4] = range_perm_8_read_access_8_qs; reg_rdata_next[11:8] = range_perm_8_write_access_8_qs; @@ -13800,7 +13929,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_8_log_denied_access_8_qs; end - racl_addr_hit_read[112]: begin + racl_addr_hit_read[113]: begin reg_rdata_next[3:0] = range_perm_9_enable_9_qs; reg_rdata_next[7:4] = range_perm_9_read_access_9_qs; reg_rdata_next[11:8] = range_perm_9_write_access_9_qs; @@ -13808,7 +13937,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_9_log_denied_access_9_qs; end - racl_addr_hit_read[113]: begin + racl_addr_hit_read[114]: begin reg_rdata_next[3:0] = range_perm_10_enable_10_qs; reg_rdata_next[7:4] = range_perm_10_read_access_10_qs; reg_rdata_next[11:8] = range_perm_10_write_access_10_qs; @@ -13816,7 +13945,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_10_log_denied_access_10_qs; end - racl_addr_hit_read[114]: begin + racl_addr_hit_read[115]: begin reg_rdata_next[3:0] = range_perm_11_enable_11_qs; reg_rdata_next[7:4] = range_perm_11_read_access_11_qs; reg_rdata_next[11:8] = range_perm_11_write_access_11_qs; @@ -13824,7 +13953,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_11_log_denied_access_11_qs; end - racl_addr_hit_read[115]: begin + racl_addr_hit_read[116]: begin reg_rdata_next[3:0] = range_perm_12_enable_12_qs; reg_rdata_next[7:4] = range_perm_12_read_access_12_qs; reg_rdata_next[11:8] = range_perm_12_write_access_12_qs; @@ -13832,7 +13961,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_12_log_denied_access_12_qs; end - racl_addr_hit_read[116]: begin + racl_addr_hit_read[117]: begin reg_rdata_next[3:0] = range_perm_13_enable_13_qs; reg_rdata_next[7:4] = range_perm_13_read_access_13_qs; reg_rdata_next[11:8] = range_perm_13_write_access_13_qs; @@ -13840,7 +13969,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_13_log_denied_access_13_qs; end - racl_addr_hit_read[117]: begin + racl_addr_hit_read[118]: begin reg_rdata_next[3:0] = range_perm_14_enable_14_qs; reg_rdata_next[7:4] = range_perm_14_read_access_14_qs; reg_rdata_next[11:8] = range_perm_14_write_access_14_qs; @@ -13848,7 +13977,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_14_log_denied_access_14_qs; end - racl_addr_hit_read[118]: begin + racl_addr_hit_read[119]: begin reg_rdata_next[3:0] = range_perm_15_enable_15_qs; reg_rdata_next[7:4] = range_perm_15_read_access_15_qs; reg_rdata_next[11:8] = range_perm_15_write_access_15_qs; @@ -13856,7 +13985,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_15_log_denied_access_15_qs; end - racl_addr_hit_read[119]: begin + racl_addr_hit_read[120]: begin reg_rdata_next[3:0] = range_perm_16_enable_16_qs; reg_rdata_next[7:4] = range_perm_16_read_access_16_qs; reg_rdata_next[11:8] = range_perm_16_write_access_16_qs; @@ -13864,7 +13993,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_16_log_denied_access_16_qs; end - racl_addr_hit_read[120]: begin + racl_addr_hit_read[121]: begin reg_rdata_next[3:0] = range_perm_17_enable_17_qs; reg_rdata_next[7:4] = range_perm_17_read_access_17_qs; reg_rdata_next[11:8] = range_perm_17_write_access_17_qs; @@ -13872,7 +14001,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_17_log_denied_access_17_qs; end - racl_addr_hit_read[121]: begin + racl_addr_hit_read[122]: begin reg_rdata_next[3:0] = range_perm_18_enable_18_qs; reg_rdata_next[7:4] = range_perm_18_read_access_18_qs; reg_rdata_next[11:8] = range_perm_18_write_access_18_qs; @@ -13880,7 +14009,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_18_log_denied_access_18_qs; end - racl_addr_hit_read[122]: begin + racl_addr_hit_read[123]: begin reg_rdata_next[3:0] = range_perm_19_enable_19_qs; reg_rdata_next[7:4] = range_perm_19_read_access_19_qs; reg_rdata_next[11:8] = range_perm_19_write_access_19_qs; @@ -13888,7 +14017,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_19_log_denied_access_19_qs; end - racl_addr_hit_read[123]: begin + racl_addr_hit_read[124]: begin reg_rdata_next[3:0] = range_perm_20_enable_20_qs; reg_rdata_next[7:4] = range_perm_20_read_access_20_qs; reg_rdata_next[11:8] = range_perm_20_write_access_20_qs; @@ -13896,7 +14025,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_20_log_denied_access_20_qs; end - racl_addr_hit_read[124]: begin + racl_addr_hit_read[125]: begin reg_rdata_next[3:0] = range_perm_21_enable_21_qs; reg_rdata_next[7:4] = range_perm_21_read_access_21_qs; reg_rdata_next[11:8] = range_perm_21_write_access_21_qs; @@ -13904,7 +14033,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_21_log_denied_access_21_qs; end - racl_addr_hit_read[125]: begin + racl_addr_hit_read[126]: begin reg_rdata_next[3:0] = range_perm_22_enable_22_qs; reg_rdata_next[7:4] = range_perm_22_read_access_22_qs; reg_rdata_next[11:8] = range_perm_22_write_access_22_qs; @@ -13912,7 +14041,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_22_log_denied_access_22_qs; end - racl_addr_hit_read[126]: begin + racl_addr_hit_read[127]: begin reg_rdata_next[3:0] = range_perm_23_enable_23_qs; reg_rdata_next[7:4] = range_perm_23_read_access_23_qs; reg_rdata_next[11:8] = range_perm_23_write_access_23_qs; @@ -13920,7 +14049,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_23_log_denied_access_23_qs; end - racl_addr_hit_read[127]: begin + racl_addr_hit_read[128]: begin reg_rdata_next[3:0] = range_perm_24_enable_24_qs; reg_rdata_next[7:4] = range_perm_24_read_access_24_qs; reg_rdata_next[11:8] = range_perm_24_write_access_24_qs; @@ -13928,7 +14057,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_24_log_denied_access_24_qs; end - racl_addr_hit_read[128]: begin + racl_addr_hit_read[129]: begin reg_rdata_next[3:0] = range_perm_25_enable_25_qs; reg_rdata_next[7:4] = range_perm_25_read_access_25_qs; reg_rdata_next[11:8] = range_perm_25_write_access_25_qs; @@ -13936,7 +14065,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_25_log_denied_access_25_qs; end - racl_addr_hit_read[129]: begin + racl_addr_hit_read[130]: begin reg_rdata_next[3:0] = range_perm_26_enable_26_qs; reg_rdata_next[7:4] = range_perm_26_read_access_26_qs; reg_rdata_next[11:8] = range_perm_26_write_access_26_qs; @@ -13944,7 +14073,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_26_log_denied_access_26_qs; end - racl_addr_hit_read[130]: begin + racl_addr_hit_read[131]: begin reg_rdata_next[3:0] = range_perm_27_enable_27_qs; reg_rdata_next[7:4] = range_perm_27_read_access_27_qs; reg_rdata_next[11:8] = range_perm_27_write_access_27_qs; @@ -13952,7 +14081,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_27_log_denied_access_27_qs; end - racl_addr_hit_read[131]: begin + racl_addr_hit_read[132]: begin reg_rdata_next[3:0] = range_perm_28_enable_28_qs; reg_rdata_next[7:4] = range_perm_28_read_access_28_qs; reg_rdata_next[11:8] = range_perm_28_write_access_28_qs; @@ -13960,7 +14089,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_28_log_denied_access_28_qs; end - racl_addr_hit_read[132]: begin + racl_addr_hit_read[133]: begin reg_rdata_next[3:0] = range_perm_29_enable_29_qs; reg_rdata_next[7:4] = range_perm_29_read_access_29_qs; reg_rdata_next[11:8] = range_perm_29_write_access_29_qs; @@ -13968,7 +14097,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_29_log_denied_access_29_qs; end - racl_addr_hit_read[133]: begin + racl_addr_hit_read[134]: begin reg_rdata_next[3:0] = range_perm_30_enable_30_qs; reg_rdata_next[7:4] = range_perm_30_read_access_30_qs; reg_rdata_next[11:8] = range_perm_30_write_access_30_qs; @@ -13976,7 +14105,7 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_30_log_denied_access_30_qs; end - racl_addr_hit_read[134]: begin + racl_addr_hit_read[135]: begin reg_rdata_next[3:0] = range_perm_31_enable_31_qs; reg_rdata_next[7:4] = range_perm_31_read_access_31_qs; reg_rdata_next[11:8] = range_perm_31_write_access_31_qs; @@ -13984,162 +14113,162 @@ module ac_range_check_reg_top reg_rdata_next[19:16] = range_perm_31_log_denied_access_31_qs; end - racl_addr_hit_read[135]: begin + racl_addr_hit_read[136]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_0_read_perm_0_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_0_write_perm_0_qs; end - racl_addr_hit_read[136]: begin + racl_addr_hit_read[137]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_1_read_perm_1_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_1_write_perm_1_qs; end - racl_addr_hit_read[137]: begin + racl_addr_hit_read[138]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_2_read_perm_2_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_2_write_perm_2_qs; end - racl_addr_hit_read[138]: begin + racl_addr_hit_read[139]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_3_read_perm_3_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_3_write_perm_3_qs; end - racl_addr_hit_read[139]: begin + racl_addr_hit_read[140]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_4_read_perm_4_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_4_write_perm_4_qs; end - racl_addr_hit_read[140]: begin + racl_addr_hit_read[141]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_5_read_perm_5_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_5_write_perm_5_qs; end - racl_addr_hit_read[141]: begin + racl_addr_hit_read[142]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_6_read_perm_6_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_6_write_perm_6_qs; end - racl_addr_hit_read[142]: begin + racl_addr_hit_read[143]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_7_read_perm_7_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_7_write_perm_7_qs; end - racl_addr_hit_read[143]: begin + racl_addr_hit_read[144]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_8_read_perm_8_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_8_write_perm_8_qs; end - racl_addr_hit_read[144]: begin + racl_addr_hit_read[145]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_9_read_perm_9_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_9_write_perm_9_qs; end - racl_addr_hit_read[145]: begin + racl_addr_hit_read[146]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_10_read_perm_10_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_10_write_perm_10_qs; end - racl_addr_hit_read[146]: begin + racl_addr_hit_read[147]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_11_read_perm_11_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_11_write_perm_11_qs; end - racl_addr_hit_read[147]: begin + racl_addr_hit_read[148]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_12_read_perm_12_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_12_write_perm_12_qs; end - racl_addr_hit_read[148]: begin + racl_addr_hit_read[149]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_13_read_perm_13_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_13_write_perm_13_qs; end - racl_addr_hit_read[149]: begin + racl_addr_hit_read[150]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_14_read_perm_14_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_14_write_perm_14_qs; end - racl_addr_hit_read[150]: begin + racl_addr_hit_read[151]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_15_read_perm_15_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_15_write_perm_15_qs; end - racl_addr_hit_read[151]: begin + racl_addr_hit_read[152]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_16_read_perm_16_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_16_write_perm_16_qs; end - racl_addr_hit_read[152]: begin + racl_addr_hit_read[153]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_17_read_perm_17_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_17_write_perm_17_qs; end - racl_addr_hit_read[153]: begin + racl_addr_hit_read[154]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_18_read_perm_18_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_18_write_perm_18_qs; end - racl_addr_hit_read[154]: begin + racl_addr_hit_read[155]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_19_read_perm_19_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_19_write_perm_19_qs; end - racl_addr_hit_read[155]: begin + racl_addr_hit_read[156]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_20_read_perm_20_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_20_write_perm_20_qs; end - racl_addr_hit_read[156]: begin + racl_addr_hit_read[157]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_21_read_perm_21_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_21_write_perm_21_qs; end - racl_addr_hit_read[157]: begin + racl_addr_hit_read[158]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_22_read_perm_22_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_22_write_perm_22_qs; end - racl_addr_hit_read[158]: begin + racl_addr_hit_read[159]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_23_read_perm_23_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_23_write_perm_23_qs; end - racl_addr_hit_read[159]: begin + racl_addr_hit_read[160]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_24_read_perm_24_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_24_write_perm_24_qs; end - racl_addr_hit_read[160]: begin + racl_addr_hit_read[161]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_25_read_perm_25_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_25_write_perm_25_qs; end - racl_addr_hit_read[161]: begin + racl_addr_hit_read[162]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_26_read_perm_26_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_26_write_perm_26_qs; end - racl_addr_hit_read[162]: begin + racl_addr_hit_read[163]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_27_read_perm_27_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_27_write_perm_27_qs; end - racl_addr_hit_read[163]: begin + racl_addr_hit_read[164]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_28_read_perm_28_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_28_write_perm_28_qs; end - racl_addr_hit_read[164]: begin + racl_addr_hit_read[165]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_29_read_perm_29_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_29_write_perm_29_qs; end - racl_addr_hit_read[165]: begin + racl_addr_hit_read[166]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_30_read_perm_30_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_30_write_perm_30_qs; end - racl_addr_hit_read[166]: begin + racl_addr_hit_read[167]: begin reg_rdata_next[15:0] = range_racl_policy_shadowed_31_read_perm_31_qs; reg_rdata_next[31:16] = range_racl_policy_shadowed_31_write_perm_31_qs; end diff --git a/hw/top_darjeeling/ip_autogen/racl_ctrl/doc/racl_configuration.md b/hw/top_darjeeling/ip_autogen/racl_ctrl/doc/racl_configuration.md index 5a32cdcf05edf..dce2842c49f5e 100644 --- a/hw/top_darjeeling/ip_autogen/racl_ctrl/doc/racl_configuration.md +++ b/hw/top_darjeeling/ip_autogen/racl_ctrl/doc/racl_configuration.md @@ -155,169 +155,170 @@ | ac_range_check.`INTR_ENABLE` | 0x4 | 0x1464004 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | | ac_range_check.`INTR_TEST` | 0x8 | 0x1464008 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | | ac_range_check.`ALERT_TEST` | 0xc | 0x146400c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`LOG_CONFIG` | 0x10 | 0x1464010 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`LOG_STATUS` | 0x14 | 0x1464014 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`LOG_ADDRESS` | 0x18 | 0x1464018 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_0` | 0x1c | 0x146401c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_1` | 0x20 | 0x1464020 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_2` | 0x24 | 0x1464024 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_3` | 0x28 | 0x1464028 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_4` | 0x2c | 0x146402c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_5` | 0x30 | 0x1464030 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_6` | 0x34 | 0x1464034 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_7` | 0x38 | 0x1464038 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_8` | 0x3c | 0x146403c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_9` | 0x40 | 0x1464040 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_10` | 0x44 | 0x1464044 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_11` | 0x48 | 0x1464048 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_12` | 0x4c | 0x146404c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_13` | 0x50 | 0x1464050 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_14` | 0x54 | 0x1464054 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_15` | 0x58 | 0x1464058 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_16` | 0x5c | 0x146405c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_17` | 0x60 | 0x1464060 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_18` | 0x64 | 0x1464064 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_19` | 0x68 | 0x1464068 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_20` | 0x6c | 0x146406c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_21` | 0x70 | 0x1464070 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_22` | 0x74 | 0x1464074 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_23` | 0x78 | 0x1464078 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_24` | 0x7c | 0x146407c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_25` | 0x80 | 0x1464080 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_26` | 0x84 | 0x1464084 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_27` | 0x88 | 0x1464088 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_28` | 0x8c | 0x146408c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_29` | 0x90 | 0x1464090 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_30` | 0x94 | 0x1464094 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_REGWEN_31` | 0x98 | 0x1464098 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_0` | 0x9c | 0x146409c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_1` | 0xa0 | 0x14640a0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_2` | 0xa4 | 0x14640a4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_3` | 0xa8 | 0x14640a8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_4` | 0xac | 0x14640ac | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_5` | 0xb0 | 0x14640b0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_6` | 0xb4 | 0x14640b4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_7` | 0xb8 | 0x14640b8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_8` | 0xbc | 0x14640bc | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_9` | 0xc0 | 0x14640c0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_10` | 0xc4 | 0x14640c4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_11` | 0xc8 | 0x14640c8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_12` | 0xcc | 0x14640cc | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_13` | 0xd0 | 0x14640d0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_14` | 0xd4 | 0x14640d4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_15` | 0xd8 | 0x14640d8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_16` | 0xdc | 0x14640dc | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_17` | 0xe0 | 0x14640e0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_18` | 0xe4 | 0x14640e4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_19` | 0xe8 | 0x14640e8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_20` | 0xec | 0x14640ec | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_21` | 0xf0 | 0x14640f0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_22` | 0xf4 | 0x14640f4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_23` | 0xf8 | 0x14640f8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_24` | 0xfc | 0x14640fc | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_25` | 0x100 | 0x1464100 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_26` | 0x104 | 0x1464104 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_27` | 0x108 | 0x1464108 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_28` | 0x10c | 0x146410c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_29` | 0x110 | 0x1464110 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_30` | 0x114 | 0x1464114 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_BASE_31` | 0x118 | 0x1464118 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_0` | 0x11c | 0x146411c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_1` | 0x120 | 0x1464120 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_2` | 0x124 | 0x1464124 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_3` | 0x128 | 0x1464128 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_4` | 0x12c | 0x146412c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_5` | 0x130 | 0x1464130 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_6` | 0x134 | 0x1464134 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_7` | 0x138 | 0x1464138 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_8` | 0x13c | 0x146413c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_9` | 0x140 | 0x1464140 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_10` | 0x144 | 0x1464144 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_11` | 0x148 | 0x1464148 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_12` | 0x14c | 0x146414c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_13` | 0x150 | 0x1464150 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_14` | 0x154 | 0x1464154 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_15` | 0x158 | 0x1464158 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_16` | 0x15c | 0x146415c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_17` | 0x160 | 0x1464160 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_18` | 0x164 | 0x1464164 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_19` | 0x168 | 0x1464168 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_20` | 0x16c | 0x146416c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_21` | 0x170 | 0x1464170 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_22` | 0x174 | 0x1464174 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_23` | 0x178 | 0x1464178 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_24` | 0x17c | 0x146417c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_25` | 0x180 | 0x1464180 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_26` | 0x184 | 0x1464184 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_27` | 0x188 | 0x1464188 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_28` | 0x18c | 0x146418c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_29` | 0x190 | 0x1464190 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_30` | 0x194 | 0x1464194 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_LIMIT_31` | 0x198 | 0x1464198 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_0` | 0x19c | 0x146419c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_1` | 0x1a0 | 0x14641a0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_2` | 0x1a4 | 0x14641a4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_3` | 0x1a8 | 0x14641a8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_4` | 0x1ac | 0x14641ac | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_5` | 0x1b0 | 0x14641b0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_6` | 0x1b4 | 0x14641b4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_7` | 0x1b8 | 0x14641b8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_8` | 0x1bc | 0x14641bc | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_9` | 0x1c0 | 0x14641c0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_10` | 0x1c4 | 0x14641c4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_11` | 0x1c8 | 0x14641c8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_12` | 0x1cc | 0x14641cc | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_13` | 0x1d0 | 0x14641d0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_14` | 0x1d4 | 0x14641d4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_15` | 0x1d8 | 0x14641d8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_16` | 0x1dc | 0x14641dc | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_17` | 0x1e0 | 0x14641e0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_18` | 0x1e4 | 0x14641e4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_19` | 0x1e8 | 0x14641e8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_20` | 0x1ec | 0x14641ec | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_21` | 0x1f0 | 0x14641f0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_22` | 0x1f4 | 0x14641f4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_23` | 0x1f8 | 0x14641f8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_24` | 0x1fc | 0x14641fc | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_25` | 0x200 | 0x1464200 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_26` | 0x204 | 0x1464204 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_27` | 0x208 | 0x1464208 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_28` | 0x20c | 0x146420c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_29` | 0x210 | 0x1464210 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_30` | 0x214 | 0x1464214 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_PERM_31` | 0x218 | 0x1464218 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_0` | 0x21c | 0x146421c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_1` | 0x220 | 0x1464220 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_2` | 0x224 | 0x1464224 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_3` | 0x228 | 0x1464228 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_4` | 0x22c | 0x146422c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_5` | 0x230 | 0x1464230 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_6` | 0x234 | 0x1464234 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_7` | 0x238 | 0x1464238 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_8` | 0x23c | 0x146423c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_9` | 0x240 | 0x1464240 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_10` | 0x244 | 0x1464244 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_11` | 0x248 | 0x1464248 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_12` | 0x24c | 0x146424c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_13` | 0x250 | 0x1464250 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_14` | 0x254 | 0x1464254 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_15` | 0x258 | 0x1464258 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_16` | 0x25c | 0x146425c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_17` | 0x260 | 0x1464260 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_18` | 0x264 | 0x1464264 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_19` | 0x268 | 0x1464268 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_20` | 0x26c | 0x146426c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_21` | 0x270 | 0x1464270 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_22` | 0x274 | 0x1464274 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_23` | 0x278 | 0x1464278 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_24` | 0x27c | 0x146427c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_25` | 0x280 | 0x1464280 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_26` | 0x284 | 0x1464284 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_27` | 0x288 | 0x1464288 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_28` | 0x28c | 0x146428c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_29` | 0x290 | 0x1464290 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_30` | 0x294 | 0x1464294 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | -| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_31` | 0x298 | 0x1464298 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`ALERT_STATUS` | 0x10 | 0x1464010 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`LOG_CONFIG` | 0x14 | 0x1464014 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`LOG_STATUS` | 0x18 | 0x1464018 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`LOG_ADDRESS` | 0x1c | 0x146401c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_0` | 0x20 | 0x1464020 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_1` | 0x24 | 0x1464024 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_2` | 0x28 | 0x1464028 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_3` | 0x2c | 0x146402c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_4` | 0x30 | 0x1464030 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_5` | 0x34 | 0x1464034 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_6` | 0x38 | 0x1464038 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_7` | 0x3c | 0x146403c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_8` | 0x40 | 0x1464040 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_9` | 0x44 | 0x1464044 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_10` | 0x48 | 0x1464048 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_11` | 0x4c | 0x146404c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_12` | 0x50 | 0x1464050 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_13` | 0x54 | 0x1464054 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_14` | 0x58 | 0x1464058 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_15` | 0x5c | 0x146405c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_16` | 0x60 | 0x1464060 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_17` | 0x64 | 0x1464064 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_18` | 0x68 | 0x1464068 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_19` | 0x6c | 0x146406c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_20` | 0x70 | 0x1464070 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_21` | 0x74 | 0x1464074 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_22` | 0x78 | 0x1464078 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_23` | 0x7c | 0x146407c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_24` | 0x80 | 0x1464080 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_25` | 0x84 | 0x1464084 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_26` | 0x88 | 0x1464088 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_27` | 0x8c | 0x146408c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_28` | 0x90 | 0x1464090 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_29` | 0x94 | 0x1464094 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_30` | 0x98 | 0x1464098 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_31` | 0x9c | 0x146409c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_0` | 0xa0 | 0x14640a0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_1` | 0xa4 | 0x14640a4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_2` | 0xa8 | 0x14640a8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_3` | 0xac | 0x14640ac | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_4` | 0xb0 | 0x14640b0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_5` | 0xb4 | 0x14640b4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_6` | 0xb8 | 0x14640b8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_7` | 0xbc | 0x14640bc | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_8` | 0xc0 | 0x14640c0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_9` | 0xc4 | 0x14640c4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_10` | 0xc8 | 0x14640c8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_11` | 0xcc | 0x14640cc | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_12` | 0xd0 | 0x14640d0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_13` | 0xd4 | 0x14640d4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_14` | 0xd8 | 0x14640d8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_15` | 0xdc | 0x14640dc | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_16` | 0xe0 | 0x14640e0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_17` | 0xe4 | 0x14640e4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_18` | 0xe8 | 0x14640e8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_19` | 0xec | 0x14640ec | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_20` | 0xf0 | 0x14640f0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_21` | 0xf4 | 0x14640f4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_22` | 0xf8 | 0x14640f8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_23` | 0xfc | 0x14640fc | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_24` | 0x100 | 0x1464100 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_25` | 0x104 | 0x1464104 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_26` | 0x108 | 0x1464108 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_27` | 0x10c | 0x146410c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_28` | 0x110 | 0x1464110 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_29` | 0x114 | 0x1464114 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_30` | 0x118 | 0x1464118 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_31` | 0x11c | 0x146411c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_0` | 0x120 | 0x1464120 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_1` | 0x124 | 0x1464124 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_2` | 0x128 | 0x1464128 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_3` | 0x12c | 0x146412c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_4` | 0x130 | 0x1464130 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_5` | 0x134 | 0x1464134 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_6` | 0x138 | 0x1464138 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_7` | 0x13c | 0x146413c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_8` | 0x140 | 0x1464140 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_9` | 0x144 | 0x1464144 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_10` | 0x148 | 0x1464148 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_11` | 0x14c | 0x146414c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_12` | 0x150 | 0x1464150 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_13` | 0x154 | 0x1464154 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_14` | 0x158 | 0x1464158 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_15` | 0x15c | 0x146415c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_16` | 0x160 | 0x1464160 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_17` | 0x164 | 0x1464164 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_18` | 0x168 | 0x1464168 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_19` | 0x16c | 0x146416c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_20` | 0x170 | 0x1464170 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_21` | 0x174 | 0x1464174 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_22` | 0x178 | 0x1464178 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_23` | 0x17c | 0x146417c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_24` | 0x180 | 0x1464180 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_25` | 0x184 | 0x1464184 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_26` | 0x188 | 0x1464188 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_27` | 0x18c | 0x146418c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_28` | 0x190 | 0x1464190 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_29` | 0x194 | 0x1464194 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_30` | 0x198 | 0x1464198 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_31` | 0x19c | 0x146419c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_0` | 0x1a0 | 0x14641a0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_1` | 0x1a4 | 0x14641a4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_2` | 0x1a8 | 0x14641a8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_3` | 0x1ac | 0x14641ac | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_4` | 0x1b0 | 0x14641b0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_5` | 0x1b4 | 0x14641b4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_6` | 0x1b8 | 0x14641b8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_7` | 0x1bc | 0x14641bc | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_8` | 0x1c0 | 0x14641c0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_9` | 0x1c4 | 0x14641c4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_10` | 0x1c8 | 0x14641c8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_11` | 0x1cc | 0x14641cc | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_12` | 0x1d0 | 0x14641d0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_13` | 0x1d4 | 0x14641d4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_14` | 0x1d8 | 0x14641d8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_15` | 0x1dc | 0x14641dc | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_16` | 0x1e0 | 0x14641e0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_17` | 0x1e4 | 0x14641e4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_18` | 0x1e8 | 0x14641e8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_19` | 0x1ec | 0x14641ec | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_20` | 0x1f0 | 0x14641f0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_21` | 0x1f4 | 0x14641f4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_22` | 0x1f8 | 0x14641f8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_23` | 0x1fc | 0x14641fc | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_24` | 0x200 | 0x1464200 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_25` | 0x204 | 0x1464204 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_26` | 0x208 | 0x1464208 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_27` | 0x20c | 0x146420c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_28` | 0x210 | 0x1464210 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_29` | 0x214 | 0x1464214 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_30` | 0x218 | 0x1464218 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_PERM_31` | 0x21c | 0x146421c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_0` | 0x220 | 0x1464220 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_1` | 0x224 | 0x1464224 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_2` | 0x228 | 0x1464228 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_3` | 0x22c | 0x146422c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_4` | 0x230 | 0x1464230 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_5` | 0x234 | 0x1464234 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_6` | 0x238 | 0x1464238 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_7` | 0x23c | 0x146423c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_8` | 0x240 | 0x1464240 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_9` | 0x244 | 0x1464244 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_10` | 0x248 | 0x1464248 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_11` | 0x24c | 0x146424c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_12` | 0x250 | 0x1464250 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_13` | 0x254 | 0x1464254 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_14` | 0x258 | 0x1464258 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_15` | 0x25c | 0x146425c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_16` | 0x260 | 0x1464260 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_17` | 0x264 | 0x1464264 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_18` | 0x268 | 0x1464268 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_19` | 0x26c | 0x146426c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_20` | 0x270 | 0x1464270 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_21` | 0x274 | 0x1464274 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_22` | 0x278 | 0x1464278 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_23` | 0x27c | 0x146427c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_24` | 0x280 | 0x1464280 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_25` | 0x284 | 0x1464284 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_26` | 0x288 | 0x1464288 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_27` | 0x28c | 0x146428c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_28` | 0x290 | 0x1464290 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_29` | 0x294 | 0x1464294 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_30` | 0x298 | 0x1464298 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_31` | 0x29c | 0x146429c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | diff --git a/hw/top_darjeeling/rtl/autogen/top_darjeeling_racl_pkg.sv b/hw/top_darjeeling/rtl/autogen/top_darjeeling_racl_pkg.sv index a48059969b4d3..0f526f965e4a1 100644 --- a/hw/top_darjeeling/rtl/autogen/top_darjeeling_racl_pkg.sv +++ b/hw/top_darjeeling/rtl/autogen/top_darjeeling_racl_pkg.sv @@ -183,6 +183,7 @@ package top_darjeeling_racl_pkg; * INTR_ENABLE: SOC_ROT (Idx 2) * INTR_TEST: SOC_ROT (Idx 2) * ALERT_TEST: SOC_ROT (Idx 2) + * ALERT_STATUS: SOC_ROT (Idx 2) * LOG_CONFIG: SOC_ROT (Idx 2) * LOG_STATUS: SOC_ROT (Idx 2) * LOG_ADDRESS: SOC_ROT (Idx 2) @@ -347,13 +348,13 @@ package top_darjeeling_racl_pkg; * RANGE_RACL_POLICY_SHADOWED_30: SOC_ROT (Idx 2) * RANGE_RACL_POLICY_SHADOWED_31: SOC_ROT (Idx 2) */ - parameter racl_policy_sel_t RACL_POLICY_SEL_AC_RANGE_CHECK [167] = '{ + parameter racl_policy_sel_t RACL_POLICY_SEL_AC_RANGE_CHECK [168] = '{ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 }; endpackage