From c643d81ebba48a0ccdc61a2962ac936fcb947080 Mon Sep 17 00:00:00 2001 From: Pascal Nasahl Date: Mon, 2 Dec 2024 15:50:42 +0100 Subject: [PATCH] [ibex,fpga] Fix FPGA related Ibex counter issue This commit fixes the reset logic of the Ibex counter module for the FPGA. Signed-off-by: Pascal Nasahl (commit is original to earlgrey_1.0.0) --- hw/vendor/lowrisc_ibex/rtl/ibex_counter.sv | 8 ++++++-- .../rtl/0002-Fix-fpga-counter-reset.patch | 19 +++++++++++++++++++ 2 files changed, 25 insertions(+), 2 deletions(-) create mode 100644 hw/vendor/patches/lowrisc_ibex/rtl/0002-Fix-fpga-counter-reset.patch diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_counter.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_counter.sv index c78e510ee41e2..b4dc7ec347378 100644 --- a/hw/vendor/lowrisc_ibex/rtl/ibex_counter.sv +++ b/hw/vendor/lowrisc_ibex/rtl/ibex_counter.sv @@ -55,8 +55,12 @@ module ibex_counter #( localparam int DspPragma = CounterWidth < 49 ? "yes" : "no"; (* use_dsp = DspPragma *) logic [CounterWidth-1:0] counter_q; - // DSP output register requires synchronous reset. - `define COUNTER_FLOP_RST posedge clk_i + if (CounterWidth < 49) begin : g_dsp_counter + // DSP output register requires synchronous reset. + `define COUNTER_FLOP_RST posedge clk_i + end else begin : g_no_dsp_counter + `define COUNTER_FLOP_RST posedge clk_i or negedge rst_ni + end `else logic [CounterWidth-1:0] counter_q; diff --git a/hw/vendor/patches/lowrisc_ibex/rtl/0002-Fix-fpga-counter-reset.patch b/hw/vendor/patches/lowrisc_ibex/rtl/0002-Fix-fpga-counter-reset.patch new file mode 100644 index 0000000000000..f2e0506dd2368 --- /dev/null +++ b/hw/vendor/patches/lowrisc_ibex/rtl/0002-Fix-fpga-counter-reset.patch @@ -0,0 +1,19 @@ +diff --git a/ibex_counter.sv b/ibex_counter.sv +index c78e510ee4..b4dc7ec347 100644 +--- a/ibex_counter.sv ++++ b/ibex_counter.sv +@@ -55,8 +55,12 @@ module ibex_counter #( + localparam int DspPragma = CounterWidth < 49 ? "yes" : "no"; + (* use_dsp = DspPragma *) logic [CounterWidth-1:0] counter_q; + +- // DSP output register requires synchronous reset. +- `define COUNTER_FLOP_RST posedge clk_i ++ if (CounterWidth < 49) begin : g_dsp_counter ++ // DSP output register requires synchronous reset. ++ `define COUNTER_FLOP_RST posedge clk_i ++ end else begin : g_no_dsp_counter ++ `define COUNTER_FLOP_RST posedge clk_i or negedge rst_ni ++ end + `else + logic [CounterWidth-1:0] counter_q; +