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[rules,opentitan] Generate non-scrambled ROM images for sim_dv
Some DV simulation test benches may choose to disable ROM scrambling in order to reduce run times. In this case they would use an un-scrambled ROM image. Signed-off-by: Samuel Ortiz <[email protected]>
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rules/opentitan/cc.bzl

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@@ -261,6 +261,9 @@ def _opentitan_binary(ctx):
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# FIXME(cfrantz): Special case: The englishbreakfast verilator model
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# requires a non-scrambled ROM image.
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#
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# DV simulation might also need non-scrambled ROM to reduce simulation
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# run times.
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if provides.get("rom32"):
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default_info.append(provides["rom32"])
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rules/opentitan/sim_dv.bzl

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@@ -54,12 +54,22 @@ def _transform(ctx, exec_env, name, elf, binary, signed_bin, disassembly, mapfil
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rom_scramble_config = exec_env.rom_scramble_config,
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rom_scramble_tool = ctx.executable.rom_scramble_tool,
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)
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# We may want to run non-scrambled ROM in DV environment, for faster
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# run times.
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rom32 = convert_to_vmem(
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ctx,
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name = name,
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src = binary,
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word_size = 32,
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)
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default = rom
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vmem = rom
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vmem32 = None
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elif ctx.attr.kind == "ram":
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default = elf
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rom = None
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rom32 = None
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# Generate Un-scrambled RAM VMEM (for testing SRAM injection in DV)
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vmem = convert_to_vmem(
@@ -99,6 +109,7 @@ def _transform(ctx, exec_env, name, elf, binary, signed_bin, disassembly, mapfil
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_tool = exec_env.flash_scramble_tool.files_to_run,
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)
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rom = None
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rom32 = None
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default = vmem
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vmem = vmem_base
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else:
@@ -115,6 +126,7 @@ def _transform(ctx, exec_env, name, elf, binary, signed_bin, disassembly, mapfil
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"binary": binary,
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"default": default,
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"rom": rom,
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"rom32": rom32,
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"signed_bin": signed_bin,
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"disassembly": disassembly,
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"logs": logs,

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