From bfc20a9dfff94e60af1f8ef76839445fab9298db Mon Sep 17 00:00:00 2001 From: Martin Velay Date: Mon, 24 Feb 2025 09:39:59 +0000 Subject: [PATCH] [acrc,dv] Multiple fixes after rebase - fix required IP name in testplan as the master contained a mistake - generate darjeeling testplan from IP template - remove racl_error_log_o port from top TB Signed-off-by: Martin Velay --- .../data/ac_range_check_testplan.hjson | 4 +- .../ac_range_check/dv/tb/tb.sv.tpl | 3 - .../data/ac_range_check_testplan.hjson | 86 +++++++++++++++++++ .../ip_autogen/ac_range_check/dv/tb/tb.sv | 3 - 4 files changed, 88 insertions(+), 8 deletions(-) create mode 100644 hw/top_darjeeling/ip_autogen/ac_range_check/data/ac_range_check_testplan.hjson diff --git a/hw/ip_templates/ac_range_check/data/ac_range_check_testplan.hjson b/hw/ip_templates/ac_range_check/data/ac_range_check_testplan.hjson index 34233e173d94b..de0a7cc8fd440 100644 --- a/hw/ip_templates/ac_range_check/data/ac_range_check_testplan.hjson +++ b/hw/ip_templates/ac_range_check/data/ac_range_check_testplan.hjson @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 { - name: "dma" + name: "ac_range_check" import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson", "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson", "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson", @@ -48,7 +48,7 @@ Checking: - If RANGE_REGWEN was cleared to MuBi4::False, the reconfigured register values - The original configuration should remain in the registers. If RANGE_REGWEN was not + The original configuration should remain in the registers. If RANGE_REGWEN was not cleared, the reconfigured values should have replaced the original ones. ''' stage: V2 diff --git a/hw/ip_templates/ac_range_check/dv/tb/tb.sv.tpl b/hw/ip_templates/ac_range_check/dv/tb/tb.sv.tpl index 2042bf3b03aea..0981ffefc3731 100644 --- a/hw/ip_templates/ac_range_check/dv/tb/tb.sv.tpl +++ b/hw/ip_templates/ac_range_check/dv/tb/tb.sv.tpl @@ -19,7 +19,6 @@ module tb; wire rst_shadowed_n; wire top_racl_pkg::racl_policy_vec_t racl_policies; wire racl_error; - wire top_racl_pkg::racl_error_log_t racl_error_log; wire intr_deny_cnt_reached; wire prim_mubi_pkg::mubi8_t range_check_overwrite; @@ -44,7 +43,6 @@ module tb; // RACL interface .racl_policies_i (racl_policies ), .racl_error_o (racl_error ), - .racl_error_log_o (racl_error_log ), // Access range check interrupts .intr_deny_cnt_reached_o (intr_deny_cnt_reached ), // Bus interface @@ -69,7 +67,6 @@ module tb; assign interrupts[DenyCntReached] = intr_deny_cnt_reached; // TODO should be monitored dynamically by an io_agent (to be created TODO MVy) // assign io_if.racl_error = racl_error; - // assign io_if.racl_error_log = racl_error_log; initial begin clk_rst_if.set_active(); diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/data/ac_range_check_testplan.hjson b/hw/top_darjeeling/ip_autogen/ac_range_check/data/ac_range_check_testplan.hjson new file mode 100644 index 0000000000000..de0a7cc8fd440 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/data/ac_range_check_testplan.hjson @@ -0,0 +1,86 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "ac_range_check" + import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson", + "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson", + "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson", + "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson"] + testpoints: [ + { + name: ac_range_check_smoke + desc: ''' + Smoke test in which we configure a randomized number of ranges to allow a transfer + and perform transfers. + + Stimulus: + - Assert range_check_overwrite_i to MuBi8::False + - Configure a random number of ranges: + * Randomize the RANGE_BASE and RANGE_LIMIT register (RANGE_LIMIT > RANGE_BASE) + * Randomize the RANGE_PERM register and set the RANGE_PERM.enable bit to 1 + * Set RANGE_RACL_POLICY_SHADOWED.read_perm and + RANGE_RACL_POLICY_SHADOWED.write_perm to 0xFFFF (disables RACL checks) + - Perform random TLUL requests where at least 1 RACL role bit is set in the TLUL + user bit vector. + + Checking: + - If a request falls outside of any configured range, the request is denied and TLUL + error is returned. Read requests return all zero as data. + - If the request falls in any of the configured range, and the TLUL request matches + the (R/W/X) permissions of the configured range, the request should be allowed. + * Write transfer goes through + * Read and Execute request return the expected data + ''' + stage: V1 + tests: ["ac_range_check_smoke"] + } + { + name: ac_range_lock_range + desc: ''' + Test the range lock functionality + + Stimulus: + - Configure a range's RANGE_BASE, RANGE_LIMIT, RANGE_PERM, RANGE_RACL_POLICY_SHADOWED + register + - Clear RANGE_REGWEN to MuBi4::False in a randomized way + - Try to reconfigure the range with different values + + Checking: + - If RANGE_REGWEN was cleared to MuBi4::False, the reconfigured register values + The original configuration should remain in the registers. If RANGE_REGWEN was not + cleared, the reconfigured values should have replaced the original ones. + ''' + stage: V2 + tests: ["ac_range_lock_range"] + } + { + name: ac_range_bypass_enable + desc: ''' + Test the bypass functionality for enabled ranges. + + Stimulus: + - Assert range_check_overwrite_i to Mubi8::True + - Configure the AC range check to block certain address ranges + * Randomize type of denial (R/W/X, RACL policies) + - Perform random TLUL requests that fall within blocked ranges and outside with: + * Random request type (R/W/X) and random RACL role + + Checking: + - Check if all transfers are allowed + - LOG_STATUS.deny_cnt must stay 0 + ''' + stage: V2 + tests: ["ac_range_check_bypass"] + } + ] + covergroups: [ + { + name: ac_range_check_log_status_cg + desc: ''' + Cover all status fields of the LOG_STATUS. + (deny_cnt and deny_range_index are not part of this). + ''' + } + ] + } diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/tb/tb.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/tb/tb.sv index 7c0465adcf555..55606f7a5c4aa 100644 --- a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/tb/tb.sv +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/tb/tb.sv @@ -19,7 +19,6 @@ module tb; wire rst_shadowed_n; wire top_racl_pkg::racl_policy_vec_t racl_policies; wire racl_error; - wire top_racl_pkg::racl_error_log_t racl_error_log; wire intr_deny_cnt_reached; wire prim_mubi_pkg::mubi8_t range_check_overwrite; @@ -44,7 +43,6 @@ module tb; // RACL interface .racl_policies_i (racl_policies ), .racl_error_o (racl_error ), - .racl_error_log_o (racl_error_log ), // Access range check interrupts .intr_deny_cnt_reached_o (intr_deny_cnt_reached ), // Bus interface @@ -69,7 +67,6 @@ module tb; assign interrupts[DenyCntReached] = intr_deny_cnt_reached; // TODO should be monitored dynamically by an io_agent (to be created TODO MVy) // assign io_if.racl_error = racl_error; - // assign io_if.racl_error_log = racl_error_log; initial begin clk_rst_if.set_active();