From 8e35473ce14035640dc57eeb99ef7f539532bec3 Mon Sep 17 00:00:00 2001
From: Miguel Osorio <miguelosorio@google.com>
Date: Wed, 18 Dec 2024 23:26:20 +0000
Subject: [PATCH] [dv] Add ROT_AUTH configuration test.

This test exercises the ROT AUTH programming sequence performed during FT stages. The ROT
AUTH partitions are used to store the ROM (e.g. root keys) of the Earl Grey top level.

Signed-off-by: Miguel Osorio <miguelosorio@google.com>
---
 hw/top_earlgrey/dv/chip_sim_cfg.hjson         | 16 ++++++++++
 sw/device/tests/BUILD                         | 27 ++++++++++++++++
 .../tests/otp_ctrl_rot_auth_config_test.c     | 32 +++++++++++++++++++
 3 files changed, 75 insertions(+)
 create mode 100644 sw/device/tests/otp_ctrl_rot_auth_config_test.c

diff --git a/hw/top_earlgrey/dv/chip_sim_cfg.hjson b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
index 9f53798d59cefb..acd94362d856cd 100644
--- a/hw/top_earlgrey/dv/chip_sim_cfg.hjson
+++ b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
@@ -874,6 +874,22 @@
       run_timeout_mins: 120
       reseed: 1
     }
+    {
+      name: chip_sw_otp_ctrl_rot_auth_config
+      uvm_test_seq: chip_sw_rom_e2e_jtag_inject_vseq
+      sw_images: [
+        "//sw/device/silicon_creator/rom/e2e/jtag_inject:img_test_unlocked0_exec_disabled:4",
+        "//sw/device/tests:otp_ctrl_rot_auth_config_test:5",
+      ]
+      en_run_modes: ["sw_test_mode_mask_rom"]
+      run_opts: [
+        "+sw_test_timeout_ns=80_000_000",
+        "+use_jtag_dmi=1",
+        "+use_otp_image=OtpTypeCustom",
+      ]
+      reseed: 1
+      run_timeout_mins: 240
+    }
     {
       name: chip_sw_otp_ctrl_ecc_error_vendor_test
       uvm_test_seq: chip_sw_otp_ctrl_vendor_test_ecc_error_vseq
diff --git a/sw/device/tests/BUILD b/sw/device/tests/BUILD
index a0379793b4ea11..bf1e3233f8378a 100644
--- a/sw/device/tests/BUILD
+++ b/sw/device/tests/BUILD
@@ -2303,6 +2303,33 @@ opentitan_test(
     ],
 )
 
+opentitan_binary(
+    name = "otp_ctrl_rot_auth_config_test",
+    testonly = True,
+    srcs = ["otp_ctrl_rot_auth_config_test.c"],
+    exec_env = [
+        "//hw/top_earlgrey:sim_dv",
+    ],
+    kind = "ram",
+    linker_script = "//sw/device/examples/sram_program:sram_program_linker_script",
+    deps = [
+        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+        "//sw/device/lib/arch:device",
+        "//sw/device/lib/base:abs_mmio",
+        "//sw/device/lib/base:macros",
+        "//sw/device/lib/dif:otp_ctrl",
+        "//sw/device/lib/runtime:log",
+        "//sw/device/lib/testing:otp_ctrl_testutils",
+        "//sw/device/lib/testing/test_framework:check",
+        "//sw/device/lib/testing/test_framework:status",
+        "//sw/device/silicon_creator/manuf/lib:individualize",
+        "//sw/device/silicon_creator/manuf/lib:individualize_sw_cfg_sival",
+        "//sw/device/silicon_creator/manuf/lib:otp_fields",
+        "//sw/device/silicon_creator/manuf/lib:sram_start",
+        "//sw/device/lib/testing/test_framework:ottf_test_config",
+    ],
+)
+
 opentitan_test(
     name = "keymgr_sideload_aes_test",
     srcs = ["keymgr_sideload_aes_test.c"],
diff --git a/sw/device/tests/otp_ctrl_rot_auth_config_test.c b/sw/device/tests/otp_ctrl_rot_auth_config_test.c
new file mode 100644
index 00000000000000..34deef8f8b4483
--- /dev/null
+++ b/sw/device/tests/otp_ctrl_rot_auth_config_test.c
@@ -0,0 +1,32 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#include <stdint.h>
+
+#include "sw/device/lib/arch/device.h"
+#include "sw/device/lib/base/abs_mmio.h"
+#include "sw/device/lib/dif/dif_otp_ctrl.h"
+#include "sw/device/lib/runtime/ibex.h"
+#include "sw/device/lib/runtime/log.h"
+#include "sw/device/lib/runtime/print.h"
+#include "sw/device/lib/testing/otp_ctrl_testutils.h"
+#include "sw/device/lib/testing/test_framework/check.h"
+#include "sw/device/lib/testing/test_framework/ottf_test_config.h"
+#include "sw/device/silicon_creator/manuf/lib/individualize.h"
+#include "sw/device/silicon_creator/manuf/lib/individualize_sw_cfg.h"
+#include "sw/device/silicon_creator/manuf/lib/otp_fields.h"
+
+#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
+
+OTTF_DEFINE_TEST_CONFIG();
+
+bool test_main(void) {
+  static dif_otp_ctrl_t otp_ctrl;
+  CHECK_DIF_OK(dif_otp_ctrl_init(
+      mmio_region_from_addr(TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR), &otp_ctrl));
+  CHECK_STATUS_OK(
+      manuf_individualize_device_rot_creator_auth_codesign(&otp_ctrl));
+  CHECK_STATUS_OK(manuf_individualize_device_rot_creator_auth_state(&otp_ctrl));
+  return true;
+}